Plasma Cleaning Application

Reinhard Windemuth
Sales Director Microelectronics Europe
Panasonic Automotive & Industrial Sales Europe GmbH

Abstract
Packaging is getting more and more important for MEMS and Sensor packages.
Flipchip Process is more and more getting important to replace conventional COB technologies such as Dieattach and Wirebonding. Main target is to shrink the Sensor package size and increase the package reliability.
Plasma Cleaning process can be used for improving any package reliability when different material are connected to each other. Such applies for Molding, Flipchipbonding, Underfill Wirbonding, Diebonding and other compound or interconnection processes.
Panasonic provides manufacturing solutions for any Plasma Cleaning application.
Basic applications will be described accordingly.
Some Flipchip approaches will be mentioned and described.
Some equipment requirements and features that are suitable for MEMS packages will be highlightes so far.

Biography
Degree of Diplom-Ingenieur in Process Engineering on Technical University in Munich / Germany in 1988. Since then Project Management & Sales for different kinds of Industy, mainly in chemical Industry. Since 1998 Sales & Project management in Microelectronics & Semiconductor Industry for F&K Delvotec, Wirebonding and Diebonding Technology. Profund experience in handling packaging projects in both Semiconductor and Device-Manufacturing Industry. Since 2006 Sales Director for Microelectronics Equipment at Panasonic Factory Solutions Europe (PFSE). Main target is to establish new PFSE business fields in the Backend and Frontend Industry in Europe: Dieattach, Flipchip, Plasma Cleaning and Plasma Etch Technolgies.

Speech and Gesture -- Futuristic Human Machine Interfaces

Rico Petrick
CEO
Linguwerk GmbH

Abstract
Technical devices are logical and functional units by nature. Their actual purpose is often very straight-forward, but also often very technical or highly complex. They measure temperatures, wash dishes, control industrial equipment, provide information, entertain, save lives, or provide support. They are operated using buttons or touch. They "speak" to us via display, LEDs, vibration, speech, sounds, shapes, colours, and sometimes not at all. In some situations user interaction without touching the device is useful. In those cases speech recognition or gesture recognition can be a solution. Linguwerk GmbH develops such technologies with a very low footprint as such, that they fit on a low price microcontroller (e. g. 1 USD). The very low hardware price is precondition to implement such future HMI technologies into customer products such as house hold devices or home automation equipment.

Biography
Rico Petrick is initiator, founder and CEO of the Linguwerk GmbH, a company that is specialized in signal processing and speech technology. He has graduated in electrical engineering at the Dresden University of Applied Sciences and received a PhD degree in electrical engineering with a specialisation in speech processing from the Dresden University of Technology. His scientific major is the robustness of speech recognition systems in real and adverse acoustic environments. He has worked in algorithmic design of digital signal processing systems and embedded speech processing since 1998 in various positions in science and industry. Selected academic positions included the University of Technology, Sydney (UTS), Australia; the Japan Advanced Institute of Science and Technology (JAIST), Kanazawa, Japan; the St. Petersburg Institute for Informatics and Automation of the Russian Academy of Sciences (SPIIRAS), St. Petersburg, Russia; and the Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. As a scientist, Rico Petrick has published about 30 national and international scientific papers, and he is further reviewer for the scientific journal Speech Communication (SPECOM), run by the world's leading speech technology organisation ISCA.

Smart Metering-Monitoring and Control

Bernd Dahlheimer
Director Marketing
Anvo-Systems Dresden GmbH

Abstract
Smart Meter - Monitoring and Control
In our everyday lives smart metering, is becoming more and more important, very much like the Internet of things (IoT). So far the focus has been on electricity meters, however, other applications and use models are evolving quickly. In addition to other meters, such as water, gas or heat meters, there is also a wide range of data loggers. All these systems require safe and secure data storage. In case of power fluctuation, or even power loss, the data must be saved securely. This challenging requirement can be addressed with nvSRAMs from Anvo-Systems Dresden, the best choice for very fast and secure data storage. These nvSRAMs can, even at complete power loss, automatically save configuration information, the last system state, or processed data from sensors or actor nodes and concentrators. The technology of these devices and possible use models with highly reliable nvSRAM Memories from Anvo-Systems Dresden will be discussed.

Biography
Bernd Dahlheimer
Director Marketing, Anvo-Systems Dresden

Bernd Dahlheimer has more than 20 years experience in international sales management, tactical and strategic marketing, business development and business unit management in high tech companies in the fields of Semiconductors (ASSPs, sensors, mixed signal non volatile memories), Optoelectronics, LED technology and Solid State Lighting.
After completing his Masters of Electronics Engineering in Darmstadt, Bernd Dahlheimer´s professional experience includes working for Jermyn, a semiconductor distributor (today part of Avnet www.avnet.com ), Hewlett Packard´s Semiconductor Products Group www.hp.com , Agilent Technologies www.agilent.com and ZMD www.zmdi.com .
In his role as Marketing Director for Anvo Systems http://www.anvo-systems-dresden.com Bernd Dahlheimer´s extensive knowledge of the semiconductor markets combined with his international management experience and network will be instrumental in rapidly achieving business results for Anvo Systems in the non volatile memory market, which is getting more and more important to fulfill today´s and future requirements for data and system security.

Solutions for the Semiconductor Market

Daniel Sälzer
Market Manager Semiconductor
Pfeiffer Vacuum

Abstract
Today, billions of transistors are inserted into a single microprocessor for computers. Incredibly large numbers of these semiconductor components are also incorporated in smartphones, flat screens, LED TVs, and digital cameras, to make them meet the ever increasing performance demands. Without the use of vacuum technology today's method of chip production would be unthinkable. With its broad product portfolio, Pfeiffer Vacuum offers comprehensive solutions for chemical and physical manufacturing processes that are commonly used in semiconductor manufacturing.

Biography
Daniel Sälzer has been working for Pfeiffer Vacuum at different positions since 15 years. He managed the Pfeiffer Vacuum operation in China for about four years and was responsible for the operation and development of Pfeiffer Vacuum Singapore for more than 2 years. Since a few years he is back in Germany and responsible for key customers in the semiconductor market. He holds a degree in Electrical Automation from the University of Applied Sciences Giessen-Friedberg.

Springless Diaphragm Valves with Replaceable-Seat from Swagelok®

Moritz Bruettinger
Field Engineer
Swagelok Co.

Abstract
Swagelok® is pleased to announce two new high purity products for our customers working with chemical canister applications. The Swagelok® DPX and DFX Replaceable-Seat, Springless Diaphragm Valves offer repeatable seat replacement and a seat seal that protects against chemical and thermal swelling and process chemistry degradation.
Building on the proven performance of the Swagelok® DP and DF series valves, the DPX and DFX valves are designed to enable advanced chemistry processing in thin film deposition applications. Unlike typical replaceable seat valves, the DPX and DFX valves' tight-fitting seat designs have minimal entrapment areas and low profiles to guard against flow area reduction, pressure drops, restricted flow, and inefficient purging; providing the added reliability and assurance users need to achieve more with their application. Swagelok® has also created a DPX and DFX Replaceable-Seat, Springless Diaphragm Valve Tool and Maintenance Kit. This includes seat removal and installation tools and an innovative seat carrier to enable precise installation into the valve body.

Biography
Moritz Bruetinger has a degree of Industrial Engineering. He began his career with Swagelok in 2009 with Swagelok Stuttgart/Karlsruhe as a Salesman in South-West-Germany. In his sales area Moritz had the whole spectrum of Swagelok key-markets. His focus was on Chemical and Petrochemical applications, Research Labs, pump manufacturer and analytical instrumentation. In 2013 Moritz joined Swagelok Company as a Field Engineer for Central and Eastern Europe.

Testing IoT devices, the next ATE challenge

Adriano Mancosu
Business Development Manager, SoC Test Business Group
Advantest Europe GmbH

Abstract
The "Internet of Things" - IoT is becoming ever present in our lives. With this, we are also seeing a huge increase in semiconductor devices being developed and manufactured, specifically for this market. For semiconductor test, many of these devices pose new challenges, which need to be addressed by test solutions. Some of these challenges will be discussed. How Advantest's V93000 Single Scalable Platform is ideally prepared to address such new requirements will be presented.

Biography
Adriano Mancosu is business development manager in the SOC business group of Advantest. He has worked in the ATE industry for over 19 years, starting his career at Schlumberger. Over the years he held various different positions in application engineering and marketing.
Adriano is a graduate in electronic engineering at the Politecnico di Milano, Italy.

Expertise in Mixed-Signal ICs Testing

Pierre Cantagrel
Hardware engineer
Analog Power Lab

Abstract
Currently, because of the omnipresent breakneck technical development, we observe the surge of ICs complexity. Therefore, the necessity of efficient automated test equipment, able to provide an optimum broad spectrum of test, is revealed.
In order to gain productiveness, the measurement methods need to be adapted to this market tendency. Owing to the application of a "customized rack", we are able to face automation challenges. Unlike frozen functionalities, this rack can be custom-made and reusable thanks to instrumentation modules.
The added value of this solution is the capacity to test the Device Under Test directly on Evaluation module, and to automate the major part of mix-signal measurements. Furthermore, the friendly user interface allows the customer to use it independently, at his locations.
Last but not least, Automation solutions developed by Analog Power Lab minimize the time allocated to the validation and reduce the cost due to stored generic sequences.

Biography
Pierre Cantagrel is an expert in electronic/micro-electronic development, hardware testing and validation. He has 12 years of experience in these domains.
P. Cantagrel obtained his Bachelor of Science degree in Microelectronics in 2004, at POLYTECH'SOPHIA. He had been acquiring valuable skills in Electronics development in different high-tech companies. Afterwards, he joined Texas Instruments France as Mixed-Signal Validation Manager and works for major phone OEM's during more than 7 years.
This strong professional experience enabled Pierre Cantagrel to co-found the company Analog Power Lab, an electronic laboratory in Sophia Antipolis. At Analog Power Lab, he manages full-validation IC's projects.

NEW Wafer Handling Solutions for high vacuum and glovebox applications.

Andreas Maas
Project Manager
ADENSO GmbH

Abstract
Substrate handling in vacuum environment often based on using carriers which means a lot of additional weight for the robot arm. Also substrates with large dimensions as like as FPD flat panel displays generates a high load for the handling robot.

Oversized gate valves cause high investment cost and operating costs due to high volumes.

Additionally a limited travel range of the robot arm restricts the design of the process areas.

The presentation touches these challenges by the example of Adenso WHR Wafer Handling Robot solutions.

Biography
Andreas Maas is an expert in automation, handling and testing substrates and devices.
He has extensive experience in the vacuum business, special purpose machinery manufacturing and semiconductor equipment.

Shop-Floor-Integration in Context of Industrie 4.0

Hans Mayer
COO
znt Zentren für Neue Technologien GmbH

Abstract
Using Industry 4.0 Concepts in Semiconductor Environment

Shop Floor Integration is an essential precondition for implementing the concepts of Industry 4.0. While in Semiconductor Front End Fabs the integration is widely implemented based on Semi Standards, the backend and facility management areas are subject to further integration efforts. Especially in the Backend area we often face proprietary communication protocols and none Semi-Standard Interface that cause high integration efforts.

The talk shall point out, which concepts and standardization activities are going on in the Indus-try 4.0 community and which approaches may also be useful for the Semiconductor Industry to close gaps in some areas of shop Floor integration.

The first part highlights the position of shop floor integration in terms of the Reference Architecture Model Industry 4.0 (RAMI4.0) that has been updated in April 2015 by the Platform Industry 4.0. In the next part ongoing integration standardization activities are presented, followed by an outlook, how the results of the activities may be used in the Semiconductor Industry. The last part shows a solutions architecture that can implement those integration concepts.

Biography
Hans Mayer (Ing.)

Hans Mayer has 28 years of experience in IT Systems for automation.

After 6 years at Siemens AG in Munich in software development for cell phones, he joined znt. With znt he implemented many automation projects as software developer and project manager for different industries with a main focus on Semiconductor and Solar Industry, Medical Device and Electronic Industry and Automotive Suppliers.

Opportunities and Challenges Using Self-Navigating Systems in Semiconductor Fabs

Karli Hantzschmann
Division Manager Automation
Roth & Rau - Ortner GmbH

Abstract
Self-Navigating Systems (SNS) with and without handling functionality are considered as one option to go beyond commercial and technical limits of traditional Automated Material Handling Systems like conveyors or overhead hoist systems.

However, these SNS are still associated with various issues, which still have to be resolved before a widespread use becomes feasible.

The presentation touches some of these challenges by the example of Roth & Rau - Ortner's SNS SCOUT®.

Biography
Dr. Karli Hantzschmann:

- Division Manager Fab Automation - Roth & Rau-Ortner (since 2011)
- Department Manager Global Customer Support Turnkey Lines - Roth & Rau - Ortner (2009-2011)
- Senior Manager Automation - Qimonda (2008-2009)
- Lead Engineer Automation Projects & Innovation - Infineon (2004-2008)
- Lead Engineer Automation Operations & Maintenance - Infineon (2003-2004)
- Systemexperte Automation / CIM - Semiconductor300 (1998-2002)

HERO unchained - Modular AGV for multiple handling applications

Burkhard Stegemann
Sales Director
HAP GmbH Dresden

Abstract
The big majority of European chip fabs still uses wafer sizes of 200mm and smaller. Most of these fabs are older and grew over many years. Hence, the infrastructure in the cleanrooms is very different from fab to fab. This is related to the available space and the positioning of equipment inside the cleanroom, but also to the carriers that are used during the transport and production. While some fabs already use open cassettes fab wide, most use different kinds of transport boxes that additionally require the un-locking and the opening of the covers. As these tasks are challenges for automation systems, most of these fabs still manually load the wafer carriers onto the systems by operators.
The HAP-HERO FAB system family addresses these diverse requirements. These fully free (no rail, cable or chain attached) navigating AGVs are able to handle different kinds of transport boxes, to un-lock and open them and to take out and load the cassettes onto the equipment loadports. SMIF pods, RSPs and FOUPs can be loaded as well.

Biography
Born in 1969, Burkhard Stegemann studied Physical Technics at the FH Aachen and completed his final year at Coventry University. In 1996 he joined Carl Zeiss in Jena in the department of microscopic wafer inspection. After two years in R&D/ application, he changed to product and project management.
As part of the acquisition of the Zeiss business field "optical wafer inspection" by HSEB Dresden GmbH in 2004, Burkhard Stegemann joined HSEB in 2007. His responsibilities were sales and service.
Since May 2014 Burkhard Stegemann is sales director of HAP GmbH Dresden.

Wafer Signature Detection - Automatic Defect Recognition and Classification

Andre Schaaf
Software Developer
SYSTEMA GmbH

Abstract
Root cause analyses have shown that back side scratches and signatures are a major cause of wafer breakage during semiconductor process steps. However, wafer back sides can have 100k+ of defects that avoid critical defect identification. Auto-classification of defect signatures is difficult and their calculation time-consuming. Hence, manual review is still common operational procedure.
HSEB develops, designs, and manufactures high-throughput AOI systems including for wafer back side inspection. SYSTEMA is a global specialist in integration of high-tech manufacturing IT.
SYSTEMA and HSEB are presenting a solution for wafer signature detection to automatically pre-filter, recognize, and classify defects allowing real-time statistical process control even for very high defect densities.

Biography
About the Speakers
André Schaaf, born in 1985, is an expert for Signature Detection of silicon wafers with a 12-year experience in both, Semiconductor and the Gaming Industry. The Senior Software Architect supports chip and wafer manufacturers in comprehensive projects, e.g. for (web) application frameworks. Before joining SYSTEMA in 2013, he has been working self-employed in a variety of projects as Senior Software Architect and Lead Developer. One of his current activities is about porting algorithms to GPUs to harvest more computing potential.
Susan Duerigen, PhD, is an application expert for wafer back side inspection. She started working in semiconductor industry in 2006 and joint HSEB in 2014 being by now responsible for the Key Account Globalfoundries Fab 1.

Behavioral modeling of cross-wafer chip-to-chip process induced non-uniformity

William Clark
Semiconductor Process/Integration
COVENTOR

Abstract
As technology continues to scale feature sizes the across wafer non-uniformities become a significant contributor to variability. Being able to model and predict these effects are key to limiting variability with adaptive process control and the reduction of total measurement error. Additionally these effects will become more pronounced as we increase the wafer footprint.

In this presentation we discuss use of the SEMulator3D ™ tool to predictively model the across wafer non-uniformities induced by various fabrication processes Including deposition and etch steps

Biography
Dr Clark has worked in all phases of Semiconductor Technology and Device integration for over 36+ years with contributions in research and development through manufacturing. After a 36 year career with IBM in VT, USA he joined COVENTOR in 2014 at the Paris, FR office as a Semiconductor Process and Integration Engineer.

Dr Clark received his Ph'D in Material Sciences from the University of Vermont. He holds 60 patents and has authored and co-authored numerous presentations.
Dr Clark is a senior member of the IEEE.

The Role of MES in Industry 4.0

Sjaak Labots
Delivery Manager
Siemens Product Lifecycle Management Software Inc.

Abstract
We are now mobile, connected and more automated than ever before. So what does that mean to semiconductor manufacturers?

While each company will answer that for themselves, Germany's Industry 4.0 is one effort to outline what manufacturers can do to compete successfully. It paints a vision of smart factories using smart machines and materials to make smart products. Leveraging the Industrial Internet of Things (IIoT), certain parts of the physical and digital value chains can merge in a connected world.

By its nature, an Industry 4.0 implementation will be incremental, not big bang. Manufacturing will still need people and centralized information applications in addition to the new IIoT data for the next several decades. This means that modern manufacturing execution systems (MES) will be required.

Find out how semiconductor manufacturers can prepare themselves for Industry 4.0.

Biography
Over the last 14 years, Mr. Labots has extensively worked with Siemens' Camstar Enterprise Platform product suite in Semiconductor, Electronics and Medical Device industries. As a Delivery Manager, Mr. Labots is responsible for the successful delivery of Camstar Manufacturing solutions to Siemens customers. Mr. Labots has experience with Camstar's full project methodology and has actively participated in all implementation phases from business development and scope definition to system design. In addition, Mr. Labots has an extensive knowledge on the vertical integration with ERP systems and Equipment Automation layers.

Prior to joining Camstar (now part of Siemens PLM), Mr. Labots spent 19+ years in manufacturing and systems design for customers in the Semiconductor, Electronics and Medical Device industries. Mr. Labots has worked in global multi-site projects for both manufacturers and integrators and has support over 25 implementations in 8 countries; and has the experience to recognize the challenges involved in complex MES projects.

Mr. Labots has a Bachelor of Science degree in Computer Science from Hogeschool Utrecht (The Netherlands).

Combine Stacked Metal Etch and Photo Resist Strip into a fully integrated efficient solution

Thomas Klaushofer
Project Development
Siconnex

Abstract
Today the market demands increased productivity and reduction in costs. Siconnex exclusively brings Metal Etching, Cleaning and Resist Strip into one fully integrated package that inherently delivers high throughput and can bring >50% savings over other wet processing concepts. There is only one solution that can bring both Siconnex BATCHSPRAY^®.

Productivity is driven by uniformity, yield and throughput. Siconnex BATCHSPRAY^® metal etch for example is outstanding in improving uniformity across the wafer and batch to batch at a much faster cycle time to single wafer wet or dry processes. Furthermore, the savings in cost come from overall cost of ownership improvements such as small footprint, less maintenance, reduction in chemical and DI water usage, exhaust, etc.

At Siconnex continuous R&D and 100% focus throughout the company on its Siconnex BATCHSPRAY^® technology makes it the most robust process available. Typical etch uniformity rates of less than 2% within wafer and wafer-to-wafer are guaranteed, from smaller wafers through 200mm to even 300mm. Real time Optical End Point Detection of the etch process will also achieve excellent batch to batch uniformity, and furthermore makes the process independent from the actual composition - age - of the chemical.

A typical process example is Al (and its alloys such as AlCu, AlSi, etc.) metal etch followed by Ti/TiN/Ti barrier layers and resist stripping with our mature SicOzone^TM process. Up to 5 processes in one sequence. Dry in - dry out.

Biography
Thomas Klaushofer is part of the Project Development department of Siconnex where he is responsible for discovering new process possibilities and cooperation with customers and research institutes.
Further he is analyzing current wet processing equipment of existing fabs and detecting cost saving opportunities.

Prior to this role, Mr. Klaushofer was in the R&D of Siconnex.
He holds a master degree in mechatronics from the University of Linz.

The Green Contactless Horizontal Wafer Shipper Solution

Jorgen Lundgren
Senior Applications Engineer
Entegris GmbH

Abstract
The traditional Horizontal Wafer Shipper with foam and interleaf was developed in early 2000. Since then many thousands have successfully been sold and used to ship hundreds of thousands of finished wafers around the globe. Recently semiconductor manufacturers started seeing issues and concerns with the Horizontal Wafer Shipper using advanced and or lensed/bumped wafers during storage and shipping applications.
Customers started reporting flattened or shared lead bumps and also stain on their wafers. Investigations revealed that the ESD coating of the inserts is a salt comprised of potassium. In the presence of moisture, the potassium coating migrates to the wafer surface and can contaminate the finished product. The shared lead bumps are caused by the interleaf surface being in contact with the wafer surface.
The request was to develop a Horizontal Wafer Shipper without the foam and interleafs. The new solution was completed in 2010 and the Contactless Horizontal Wafer Shipper (CL HWS)was developed. CL HWS consists of a base and top cover and 26 rings, the rings stack on top of each other and keep the wafers from contacting each other. The CL HWS is designed for standard, thin, 3D, MEMS and bumped wafers and eliminates the need to use inserts and foam cushions. The CL HWS significantly reduces the number of particles during shipments, has ESD properties is automation compatible and reusable.
The CL HWS family includes products for 150mm, 200mm and 300mm wafers and can accommodate wafer thicknesses from 150um up to 950um for the 150mm and up to 1100um thick for the 200mm and the 300mm CL HWS product.

Biography
Senior Field Applications Engineer with electronic engineering degree from Sweden.
Previously with a Swedish International company for 10 years in a world wide technical support function, 5 of those based in Germany.
Worked for Entegris for the last 18 years supporting the Semiconductor Industry in many different technical roles with focus on wafer and reticle handling, transport and contamination control.
Heading up key projects such as product qualification of a number of 300mm fabs in Europe, European fab conversions, as well as a large number of individual customer development projects.
Active contributor to Entegris/CEA-Leti collaboration FOUP polymer contamination/decontamination research Project.
Partner in the Catrene 3D European wafer handling Project. Active SEMI participant.

Key challenges of DRIE Technology for MEMS devices

Yannick Pilloux
Business Development Manager for MEMS Market
PlasmaTherm

Abstract
MEMS devices become more and more tiny to be integrated in smartphone, tablets, as well as automotive industry. In addition, quality needs to be improved to keep reliable devices and to increase the yield per wafer. As for mature MEMS devices, production cost has to be reduced in order to be prepared for the large volume manufacturing for the Internet of Things ( IoT ) "Smart Home" and "Smart City".

Complex MEMS devices can be very challenging to manufacture. Gyroscopes, accelerometers, and microphones are established devices in automotive and consumers products. Emergent new complex devices include pico-projectors and energy-harvesting systems.

For many years Plasma-Therm has delivered the most advanced DRIE solutions for R&D, focusing on feature quality control (smooth sidewalls, notching control, and nanoscale etch). Now, Plasma-Therm is expanding into large production solutions, augmenting the Versaline® product platform with the introduction of DSE IV technology. This recent addition offers a competitive solution reducing the Cost of Ownership (CoO) for manufacturing MEMS devices.

DSE IV innovations extend the extreme selectivity of silicon etching to oxides, polyimide, PBO and metals, resulting in the ability to etch silicon without damaging sensitive materials like aluminum, gold and copper without needing to protect these layers, making this technology ideal for MEMS devices containing shiny mirrors.
The time-multiplexed anisotropic etching, also known as Bosch process, has greatly improved the MEMS manufacturing capability especially for deep etch requirement and is now extended to Thru Silicon Via (TSV) for 2.5D and 3D packaging.

This presentation will focus on the trends and evolution of the Deep Silicon Etch technology for the MEMS Market and particularly on the most recent process needs. Challenges of DRIE technology to manufacture MEMS devices will be addressed in this presentation, from mature to emerging sensor.

Biography
Yannick Pilloux is Business Development Manager at Plasma-Therm, where he is responsible for the MEMS Market. Prior to Plasma-Therm, he was Product Manager at Tegal and Alcatel Micro Machining System for about 13 years, leading the DRIE technology for MEMS Industry as well as TSV applications. Yannick holds a Master degree from CESI Lyon France.

Trends in Device Encapsulation and Wafer Bonding

Thomas Uhrmann
Director of Business Development
EV Group

Abstract
Future needs for MEMS devices is the need of high vacuum encapsulation, where future indoor and outdoor motion sensing are up and coming applications, that demand new wafer bonding technology. However, vacuum encapsulation needs for future MEMS devices are changing. With increased sensing accuracy for more reliable motion sensing, control of vacuum levels, gas compositions and hermetic sealing are getting at center stage. One attempted solution today is the use of getter materials that are chemically binding oxygen the cavity of the MEMS after bonding. The biggest issue, however, is the special process requirements and also the need for a high temperature activation step, which is both sacrificing device performance and restricting the process latitude. With the introduction of a new wafer bonding process, the wafers are preprocessed in vacuum, which means bake out and joining is all done in vacuum. In this presentation we will focus on metal, fusion and covalent bonding technology for vacuum encapsulation with respect to future device requirements.

Biography
Dr. Thomas Uhrmann is director of business development at EV Group (EVG) where he is responsible for overseeing all aspects of EVG's worldwide business development. Specifically, he is focused on 3D integration, MEMS, LEDs and a number of emerging markets.

Prior to this role, Uhrmann was business development manager for 3D and Advanced Packaging as well as Compound Semiconductors and Si-based Power Devices at EV Group. He holds an engineering degree in mechatronics from the University of Applied Sciences in Regensburg and a PhD in semiconductor physics from Vienna University of Technology.

Deposition of hermetic glass thin films for Opto and MEMS

Ulli Hansen
CEO
MSG Lithoglas GmbH

Abstract
Hermeticity permitting elevated lifetimes is an essential characteristic of higher quality devices, esp. in sensors and actuators. In many cases the desired reliability of a device can only be achieved by complex packaging solutions, which are designed to keep moisture and aggressive media away from the silicon circuitry while not impairing its interaction with the outside world.

Lithoglas offers an unique solution to apply thin borosilicate glass films directly onto semiconductor surfaces to create a hermetic sealing right on the active or sensitive circuitry, allowing for simplified packaging solutions and smaller overall device sizes. The deposition is conducted at very low temperatures (<80°C) allowing for a wide variety of materials to be processed. The glass films can be precisely structured by lift-of-lithography.
Opto-electronics widely uses glass components to create optical windows within the package. These can be replaced by directly coating glass onto the device or by creating glass cavity caps, which can be integrated into the package. MEMS devices widely rely on the hermeticity of anodic bonding, employing borosilicate glass wafers in conjunction with the silicon devices. There are drawbacks to these solutions, as the glass is a much more rigid material, which can influence the silicon transducer when thermal or mechanical stress is applied. Replacing glass wafers by glass coated silicon wafers in anodic bonding significantly reduces this disadvantage.
In MEMS capping cavity structures are joined with silicon devices e.g. by glass frit or eutectic bonding to create hermetic sealing. Using deposited borosilicate glass films such structures can be anodically bonded with high precision at reasonable cost. Especially favorable is the possibility to bond deposited glass to deposited aluminum structures, allowing for a higher freedom of design without the need of bare silicon in the bond interface.

Biography
Ulli Hansen is co-founder and CEO of Dresden-based MSG Lithoglas. He received his Ph.D. in 2004 from the Techn. University of Braunschweig in the field of TCAD for MEMS prior to engaging in the development and commerzialization of the proprietary Lithoglas glass deposition technology in 2006.

microDICE - TLS-Dicing Technology for Wafer Separation

Ronny Neubert
Sales Manager Europe
3D-Micromac AG

Abstract
TLS-Dicing is a laser based cleaving method to separate brittle materials. TLS (Thermal Laser Separation) uses thermal induced mechanical stress. A combination of heating (by laser) and cooling (by a very small amount of DI water spray) induces mechanical stress pattern into the wafer. This mechanical stress field guides a well-defined crack through the brittle material. The cleave needs for initiation a small local defect, called I-Scribe. This scribe can also be used, to extend the range of applicable products, e.g. by removing metal from the street [1].

TLS-Dicing shows manifold advantages in comparison to mechanical sawing and ablative laser processes: The cleaving speed is up to 300 mm/s (mechanical sawing speed for SiC is 7 mm/s). The material is not affected by chipping - consecutively no particles are generated. The process causes no negative residual thermal impact or stress pattern on the device. In opposite to stealth dicing TLS separates the material completely in one pass over the whole vertical thickness. Even thin backside metal is separated at the same time without any delamination. TLS requires no limiting design rules and can also be applied with metal in the street by using a preparing laser step.

These benefits make TLS the perfect dicing method for SiC-based products [2]. Hence the focus for process development was first on SiC.

The presentation will give an introduction in TLS-dicin in general, followed by a case study for the dicing costs of a given SiC-wafer. It will be concluded with an introduction of the new generation of the dicing tool microDICE.

[1] H.-U. Zuehlke, "Thermal laser separation for wafer dicing," in Solid State Technology, 2009.
[2] K. O. e. A. Dohnke, "Comparison of different novel chip separation methods for 4H-SiC (Infineon Technologies AG)," in ECSCRM, Grenoble, 2014.

Biography
Ronny Neubert was born in 1975. He studied business informatics at Hochschule Mittweida. He joined 3D-Micromac in 2002. Now, Ronny is working as Sales Manager Europe.

3D-Micromac is one of the leading solution providers for laser micro machining.

FD-SOI film thickness metrology tool

Bernd Srocka
Manager R&D
HSEB Dresden GmbH

Abstract
The newly evolving technology of building transistors superior in speed and/or power consumption on fully depleted silicon on insulator wafers (FD-SOI) is well known to be critical dependent on film thickness homogeneity of the silicon and BOX layers used. For certain products these transistors compete with the early FINFET or if combined with it makes its production easier while boosting FINFET performance to even higher parameters at the same time. The threshold voltage of a FD-SOI transistor is reported to depend with 25 mV/nm on a nominal 8.5 nm thick silicon SOI film thickness (Khafikirooz et al, 2010). Hence, in order to gain the full benefit of the FD-SOI technique the silicon film thickness and its homogeneity needs to be tightly controlled during wafer and chip manufacturing. Any thickness variation makes the low voltage operation worse by dictating to run the chip at the voltage level of the worst transistor. We present a new metrology tool dedicated to this purpose. The system combines the extreme thickness resolution and accuracy of sub-Angström range with the needed high spatial resolution and a high volume wafer throughput, as it is inevitable for a production control system. The lateral resolution can be adjusted by recipe parameters to the user needs from full wafer overview to sub-micron resolution. We use an all optical method with special emphasis on high reliability and reproducibility. Results of the tool performance checks like reproducibility and accuracy are reported. Measurement results are presented for a range of production wafers. The tool is a new part of HSEB's field proven modular tool platform for fully automated inspection and metrology applications. Thus, it can run fully automatic as well as in a manual mode and incorporates all automation requirements in a SEMI conform manner.

Biography
Dr. Bernd Srocka studied physics and obtained his PhD in semiconductor physics at the Technical University Berlin in 1993. Starting with his diploma and thesis he was all the years dedicated to semiconductor metrology and processing physics as well as to equipment development for the semiconductor industry. Since 2004 he has been working for HSEB in several positions. Today he is the director of the HSEB R&D department.

Atomistic Simulations for the Design, Fabrication, and Reliability of Semiconductor Devices

Volker Eyert
Senior Scientist
Materials Design s.a.r.l.

Abstract
With feature sizes of semiconductor devices reaching the nano-scale, the design, fabrication, and reliability face unprecedented challenges. Atomic-scale phenomena play an increasingly critical role and can have a major impact on materials properties. In this context, atomistic simulations offer unique capabilities for predicting key materials properties needed in the design of novel devices, to optimize the various processing steps in fabrication, and to control the reliability of the devices by anticipating possible failure mechanisms. With the recent advances in computational methods and computing power, atomistic simulations have evolved as an integral part of materials research and engineering. The MedeA® computational environment of Materials Design is geared towards the high demands of the semiconductor industry and is already adopted by an increasing number of leading industrial players worldwide. The capabilities of MedeA® will be illustrated by selected examples regarding interfacing with TCAD simulations, critical design parameters such as Schottky barriers and effective work functions, and transport properties including thermal conductivity. Demonstrating the benefits of atomistic simulations our presentation will address a broad audience with various technological and business perspectives of the value chain.

Biography
Volker Eyert is senior scientist at Materials Design, a company providing software, support, consulting, and contract research for materials research. He received a physics degree (Dipl.-Phys.) in 1986 from the University of Münster and a doctoral degree (Dr. rer. nat.) in physics in 1991 from the Technical University of Darmstadt. After taking a postdoctoral position in the group of Prof. O. K. Andersen at the Max-Planck-Institute for Solid State Research in Stuttgart he got an offer from the Helmholtz-Center Berlin to form a new group on atomistic simulations for photovoltaic applications in 1995. In 1998, Dr. Eyert finished his habilitation in theoretical physics at Augsburg University (Priv. Doz.), where he joined the faculty of the Institute of Physics as well as the Center for Electronic Correlations and Magnetism as an assistant professor, prior to becoming a member of the Materials Design team in 2011. During his time at Augsburg University, Dr. Eyert played an essential role in initiating and leading multi-institutional and interdisciplinary advanced research projects (SFBs) as funded by the German Science Foundation. In addition to having given numerous lectures worldwide, Dr. Eyert is author and co-author of over 130 scientific publications and book chapters as well as a monograph.

Non-destructive high-resolution 3D imaging for next generation packaging

Ennio Capria
Business development manager
Nanoelec Advanced Characterisation Platform

Abstract
With a density of integration continuously increasing, driven by a need of an always growing power efficiency and performance, 3D integration represent today the most promising strategy to adopt for next generation packaging.

Although, various designs are considered, whatever the proposed technology, all of them share the same need to find critical defects (to be correlated with failure events) or to verify the compliance of structural elements in the bulk.

X-rays are a powerful tool for this kind of analysis, in particular because they allow a non-destructive approach. 3D characterisation of the device can be obtained, whilst keeping the device functionality, enabling multimodal characterisation and in-situ/in-operando analysis. However, today, the instruments delivering 3D X-ray imaging ("computed tomography") available for conventional laboratory purposes, offer a too poor resolution, compared to the needs of nano-electronics. Thanks to the power of synchrotron radiation, this limit can be now overcome.

This talk will illustrate the opportunities offered by synchrotron X-ray 3D imaging operated at the European Synchrotron in Grenoble (France) in collaboration with CEA-LETI. We will describe the unmatched characterisation opportunity offered by the new generation nano-tomography instruments on some standard 3DIC components. This presentation will demonstrate the power of this novel investigation tool, and their importance to boost the packaging innovation. Moreover, we will describe the complementarity between synchrotron X-ray 3D imaging and other traditional nano-characterisation techniques, to offer a multi-modal/multi-scale/multi-technique approach to the future challenges of characterisation in micro and nano-electronics.

Finally, we will introduce the Nanoelec Advanced Characterisation Platform, which has been recently established in Grenoble, in order to offer these characterisations on a service based approach.

Biography
Dr.Ennio Capria gained his PhD in Applied Physics at Cranfield University (UK). He then undertook a series of academic and industrial positions in different sectors of nanotechnology. In his research career he has worked on the development of nanobiosensors and on nanocomposites for various applications. In 2011 Ennio joined Elettra where he worked on manufacturing of optoelectronic devices and particularly their characterisation with synchrotron light. Finally, from September 2013 Ennio joined ESRF as the IRT NanoElec Industrial Liaison Engineer, dedicated to the domain of micro-electronics.
Ennio has a strong background in the application of a wide range of synchrotron techniques to industrial and applied R&D problems.

3D IC? 3D Metrology!

Bastian Marheineke
President
FRT GmbH

Abstract
to be published soon

Biography
Bastian Marheineke graduated in Physics at RWTH Aachen and received his PhD from University of Ulm, working on MOCVD and PVD technologies for deposition of compound semiconductors. In 1998 he joined AIXTRON AG, Aachen Germany. Until end of 2013 he filled various management positions in Sales and Business Development for deposition tools for compound and organic semiconductors. In 2006 Bastian was appointed Vice President Sales, being in charge of global sales and service organisation. Beginning 2014 Bastian joined FRT GmbH, Bergisch Gladbach, Germany. He also appoints FRT as co-president.