GaN - the future for rectifiers.

Odd Roar Schmidt
Project director r&d
Eltek A/S

Abstract
New devices based power converters and systems Keywords—Wide band Gap semiconductor used in rectifier with focus on GAN transisitor When dealing with power conversion in a data center, the efficiency and cost-effectiveness is key! Due to the size and capacity of a modern data center, even small efficiency improvements in the power conversion from the incoming AC to the server load have great impact in terms of cost saving. Over time, Eltek has been exploring wide band gap technology, using GaN transistors instead SiMoS Fets in order to achieve higher efficiency and reliability. Together with Infineon, Eltek have for more than 2 years participated in an EU research program which now has resulted in a new 3kW/48Vdc rectifier with a peak efficiency of 97,8%. The combination of Eltek’s proven High Efficiency (HE) technology and Infineon’s GaN transistors has enabled a truly cost effective rectifier in the Super High Efficiency range. With modern silicon devices it is feasible to raise efficiency in the 230Vac-48Vdc conversion step to 98%, but based on the experience from our extensive research we are convinced that this efficiency can better be achieved by utilizing the GaN technology; simpler, more reliable and more cost effective. In our Super High Efficiency rectifier, we have been using totem pole topology with a lot of different technical issue. The PFC has a peak efficiency of approx. 99% and the rectifier has peak efficiency of 97.8% Totem pole PFC This paper will describe how and why GaN is the key to achieve reliable 98%+ efficiency.

Biography
Odd Roar Schmidt(m): R&D Project Director with Eltek. MSc in power electronics from NTNU. He has an extensive experience, 37 years,from industrial R&D and industrialisation of power converters. Formerly, director for Telecom division in Power-One where he was responsible for System, Controller and Rectifier/Converter technology and products. He has also been technical director for Power-One and Eltek.

Design of a 10kW Three Phase PFC with Silicon Carbide

Massimo Paglia
Application Engineer
ON Semiconductor gmbh

Abstract
A typical On Board battery Charger application for electric vehicles consists of a power factor correction stage (PFC) and a DCDC converter stage, both require the highest efficiency possible in order to deliver as much power as possible to the battery pack. Focus of this work is the 3 phase 10 kW PFC based on Silicon Carbide Mosfet which regulates the output voltage to 700V starting from a nominal input voltage of 230Vrms at 50Hz. Three parameters measure the performances of the system: total harmonic distortion, power factor and efficiency. Ideally they should be zero, one and 100% respectively. The configuration selected is typically known as inverter, made by 3 half bridges with each central point connected to a dedicated boost inductor, and each high side drain and low side source connected to the bus capacitor. 1200V SiC MOS 80m devices were used together with the recently released ON Semiconductor dedicated SiC gate driver, NCV51705. A digital control has been adopted by means of a mid-range microcontroller. The implemented strategy is based on a field oriented control approach where the rotating DQ domain has been selected aligning the D axes with the input voltage space vector. The selected HW together with the digital implementation represents a bidirectional system, therefore power can flow either ways by modification of the D axis reference current sign. The control strategy works on an interrupt running at 20 kHz using one ADC, 12 bits 1Mbs and one sample and hold. PWM frequency set to 70kHz. Experimental results demonstrate that the PFC was able to achieve as high as 98.7% at 6.6kW with a consistent efficiency above 98% at higher power output. THD was well below 5% from 3kW onwards and PF is above 0.99 from 4kW. All evaluated at nominal input voltage, 230Vrms.

Biography
Massimo Paglia received his B.Sc and M.Sc degree in Electrical Engineering from University of L'Aquila in 2004 and 2008 respectively. From 2009 to 2014 he was with the R&D team at Whirlpool Europe where he worked on the development of 3 phase motor control algorithms. In 2014 he joined ON Semiconductor as part of the Solution Engineering Center supporting the European Sales & Marketing group. His actual assignment is development of smart algorithms for three phase systems in power applications.

Electroless ternary nickel alloys for under bump metallization (UBM) on power semiconductors for high temperature process conditions or applications

Andreas Walter
Electroless Team Manager
Atotech Deutschland GmbH

Abstract
The presentation will show benefits and feasibility results for electroless plating of different ternary nickel alloys in comparison to the standard electroless phosphorous-containing nickel for packaging in growing power electronics or automotive industry. Standard electroless phosphorous-containing nickel for ENEP* or ENEPIG** under bump metallization has the disadvantage that at temperatures above 350°C a phase transition occurs which leads to a layer stress change and may cause cracks in the under bump layer. Ternary nickel alloys reveal no phase transitions up to 600°C, and are an excellent alternative to the standard electroless medium or high phosphorous-containing nickel for high temperature processing post nickel deposition, and high temperature soldering or applications. The paper will showcase results of the advanced properties of three different electroless ternary nickel alloys in comparison to a standard medium phosphor and a low phosphor nickel, with regards to thermal behavior, stress shift, and facture toughness. *electroless nickel, electroless palladium ** electroless nickel, electroless palladium, immersion gold

Biography
Andreas Walter has more than 18 years experience in the semiconductor industry and is currently working as head of application for electroless plating processes for Semiconductor Advanced Packaging at Atotech. Prior to joining Atotech in 2009, he worked for 3 years as an Senior Engineer at Qimonda for process integration of new memory systems, and for 7 years as a Development Engineer at Infineon, where he was responsible for material development and process integration in 300 and 200mm fab for D-RAM and resistive memories. Andreas received his Diploma and PhD in chemistry at the Martin Luther University in Halle, where he started as a scientist for synthesis of OLED dyes and organic semiconductors.