Ionut Radu
Senior Scientist, R&D
SOITEC

Biography
Ionut Radu joined Soitec's R&D organization in 2006 as staff scientist to develop wafer bonding solutions for advanced SOI substrates, such as sSOI, UTBOX and FD-SOI. He held several positions including group and project leader, and since 2008 he led the development of new applications for wafer bonding, including layer stacking technologies for 3D device integration and advanced CMOS. Dr. Radu is currently involved with academic and industrial research collaborations to support strategic developments of advanced substrate materials and technologies. Dr. Radu has 15 years experience in R&D semiconductor industry. Prior to joining Soitec, he was with Max Planck Institute of Microstructure Physics in Halle, Germany where he developed wafer bonding and thin film layer transfer technologies for semiconductor and ferroelectric materials. His experience also includes design of semiconductor components and optimized layout design at Semiconix Design Center in Bucharest. Ionut Radu obtained his B.S. in physics from University of Bucharest in 1999 and Ph.D (Dr. rer. nat.) in physics from Martin-Luther University Halle-Wittenberg in 2003. He has co-authored more than 60 papers in scientific journals, conference proceedings and reference handbooks and holds several patents in the field of semiconductor technologies. Dr. Radu is a member of IEEE society and was an invited speaker at ECS 2008 and 2010, IEEE LTB-3D 2010 and 2012 and ICICDT 2011.

Wafer-Level-System-Integration (WLSI) Technologies For 2D and 3D System-in-Packaging

Douglas Yu
Senior Director, TSMC R&D
TSMC

Abstract
New semiconductor market demands driven by smart mobile computing, cloud computing and Next Big Things (wearable, IoT, etc) are pushing existing packaging technologies, such as flip-chip, multi-chip-module (MCM) and package-on-package (PoP), beyond their technology limitation. Small form-factor and power efficiency requirement are the main challenges. These coupled with the specific product requirements such as highly cost sensitive mobile consumer market, fast increasing memory bandwidth and thermal dissipation challenges for performance-oriented device market, and the continuation of Moore's Law, that is a major concern involving every product segments have pushed not only the technology front, but also make change to the whole conventional semiconductor supply chain. New System-in-Package (SiP) with innovative Wafer-Level-System-Integration (WLSI) technologies have been proposed for flexible and powerful integration of 2D and 3D systems. Examples including CoWoSTM, Integrated Fan-Out and WLCSP will be presented in this talk.

CV of presenting author
Douglas Yu is a Senior Director of TSMC R&D. He has been in charge of advanced backend technology development for 9 major technology nodes. He assumes both principal technical contributor and program manager roles and responsibilities. He led TSMC teams to deliver industry's first production of on-chip interconnects- Cu/Low-K (k= 2.9) in 2001 at TSMC's 0.13m technology node and Low-R/ULK (k= 2.6) in 2009 at 28nm node. His success in delivering these industry standard-setting technologies significantly advanced the performance of ICs and alleviated what ITRS called "Submicron Grand Challenge"- the interconnect limitation to scaling. In addition, the success established the foundry industry as viable providers of high performance technology and indirectly enabled the modern vibrant fabless industry fab-lite companies. More recently, Dr. Yu led TSMC teams to deliver first advanced packaging technologies developed by foundry. He played leadership role to innovate TSMC Cu_BOT (Bump-on-Trace) technology and resolve package-induced issues. This is first foundry's solution of low-cost, and high Cu-bumping density advanced flip-chip (FCCSP) technology. He also established and led TSMC 3D-IC team to deliver industry's first high performance 3D-IC, with innovative CoWoSTM process flow and TSV (Through-Si-Via) architecture, to volume production. The products include both homogeneous and heterogeneous integrations of advanced Logic ICs. His works on advanced packaging and 3D-IC technologies enable chip-partition of advanced Logic ICs and sustain Moore's Law longer. These works have profound impact on the landscape of semiconductor manufacturing. Doug served as general co-chairs of IEEE IITC and chaired ITRS Interconnect conferences. He is an advisory board member of IEEE IMPACT and an Industrial Advisory Board member of Microsystems Industrial Group at Microsystems Technology Laboratories/MIT. He received Ph.D. degree on Material Science and Technology from Georgia Institute of Technology, currently holds more than 430 granted US patents with numerous publications on semiconductor technologies. Doug is an IEEE Fellow.

3D System Integration - Technology choices and challenges

Antonio La Manna
Program Manager
imec

Abstract
3D integration technologies allow for a significant power reduction together with a strong increase in interconnect bandwidth. This is achieved by reducing both the interconnect connection pitch and wire-length. This can be done at different levels of the electronic system hierarchy and by repartitioning the electronic system. This results in a hierarchy of 3D technologies, which we group into 3 main categories: 3D-stacked-IC or 3D-SIC (Die-to-die, or Die-to-wafer stacking), 3D-System-on-chip or 3D-SOC (Wafer-to-Wafer stacking) and the 3D device stacking or 3D-IC technologies. On the other hand, the applications requirements and the technology limitations imply a decision process that can accelerate or delay the adoption of 3D technology for volume production. As example, due to thermal limitations, some applications require the use of a so-called interposer substrate to realize high bandwidth interconnects between subsystems. The imec 3D system integration program address these technology questions in detail, both from a system level and a technology perspective. In this presentation the technology choices and challenges for 3D integration will be discussed.

CV of presenting author
Antonio La Manna is currently program manager for 3D integration at IMEC, Belgium. Prior to join IMEC, he held various technical positions at ST Microelectronics and Infineon/Qimonda. Antonio has more than 12 years' experience in semiconductors industry and covered roles from IC package design to project management for assembly and 3D integration. He has authored or co-authored over 30 publications in international conferences and scientific journals. Mr. La Manna's activities involve the areas of 3D IC integration: TSV, wafer thinning, bumping and stacking. He earned a M. S. Degree in Electronic Engineering from the University Federico II in Naples (Italy).

Technological challenges and applications of 3D sequential integration

Claire Fenouillet-Bearnger
Senior scientist
CEA/LETI/Minatec

Abstract
An alternative approach to conventional planar integration for future nodes is the 3D monolithic or sequential integration. Compared to TSV-based 3D ICs, monolithic offers the possibility to stack devices with a strong alignment precision enabling contacts introduction at the device level. However, this integration has to face the challenge to realize a high performance transistor at the top level without impacting the electrical characteristics of the bottom one. One of the issues consists in integrating transistors with low temperature process steps. The first technological challenge is the realization of a mono-crystalline and defect-free top semiconductor layer at low temperature while keeping a good uniformity to ensure good mobility and performance. The second one is the processing of low temperature top transistor with performance as good as the bottom one. Our previous works have highlighted the fabrication of low temperature devices around 600°C. Recent results demonstrate some integration solutions, such as junction activation by Solid Phase Epitaxy Regrowth below 600°C. In addition, the maximum thermal budget allowed at the top level for future technological nodes has been determined through morphological and electrical characterization. This presentation will review all the main challenges of the 3D sequential process integration and will give some example of applications.

CV of presenting author
Claire Fenouillet-Beranger was born in Grenoble, France in 1974. She received the postgraduate diploma in microelectronics and PhD degree from the Institut National Polytechnique de Grenoble, France, in 1998 and 2001, respectively. In 1998, she joined LETI, Grenoble, where she carried out her PhD. work on the integration and characterization of SOI devices. From 2001 to 2013 she worked as a CEA/LETI assignee in advanced R&D STMicroelectronics center, Crolles, France on FDSOI (Fully-depleted SOI) technology platform development and characterization. Since 2013 she is senior scientist and works as the project leader of the low temperature MOSFETs development for 3D sequential integration. She is the author and co-author of more than 130 publications in major conferences and journals and of more than 20 patents. She was the co-recipient of the Grand Prix du Général Ferrié in 2012 for her work on FDSOI.

Hybrid wafer bonding for 3D IC

Thorsten Matthias
Business Development Director
EV Group (EVG)

Abstract
3D Integration by wafer-to-wafer integration offers significant technical advantages over die-to-wafer or die-to-die stacking. Wafer-to-wafer alignment can be performed with very high accuracy in the deep sub-micrometer range at throughputs compatible with high volume manufacturing. This enables the implementation of TSVs with small diameter and small pitch and thereby enables high density TSV architectures. Wafer thinning happens usually after permanent wafer bonding, which means that one wafer acts as permanent carrier for the other wafer. This allows wafer thicknesses of 10µm or even below, which in consequence allows "shallow TSVs" with a moderate aspect ratio. This allows reducing the manufacturing costs for the TSVs significantly. In addition most wafer-to-wafer stacking techniques do not require microbumps or bumps. This "bumpless stacking" allows to further reduce the cost of 3D IC. Hybrid wafer bonding allows to establish the mechanical joint as well as the electrical contact within one process. It is a room temperature bonding process, which enables highest alignment accuracy as there is no thermal expansion of the wafers. After this room temperature bonding the wafer stack needs to be annealed. However, between bonding and annealing the wafer stack can be inspected for defects and if necessary being reworked, which enables very high yields. In this talk recent developments of hybrid wafer bonding for 3D ICs will be presented.

CV of presenting author
Dr. Thorsten Matthias is director of business development at EV Group (EVG) where he is responsible for overseeing all aspects of EVG's worldwide business development. Specifically, he is focused on 3D integration, MEMS, LEDs and a number of emerging markets. Prior to this role, Matthias was director of technology of EV Group North America in Tempe, Arizona. He began his career with EVG in 2002 as the product manager for the SmartView wafer bonding alignment system. Matthias received his doctorate degree from Vienna University of Technology with a thesis in solid-state physics in 2002.

Next Generation Contactless Shipping Solution for bumped wafers / glass substrates at 80um -1100um thickness

Jorgen Lundgren
Senior Field Applications Engineer
Entegris GmbH

Abstract
Technology is quickly shifting to a higher overall percentage of thinner and more sensitive wafers. The main driver behind the thinner, more sensitive wafers is the consumer electronics industries need for smaller, higher performing and lower cost device configurations. These devices are used in advanced chip designs for 3D, 2.5D, SOC, MEMS, LED and power semiconductors. These new requirements along with 3D applications are pushing demand for more thin and ultrathin, lens or bumped semiconductor wafers. As wafer thickness decrease, manufacturing challenges arise. Ultrathin wafers are less stable and more vulnerable to stresses, and the die can be prone to breaking and warping. This presentation will be about the new 200mm contactless substrate shipper which helps address shipping requirements for, thin, 3D, lensed or bumped wafers. 200mm CL HWS eliminates the use of TYVEK separators and pink foam cushions and enhance automation compatibility. Presentation will also highlight 150mm and 300mm contactless Horizontal Wafer shipper and vital use of moisture barrier bags.

CV of presenting author
Jorgen Lundgren Entegris GmbH Dresden German. Senior Field Applications Engineer with electronic engineering degree from Sweden. Previously with a Swedish International company for 10 years in a world wide technical support function, whereof 5 of those based in Germany. Worked for Entegris for the last 17 years supporting the Semiconductor Industry in many different technical roles with focus on wafer and reticle handling, transport and contamination control. Heading up key projects such as the first 300mm fab in Dresden, European fab conversions, new product qualifications as well as individual customer development projects. Active contributor to Entegris/CEA-Leti collaboration FOUP polymer contamination/decontamination research Project. Partner in the Catrene 3D European wafer handling Project. Active SEMI participant.