Maurizio Zuffada
R&D Director
STMicroelectronics

Biography
Maurizio Zuffada received the Laurea Degree in Electrical Engineering from Università di Pavia. He joined SGS-ATES Semiconductors in 1981 as analog design engineer. Since 1985 he has been managing a team of analog designers aimed at industrializing analog mixed signal integrated circuits for the consumer market applications. In 1990 he joined the Data Storage Division beginning a new R&D initiative in analog mixed signal ICs for hard disk drives rw-channel applications. In 1994 he was appointed R&D Director of the Data Storage Division, inside the Telecommunication Peripheral and Automotive Group of STMicroelectronics. In 1996 he took the R&D responsibility of peripheral products targeting the hard disk drive, tape storage and printer applications. In 2003 with the foundation of the Computer Peripheral Group he was appointed R&D Group Director. In 2005 he moved to Advanced R&D with particular emphasis on strategic IPs. In 2005 he joined the Medea_Plus European R&D organization as representative for STMicroelectronics Italy. Since 2006 he is the president of the Scientific Steering Committee of the Studio di Microelettronica which is an R&D ST Lab joint with and housed inside the University of Pavia. Currently he is involved in strategic researches and R&D programs for high speed low energy communications. He is currently inside the Catrene SGA European's organization and EPIC's board member. During the last 8 years he and his R&D team were following the progresses on the emerging "Silicon Photonics Technology". On that particular technology he has summarized the state of the art and his vision in the joint plenary session of the ESSCIRC 2012, EU Nanotech Forum 2012, in the work shop of EU Photonics21 2013, ECOC 2013 and SEMICON 2013. He holds many patents of which 28 are US patents.

Maurizio Zuffada
R&D Director
STMicroelectronics

Biography
Maurizio Zuffada received the Laurea Degree in Electrical Engineering from Università di Pavia. He joined SGS-ATES Semiconductors in 1981 as analog design engineer. Since 1985 he has been managing a team of analog designers aimed at industrializing analog mixed signal integrated circuits for the consumer market applications. In 1990 he joined the Data Storage Division beginning a new R&D initiative in analog mixed signal ICs for hard disk drives rw-channel applications. In 1994 he was appointed R&D Director of the Data Storage Division, inside the Telecommunication Peripheral and Automotive Group of STMicroelectronics. In 1996 he took the R&D responsibility of peripheral products targeting the hard disk drive, tape storage and printer applications. In 2003 with the foundation of the Computer Peripheral Group he was appointed R&D Group Director. In 2005 he moved to Advanced R&D with particular emphasis on strategic IPs. In 2005 he joined the Medea_Plus European R&D organization as representative for STMicroelectronics Italy. Since 2006 he is the president of the Scientific Steering Committee of the Studio di Microelettronica which is an R&D ST Lab joint with and housed inside the University of Pavia. Currently he is involved in strategic researches and R&D programs for high speed low energy communications. He is currently inside the Catrene SGA European's organization and EPIC's board member. During the last 8 years he and his R&D team were following the progresses on the emerging "Silicon Photonics Technology". On that particular technology he has summarized the state of the art and his vision in the joint plenary session of the ESSCIRC 2012, EU Nanotech Forum 2012, in the work shop of EU Photonics21 2013, ECOC 2013 and SEMICON 2013. He holds many patents of which 28 are US patents.

Hetero Silicon Photonics: Components, systems, packaging and beyond

Tolga Tekin
Group Manager Photonic & Plasmonic Systems
Fraunhofer IZM

Abstract
A key bottleneck to the realization of high-performance microelectronic systems, including SiP, is the lack of low-latency, high-bandwidth, and high density off-chip interconnects. Some of the challenges in achieving high-bandwidth chip-to-chip communication using electrical interconnects include the high losses in the substrate dielectric, reflections and impedance discontinuities, and susceptibility to crosstalk. Obviously, the motivation for the use of photonics to overcome these challenges and leverage low-latency and high-bandwidth communication. The objective is to develop a CMOS compatible underlying technology to enable next generation photonic layer within the 3D SiP towards converged microsystems. Targeting high-performance, low-cost, low-energy and small-size components across the entire interconnect hierarchy level can definitely not rely on a single technology platform. Objective: - Create the optimal synergies between different technologies streamlining their deployment towards Tb/s-scale, high-performance, low-cost and low-energy optical interconnect components and sub-systems - "Mix & Match" components / building blocks to deliver the optimal heterogeneous integration and to align their synergistic deployment towards the specific needs of individual functions Advanced packaging technologies will improve future systems: - Packaging determines functionality, cost and reliability of future systems. - System-in-Package is the way for future subsystems. - Future systems are very high complex systems and contain different physical functions. Therefore modularity in heterogeneous integration is required. - Future systems combine optical and ultra high frequency functions. They contain antennas, batteries, sensors, optical components, and microelectronic devices. With this a large variety of materials will be applied. For all these components a common smart support substrate such as 'Silicon' will be of importance for future systems.

CV of presenting author
Tolga Tekin received his Ph.D. degree from Electrical Engineering and Computer Science at TU Berlin in 2004. He was a Research Scientist with the Optical Signal Processing Department, Fraunhofer HHI, where he was engaged in advanced research on optical signal processing, 3R-regeneration, all-optical switching, clock recovery, and integrated optics. He was a Postdoctoral Researcher on components for O-CDMA and terabit routers with the University of California. He worked at Teles AG on phased-array antennas and components for skyDSL. At the Fraunhofer IZM, he led projects on optical interconnects and Si photonics packaging. He is Senior Scientific Assistant and Research Coordinator at the Research Center of Microperipheric Technologies, TUB, engaged in microsystems, photonic-integrated system-in-package, photonic interconnects, and 3-D heterogeneous integration research activities. He is Photonic & Plasmonic Systems Group Manager in System Integration & Interconnection Technologies Department, Fraunhofer IZM. Tolga Tekin is Senior Member of IEEE.

Recent Progress in 300mm Si-Photonics R&D and Manufacturing

Frederic Boeuf
Silicon Photonics, BiCMOS and Advanced Device Process Integration Manager
STMicroelectronics

Abstract
The maturity level reached in the integration of the key photonics devices into silicon substrate has generated an increased interest in developing a Silicon Photonics technology platform capable of fulfilling HPC and Data Center requirements. Already present in the optical communication market through the development of dedicated BiCMOS technologies, STMicroelectronics started the development and qualification of a 300 mm Silicon Photonics technology. We will describe the process integration and the key devices allowing to achieving efficient electro-optical transceivers. The advantage of 300mm process control over 200mm will be discussed. Performance of optical passive component, and especially grating coupler I/Os will be described. Integration and performance of 25Gb/s compatible High Speed Phase Modulator and Ge-based High-Speed Photodiode with Electronic chip using a 3D approach will be shown.

CV of presenting author
Frédéric Boeuf , born 1972, obtained his M.Eng. and M.Sc. degree from Institut National Polytechnique de Grenoble in 1996 and Ph.D. from the University Joseph Fourier of Grenoble (France) in 2000. Then he joined STMicroelectronics where he was successively responsible for the research phases of 65nm, 45nm, 32nm UTBB and 20nm FDSOI CMOS technologies. In 2012 he co-received the French "General Ferrie" Grand Prize Award for his work on FDSOI technology. He authored and co-authored over 150 technical papers. Since 2010 he is managing the Silicon Photonics, BiCMOS and Advanced Devices Technology group inside STMicroelectronics's Silicon Technology Development Group.

Low-Cost Access to Advanced Photonic Foundry Processes in InP

Michael Wale
Director Active Products Research
Oclaro Technology Ltd.

Abstract
Photonic integrated circuits (PICs) provide a highly efficient means of realizing complex optical and opto-electronic functions in monolithic form. PICs in indium phosphide (InP) can provide a particularly complete set of functions, including optical amplification, laser operation, modulation, signal routing, wavelength multiplexing and detection, in arbitrary combinations. Over the last decade, European researchers and manufacturers have established generic platforms for InP PICs, based on libraries of standard (parameterized) building blocks and standard manufacturing processes, defined by process design kits (PDKs) and supported by sophisticated design tools . In this way access to PIC technologies becomes much more straightforward and less expensive, as a single platform now serves the needs of many users and applications; furthermore the standard process and building blocks facilitate the execution of multi-project wafer runs, further reducing development and prototyping costs. This route was pioneered in the silicon microelectronics industry 30 years ago but in optics the concept is still very new. More than 100 application-specific PICs have been successfully designed and fabricated on the platforms supported by the Joint European Platform for InP-Based Photonic Integrated Circuits (JePPIX) and the underlying platforms are now emerging from the research phase into commercial operations. The paper will review the current status of generic PIC platforms in InP and give pointers towards future developments.

CV of presenting author
Prof. Michael Wale is Director Active Products Research at Oclaro, a major supplier of photonic components for the global optical communications market, based at Caswell, Northamptonshire, UK. Mike received his B.A., M.A. and D. Phil. degrees in physics from the University of Oxford. Since moving into industry in the early 1980s, he has been involved in many different aspects of research, development and manufacturing of photonic devices and systems, with particular emphasis on photonic integrated circuit technology. Alongside his role at Oclaro, where he has responsibility for strategic technology activities, he is Professor of Photonic Integration/Industrial Aspects at Eindhoven University of Technology, The Netherlands, and an Honorary Professor at the University of Nottingham in the UK. Prof. Wale is a member of the Executive Board of the European Technology Platform, Photonics21, and chairman of its Working Group on Design and Manufacturing of Optical Components and Systems.

Silicon photonics on 300mm platform

Delphine Marris-Morini
Assistant professor
Univ. Paris Sud

Abstract
Silicon-based photonics has generated a strong interest in recent years, mainly for optical telecommunications and optical interconnects in integrated circuits. The main rationales of silicon photonics are the reduction of photonic system costs and the increase of the number of functionalities on the same chip combining photonics and electronics. Silicon based-optoelectronic devices (source, modulator and photodetector) have been particularly studied as key building blocks for the development of silicon photonics. Their successful demonstrations proved the capability of silicon photonics to be used for high speed communication for different length range from chip to chip to long haul communications. From the stand-alone devices, today's important challenge is the integration of both photonic and electronic circuits (modulator with electrical driver, photodetector with TIA amplifier...). Before this ultimate integration, a crucial intermediate step is the fabrication of high-performance building blocks in large-scale microelectronic foundries. Silicon modulators and germanium photodetectors have recently been processed on 300 mm SOI wafers in microelectronics foundry. Such a platform allows mass production of silicon photonic circuits compatible with advances sub-65nm CMOS node, using state of the art 193nm photolithography with sub-50nm resolution as well as a good thickness uniformity. A 40Gbit/s optical link has thus been demonstrated by coupling a silicon (Si) optical modulator to a germanium (Ge) photo-detector from two separate photonic chips fabricated on 300 mm SOI wafers. These demonstrations paved the way of achieving further technological nodes, targeting high-performance and low power consumption of microelectronic chips.

CV of presenting author
Delphine Marris-Morini received her PhD in 2004 on optical modulation in silicon. She then became an assistant professor at the University of Paris Sud, pursuing her research at the Institute of Fundamental Electronics (IEF). Her activities are dedicated to silicon optoelectronics and cover modulators and photodetectors made of silicon and germanium. Delphine Marris-Morini participated to a numerous of French and European international projects focused on silicon photonics. She has published more than 60 papers in international journals. She contributed to several books on silicon photonics and is holder of 4 patents.