Graef Mart

Mart Graef
Strategic Programma Manager
TU Delft

Abstract
The International Technology Roadmap for Semiconductors (ITRS), is the fifteen-year assessment of the semiconductor industry's future technology requirements. These future needs drive present-day strategies for world-wide research and development at industrial research facilities, universities and institutes. The objective of the ITRS is to guide the semiconductor community to cost-effective advancements in the performance of integrated circuits and the products that employ such devices, thereby enabling the continued success of this industry and innovation in all sectors of the economy. Through the cooperative efforts of the global chip manufacturers, equipment suppliers, research communities and consortia, the ITRS teams identify critical challenges and encourage innovative solutions. In its 20+ years of existence, the ITRS has clearly demonstrated the benefits that roadmapping brings to the semiconductor industry: the alignment of the research ecosystem on its future needs, enabling an efficient use of R&D resources, resulting in the shortening of development cycles and decreased development costs. Recently, the ITRS has expanded its scope both in terms of technologies (beyond Moore's law, including the "More than Moore" trend) and in the coverage of the value chain (linking technologies and applications). While ITRS has essentially been a bottom up roadmap where products were designed by utilizing standard logic, graphics and memory components, it is evident that, in the present ecosystem, products are now driving the requirements of the semiconductor industry. In ITRS 2.0, which has been launched this year, the roadmapping methodology is based upon the combination of top down generated technology requirements with bottom up availability of new components amenable to new applications.

CV of presenting author
Mart Graef is strategic program manager at the Delft Institute of Microsystems and Nanoelectronics (DIMES) at the Technical University of Delft. He is involved in various technology partnerships, mostly within the framework of European cooperative projects. He is a member of the International Roadmap Committee, which guides the creation of the International Technology Roadmap for Semiconductors (ITRS). Mart Graef received a PhD in Solid State Chemistry from the University of Nijmegen, the Netherlands in 1980. Subsequently, he joined Philips Research, where he held various positions in Eindhoven (the Netherlands) and Sunnyvale (USA) as a scientist and manager in the field of semiconductor process technology. Later, he joined Philips Semiconductors and NXP as a strategic program manager. Assignments included the coordination of European cooperative projects, such as the Joint Logic Project, and chairing the Lithography Program Advisory Group at Sematech. He was a member of the Technology Steering Group of MEDEA+ and CATRENE (Eureka), and participated in the creation of the Strategic Research Agendas for ENIAC (European Nanoelectronics Initiative Advisory Council) and Point-One (Pole of Innovation in Advanced Technologies).

System Integration: More Moore

Mustafa Badaroglu
Sr Program Manager
Qualcomm Technologies

Abstract
CMOS scaling enabled simultaneous system throughput scaling by concurrent delay, power, and area shrinks with thanks to Moore's law. System scaling brought in requirements that require a holistic approach for the optimal balance of performance and power under the limits of technology. We will address requirements and gaps in the new ITRS2.0 roadmap to maximize benefit from More Moore scaling.

CV of presenting author
Mustafa Badaroglu is senior program manager at Qualcomm, Leuven, Belgium. In this role, he has the responsibility to assess/track feasibiliy and supply chain readiness of new technologies through consortia projects and supplier collaborations in the areas of logic and memory, interconnect, lithography, optical IO, and 3D integration. Prior to joining Qualcomm, he was principle scientist at imec, Leuven, Belgium, working on targeting on More Moore technology requirements for design. Before imec he was design manager with ON Semiconductor in the automotive and power product development division, leading chip product development activities to hand over to high volume production. Dr. Badaroglu received the B.Sc. degree from Bilkent University, the M.Sc. degree from the Middle East Technical University, the Ph.D. degree from the Katholieke Universiteit Leuven (KU Leuven), all in electrical engineering, and the M.Sc. degree in Industrial Management from KU Leuven. He is the chair of the Process Integration, Devices, and Structures (PIDS) chapter of the International Technology Roadmap of Semiconductors (ITRS).

Outside system connectivity

Patrick Cogez
Director, Innovation and External Research
STMicroelectronics

Abstract
Connectivity is nowadays a main driver of the semiconductor industry, on a par with data processing and storage requirements, and the much-publicized "Internet of Everything" wave will reinforce that trend. This calls for technology that provides cost effective energy efficient connectivity whatever the environment. Within the so-called "ITRS 2.0" structure, the Outside System Connectivity (OSC) Team was established in order to identify the capabilities required to support these connectivity needs over a fifteen years horizon, and work with ITRS technology competence centers to translate these future communication capabilities into components and technologies roadmaps. The talk will present the initial technologies being included in the scope of the OSC Focus Team, the roadmapping process envisioned by the team, and the stakeholders it would like to engage with.

CV of presenting author
Patrick COGEZ graduated from Ecole Polytechnique and from Ecole Nationale des Ponts et Chaussées. He also holds a MSc. Degree in Operations Research and a PhD in Industrial Engineering, both from University of California, Berkeley. After starting his career as a civil servant in the French Ministry of Industry, he joined STMicroelectronics, where he held various management positions in Information Systems, Knowledge Management, and Central R&D Program Direction. Since 2005, he is in charge of innovation and external research for Crolles site, within STMicroelectronics Embedded Processing Solutions Sector. Patrick COGEZ is STMicroelectronics representative within the steering committee of the International Technology Roadmap for Semiconductors, and Chair of the European Nanoelectronics Infrastructure for Innovation (ENI²).