Mart Graef
Strategic Programme Manager
TU Delft

Biography
Mart Graef is strategic program manager at the faculty of Electrical Engineering, Mathematics and Computer Science at Delft University of Technology (TU Delft) in The Netherlands. In this position, he develops technology partnerships with companies, institutes and universities, often within the framework of national and European cooperative projects. He participates in various initiatives aimed at defining strategies and technology roadmaps for electronic components and systems. He is a member of the International Roadmap Committee, which guides the International Roadmap for Devices and Components (IRDS). He is the chair of the AENEAS Scientific Council and participates in the AENEAS Management Committee. Mart Graef received a PhD in Solid State Chemistry from the University of Nijmegen, the Netherlands, in 1980. Subsequently, he joined Philips Research, where he held various positions in Eindhoven (the Netherlands) and Sunnyvale (USA) as a scientist and manager in the field of semiconductor process technology. He was strategic program manager at Philips Semiconductors and NXP until 2009, when he joined TU Delft, also as strategic program manager.

DSA: Progress Toward Manufacturing Readiness

Raluca Tiron
senior researcher
CEA-Leti

Abstract
Density multiplication of patterned templates by directed self-assembly (DSA) of block copolymers (BCP) stands out as a promising alternative to overcome the limitation of conventional lithography. Using the 300mm pilot line available in LETI and Arkema’s materials, the main objective is to integrate DSA directly into the conventional CMOS lithography process in order to achieve high resolution and pattern density multiplication, at a low cost. In this paper the recent achievements in LETI will be discussed. Thus we investigate the potential of DSA to address both contact and via level as well as line and space patterning, by using the graphoepitaxy of block copolymers. These results show that DSA has a high potential to be integrated directly into the conventional CMOS lithography process.

Biografie
Dr. Raluca Tiron, received her PhD degree in molecular magnetism from University Joseph Fourier France in 2004. In 2005 she integrates Resist Expertise Center at CEA-LETI, working on advanced lithography, process development, resist characterization and mechanisms comprehension in 193 nm lithography. Starting with 2008, her research interest focuses on directed self-assembly (DSA) of block copolymers and she is currently leading this activity at CEA-LETI. She has been CEA-Leti project leader in several national and European projects and she is in charge of industrial collaborations around the DSA. She has authored and coauthored more than 80 papers in international reviews and more than 15 patents.

Lithography Material Readiness for HVM EUV Technology

Danilo De Simone
PMTS
IMEC

Abstract
In the last years the continuous efforts on the development of extreme ultraviolet (EUV) lithography has allowed to push the performance of EUV photoresists on the ASML NXE:3300 full field exposure tool. Today N5 logic technology node is considered to be the first scaling node at which industry will likely insert EUV into production which will bring a reduction in total cost of ownership. For this purpose, imec test vehicles have been developed to evaluate EUV patterning performance with N5 design rules. In this landscape EUV materials are key enablers of EUV technology and these test vehicles are used to debug the patterning capability of such materials aiming to find robust solutions that offer the best performance in terms of sensitivity, resolution, roughness and defectivity. Furthermore, it is imec’s objective to bring novel valuable material concepts, that are at an early development stage, to a higher level of maturity and propose them as alternative materials for nano scaling through an incubator path model named at imec “Lab-to-Fab”. In such a context today both chemically amplified (CA) and metal-oxide (MO) EUV resists are part of the patterning strategy for the critical N5 BEOL layers. However, HVM requirement to have a cost-effective low exposure dose photoresist (<20mJ/cm2) still remains a big challenge. In this work the state-of-the-art of EUV patterning materials are discussed in multiple aspects: i) the patterning challenges for critical features as 16nm dense line space patterning and 18nm dense contact hole and pillar patterning, ii) the integration of EUV resists in novel process schemes, as the tone reversal process, iii) the impact on patterning performance of substrates underneath the photoresist, iv) the challenges of EUV metal-oxide resist to move to HVM environment. Finally the latest patterning developments for N3 technology node are introduced.

Biografie
Danilo De Simone holds a MS degree in Chemistry from University of Palermo (Italy) and he has 17 years of experience in semiconductor R&D in the field of nanolithography. For seven years he leaded the development of lithographic materials for 90nm and 65nm NOR flash devices for STMicroelectronics (STM) in Italy and covered the role of assignee at STM Alliance in France and STM in Singapore working on multiple R&D and production projects. In 2008 he moved to Numonyx leading the R&D on lithographic materials and taking the co-ownership to develop 32nm double patterning modules for Phase Change Memory (PCM) devices. In 2011 he moved to Micron Technology working as principal engineer to introduce 45nm PCM devices in HVM and to develop lithographic solutions for novel devices. In 2013, he joined the international nanoelectronics research center IMEC in Belgium as principal member of technical staff leading the research on photo materials for EUV lithography.

Applications for Mapper technology

Bert Jan Kampherbeek
Co-founder & CEO
Mapper Lithography

Abstract
Introducing a fast direct writing machine to the semiconductor industry opens up a wide range of new applications. In this presentation several examples will be provided such as a) making each chip truly unique in the hardware which can be used in iot security, but also b) extension of resolution for 200 mm fabs which can be used for the manufacturing of 5G devices. In addition the technical status of the machine development will be presented.

Biografie
Bert Jan Kampherbeek (CEO and co-founder) is one of the three founders of Mapper. He is responsible for the market development and positioning of Mapper in the industry. Bert Jan holds a Master's degree in Applied Physics from Delft University of Technology.

Laser Direct Imaging (LDI) for Advanced Packaging

Michael Toepper
Business Development Manager
Fraunhofer IZM

Abstract
Embedding die technology is one of the hottest topics in the area of Advanced Packaging. It migrated over the last decade to two types: Embedding into PWB (embedded die) and reconfigured molded wafer. FO-WLP (Fan-Out Wafer Level Packaging) has been proven as one of the most versatile packaging technologies in the last years. The technology is combining high performance, increased functionality with a high potential for heterogeneous integration and reduce the total form factor. Main advantages of FO-WLP are the substrate-less package, lower thermal resistance and higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or bumps. Especially the inductance of the FO-WLP is much lower compared to FC-BGA packages. In addition it can be used for multi-chip packages for SiP. Lithography is a key aspect for this technology because the lines and space requirements are reaching the area of thin film processing. Cost reduction has been achieved by moving to 330 mm-Technology and the move to panel level processing will push the technology further to lower cost. This can be viewed as a merge between the Embedded Die technology based on PWB infrastructure and the FO-WLP on Wafer Level. In this presentation the high potential of LDI (Laser Direct Imaging) will be discussed for the applications in FO-WLP with a focus on Panel Level Packaging.

Biografie
Michael Töpper has a M.S. degree in Chemistry and a PhD in Material Science. Since 1994 he is with the Packaging Research Team at TU Berlin and Fraunhofer IZM. In 1997 he became head of a research group. In 2006 he was also a Research Associate Professor of Electrical and Computer Engineering at the University of Utah, Salt Lake City. The focus of his work was Wafer Level Packaging applications with a focus on materials. Since 2015 he is part of the business development team at Fraunhofer IZM. Michael Töpper is Senior Member of IEEE-CPMT and has received the European Semi-Award in 2007 for WLP. He has published several book chapters and is author and co-author of over 250 publications.

Metrology in the context of holistic lithography

Jeroen Ottens
Product System Engineer
ASML

Abstract
As the requirements for Overlay, Focus und CD uniformity continue to tighten we present the approach by ASML to address those requirements by actively implementing the holistic lithography approach. This approach is based on three key pillars, which are the lithographic scanner itself with a large number of adjustable parameters, the ability to model and predict the scanner performance under different conditions and the availability of accurate and precise metrology for the parameters of interest. In this presentation we show examples of how the combination of these capabilities leads to solutions to advanced process challenges.

Biografie
Master Mechanical Engineer, graduated in 1997 Work history 1997-1998: Mechanical analist for VIRO Engineering 1998-1990: Senior Designer at The LEGO Group 2000-2005: Mechanical analist at ASML 2005-2007: Overlay system engineer at ASML 2007-2010: Waferstage system engineer at ASML 2010-2017: Product system engineer at ASML (of which the last 2 years for Yieldstar)

Misalignment detection through Support Vector Machine algorithm implementation

Daniele Vinciguerra
APC Manager
ST Microelectronics

Abstract
In the last decade, most semiconductor Fabs have implemented FDC in order to reach the benefits of better process monitor and yield improvement. In this work, we show how we applied Machine Learning algorithms in order to make the most of data already collected by FDC architecture, to extract insights and make predictive control. We applied Support Vector Machine algorithm in order to predict the litho misalignment of wafers based on the raw data that the lithography equipments return as values. The methodology was extended to all masks but the real problem that we wanted to solve was specifically related to mask levels after EPI growth. In fact the EPI growth can change the AGA, signs that the equipment uses to align the wafer to previous mask, so that they seems to be shifted. Therefore, the equipment aligns wrongly but it “thinks” to have done a good job. This problem is very hard to detect by usual FDC analysis. We developed and optimized an SVM algorithm to detect anomalies in collected data. Many experiments were performed on off-line data and on real production to verify the stability of the system and to understand the levels of precision and recall. We started testing a supervised approach. We collected more than 40K wafers and classified them GOOD or BAD based on electrical data results. Then we trained the algorithm on a six dimension space. Successively we optimized the SVM parameters in order to obtain the best results on validation set. Results indicated a 100% accuracy. Then we shifted the approach to an unsupervised algorithm, the one class SVM. In this case, we trained the algorithm with only good wafers and removed the bad wafers. The algorithm was transformed into an anomaly detection algorithm. Results We tested again the new algorithm with the previous offline data and put it in production with real data. Further parameters optimizations let us reach a True Fail/Predicted Pass ratio of zero and a True Pass/ Predicted Fail ratio of 0.05%.

Biografie
Daniele Vinciguerra received the Master degree in Nuclear Physics from University of Catania, Italy, in 1996. He is working for ST Microelectronics as APC/SPC Manager in Catania site. His current research interest is big data and machine learning for semiconductor manufacturing