Andy Longford
Consultant
PandA Europe

Biography
Andy Longford C.Eng FIET Andy is Managing Partner (CEO) and Senior Consultant at PandA Europe, a technical & market Consultancy Company involved in Semiconductor chip Packaging and Electronics Interconnection. He has worked on chip package designs for a number of years and is currently involved with emerging chip package design analysis and technical support work. He is a member of a number of technical committees, including SEMI Europe (APC) and ESPAT (a SEMI SIG) PandA also provides Secretariat Services for IMAPS-UK. For further information contact: Andy Longford PandA Europe 1 Beach Street Dawlish Devon EX7 9PN UK Tel: + 44 1626 862669 Mob: +44 7710 209640 Email: andy@pandaeurope.com

Advanced Packaging: A very dynamic ecosystem!

Andrej Ivankovic
Technology and Market Analyst
Yole Developpement

Abstract
To be announced

Biografie
Andrej Ivankovic is a Technology & Market Analyst, in the Advanced Packaging and Semiconductor Manufacturing team, at Yole Développement the "More than Moore" market research and strategy consulting company. He holds a master’s degree in Electrical Engineering, with specialization in Industrial Electronics from the University of Zagreb, Croatia and a PhD in Mechanical Engineering from KU Leuven, Belgium. He started as an intern at ON Semiconductor performing reliability tests, failure analysis and characterization of power electronics and packages. The following 4 years he worked as a R&D engineer at IMEC Belgium on the development of 3D IC technology, focusing on electrical and thermo-mechanical issues of 3D stacking and packaging. Part of this time he also worked at GLOBALFOUNDRIES as an external researcher. He has regularly presented at international conferences authoring and co-authoring 18 papers and 1 patent.

Sensors and electronics for electric vehicles: recent trends and upcoming developments

Andreas Middendorf
scientist business development
Fraunhofer IZM

Abstract
Achievements in technology of sensors and electronics are the main drivers for the amazing innovations in the automobile industry in the past two decades. Safety, efficiency and comfort attributes are today realized in almost all vehicle classes. The ongoing miniaturization and integration processes enable the scale effects and cost reduction potentials. Electric vehicles and the therefore needed infrastructure demand further efforts, especially if transportation systems are combined with the smart energy grid or autonomous driving performance is realized. For this scenarios further, sometimes new electronics, sensors and actuators have to be integrated in the vehicle and one challenge is the safeguard of reliability with simulation, qualification and test. Reasons are totally different use cases and mission profiles and the need to bring the latest technology to the market. The presentation outline mainly the hardware aspects like packaging or sensor fusion.

Biografie
Andreas Middendorf Dr.-Ing. Electrical Engineering Andreas Middendorf works in the Business Development Team of the Fraunhofer Institute for Reliability and Microintegration (IZM). He was working as a scientist in the department Environmental and Reliability Engineering of the Fraunhofer Institute for Reliability and Microintegration (IZM) and of the Technical University Berlin since May 1995. He was responsible for the development and implementation of methods and demonstrators for the estimation of lifetime for electronic appliances. Further on he is investigating technological aspects which combine the electronics design with environmental engineering techniques. This includes environmental assessments through LCA and through other methods, especially for Eco-Design, the evaluation of recycling attributes, the development of databases and software as well as environmental oriented product evaluation. He carried out courses on EcoDesign for electronic companies, holds four patents and has coordinated several cooperative research projects in Germany and Europe. Since 2010 until 2015 he was senior manager for the application field automotive and transportation systems and in charge for the System Reliability and Measurement Group at IZM. He studied electrical engineering at the Technical Universities of Aachen and Wuppertal where he specialized on information and communication technologies.

eWLB (FO-WLP) as an Innovative Integration Solution of SiP

Seung Wook Yoon
Director
STATS ChipPAC Pte Ltd

Abstract
New and emerging applications in the consumer and mobile space, the growing impact of the Internet of Things (IoT) and wearable electronics (WE), and the complexities in sustaining Moore's Law have been driving many new trends and innovations in advanced packaging technology. Advanced embedded Wafer Level Ball Grid Array (eWLB) technology provides a versatile platform for the semiconductor industry’s technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. This presentation reports developments that advanced eWLB/FO-WLP technology, including integration of multi-die, discretes, embedded passives and crystals. This will also discuss the adoptions and new features available for mobile, IoT and WE. This advanced technology is well designed for MEMS/sensors SiP modules as well as thin, highly integrated packaging. Innovative 2.5D/3D packaging features will be also introduced with the merits and characterization data for specific applications. To enable higher interconnection density and signal routing, packages with multi layer redistribution (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. This presentation will describe the new manufacturing module approach and the results of process characterization for products produced in the module. Also there will be discussion of large panel level fan-out WLP including current development status and technical challenges ahead.

Biografie
Name: Seung Wook Yoon, Ph.D, MBA Title/ Position: Director Company: STATS ChipPAC Pte Ltd. Dr. YOON is currently working as director of Advanced Products & Technology Marketing , STATS ChipPAC Pte. Ltd in Singapore. His major interests are for wafer level products including eWLB/Fanout WLP, WLCSP, IPD, bumping, TSV (Through Silicon Via) technology, flipchip and integrated 3D IC packaging. Prior to joining STATS CHIPPAC LTD, He was deputy lab director of IME (Institute of Microelectronics), A*STAR (Agency of Singapore Technology and Research), Singapore. ”YOON” received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 250 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging.

Packaging of Image Sensors and Devices

Lutz Mattheier
Manager Assembly Technology Development
First Sensor Packaging GmbH

Abstract
In the past Imaging Sensors and Devices have been mostly assembled in ceramic single packages or ceramic substrates. So mainly the requirements for cleanliness and temperature management could be fulfilled by single devices. Meanwhile Imaging Sensors and Devices are more and more seen as part of a whole Printed Circuit Boards (PCB) Assembly and will be implemented as part of an active circuitry on a PCB. The packaging process flow has to be designed in a way to guaranty electrical function and module reliability. Can this be done in compliance with the requirements of the Automotive customers? Usage in harsh environments, high robustness and reliability, long lifetime combined with zero defect yield targets. Could this be achieved by use of the COB Technology? First Sensor AG will support their customer base on this difficult way. Mobility and information Technology mainly drive the market into higher reliability requirements, smaller packaging and lower cost. But Chip-Size-Packages and Wafer-Level-Packaging stand for high number of devices to cover high equipment, setup and tooling costs. First Sensor Packaging GmbH Dresden did search for partners and new technologies to make such solutions available for Prototyping and affordable for small customers and their small demand of devices. Here we talk about combination of classic Chip On Board (COB) Technology with new methods: - Assembly of large Imager-Die’s (up to 200mm by 150mm) - Assembly of Matrix Devices (e.g. 4 x 4 die matrix, 32mm by 32mm) - Assembly of Die’s developed in Through Silicon Via (TSV) Technology - Customized design and molding - Adapting of such solutions to the needs of the Automotive industry Outlook: - Special and new methods of PCB creation (2.5D Technology) - Modified materials and methods to create glass cover for optical Sensors and Devices.

Biografie
Lutz Mattheier, Manager Assembly Technology Development, First Sensor Microelectronic Packaging GmbH Lutz Mattheier begann im Juli 2007 als Manager Process Technology bei der Microelectronic Packaging Dresden GmbH und ist seit 2017 für die Technologie- und AVT-Prozessentwicklung verantwortlich. Seit 1994 arbeitete er 3 Jahre für Siemens Regensburg in der Die und Wire Bonding Entwicklung, 3 Jahre als Assembly Engineering Manager bei White Oak Semiconductor in Richmond Virginia, 2 Jahre für ESEC Schweiz als Director Process Technology Wire Bonding, 1 Jahr für Kulicke&Soffa Deutschland als Manager Center of Excellence und 4 Jahre als Head Process Technology bei der Swissbit Germany AG Berlin. Zuvor arbeitete er für 8 Jahre im Zentrum Mikroelektronik Dresden in der Entwicklung der Thermosonic und Ultrasonic Drahtbondtechnologie. Lutz Mattheier erhielt sein Diplom der Elektronik Technologie 1986 an der Technischen Universität Dresden.

Silicon Wafer Integrated Fan-out Technology (SWIFT®)

David Clark
Sr Director marketing, business development
AMKOR TECHNOLOGY EUROSERVICES

Abstract
This paper reviews Silicon Wafer Integrated Fan-out Technology (SWIFT®) packaging methodology and its performance in a typical mobile application. In addition, the advantages of a SWIFT® design are reviewed in comparison to a conventional competing 3D packaging technology. Package information, electrical simulation, and reliability test data will be presented to show how SWIFT® technology is poised to provide robust, reliable, and low-cost 3D packaging solutions for advanced mobile products.

Biografie
David Clark currently holds position of Senior Director - Advanced Products Business Unit at Amkor Technology Europe. In this role, David is responsible for strategic business development and marketing of advanced package and test technology for Amkor. Prior to that he has held various roles in sales and business development at FlipChip International, research posts at University of Cambridge, application, product development and process engineering at Vistec Lithography and Agilent Technologies. David has an Honors Degree from University of Glasgow in Electronic, Electrical and Optoelectronic Engineering.

Graham Jones
CEO
CMT Semiconductor Services

Biography
European General Manager for Ablestik Laboratories from 1989 to 2009 when the business was acquired by Henkel. Thereafter until his retirement in 2013, Graham was Sales Director for the Henkel Electronic Adhesive business in Europe, Middle East and Africa. Currently he works for CMT Corporation, headquartered in Korea and acts as an advisor for several Asian Equipment supplies, his main focus being on pressure ovens from APT in Taiwan specifically designed for curing polymers without voids.

Requirement to Automotive Packaging Technologies

Michael Guyenot
Manager
Robert Bosch GmbH

Abstract
Until till now, there is the trend of more consumer packages in automotive applications. The main motivation is the reduction of the cost and integration of new functions, e.g. entertainment or car to car communication. Consumer packages are optimized for miniaturization, high volume production and low cost. On the other side the reliability of consumer packages is often not specified and tested for automotive requirements. Cars are long life products with a durability of more than 15 years or 300.000 km or 6.000 hours of operation. With the change to electro mobility there are more permanent working units with up to 100.000 hours of operation in the car, e.g. charger, battery management. The improvement of these higher request and necessary reliability tests are the issue for consumer packages in automotive applications. Especially the need of front load development and simulation capability for higher product quality, e.g. autonomic driving, have to be solved for the consumer packages.

Biografie
Dr. Michael Guyenot studied Technical Physics and Economy at University of Bayreuth, Germany. He holds a PhD degree as engineer in materials science from the University of Bremen, Germany. Michael started 2002 at Robert Bosch GmbH in the business unit “Automotive Electronic” as a Senior Expert for reliability testing of automotive electronics. Since 2007 he works as Senior Manager in Corporate Research of Bosch and is leading a research group for electronic packaging and interconnection technology. Michael is involved as specialist for automotive and power electronics in public funding projects.

Conductive Die Attach Adhesives – Effect of Aging at 200C and correlation with Chemical Base

Tony Winster
Technical Advisor
Henkel Ltd

Abstract
The choice of die attach adhesive used within a molded package can have an effect on the package reliability and lifetime. Latest generation automotive electronic components tend to have higher power dissipation than previously, and also are frequently located in harsher environments, leading to significantly increased operating temperatures – in some cases up to 200C. Therefore the selection of all materials becomes more critical. This work reports the results from an on-going study of a range of electrically conductive die attach materials, based on different chemistries (Epoxy, BMI, Polyimide and Silicone) applied in paste and film formats. Chips with bare silicon and silver metaillised backsides are included in the evaluation, as are leadframes with bare Cu, silver plating and PPF plating. The aim is to allow selection of the most appropriate chemistry for existing applications, and to guide product development for future requirements.

Biografie
Tony Winster is an Application Engineer supporting Henkels Semiconductor packaging products in Europe. He studied Metallurgy & Materials Science, before working on materials & packaging methods for high reliability circuits. He joined Ablestik in 1989, and has continued his technical support role with Henkel since 2008.

Conformal/ Selective Coating Materials for enhanced performance in Automotive Electronics Applications

Karen Wilken
Application Development Engineer – Electronics
Momentive Performance Materials GmbH

Abstract
Recent trends in the electronics industry, call for higher functionality, miniaturization. and improved reliability performance of printed circuit boards. Conformal coating materials are already widely used in such applications. Compared to organic polymers, silicone conformal coating materials have insulation, heat resistance, & cold temperature resistance advantages, & due to their softer properties, excel in their ability to absorb stress.Performance requirements for conformal coatings include: 1.Durability: The ability to provide long-term dielectric stability under high temp & high humidity 2.Adhesion: Good adhesion to PCB & component surfaces 3.Corrosion Prevention: Protection against corrosion 4.Flexibility: Elasticity of the coating layer to absorb stress 5.Chemical Resistance: Resistance to solvents & oil 6.Fast Cure: Fast cure @ low temp 7.Processability: Ease of application 8.Toxicity: Minimize harmful effects on operators and the environment. 9.Optical Clarity: Transparency or translucence Organic conformal coating materials such as acrylics, polyurethane and epoxy are known to have inherent disadvantages associated with temperature resistance, cure shrinkage and toxicity.Silicone conformal coating materials consist of silicone resin that typically is solvent borne, or silicone rubber that is formulated without solvents and cures by either heat (addition) cure or room temperature (moisture) cure. Based on the performance requirements of conformal coating materials, as long as cure time can be shortened, room temperature cure silicone rubber materials are considered good candidates due to their ease of use and ability to eliminate curing equipment from manufacturing processes. Our latest materials with enhanced reliability performance are highlighted below:Momentive’s ECC3011 and ECC3051S silicone conformal coating materials employ a unique formulation that can help prevent the occurrence of corrosion on vital PCB components and surfaces.

Biografie
05/2017- present: Application Development Engineer - Electronics @ Momentive Performance Materials GmbH 06/2016–12/2016 Research Associate at Forschungszentrum Jülich GmbH, Institute of Energy and Climate Research 5–Photovoltaics 06/2013–05/2016 Ph.D. Student at Forschungszentrum Jülich GmbH, Institute of Energy and Climate Research 5–Photovoltaics: “Low Temperature Thin-Film Silicon Solar Cells on Flexible Plastic Substrates” (submitted: 11th October 2016) 06/2013–12/2016 HITEC Graduate School for Energy and Climate 10/2007–05/2013 Darmstadt University of Technology Field of study: Material Science Grade: Very Good 11/2012–05/2013 Diploma Thesis at Forschungszentrum Jülich GmbH, Institute of Energy and Climate Research 5–Photovoltaics: “Tandem Cells providing high Open Circuit Voltages for photoelectrochemical Water Splitting” 08/2011–10/2011 Internship at BASF SE in Ludwigshafen: “Simulation and Degradation of Organic Light Emitting Diodes (OLED)” 01/2011–02/2011 Practical Specialisation in the Department of Electronic Materials: “Investigation of Trap States in Organic Semiconductors”

Innovative Package Solutions for Automotive Application

Tom Tang
Engineer
Siliconware precision Industries Co., Ltd.

Abstract
Recently,the electronics industry is moving maturely on the mobile/tablet market.With the aggressive demand on self-drivng car,the next fast growing market will be Automotive in the near future.Advance technology/packages are needed to provide ideal solutions for reliablitly and high electrical performance.Multi-function integration is also one of the critical requirements.To approach these requirements,innovative packages including System in Package (SiP),2.5D IC and advance Flip Chip are the potential solutions. SiP is a combination of one or more semiconductor devices plus optional passive components that form a certain functional block within a package.In this paper, an alternative 3D SiP technology will use surface mount technology (SMT) and 3D structure of stacking die on passives to shrink the package size and enhance the package reliability.The package size can be shrunk around 25% from 11.5 x 11.5mm2 to 10x10mm2 package size.SiP also could offer different function blocks for high electrical and integration performance into Automotive Telematics including GPS /connectivity system.Considering the cost,reliability and time-to-market,such as wireless connectivity module in car,will become the major driving force for SiP platforms in near marketing. 2.5D IC and advance Flip Chip are the solutions to meet the increasing preformance requirements for the infotainment and ADAS applications in car.2.5D IC is a platform for mono- or multi-functional integration. CPU,GPU,DRAM and main-broad might be all shrunken into one chip package.2.5D IC is a solution of high bandwidth, small form factor and multi-function integration. In this paper, a 2.5D IC device was demostrated for the potential autonomous car application.

Biografie
Another FCBGA device with Heat-sink also was developed,it not only provides the high computing performance but also passed the Automotive related qualification and is under production. Finally,this paper will sum up the progress of advanced packages-SiP module,2.5D IC and advance Flip Chip for the Automotive application. Name, Tom Tang Job Title,Senior Engineer Dept., Engineering Center Company, SPIL

Ultra-Low Warpage Liquid Compression Molding (LCM) Development for Advanced Wafer Level Packaging

Jay Chao
Sr. Scientist
Henkel Electronic Materials LLC

Abstract
As the size of electronic devices is getting thinner and smaller, the requirements for semiconductor and automotive packaging materials become more and more challenging. Especially in Wafer Level Packaging (WLP), there’s a strong need for advanced liquid compression molding (LCM) materials with improved warpage control and finer filler in order to meet the more sensitive process requirements. Regardless the package design variation, Fan-Out or Fan-In type, the warpage issue is driven by the reduced (thinner) package dimensions and the nature of CTE mismatch between thermoset encapsulant and silicon wafer. On top of this, tighter environmental requirements driven by REACH are asking for replacement of anhydride based resins being commonly used in LCM materials today. Recently, Henkel developed a new type of anhydride free LCM material with lower cure shrinkage and finer filler that demonstrates much improved (ultra-low) warpage control after molding of Fan-Out type of wafer level packages. Furthermore, the low warpage level is maintained after several process steps and thermal aging. The low warpage and less cure shrinkage allows polymer molecules to have less stress during reliability tests. Compared to traditional anhydride-based LCM, our reliability data (after 500 cycles of uHAST & AATC) already demonstrates advantage of no filler-fall-off, no delamination, better chemical resistance, etc. For workability, the new system has improved work-life, fast-cure at 110-130 Celsius, good gap filling, etc. Taking advantage of the proprietary resin and formulation design, Henkel’s new LCM materials are currently widely evaluated with positive results in new FO-WLP designs and WLCSP applications asking for 5-side or 6-side protection.

Biografie
Jay Chao, earned Ph. D in Materials Chemistry at the University of Michigan. He started as project supervisor in 2003 with National Starch (later, part of Henkel Electronics, based at Bridgewater, New Jersey, USA). He then became scientist and senior scientist with the company, having in-depth experience in many electronic adhesive areas, such as electronic die-attach, barrier and sintering materials, advanced packaging materials. He is currently product development senior scientist at Henkel Electronics, Irvine, CA.

Peter Cockburn
Senior Product Manager - TCI
Xcerra Corporation

Biography
Peter Cockburn has worked in the ATE industry for over 27 years at Schlumberger, NPTest, Credence, LTX-Credence and now Xcerra. After developing real-time and GUI software for ATE systems, he moved into product marketing and managed the launch of several SOC ATE systems and new analog test options as well as providing marketing and sales support in USA, Asia and Europe. As Senior Product Manager of the Test Cell Innovation team, he is responsible for defining and delivering complete test cells to customers that reduce cost, increase uptime and improve quality when testing semiconductors. He has an Engineering degree from the University of Southampton, UK.

Wafer & Final Test in the new era of electronics

Martin Sallenhag
CEO
RoodMicrotec GmbH

Abstract
The shift in automotive, industrial and healthcare markets towards a higher content of electronics puts a new set of demands on wafer and final test solutions. Moving into more complex and miniaturized solutions makes the implementation of test solutions much more important including being part of the design phase from the beginning. We at RoodMicrotec see new demands from the market to do multiple temperature and voltage tests both at wafer level as well as on packaged parts. This requires additional equipment to be able to do it in conjunction with partnerships with both the design houses as well as the packaging houses. This to find the optimal solution for all different applications. The evaluation of test data, from PCM to final test, is also a challenge for the test houses. Installation of tools such as YieldMann helps getting the data in a format that enables us to cooperate with the wafer fab to get the optimal yield for a specific product. It is also very important to have a well-defined name structure for all the data that is generated to be able to quickly analyze and take measures to improve the yield. Being part of the complete supply chain, as RoodMicrotec is with its Turnkey solutions, improves the possibilities to ramp a product to high volume production in a short time with good yield from the beginning.

Biografie
Martin Sallenhag, CEO and Managing Director RoodMicrotec N.V. Martin Sallenhag joined RoodMicrotec in March 2015 as CTO and was appointed CEO and Managing Director in June 2016. He is responsible for the overall management of the company together with COO Reinhard Pusch and specifically managing the engineering departments, quality, human resources, purchasing and IT. He has over 25 years of experience in the semiconductor business in various management positions within Samsung Electronics, Dialog Semiconductor and Ericsson. He holds a Master of Science degree in Electrical Engineering from Lund University with focus on Mixed Signal ASIC design.

Probers with Physical Stimulus – introduction to technology and benefits on WLP MEMS sensor final test.

Ari Kuukkala
Sales Director
Afore

Abstract
Two wafer probers with physical stimulus are presented. The other one is for environmental sensor having stimuli for pressure, temperature, humidity or other gases. Another is meant for final testing of motion sensors: accelerometers, gyroscopes and magnetometers. The handling of miniature size, light weighted, sensors is getting more complicated. Many of the P&P systems are limited to package size of 2x2 mm. New wafer level packaging technologies enable much smaller form factors, sensors smaller than 1x1 mm. Using probers, DUTs are well organized on adhesive tape and the handling is smooth during the whole process. The presentation shows how the Cost of Test can be brought down by using probers with physical stimulus in MEMS final testing. The sensors can be fed directly from wafer dicing to the prober. The wafer ring with adhesive tape works as a carrier through the whole process. By this new handling method it is possible to shorten tremendously the manufacturing process and decrease the investment costs. The other benefit of a prober with physical stimulus is much higher capacity compared to traditional test systems, such as Pick & Place based test systems. Thousands of sensors can be fed simultaneously to the prober and the time is mainly used for testing, not for loading and unloading like with P&P systems. Due to constant MEMS sensor price dilution the industry is facing a huge cost pressure. In addition, there is a high demand for smaller, miniature size, sensors. New wafer level packaging technologies are responding to both of these challenges. However, the package type itself doesn’t reduce the cost of test (COT), which is one of the biggest manufacturing costs of MEMS sensors. A real case calculation concerning testing of 3-axis accelerometer shows how the final testing with a prober with physical stimulus leads to lowest cost in the market.

Biografie
Mr. Kuukkala has degree in Mechanical Engineering and is working on degree in Electrical Engineering. In addition he has studies in economics. He has worked for Afore over 10 years in different positions; as a mechanical designer, service engineer and R&D manager. Currently he is working in business development and sales still being highly involved to new product development.

Wafer probing challenges and solutions

Joe Mai
Managing Director
JEM Europe

Abstract
Semiconductor packaging has always been inherently linked to wafer probing. On the one hand, package features influence, or even define, pad and bump features (sizes, locations, dimensions, and materials). On the other hand, wafer probing methods and probe card limitations (probe geometries, pitch, etc.) also constrain package development. In addition, the contact between probes and pads/bumps inevitably damages the latter, which can affect bond reliabilty and require complex and costly reliabilty studies. This presentation will first describe some of the links between packaging and wafer probing, and the related challenges, including those of testing at high/low temperatures and at high/low power. Then, we will present the latest probe card technologies and probing methods to address these challenges.

Biografie
Joe Mai is managing director of JEM Europe (located in France), a subsidiary of Japan Electronic Materials, which is a top-4 probe-card supplier. He has been with JEM for over 20 years, playing both technical and business-development roles in the US, Europe and Asia. Throughout his career, he has enjoyed working closely with customers to improve their test capabilities. So please feel free to approach him to discuss any problems or challenges you might have - or if you want to play basketball. :)

Test Floor Automation – is it finally due, after years of talking?

Andreas Bursian
Director InStrip & InMEMS Products
Xcerra

Abstract
While semiconductor front end automation took place years ago, the back end test floor material handling is still barely automated. The semiconductor back end has had to deal with a variety of different package types and form factors, resulting in different transport media, such as bulk, tube, metal magazine, tray and reel. Even though SEMI has started to standardize this media, there are still many different form factors to consider. This has made it impossible to come up with a global material loading and unloading standard for all equipment. To offset this lack of automation, and still achieve their cost targets, semiconductor manufacturers moved backend test operations into countries with low labor costs. After decades of just talking about backend automation, there are now signs on the horizon that the industry is getting serious about automating the backend test floor. This presentation will analyze what mechanisms are driving this trend to automation and what conditions changed to generate the current momentum. It will further show how the suppliers and some test floor managers are preparing for this process enhancement.

Biografie
Dipl. Ing. Andreas Bursian is Director InStrip & InMEMS Products at Multitest the Handler Group of Xcerra. He got his degree at the University of Applied Sciences and Arts of Dortmund in Electrical Engineering. After University he spent 10 years in SPICE based simulation and characterization of semiconductor devices as well as in electromagnetic field simulation. In 1997 he joined Multitest working as a Software Engineer for Pick&Place handlers and as a specialist for software interfaces. Since 2013, he has been responsible for InStrip & InMEMS Products at Multitest.

Steffen Kroehnert
Director of Technology
NANIUM S.A.

Biography
Steffen Kroehnert is Director of Technology at NANIUM since 2010. He worked for 20 years in different R&D and management positions at Siemens Semiconductors, Infineon Technologies, Qimonda and NANIUM in Germany and Portugal. Steffen is active member of several technical conference committees of IEEE CPMT, IMAPS, SMTA and SEMI. Since begin of 2016 he is chair of the European SEMI integrated Packaging, Assembly and Test Special Interest Group (ESiPAT). Steffen is author and co-author of 23 patent filings in the area of Packaging Technology. He received his Master of Science degree in Electrical Engineering and Microsystems Technologies from the Technical University of Chemnitz, Germany, in 1997.

Packaging for Automotive – Challenges and Solutions

Thorsten Meyer
Principal Engineer
Infineon Technologies

Abstract
First modern electronics entered automotive vehicles in the 1950’s and 1960’s with the introduction of semiconductor transistors in car radios and power diodes in alternators. Since then electronics have spread into all relevant areas of the automobile. They are supporting applications in the area of motor and chassis functions, comfort and security and safety, about 80% of all innovations are created by electronics already today. Autonomous driving, electro mobility, connectivity and energy efficiency will give another boost to electronics in the automobile industry. The mayor elements will be “intelligent” sensors, powerful electronic control units and “mechatronic” actuators. Those automotive electronics require highly integrated solutions with technology and packaging features from consumer electronics, but designed and qualified for harsh conditions of automotive industry. We will introduce to packaging technologies for integrated systems, sensors and MEMS with focus on chip package interaction. The mm-wave radar devices application, sensors including MEMS devices and different kinds of power devices like drivers for LEDs will be discussed from package point of view. Embedded Die technology, also an important future packaging technology for the support of system integration, will be discussed. We will show that there is a strong importance of Co-Design for package integration. For the ever increasing reliability requirements the selection of the right packaging materials and processes is crucial and will be discussed. Finally an advanced package integration concept has to also fulfill the thermal and performance requirements as well as to meet cost targets. This plurality of requirements to electronics in automotive shows, that there will be no single package solution fulfilling all needs. In this presentation we will introduce into the manifold of package solutions.

Biografie
Thorsten is Principal Engineer Package Concept Engineering at Infineon Technologies in Regensburg, Germany, responsible for New Package Platforms and New Package Definition. Until March 2015 he was leading the Package Technology and Innovation department at Intel Mobile Communications (IMC) in Regensburg. Prior joining IMC, he was overall project leader for the development of Wafer Level Packaging Technologies at Infineon in Regensburg. Thorsten is author of multiple publications and holds more than 140 patents and patent applications in the area of advanced packaging.

Packaging challenges for robust miniaturization

Laurent Herard
Group VP - Head of packaging R&D
STMicroelectronics

Abstract
The computing power embarked in latest generation cars keeps increasing in terms of content and complexity. This is typically the situation for microcontrollers and ADAS chips, for which interconnection requirements are on par with consumers advanced computing products in terms of miniaturization, signal integrity, power dissipation and cost. Recent improvements in packaging materials and equipment lead to higher package level reliability of the recent interconnection technologies, becoming compatible with quality requirement requirements for automotive include higher temperature storage conditions. The main challenge remains on more severe board level reliability with tough thermal cycling and vibration conditions. This paper gives an overview of the challenges driven by automotive mission profile for adoption of some advanced packaging innovation such WLCSP, flip chip, QFN. The focus is on packaging design, material.

Biografie
Laurent Herard is Group VP – Head of the Back End Manufacturing & Technology R&D at STMicroelectronics. He is located in Singapore. He received an Engineering Degree in physics of semiconductor from the INP Grenoble. In 1991 he joined the advanced packaging department of Bull France as a process engineer for development of high performance Multi Chip Modules. In 1994 he joined STMicroelectronics packaging department. He pioneered the development and industrialization of BGA design and manufacturing at ST. For the past 12 years, he has worked as Technical and Engineering Director at ST Back End manufacturing plants in Morocco, Singapore and Malaysia. During this experience, he led design, process optimization and automation activity for ST packaging portfolio.

How to dice Molded WLCSP's ?

Richard Boulanger
Managing Director
ASM Pacific Technology

Abstract
HOW TO DICE WAFER LEVEL CHIP-SCALE PACKAGES THAT HAVE BEEN MOLDED TO INCREASE RELIABILITY ? Richard Boulanger, Jeroen van Borkulo, Eric M.M. Tan. ASMPT Laser Separation International B.V. Beuningen, The Netherlands RBoulanger@alsi.asmpt.com ISSUE The introduction of Wafer Level Chip Scale Package (WLCSP) has become one of the key packaging solutions in the semiconductor industry. One of the key innovative package solutions is the Molded Wafer Level CSP (m WLCSP) due to the robust 5 side or 6 side protection of the devices with epoxy mold compound (EMC) This application enhances reliability of the package by reducing chipping and handling damage and improving board level reliability. This paper will address the challenges of dicing m WLCSP’s while ensuring the dies are individually encapsulated to prevent delamination. SOLUTION The demand for molded wafer level chip scale package (m WLCSP) has experienced a significant growth due to the large demand in the mobile phones , wearable technology and automotive markets. The challenging demands of m WLCSP technology require more dies per wafer. As a result, street lane design has to be narrower and allow a sufficient amount of mold compound to remain on the sidewall of the devices. Blade dicing is the Process of Reference for WLCSP but the demands for a more narrow dicing kerf in m WLCSP are too challenging so Laser Dicing is now being explored Multibeam laser dicing will allow the distribution of the laser power into uniform low spot energy to create more narrow dicing kerfs and higher speeds. There are many new challenges such as the coating adhesion, filler size and the wafer alignment. The epoxy material has very unique adhesion properties and coating , materials needed to be optimized The typical coating material had to be modified to improve the adhesion to the Mold Compound and coverage around the Solder Bumps. The filler size needs to be carefully chosen as it affects both kerf width and speed. The filler material is made of fused silica which is evaporated during laser processing and the holes left behind can cause “mouse bites ”on the top and bottom kerf as well as leave a sidewall with multiple craters. Since the wafer is covered with Epoxy, the alignment becomes more challenging. The typical process would remove the outer mold material to expose the wafer and the half cuts done by the Blade Dicing. The machine alignment would then move around the edge to first recognize the crossings and then correct for alignment and then verify before starting dicing Another method being considered is Illumination through the backside of the wafer that needs to transmit through the dicing chuck , the Silicon Wafer and the Mold Compound to a specially equipped camera to capture the information. There are technical challenges to design an optical path that can share an alignment camera and a laser to allow live kerf check. CONCLUSION The m WLCSP package is increasing in popularity due to the demands of increased reliability for the automotive and mobile markets. Several companies are working to develop a mature process which should happen in 2017. This process will include laser dicing instead of blade dicing and has to overcome several challenges that are addressed in this presentation.

Biografie
Richard Boulanger, Managing Director and Vice-President, ASM Pacific Technology, Netherlands rboulanger@alsi.asmpt.com Biography: Richard Boulanger graduated from Ecole Polytechnique at the University of Montreal in Industrial Engineering. He worked at IBM in Bromont, Canada at their Semiconductor Assembly and Test Facility. Over the course of 18 years, he worked in several functions such as Site Quality manager, Memory Business Unit, Sales Director and Strategy Director as well as some assignments in Corporate Headquarters in the USA. He moved to Binghamton, NY as Vice President of a newly formed Business Unit to design, build and sell Flip Chip machines based on a proprietary Linear Motor technology to achieve world class accuracy. He was also responsible for the SMT Process labs in China and the USA. He then went to Switzerland to become the Die Bonder Vice President of Kulicke and Soffa and Managing Director of the newly acquired company Alphasem. Following a short stint as Chief Operating Officer for Synova he became CEO of ALSI in the Netherlands which was then sold to ASM Pacific Technology where he is now the Managing Director of ALSI B.V.

Corrosion behaviour of printed circuit board surface finishes in mixed flowing gas testing

Laura Frisk
CEO
Trelic Ltd

Abstract
Corrosion resistance is vital for the reliability of many electronics devices especially in industrial use. Corrosion may cause both open and short circuits and therefore, especially for products having long use lives, corrosion may be a major reliability issue. Corrosion can be caused by different environmental contaminants and impurities due to manufacturing processes. The corrosion resistance can be tested using several test methods. In mixed flowing gas (MFG) testing the effect of high temperature, humidity and several different corrosive gases can be studied simultaneously. Such testing can be used to imitate different corrosive environments. In printed circuit boards (PCB) several different metal materials are typically used close to each other which makes them especially vulnerable to corrosion. For example, it is common that copper tracks on PCBs are covered using metallic surface finishes to both protect them and ensure good solderability. Typical surface finishes include electroless nickel immersion gold (ENIG), hot air solder leveling (HASL), immersion tin and immersion silver. Additionally, non-metallic organic solderability preservative (OSP) is commonly used. Even though the aim of the surface finishes is to protect the copper tracks, they may also make them more vulnerable to corrosion. For demanding use environments understanding the corrosion behaviour of the surface finishes is critical. In this study corrosion resistance of copper tracks with the five above-mentioned surface finishes were studied. No additional coatings were used. Surface insulation resistance test structures (SIR) were used to assess the corrosion behaviour. The test PCBs were tested in a MFG test and their SIR structures were periodically measured. Additionally, visual inspection was used and after testing detailed analysis of the corrosion process was conducted. Considerable differences between the surface finishes were seen with ENIG having the worst electrical performance.

Biografie
Laura Frisk received her M.Sc. degree in materials sciences and her Ph.D. degree in electronics from Tampere University of Technology (TUT), Finland, in 2000 and 2007 respectively. In 2013 she was granted Adjunct professorship (TUT) in the field of Reliability issues in electrical engineering. She worked for several years in TUT, Department of Electrical Engineering as the head Reliability Research Group. From 2013 to 2015 she worked as an EU Marie Curie Visiting Research Fellow in Imperial College London (ICL). Dr. Frisk has authored over 90 papers in peer-reviewed journals and conference proceedings. In 2016 Laura Frisk started as a CEO of TReliC Ltd, a company which offers consultation and solutions for challenging electronics packaging, materials and reliability issues. Trelic (Ltd) is a spin-off company from Tampere University of Technology. Trelic offers services in electronics packaging, materials characterisation and reliability analysis including planning of reliability testing, failure analysis and accelerated life testing. Additionally, the company offers courses in several areas. The company works in many industrial areas including, for example, consumer electronics, industrial electronics, medical electronics and power electronics.

Strategy to Assess and Mitigate Chip Package Interaction Risk Factors for Automotive Application

Frank Kuechenmeister
Principal Member Technical Staff
GLOBALFOUNDRIES Inc.

Abstract
Automotive is the fastest growing segment in the Foundry business and a major driver for innovation in electronics. The development in the automotive industry is increasing tremendously the complexity and variety of the electronics in modern cars. And these requirements for substantial computing power resulting in the need of advanced silicon solutions. Package-induced failures in the Back End of Line (BEoL) metallization layers in advanced silicon technology nodes have drawn attention in the industry resulting in significant research and development activities. The concern is caused by the selection of the set of materials in BEoL, the transition from SnAg bumps to Cu Pillars, the transition from Au to Cu wire bond and the use of cost improved package solutions. A systematic approach is needed to understand CPI related risk factors especially in conjunction with the application in the automobile industry. The understanding of the different failure modes and their influencing factors is essential to reach highest level of reliability. One approach is the establishment of methods which can give quantitative data beyond the standard reliability stress tests. The paper will reveal a general strategy to assess these risks starting from data generated on wafer level (blanket film and integrated BEoL stack) to an early risk assessment on package level. The understanding of the different failure modes for automotive application and their influencing factors is essential to reach highest level of reliability. The approach is the establishment of methods which can give quantitative data beyond the standard reliability stress tests for consumer application. The paper will discuss the design and functionality of CPI test structures incorporated on the test vehicles. The paper will reveal data for the qualification envelope for different interconnect technologies including wire bond and wafer level packaging fan-out with focus on 22FDX® technology.

Biografie
Dr. Frank Kuechenmeister received a Diploma in Polymer Chemistry and a doctorate in Chemistry from the University of Technology in Dresden, Germany. He held post-doctoral appointments at the Departments of Polymer Science at the ETH Zuerich, Switzerland, the University of Massachusetts in Amherst, USA and the Department of Electrical Engineering and Micro Systems at the University of Technology in Dresden, Germany. He joined AMD in 1999, which converted to become GLOBALFOUNDRIES in 2008 as process engineer working the area of C4 bumping. He was promoted to principal member of technical staff in 2016. He currently leads the chip-packaging interaction team and coordinates all related efforts throughout all technology nodes at GLOBAL-FOUNDRIES. Dr. Kuechenmeister holds more than 30 C4 bump and packaging-related patents and trade secrets.