Wednesday, November 16, 2022
 

New Computing Paradigms

13:00 Opening remarks
13:10 Opening keynote, Michael Peeters, VP of R&D for Connectivity, imec
13:20
Will More-than-Moore technologies with 3D integration meet the challenges of edge AI devices ?
  Sylvie Joly, Parnerships Manager 3D integration and packaging, CEA-Leti
Will More-than-Moore technologies with 3D integration meet the challenges of edge AI devices ?
Sylvie Joly

Sylvie Joly
Parnerships Manager 3D integration and packaging
CEA-Leti

Sylvie Joly

Abstract
In the world of high performance computing, over a decade the performances of the computing has constantly increase beyond the almost automatic but slowing down improvement in processor performance with Moore's Law. Big players have moved to new architectures such as chiplets only possible thanks to the integration of More-than-Moore technologies. 2.5D and 3D integration, memory cubes, accelerators and heterogeneous architectures are key elements of the success towards performance and energy efficiency. This transition has shown clear benefits and sustainability for HPC market. The question is still open for Edge AI components where real time, ultra-low power, large amount of data, low cost are the main drivers: how can 3D integration play a role for these embedded processors? CEA-Leti has been involved for more than two decades in 3D integration with industrial partners. This presentation will discuss about:- What are the main drivers for computing in edge devices ?- What could be the architectures’ new paradigm ?- How 3D integration will be an enabler, and how CEA-Leti’s roadmap supports this promising technology

Biography
Sylvie Joly is currently working as 3D integration and packaging Partnerships Manager at CEA-LETI. Sylvie received M.Sc. in Microelectronics from ISEP "Institut Supérieur d'Electronique de Paris" in 1989. She completed her education with a Master in Marketing and Innovation at the Grenoble Ecole de Management (GEM) in 2001. Prior to this position, she worked for more than 8 years as display business developer at CEA-LETI. In 2004 as Sr. Marketing Engineer in the CEA's Technology Transfer Department, she built a strong experience in setting up and managing technical marketing surveys. Before joining CEA, she spent 10 years in the industry as an R&D engineer, and 8 years as Sales engineer in several companies including Hewlett Packard and Ericsson.

13:40 FMD NGC and Green ICT project, Stephan Guttowski, Fraunhofer
14:00 Reserved for business partner
 

Low Power Computing for Edge Devices

14:30
A Materials to Systems Understanding of a BEOL Embedded Analog NVM Memory Technology for Edge Compute Applications
  Michael Chudzi, VP of Technology for IMS, Applied Materials
A Materials to Systems Understanding of a BEOL Embedded Analog NVM Memory Technology for Edge Compute Applications
Michael Chudzi

Michael Chudzi
VP of Technology for IMS
Applied Materials

Michael Chudzi

Abstract
Coming Soon

Biography
Dr. Chudzik is VP of Technology for IMS at Applied Materials focusing on device and module engineering solutions in the specialty and packaging segments.He has a PH.D in Electrical engineering from Northwestern University. Mike has been at Applied Materials for 8 years and prior to that he worked at IBM for 14 years in various roles in DRAM and CMOS process integration and management.

14:50
MicroLED Advance Bonding Method to enable AR Metaverse
  Ran Yan, Business Unit Director, GLOBALFOUNDRIES
MicroLED Advance Bonding Method to enable AR Metaverse
Ran Yan

Ran Yan
Business Unit Director
GLOBALFOUNDRIES

Ran Yan

Abstract
Mark Zuckerberg and companies seem to think that smart glasses will one day replace smartphones. They’re not alone, and it will probably happen at some point in the not-too-distant future. But for such a product to exist, we still face plenty of challenges both in hardware and software, especially in the microdisplay that is required for smart glasses. MicroLED is one of the best microdisplay solutions for smart glasses. The key challenges are how to integrate LED arrays from a small epi wafer to a full-size CMOS backplane wafer in a way that is cost-effective. A crude method is coring: the larger CMOS wafer is cored to the size of the epi wafer and the two are bonded with wafer-to-wafer (W2W) bonding tools. This is suitable for R&D and low volume production, but there is too much wasted CMOS wafer to be valid for mass production. Another method is Direct Die-to-Wafer (D2W) Integration: the pixelated frontplane epi wafer is diced and the resulting dies are then bonded to corresponding locations on the backplane wafer. While this reduces the amount wasted, bonding accuracy becomes more challenging, and throughput is potentially slower. GF believes that innovative D2W integration is a good way to increase throughput. In this method, epi dies are first transferred to blank wafer of the same size as the backplane wafer. Standard W2W bonding is then used to finish the integration of frontplane and backplane. In this paper, we will present GlobalFoundries® (GF®) advanced D2W bonding solution to resolve the microLED manufacturing challenges.

Biography
Ruby is a Business Line director in AIM Strategic Business Unit. She is responsible for HMI (Human-Machine-Interface) product line in wearable, AR/VR, smart home and machine vision applications.

15:10 Reserved for Mariano Mailos, Microsoft Hololens