Opening Keynote presentation

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Abstract
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Biography
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Riding the Perfect Storm: Enabling Europe's Next Wave of Advanced Packaging

Ossmann, Christian
VP & COO
ACCRETECH GmbH

Abstract
Europe's semiconductor industry is facing a perfect storm. Increasing technological complexity, cost pressure, demographic change and global competition are reshaping semiconductor manufacturing. Yet, like offshore racing, where skilled sailors turn challenging conditions into competitive advantages, these forces also create significant opportunities.Advanced Packaging is becoming increasingly important for Europe's semiconductor ecosystem. Meeting the requirements of these applications demands more than individual high-precision machines. It requires the intelligent integration of manufacturing technologies, metrology, automation and process control.Drawing on ACCRETECH's broad technology portfolio, spanning wafer grinding, polishing, highprecision blade and laser singulation , wafer probing and precision metrology, particular attention will be given to the integration of measurement technologies into manufacturing equipment to enhance process monitoring and control. Advanced equipment and factory automation will be discussed as responses to Europe's demographic challenges and skilled-labor shortage, while Big Data and artificial intelligence offer new opportunities for process optimization, yield improvement and predictive maintenance. However, technological innovation must also be supported by operational reliability. High equipment availability, combined with a strong local service infrastructure, is essential for sustainable manufacturing performance. With approximately half of ACCRETECH Europe's workforce deployed at customer sites for maintenance and technical support, local expertise forms an integral part of its technology offering.The future of Advanced Packaging will not be defined by individual machines alone, but by the integration of precision manufacturing, metrology, automation, data intelligence and reliable lifecycle support, creating the foundation for closed-loop process control across the manufacturing chain.For Europe's semiconductor industry, the perfect storm represents not only a challenge, but also an opportunity to accelerate innovation and strengthen competitiveness.

Biography
Christian Ossmann is Vice President and COO of ACCRETECH (Europe) GmbH, where he is responsible for the company's semiconductor and metrology businesses in Europe. He has extensive international management experience, having held several leadership positions at semiconductor equipment manufacturers serving the back-end industry. His professional background combines technology-driven business development, strategic management and international sales leadership.At ACCRETECH, he focuses on strengthening the company's position in the European semiconductor market, with particular emphasis on advanced packaging and automation. Christian studied at the Technical University of Braunschweig, Germany.

Bridging the Gap from Prototype to Production: High-Volume Manufacturing Test and Qualification for Co-Packaged Optics

Malsam, Dimitri
Product Marketing Specialist
Advantest America, Inc.

Abstract
Co-Packaged Optics (CPO) enables higher bandwidth density and lower power for AI, HPC, and next-generation data centers by placing optical engines close to advanced compute and networking devices. However, scaling CPO from prototypes to high-volume manufacturing (HVM) requires more than photonic integration and advanced packaging. The main challenge is to build a production-ready test and qualification infrastructure that can handle optical, electrical, thermal, mechanical, and operational requirements with the repeatability and throughput expected in semiconductor manufacturing. Key barriers include reliable optical connectivity at package level, insertion-loss control, polarization preservation, connector wear, contamination sensitivity, precision alignment, external laser delivery, calibration stability, thermal-mechanical integration, serviceability, and long-term reliability. These issues affect both Final Test (FT) and System-Level Test (SLT) and must be solved without compromising automation, changeover efficiency, equipment utilization, or cost of test.This paper presents a modular platform architecture to address these challenges. It extends existing semiconductor test cells with a dedicated co-packaged interface layer that supports optical routing, laser delivery, calibration, diagnostics, cleaning concepts, and photonic test integration while maintaining compatibility with current handlers, sockets, load boards, and automated test equipment. The platform approach allows different optical engine designs, connector concepts, and production test strategies — such as optical loopback, instrument-assisted characterization, and system-level qualification — to be supported without redesigning the full manufacturing cell.By combining standardized interfaces, automated calibration, contamination mitigation, serviceable optical paths, and scalable test flows, the proposed architecture provides a practical path from New Product Introduction (NPI) to HVM. It helps manufacturers manage yield, reliability, throughput, and ecosystem interoperability as CPO devices move into production for photonic-enabled AI and HPC systems.

Biography
Dimitri Malsam is a Product Marketing Specialist at Advantest, focusing on photonic test solutions. With close to 20 years of experience in the test and measurement industry, he has a strong background in developing and supporting the photonic test business across Europe and globally. His current work focuses on the test challenges associated with bringing Silicon Photonics (SiPh), Near-Package Optics (NPO), and Co-Packaged Optics (CPO) into high-volume semiconductor manufacturing. He holds a master’s degree in electrical engineering from the University of Erlangen, Germany.

Enabling Sustainable AI Through Power Semiconductor Innovation and Test

Tonti, Giacomo
Marketing & Business Development Manager
Advantest Europe GmbH

Abstract
Modern test systems are no longer simply production tools; they are strategic enablers of innovation. As AI reshapes the world's energy landscape, Advantest power test solutions help unlock next-generation power semiconductors full potential by ensuring uncompromising efficiency, reliability, and performance.

Biography
Giacomo Tonti, born in Italy in 1978 and entered the semiconductor industry in 2000 following studies in Electronics and Telecommunications. He spent the first part of his career as a Service and Application Engineer specializing in analog and mixed-signal semiconductor devices.In 2015, he moved into Account Management, leading growth initiatives and business development activities for semiconductor customers. Since joining Advantest in 2024, he has been serving as Marketing and Business Development Manager for CREA, supporting strategic market expansion and customer engagement across the power semiconductor ecosystem.

Advanced Packaging for high mix and low volume, Flip Chip capabilities beyond the standard in Europe

Lieske, Daniel
Senior Expert Advanced packaging
AEMtec GmbH

Abstract
This presentation will showcase AEMtec's flip chip capabilities especially developed for harsh environments like applications in space. It will give first reliability results and processes, that have been used for qualification purpose under the support of ESA (European Space agency). Furthermore we will show the demand in future for FOWLP, Copper pillar and micro bump in the field of flip chip and chiplet applications.Discover how AEMtec transformed from an IDM into a leading specialized OSAT, carving out a unique position in the European semiconductor landscape. While industry roadpaths often follow rigid lines, AEMtec thrives on complexity: we build custom-specific package designs that lay the groundwork for future technologies.

Biography
Daniel Lieske, Senior Expert Advanced Packaging @ AEMtec GmbHDaniel Lieske is Senior Expert for Advanced Packaging Technologies at AEMtec in Berlin.In this role, he supports both product and process development teams and advises the sales department on new customer projects. His technical focus includes advanced packaging technologies such as Fan-Out WLP, RDL, Flip Chip, and photonics packaging, ensuring that AEMtec meets current and future market demands.He holds a diploma in Microelectronics and Microsystems from Brandenburg University of Technology in Cottbus. Daniel began his career as a Process Engineer at Infineon Technologies Dresden and Qimonda, working in the Backend on development, production, and technology transfer of multi‑chip modules to high‑volume manufacturing sites. As a Project Engineer at Freudenberg Mechatronics, he developed and optimized production equipment for automotive lighting applications.For the past 15 years at AEMtec, he has been responsible for wafer‑level solder ball attach, printing technologies, solder reflow, and failure analysis.

From Plasma-System Design to Deployment: An Integrated Engineering and Global Supply-Chain ApproachSubtitle: From Process Requirements to Upgradeable Process Platforms

Vajpayee, Manikya
CEO
Aether Semiconductors

Abstract
Session OverviewBuilding specialized semiconductor equipment takes more than process expertise; it requires coordinated system engineering, precision manufacturing, subsystem integration, and resilient supply-chain execution. This session shows how Aether Semiconductors, headquartered in India with a local engineering presence in the Netherlands, applies this integrated approach to plasma-based deposition and etch equipment for advanced- and mature-node applications.Using a representative equipment case, we show how process requirements are translated into modular system architectures spanning plasma chambers and sources, gas delivery, RF and microwave power, thermal management, vacuum systems, and controls and automation, with emphasis on system integration, interface management, qualification, and lifecycle upgradeability.We also examine how Aether’s engineering capability, combined with manufacturing and supply-chain collaboration across India, Europe, and Asia, supports adaptable plasma platforms, stronger supply resilience, faster development cycles, and long-term support.Keywords: Plasma Equipment Engineering, Global Supply Chain, System Integration

Biography
Manikya Vajpayee is the Founder & CEO of Aether Semiconductors, where he is building the next generation of scalable and upgradeable semiconductor process equipment. With over a decade of industry experience, he leads the company’s initiatives across equipment engineering, plasma process technologies, system integration, manufacturing, and global supply-chain development. His vision is to transform advanced engineering into production-ready platforms that enable the future of semiconductor manufacturing.

Chip-scale, Software-Defined Hyperspectral Intelligence

Liapis, Andreas C.
CTO
Agate Sensors

Abstract
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Biography
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Air Liquide Advanced Materials : European solutions for chip manufacturing technology innovation

Castrogiovanni, Lorenzo
Vice President Electronics Europe
Air Liquide

Abstract
Air Liquide stands as the global and European leader in industrial and specialty gases, equipment, and advanced materials for the semiconductor industry. At the core of its regional strategy is the Advanced Materials Center of Chalon-sur-Saône, an innovation powerhouse that provides a highly resilient, European-based supply chain. This strategic proximity enables chip manufacturers to mitigate geopolitical tensions, international tariffs, and logistics disruptions while benefiting from flexible, high-precision local production.This competency, knowledge, and assets allow rapid deployment of advanced molecule samples and the co-development of new molecules—benefiting from a 20-year-old R&D library of development. This aims for very rapid industrialisation to effectively supply resilient and innovative molecules for European chip makers with a strong appetite for innovation.Over the past two decades, Air Liquide’s material innovations have consistently enabled major technological breakthroughs in Atomic Layer Deposition, Chemical Vapor Deposition, and etch processes. The state-of-the-art Chalon facility continues this trajectory with dedicated cleanrooms, advanced analytical laboratories, and flexible, automated manufacturing units. Backed by rigorous ISO quality certifications and continuous capacity expansions, an expert team oversees a rapidly growing portfolio of dozens of high-purity precursor molecules engineered for next-generation semiconductor architectures.Beyond precursor synthesis, the site delivers a holistic, end-to-end service model tailored to every stage of industrial maturity, spanning initial studies, pilot lines, and high-volume manufacturing. The operational scope integrates advanced low vapor pressure chemical distribution, specialized fleet canister maintenance, and ultra-high-purity analytical capabilities such as ICP-MS and air-sensitive quality testing. This comprehensive ecosystem ensures seamless operational reliability and stringent quality assurance across all customer facilities.Looking to the future, Air Liquide is actively pioneering environmentally conscious chemical technology by developing low global warming potential etch gases that align with industry sustainability imperatives. Furthermore, the Chalon facility expands beyond traditional microelectronics to drive forward-looking innovation in quantum computing, isotope supply, and novel thin-film applications. By bridging advanced chemical engineering with emerging manufacturing needs, the center reinforces its position as an indispensable partner for the next generation of semiconductor innovation.

Biography
Lorenzo Castrogiovanni is a distinguished international business leader and industrial engineer who serves as Vice President Europe – Electronics at Air Liquide.Over a career spanning more than two decades across Europe and international markets, he has established a strong record of strategic vision, multi-country organizational leadership, and executive governance. His expertise encompasses high-tech semiconductor sectors, heavy process industries, clean energy transition initiatives, and digital transformation, where he consistently builds high-performing, multi-cultural teams and drives sustainable corporate growth.Throughout his tenure at Air Liquide, Lorenzo has held key executive positions across key European regions and global account networks. In his current capacity, he leads broad industrial operations and top-level executive engagement with leading technology and semiconductor global accounts. Earlier roles include directing major regional business units in Russia and Italy, leading strategic corporate alignment under top group executives in Paris, and driving forward-thinking commercial initiatives in energy efficiency, industrial IoT, and hydrogen clean technologies.His academic foundation combines rigorous technical education with executive management development. He holds a Master’s Degree in Industrial Engineering & Management from Università di Roma, alongside post-graduate studies at École des Ponts ParisTech, an MBA from Collège des Ingénieurs, and executive leadership credentials from INSEAD. A multilingual professional fluent in Italian, English, and French, with proficiency in German, Russian, and Spanish, he brings an exceptionally global, adaptive, and culturally agile perspective to senior leadership.Beyond his professional achievements, Lorenzo is recognized for his resilient, empathetic leadership style and dedication to continuous personal growth. His commitment to endurance and personal challenge is demonstrated by completing demanding athletic accomplishments, including the Marathon des Sables ultra-marathon and swimming across the Messina Strait. Guided by a strong customer-centric philosophy, he continues to lead transformational initiatives that blend industrial excellence with innovation and strategic foresight.

AI-ready Subfab Infrastructure – A Foundation for Edge Intelligence and Energy-Optimized Subfab Operation

Hammer, Stefanie
General Manager
algorismic gmbh

Abstract
Semiconductor manufacturers face growing pressure to reduce emissions and energy consumption in the subfab while maintaining strict process stability and uptime. A major obstacle to deploying artificial intelligence (AI) in this environment is the lack of a unified, high‑resolution data layer connecting process tools, vacuum systems and scrubbers. This presentation introduces a subfab control and monitoring platform implemented at a high‑volume manufacturing site, where it is used as the backbone for future edge AI applications in energy and emissions optimization. The case study follows the journey from initial deployment to AI‑ready operation in a 300 mm fab with complex multi‑chamber process tools and clustered scrubber systems. It explains how standardized interfaces between process tools and subfabequipment were established, which data (e.g. flows, status signals) are collected at high frequency, and how this information is synchronized and contextualized at the tool and chamber level. On this basis, the fab engineering team can now analyze process‑gas usage and scrubber loading patterns across the tool base consistently, without changing existing production workflows. Building on this foundation, the presentation highlights several AI use-cases for edge deployment. These range from learning typical exhaust and loading patterns to optimize the interaction between process tools, vacuum systems and scrubbers, to dynamically adapting operating parameters such as fuel‑gas setpoints or post‑combustion times within defined safety limits. By positioning the subfab platform as an open enabler rather than a proprietary black box, both semiconductor manufacturers and subfab equipment suppliers gain a flexible environment to develop, validate, and scale AI‑driven energy efficiency optimizations over time. This case study demonstrates how investing in AI‑ready subfab infrastructure can translate into measurable reductions in fuel‑gas consumption, emissions and unplanned downtime, supporting nature‑positive production and enable energy efficiency optimization in real manufacturing conditions using AI.

Biography
Stefanie Hammer, General Manager of algorismic gmbh has 12 years of experience in technology, strategy and digital transformation. She holds a Bachelor’s degree in Digital Business & Innovation and focuses on digitalization, software management, digital business model development and international project management. In her work she builds bridges between business and technology to turn digital transformation into concrete results and measurable impact.

The Optical Interface Between Human and AI: Rethinking the Power Problem for AI Eyewear.

Koch, Tanja
Chief Business Officer
AlphaLum SA

Abstract
Every smart glasses maker is fighting the same battle: power. A display drains the battery. Running AI to understand what the user wants drains it further, typically through power-hungry cameras and inference pipelines that can't realistically stay on all day, and even when they do run continuously, low frame rates miss the fast, subtle signals that actually carry intent. Most solutions optimize one side of this equation, a more efficient display, or a lower-power sensor, but treat the other as someone else's problem. AlphaLum optimizes both, on a single optical platform.Our holographic combiner architecture delivers a step-change in display efficiency, easing the power cost of getting information in front of the eye. At the same time, our optical micromotion sensing platform reads subtle eye and skin signals directly, combining always-on operation with high temporal resolution, capturing fast micromotions continuously rather than trading one for the other, at a fraction of the power of camera-based AI interaction. The result is a combiner that cuts power on both the output and the input side of the human-AI loop, without forcing a choice between staying on and seeing enough.This talk covers why power has to be solved on both sides of the interaction, not just the display, why the combination of always-on and high temporal resolution is the precondition for genuinely useful AI interaction on the face, and what that means for how AR glasses get designed, built, and scaled toward true all-day wear.

Biography
Tanja Koch is the co-founder and Chief Business Officer of AlphaLum, a deep-tech photonics startup based in Lausanne developing next-generation optical systems for smart glasses. She brings over nine years of experience across startup founding, venture capital, and innovation strategy, with a particular focus on the AR hardware space.Before AlphaLum, Tanja served as Senior Product Manager at ams OSRAM, one of the world's leading optical semiconductor companies, where she gained direct experience bringing complex photonic and sensing technologies from R&D to market. That industry grounding, combined with her background as both a founder and a venture capitalist, gives her an unusual vantage point: she understands what it takes to build deep-tech products from the inside, and what it takes to scale and commercialize them.Tanja holds a Master of Science in Management from the Technical University of Munich (TUM) and has continued her education at Stanford University. Her academic foundation in design thinking and user-driven innovation shapes how AlphaLum approaches product development: starting from real user constraints, including power, form factor, and all-day wearability, rather than from technology capabilities alone.At AlphaLum, she leads business development, partnerships, and go-to-market strategy as the company advances its two core platforms: an ultra-efficient holographic waveguide display and an always-on optical micromotion sensing system, together forming a bidirectional interface layer between humans and AI.

Accelerating Fab Performance with Connected Intelligence

Munipella, Kedar
Vice President, Digital Enablement Group - Applied Global Services
AMAT

Abstract
The next wave of semiconductor manufacturing performance will be driven not only by technology innovation, but also by the ability to transform data into actionable intelligence. This session examines how connected data, AI-driven insights, and automation are reshaping fab operations and enabling faster, more informed decision making. Through industry perspectives and practical examples, the presentation highlights the opportunities and challenges of building a connected manufacturing environment that can improve agility, accelerate learning, and create sustainable competitive advantage.

Biography
TBD

Does the Most Advanced Packaging Require the Most Advanced Metrology

OToole, Eoin
R&D Director
Amkor Technology Portugal

Abstract
The cutting edge of advanced packaging includes tens of stacked memory dies with intricate wire bond connectors as the top layer of a Package on Package solution for an application processor (for example). The application processor will likely have fine pitch micropillars for a flip chip connection to a multilayer RDL interposer. The RDL interposer can have line width and line space features down to single digit microns, requiring organic CMP processing to achieve the necessary interlayer coplanarity. The question remains as to whether the most advanced metrology solutions are required to control such an advanced process. This presentation aims to answer that question.

Biography
Eoin OToole is a the R&D director of Amkor Technology PortugalOriginally from Dublin Ireland where he obtained his primary and master degrees in material science from Trinity College Dublin.

From Seeing to Understanding: Optical Sensing for the Age of Physical AI

Stübinger, Julia
Global Head of Product Marketing
ams-OSRAM

Abstract
As AI moves into the physical world, devices need to understand more than images – they need to perceive light, color and space. At the same time, sensors are becoming smaller, more integrated, and increasingly hidden behind displays and cover glass.This talk explores how advanced spectral sensing and multi-zone Time-of-Flight address these challenges, enabling devices to understand ambient light, reproduce colors more naturally and add depth and spatial awareness. From smartphones and wearables to AR glasses, these technologies are helping optical sensing evolve from simply measuring the world to enabling devices to better understand it.

Biography
Julia Stübinger is Global Head of Product Marketing for the Integrated Optical Sensors (IOS) business at ams OSRAM. She leads global marketing activities for ams OSRAM’s optical sensing portfolio, spanning applications in smartphones, wearables, smart glasses and other consumer devices.Julia has held several leadership roles at ams OSRAM across strategy, product marketing and business development, with a strong focus on bringing advanced sensing technologies to market.Prior to joining ams OSRAM, she worked in management consulting at Kearney. She holds a strong passion for translating complex technologies into market opportunities and tangible customer value.

Data Enablement as a Business Imperative in Semiconductor Manufacturing

Schilz, Christof M.
Vice President for Operations Technology
ams-OSRAM International GmbH

Abstract
Data-driven manufacturing, AI, digital twins, and advanced analytics are rapidly becoming key competitive differentiators in the semiconductor industry. Yet many organizations struggle to scale these initiatives because the underlying data ecosystem is fragmented, inconsistent, or incomplete. Structured Data Enablement is therefore no longer optional. It is a business-critical capability and a prerequisite for sustainable operational excellence and future innovation. Based on an ongoing data platform transformation at ams OSRAM, this joint presentation shares how manufacturers can establish a holistic foundation for data-driven production and AI transformation. The session highlights the role of Industrial Data Platforms, the importance of separating data, semantic, and intelligence layers, and the value of a structured, step-by-step transformation approach. Attendees will gain practical insights into the drivers, objectives, challenges, and early lessons learned from building the foundation for scalable analytics, AI, and next-generation manufacturing use cases.

Biography
Dr. Christof M. Schilz is Vice President for Operations Technology at amsOSRAM, where he drives strategic initiatives related to digital manufacturing, automation and AI enablement. His expertise includes manufacturing execution systems, industrial data platforms, data governance, and the enablement of AI and advanced analytics. With more than 25 years of experience in operations, information technology, and quality management across the semiconductor industry, he combines deep technological expertise with a strong understanding of manufacturing processes and operational excellence.Marco Grafe is a Solution Specialist for Smart Manufacturing at ZEISS Digital Innovation, where he coordinates development activities related to Industry 4.0. His areas of expertise include modern manufacturing organizations, industrial data platforms, and digital twins. With more than 15 years of experience in mechanical and plant engineering and project work across the semiconductor, automotive, and pharmaceutical industries, he combines deep technological expertise with a strong understanding of industrial processes.

New Collaborations, Materials & Market for Photonics

Ertl, Sabine
Senior Vice President & General Manager
ams OSRAM

Abstract
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Biography
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Future-proofing your fab: from automation (A) to impedance (Z)

Britz, David
Managing Director, Strategic & Product Marketing
Applied Materials

Abstract
200 millimeter fabs are foundational for the semiconductor industry. As the semiconductor industry evolves, 200mm fabs also are evolving. This evolution includes building on learnings from 300mm fabs, as well as building specialized capabilities to handle new wafer types, improve existing tools, and even produce new device types. The power electronics industry has embraced these changes. In this talk, I will share examples of how Applied Materials has adapted our equipment offerings to support the future of 200mm fabs to support such improvements, from A to Z.

Biography
Dr. David Britz leads the Strategic Marketing & New Product organization for the ICAPS business at Applied Materials. Prior to Applied, David has experience at both Fortune 100 and startup companies in strategy, business development, and product management. David has an MBA from MIT Sloan and a DPhil in Materials from the University of Oxford.

Hydrodynamics-Driven wet etching for scalable fabrication of high-aspect-ratio through-glass vias in glass core substrates

Zürcher, Stefan
Head of Process Technology
AP&S International GmbH

Abstract
The scalable fabrication of high-aspect-ratio through glass vias (TGV) in large-area glass core substrates remains a critical bottleneck for next-generation advanced packaging technologies. While hybrid laser–etching approaches have demonstrated fundamental feasibility, the lack of precise control over etch homogeneity, via geometry, and process scalability continues to limit their implementation in high-volume manufacturing. This work presents an integrated, simulation-driven wet processing approach that addresses these limitations by introducing hydrodynamic control within the etching stage, enabling deterministic shaping of TGV structures at wafer and panel scale.The proposed solution builds on a combined femtosecond laser modification and selective wet chemical etching process chain, in which laser-induced structural changes in the glass bulk define regions of enhanced chemical reactivity. The key innovation presented here lies in the subsequent etching process: by engineering the fluid dynamics within the etch environment, mass transport limitations are actively mitigated.Within AP&S wet processing equipment, a novel hydrodynamic design enables uniform delivery of the etching medium. This controlled flow regime enhances local reactant availability while ensuring efficient removal of reaction by-products, resulting in improved etch kinetics and uniformity. Compared to conventional immersion-based approaches, the method allows for tighter control of critical geometrical parameters, including via diameter (20–100 µm), aspect ratios exceeding 10:1, and well-defined sidewall profiles across the entire substrate.A central contribution of this work is the integration of computational fluid dynamics (CFD) into both equipment and process design. By leveraging simulation-based optimization, the hydrodynamic conditions can be pre-configured for varying substrate dimensions and layout densities without empirical iteration. This not only reduces development time but also enables rapid process transfer across different product configurations.The results demonstrate that hydrodynamically optimized wet etching represents a key enabler for translating laser-based TGV fabrication from laboratory to industrial-scale manufacturability. The presented approach establishes a pathway toward highly uniform, high-throughput, and geometry-controlled TGV formation, thereby addressing a challenge in the deployment of glass core substrates for advanced electronic systems.

Biography
Stefan Zuercher is the Head of Process Technology at AP&S and has more than 15 years of experience in the semiconductor industry. He joined AP&S in 2011 as a process engineer for wet processes (etching, cleaning, drying, electroless UBM metallization), installing and qualifying wet process equipment worldwide for over a decade.In 2014, he became the manager of the newly established AP&S DemoCenter, and in 2017 he advanced to Process Manager. In this role, he was responsible for all process-related tasks, including tool qualifications and optimization, as well as process development across AP&S equipment platforms for singlewafer, batch, and parts-cleaning applications for advanced semiconductor manufacturing.Since 2024, as Head of Process Technology, he has fully focused on delivering customer-oriented process solutions across the AP&S product portfolio and DemoLAB, as well as driving advancements in simulation engineering within the AP&S SimLAB.

Coming Soon

J. Díaz-Otero, Francisco
CEO
Ardora III-V

Abstract
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Biography
Francisco is a telecommunications engineer with a PhD in photonic technologies and more than 25 years of experience spanning research, academia, and industry. He is the co-founder and CEO of Ardora III-V, Spain’s first merchant compound semiconductor foundry specializing in III–V technologies. The company is dedicated to strengthening Europe’s industrial capabilities in this highly strategic sector.

Semiconductor & Electronics Opportunities in India

Keskar, Sanjeev
CEO
Arvind Consultancy

Abstract
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Biography
Sanjeev Keskar is Chief Executive Officer of Arvind Consultancy. After his successful stint of 35 years in corporate world, out of which about 29 years in semiconductor industry, Mr. Keskar incorporated Arvind Consultancy, an advisory firm in the field of developing High Value-Added Eco- System for Semiconductor and Electronics Industry in India in Nov. 2020.Prior to this, Mr. Keskar was Managing Director India at Arrow Electronics for India, a leading electronic component global distribution company for five and half years. Earlier he was Managing Director Sales at PMC-Sierra for India and SEA.He was also elected Chairman of IESA (India Electronics and Semiconductor Association) for year 2013-14 and in current year he is part of Executive Council of IESA.Prior to PMC Sierra, he was Country Manager, Sales, at Freescale Semiconductor ( Motorola ) for 5 years and Country Manager, India, for AMD Far East Ltd., where he started AMD India operations as the first Country Manager and established AMD India.Mr. Keskar has also worked at National Semiconductor as Country Manager and at Max India Ltd. as Regional Manager.Mr. Keskar is Professor of Practice at IIT Roorkee. Mr. Keskar is also Executive Director at EPIC Foundation.Mr. Keskar received a master’s degree in management science in Marketing and a Bachelor’s in Electronics and Communication Engineering and Technology, from Pune University.

Scaling Advanced Packaging: The Wafer-to-Panel Revolution

Tien, Nicole
Senior Technical Program Manager
ASE

Abstract
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Biography
Nicole Tien is a Senior Technical Program Manager at ASE Europe, where she drives advanced packaging technology development and innovation to support customer growth and ecosystem collaboration. She focuses on high-performance heterogeneous integration, including multi-die and 3D packaging solutions, enabling improved system-level performance, bandwidth, and energy efficiency. Nicole works closely with customers and industry partners to translate emerging requirements into scalable packaging solutions, supporting applications across AI, automotive, and high-performance computing. She is actively involved in advancing packaging strategies that push the limits of thermal, electrical, and mechanical performance, helping to enable next-generation semiconductor systems

Closing Remarks by Session Chair

MacLeod, Patricia
Senior Director, Corporate Communications & Industry Partnerships
ASE Global

Abstract
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Biography
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Enabling tomorrow’s memory and logic through materials innovation

Leonhardt, Alessandra
Manager, Process Engineering
ASM

Abstract
As memory and logic technologies continue to scale and diversify, progress increasingly depends on discovering new materials and engineering them at the atomic level. This talk will explore how materials science, process engineering, and device physics can connect fundamental materials understanding with device requirements and manufacturable processes, accelerating innovations in gate stacks, engineered interfaces, and emerging functional materials from discovery to application. These advances can unlock new pathways for improved performance, power efficiency, reliability, and continued scaling in next-generation memory and logic devices.

Biography
Dr. Alessandra Leonhardt is an R&D Program Manager at ASM, specializing in advanced materials and process technologies for semiconductor applications. Her expertise spans atomic layer deposition (ALD) of oxide semiconductors, high-k and ultra-high-k dielectrics, and metal gate stacks, with a strong focus on translating materials innovation into device performance improvements aligned with industry roadmaps. After completing her PhD at imec in 2020, Alessandra joined ASM, where her work has focused on materials discovery and the development of advanced semiconductor technologies. Since 2024, she has led programs within ASM’s Corporate R&D organization focused on advanced technologies for next-generation logic and memory applications.

Pantel Discussion Moderator

Seng, Seraphina
Global Head of Public Affairs
ASM International

Abstract
Chips Act 2.0 and International Collaboration with Trusted Partners

Biography
As Europe moves towards the implementation of the Chips Act 2.0, strengthening international partnerships will be essential to building a more resilient, secure and competitive semiconductor ecosystem. Europe’s position across the semiconductor value chain depends not only on strengthening domestic capabilities, but also on deeper cooperation with trusted partners, including the US, Japan, Taiwan and South Korea.This session will examine how the Chips Act 2.0 can reinforce Europe’s strategic positioning and translate international partnerships into practical cooperation on supply chain resilience, technology, investment and innovation. It will also explore the role of initiatives such as ICOS in connecting European capabilities with trusted international ecosystems.

Powering the Future with 8-Inch SiC Technology Across the Voltage Spectrum

Gong, Xiao

A*Star

Abstract
Silicon carbide (SiC) power devices are key enablers for the next generation of high-efficiency and high-voltage power electronics. In this work, we present our latest progress from A*STAR in developing an 8-inch SiC power device technology platform, spanning a broad range of voltages from 400 V to more htan 10 kV.The platform encompasses the fabrication and characterization of 8-inch SiC planar MOSFETs, trench MOSFETs, superjunction MOSFETs, and Fin-MOSFETs, with a strong focus on improving device performance, scalability, process integration, and manufacturability on large-area wafers. In addition, the development of 6.5 kV SiC PiN diodes will be presented to address the requirements of high-voltage and high-power systems. Key advances in device architecture, process technology, and electrical performance will be highlighted, demonstrating the potential of 8-inch SiC technology to enable future energy-efficient power conversion systems for automotive, data-center, renewable-energy, grid, and industrial applications.

Biography
Prof. Xiao GONG is currently the Head of Department for Power Electronics in the Institute of Microelectronics, A*STAR, and is concurrently the GlobalFoundries Chair Associate Professor in the ECE Department of the National University of Singapore (NUS). He obtained his Ph. D Degree from NUS in 2023 and was a Visiting Scientist at MIT in the year of 2014. His research interest includes advanced transistors and emerging memories for in-memory computing, ultra-wide bandgap power device technology, monolithic 3D integration, and opto-electronic integrated circuits. He has won many awards, including the Bronze Medal at the 6th TSMC Outstanding Student Researcher Award, the Best Student Paper Award at VLSI Symposium (2017, 2021, 2024, and 2026), the Best Demo Paper Award at VLSI Symposium (2022, 2023, and 2025), the Best Paper Award in EDTM (2025), the Best Student Paper Award at ICICDT (2019, 2021, 2023, and 2024), Emerging Leaders in Journal of Physics D 2021, and NUS Engineering Teaching Excellence Award (2018, 2023, and 2024). He has more than 450 publications in international journals and conferences, including more than 120 papers in IEDM and VLSI Symposium. He has delivered over 40 short courses/tutorial/invited talks in major conferences, including DRC, EDTM, VLSI-TSA, SSDM, ECS, MRS, etc. He is the Technical Program Chair in ICICDT (2019, 2022, 2023, 2024) and Sub-committee Chair in ICICDT (2021) and EDTM (2022, 2023, 2025, 2026, 2027), and in the technical committees of IEDM (2021, 2022), IMW (2025, 2026, 2027), VLSI-TSA (2022, 2023, 2024, 2025, 2026, 2027), ECS (2014, 2016, 2018, 2020, 2022, 2024), ICMAT (2017), EDTM (2017 to 2021), IWJT (2021, 2023, 2025), IRPS (2026, 2027), IPFA (2026), etc. He is the Editor of IEEE Electron Device Letters.

Singapore's Semiconductor Ecosystem: Accelerating Innovation Through Strategic Partnerships

Yee Chia, Yeo
Deputy CEO & EVP SG Semiconductor
A*STAR

Abstract
The semiconductor industry is experiencing an unprecedented acceleration in microelectronic technologies, driven by the explosive growth of artificial intelligence applications. In response, Singapore has launched its SG Semiconductor initiative, building on a globally connected ecosystem to meet the industry's need for multidisciplinary expertise and specialized infrastructure that shortens time to market. This keynote examines Singapore's position as a semiconductor hub, its holistic, ecosystem-based approach, and its role as a technology accelerator across the value chain, from upstream to downstream. It highlights the core technology areas where Singapore is investing billions of dollars. As the global race for semiconductor leadership intensifies, no company, whether a multinational or a small or medium-sized enterprise, can succeed alone. Strong, trusted partnerships across industry, academia, and government are what will turn investment into lasting outcomes. The keynote closes with an explanation on how Singapore is working with partners worldwide to secure the future of the semiconductor value chain.

Biography
Professor Yeo Yee Chia leads Singapore's first RIE Flagship in Semiconductors and is A*STAR's Deputy Chief Executive (Innovation & Enterprise), helping to shape the future of one of Singapore's most strategically important industries. He is also Professor of Electrical Engineering at the National University of Singapore (NUS). An award-winning, internationally recognised semiconductor researcher, Professor Yeo has published over 700 research papers and is an inventor of over 400 US patents. More than 40 PhD students graduated under his tutelage. Recognised with the Singapore Young Scientist Award in 2006 for his research in nanoelectronics and semiconductor devices, Professor Yeo went on to receive the National Research Foundation Fellowship (NRFF) in 2008. The Fellowship enabled him to establish an independent research programme at the National University of Singapore, where he pursued research in strain engineering for next-generation semiconductor manufacturing, deepening his work on transistor technologies aimed at enabling faster and more energy-efficient chips. His research leadership later took him to TSMC, where he served as Director of Research and Development. Working at the forefront of semiconductor innovation, he co-developed TSMC's industry-leading 7 nm, 5 nm, and 3 nm technologies, which have impacted the world in areas such as high performance computing, artificial intelligence, and consumer electronics. Supported under the Returning Singapore Scientists Scheme, Professor Yeo returned to Singapore and joined A*STAR in 2022, bringing with him the experience of translating cutting-edge research into industrial innovation at global scale. Drawing on experience across academia, industry and national R&D, he now leads efforts to deepen Singapore's semiconductor capabilities, accelerate research translation, strengthen industry partnerships and nurture the next generation of scientific talent.

Turning ambition into action across the value chain

Stevenson, Clara
Global Lead for Sustainability Engagement
Atlas Copco Group

Abstract
As sustainability priorities become increasingly central to semiconductor manufacturing, organizations must balance regulatory readiness with business performance and resilience. In this session, Edwards will share how environmental and societal considerations are embedded across its operations, supply chain and technology development including approaches to decarbonization, resource efficiency and safety. The discussion will demonstrate how collaboration drives innovation, strengthens competitiveness and supports customer success.

Biography
Coming Soon

Panelist

Rothrock, Stephen
Founder & CEO
ATREG

Abstract
Panelist

Biography
Stephen Rothrock founded ATREG in 2000 to help the world’s advanced technology companies divest and acquire infrastructure-rich manufacturing assets, including semiconductor wafer fabs (front- and back-end) as well as MEMS, display, solar, and R&D facilities. Over the last 10 years, his firm has completed 70% of all global operational wafer fab sales in the semiconductor industry, with five of these involving 300mm operational fabs. Recent global acquisitions and dispositions have involved Allegro MicroSystems, Bosch, Elmos, Fujitsu, GlobalFoundries, IBM, Infineon, Japan Display Inc., Micron, Nexperia, NXP, onsemi, Plessey, Qualcomm, Renesas, Solidigm, Sony, Texas Instruments, TSI, and Vanguard to name just a few. Prior to founding ATREG, Stephen established Colliers International’s Global Corporate Services initiative and headed the company’s U.S. division based in Seattle, Wash.Before that, he worked as Director for Savills International real estate brokerage in London, UK, establishing their global corporate services platform serving large multinationals, including AT&T, British Telecom, Cisco, Ericsson, and Microsoft, among others. Stephen also served on the UK-listed property company’s international board. He also spent four years near Paris, France working for an international NGO. Stephen holds an MA degree in Political Theology from the University of Hull, UK and a BA degree in Business Commerce from the University of Washington in Seattle, USA.

Panelist

Del Maffeo, Fabrizio
CEO & Co-Founder
Axelera AI

Abstract
Coming Soon

Biography
Fabrizio Del Maffeo is the CEO and co-founder of Axelera AI, the Netherlands-based startup delivering the world’s most powerful and advanced solutions for AI at the Edge. In his role at Axelera AI, Fabrizio leads a world-class executive team, board of directors and advisors from top AI Fortune 500 companies. In 2025 Fabrizio was named in the Top 25 AI CEOs globally, he is a frequent industry speaker, and a sought after expert on decentralized compute. Before establishing Axelera AI, Fabrizio Del Maffeo served as Head of AI at the Bitfury Group, a globally recognized emerging technologies company. Prior to joining Bitfury, Fabrizio was Vice President and Managing Director of AAEON Technology Europe, the AI and internet of things (IoT) computing company within the ASUS Group.

Personal Agents, Collective Resilience: Building Supply Chain Agility with AI.

Onyeka, Thelma
Co-CEO
Beebolt

Abstract
Every so often a supply chain team catches a signal early (a shift in export policy on gallium, or a lead time quietly stretching at a key supplier) and turns it into a decision while there is still room to plan. That is not luck. It is years of industry judgment, and a team that knows how to move together.Across conversations with foundries, IDMs, and equipment makers, Beebolt’s team has found that what the industry wants most is trust, accuracy, and execution. In this session, you’ll learn how Beebolt is bringing those to life with personal AI agents inside Conductor, Beebolt’s intelligence command center for the semiconductor supply chain, built with SEMI. Each agent follows the dependencies one person cares about, raises a flag when a threshold they set is crossed, and helps share it with colleagues in the way each of them prefers to work. Behind every agent sits a multi-agent system, with industry experts reviewing the signals it flags as most important.Personal agents start with one person. Resilience, in our experience, is something an industry builds together. The strongest teams already work this way. What they need are tools that work this way too.We would love to hear how your teams are approaching resilience, so bring your questions to the Q&A that closes the session.

Biography
Talal Abu-Issa is Co-Founder and Co-CEO of Beebolt, the AI supply chain technology company behind the intelligence layer for critical industries. Beebolt built Conductor™, the intelligence layer for the semiconductor supply chain, with SEMI and its Industry Advisory Council, and it is shaped by the companies who use it. Multi-agent AI reads the signals. Beebolt’s analysts and its Fellowship Network of industry experts then add the context and judgment behind them, so leaders get intelligence they can trust, verify, and act on.Talal co-founded Beebolt in 2021 after a career in trading and investment analysis. That background shapes his conviction that the advantage does not go to whoever holds the most data. It goes to whoever connects the right signals early. He is a growing voice on co-intelligence, supply chain resilience, and why AI alone cannot run a semiconductor ecosystem. Talal sits on the advisory board of Akama Fund, a UK-registered charity that makes it easier for organizations to fund higher education scholarships. He holds a degree in Business Administration from Northeastern University and splits his time between the UK and Dubai.

Personal Agents, Collective Resilience: Building Supply Chain Agility with AI.

Abuissa, Talal
Co-CEO
Beebolt

Abstract
Every so often a supply chain team catches a signal early (a shift in export policy on gallium, or a lead time quietly stretching at a key supplier) and turns it into a decision while there is still room to plan. That is not luck. It is years of industry judgment, and a team that knows how to move together.Across conversations with foundries, IDMs, and equipment makers, Beebolt’s team has found that what the industry wants most is trust, accuracy, and execution. In this session, you’ll learn how Beebolt is bringing those to life with personal AI agents inside Conductor, Beebolt’s intelligence command center for the semiconductor supply chain, built with SEMI. Each agent follows the dependencies one person cares about, raises a flag when a threshold they set is crossed, and helps share it with colleagues in the way each of them prefers to work. Behind every agent sits a multi-agent system, with industry experts reviewing the signals it flags as most important.Personal agents start with one person. Resilience, in our experience, is something an industry builds together. The strongest teams already work this way. What they need are tools that work this way too.We would love to hear how your teams are approaching resilience, so bring your questions to the Q&A that closes the session.

Biography
Talal Abu-Issa is Co-Founder and Co-CEO of Beebolt, the AI supply chain technology company behind the intelligence layer for critical industries. Beebolt built Conductor™, the intelligence layer for the semiconductor supply chain, with SEMI and its Industry Advisory Council, and it is shaped by the companies who use it. Multi-agent AI reads the signals. Beebolt’s analysts and its Fellowship Network of industry experts then add the context and judgment behind them, so leaders get intelligence they can trust, verify, and act on.Talal co-founded Beebolt in 2021 after a career in trading and investment analysis. That background shapes his conviction that the advantage does not go to whoever holds the most data. It goes to whoever connects the right signals early. He is a growing voice on co-intelligence, supply chain resilience, and why AI alone cannot run a semiconductor ecosystem. Talal sits on the advisory board of Akama Fund, a UK-registered charity that makes it easier for organizations to fund higher education scholarships. He holds a degree in Business Administration from Northeastern University and splits his time between the UK and Dubai.

Panelist

Huyghebaert, Cédric
CTO
Black Semiconductor

Abstract
Panelist

Biography
Cedric Huyghebaert is currently Chief Technology Officer at Black Semiconductor, a German start-up that aims to develop technology to inspire the semiconductor world to rethink data transfer in advanced computing systems. He got his master degree in Physics from the UGhent. He started in 1999 as a junior researcher in the Materials and Component Analyses group at imec. He received his PhD in Physics in 2006 at the KULeuven in Belgium. In 2005 he joined imecs pilot line as a support integration engineer, especially dealing with the process contamination control. He was part of the packaging group from end 2007 till begin 2010, working as a senior integration engineer dealing with 3D-stacked IC integration. From 2010 to 2019, he led the nano-applications and –material engineering (NAME) group at imec. He guided the transition for 2D materials from lab to fab. From 2019 to 2022 he worked as Program manager of exploratory processes and modules, dealing with material exploration and early module integration for functional applications. He was the technical lead of the 2D experimental Pilot line division in the Graphene Flagship. He (co-)authored more than 250 journal and conference papers.

SiC Update: Technology Changes, Market Outlook & Order Trends

Marchetti, Benjamin
Vice President Engineering Wide Band Gap Semiconductor
Bosch

Abstract
Coming soon

Biography
Coming soon

Beyond Perception: How MEMS Sensors Redefine Our Experience

Domdey, Desislava
Director Sensor Development
Bosch Sensortec

Abstract
What if sensors could not only perceive the world but help define how humans and machines experience it? From wearables and smart devices to next-generation robotics and immersive digital realities, MEMS technology is emerging as a key enabler of future innovation. This presentation discover how Bosch Sensortec’s diverse sensing roadmap combines breakthrough hardware, software, and AI to create tailored solutions for an ever-expanding universe of applications, featuring the latest generation of high-performance IMUs that push the boundaries of motion perception and contextual intelligence. Together, we will explore how tiny silicon structures are becoming the foundation of tomorrow’s connected, intelligent, and increasingly autonomous world.

Biography
Desislava Domdey is Director of MEMS Consumer Sensor Development at Bosch Sensortec, where she leads global teams developing and bringing to scale next-generation Inertial Measurement Units (IMUs).She began her career at Bosch in 2008 as a MEMS design engineer, specializing in modeling and system simulation, and quickly progressed through leadership roles spanning customer projects, application support, and product management in the automotive sector. Today, she combines deep technical expertise with a strong business perspective to drive innovation from concept to high-volume production.Her work focuses on translating cutting-edge MEMS technologies into scalable solutions for real-world applications. A recent highlight is the successful 2024 launch of the world’s smallest accelerometer. Originally from Sofia, Bulgaria, Desislava has lived in Germany since 2001 and resides with her family in Reutlingen.

Europe's Semiconductor Future: Perspectives on Competitiveness

Sah, Nadim
Partner
Boston Consulting Group

Abstract
A perspective on Europe’s semiconductor future, exploring how reinvigorating industrial competitiveness, embracing technological innovation, and making strategic choices can strengthen Europe’s position in an increasingly complex global landscape.

Biography
Nadim is a Partner at the Boston Consulting Group and a core member of its Technology, Media & Telecommunications (TMT) practice, with a focus on semiconductors.Nadim joined BCG in 2015 and has worked extensively in strategy, organization, and go-to-market, as well as transaction-related topics. In his work with semiconductor clients and other tech companies, he often focuses on how to branch into adjacencies, innovate business models, build ecosystems or unlock new pathways through M&A.During his doctoral studies he worked briefly at the CERN (European Organization for Nuclear Research) and at the Deutsche Bundesbank.

Mapping the ETSI Memory-Safety Technical Standard to CHERI

Jenkinson, Graeme

Capabilities Limited

Abstract
Memory unsafety remains the leading cause of exploitable software vulnerabilities across systems software. While mitigations range from probabilistic software and hardware mechanisms to memory-safe languages and formal verification, the security community has historically lacked a common, vendor-neutral taxonomy to evaluate and compare these approaches.To address this gap, ETSI TC CYBER is developing TS 104 198, establishing formal definitions for memory-access models, memory-safety properties, enforcement semantics, completeness, and assurance levels. This talk provides a structured, technical exploration of the standard and its mapping to CHERI architectural capabilities and real-world CHERI platforms:- Introduction & Motivation: An overview of ETSI TS 104 198, establishing why a technology-neutral vocabulary for memory safety is essential for industry procurement and technical roadmaps.- Introduction to ETSI TS 104 198: A deep dive into the abstract memory-access models and core memory-safety properties defined in the standard, including reference, spatial, and temporal safety.- Mapping CHERI Hardware Capabilities to ETSI Properties: A detailed technical mapping showing how CHERI's unforgeable capabilities, approximate bounds, and revocation mechanisms satisfy normative criteria for complete, deterministic memory safety. Known limitations of CHERI against the standards properties will also be presented.- Broader Industry Impact & Future Work: Overview on the envisaged usage of the standard to develop and publish transparent product roadmaps. Brief updates on current work on the draft specification and opportunities to participate in ETSI standardisation activities.

Biography
Graeme Jenkinson serves as Director of Applied Technology at Capabilities Limited, where he has led various projects, such as web-service compartmentalisation and porting the V8 JavaScript Engine and Chromium web-browser to CHERI C/C++ on ARM Morello. Bringing over two decades of expertise across industry and academia, Dr. Jenkinson has previously managed a security research domain at BAE Systems, engineered confidential computing platforms at Apple, and contributed to the DARPA Transparent Computing program while at the University of Cambridge. As an active member of the ETSI TC CYBER memory safety working group (DTS/CYBER-00165 / TS 104 198), he has made significant contributions to specifying the memory-access models, formal property definitions, and vendor-neutral terminology.

Data Enablement as a Business Imperative in Semiconductor Manufacturing

Grafe, Marco
Solution Specialist for Smart Manufacturing
Carl Zeiss Digital Innovation GmbH

Abstract
Data-driven manufacturing, AI, digital twins, and advanced analytics are rapidly becoming key competitive differentiators in the semiconductor industry. Yet many organizations struggle to scale these initiatives because the underlying data ecosystem is fragmented, inconsistent, or incomplete. Structured Data Enablement is therefore no longer optional. It is a business-critical capability and a prerequisite for sustainable operational excellence and future innovation. Based on an ongoing data platform transformation at ams OSRAM, this joint presentation shares how manufacturers can establish a holistic foundation for data-driven production and AI transformation. The session highlights the role of Industrial Data Platforms, the importance of separating data, semantic, and intelligence layers, and the value of a structured, step-by-step transformation approach. Attendees will gain practical insights into the drivers, objectives, challenges, and early lessons learned from building the foundation for scalable analytics, AI, and next-generation manufacturing use cases.

Biography
Dr. Christof M. Schilz is Vice President for Operations Technology at amsOSRAM, where he drives strategic initiatives related to digital manufacturing, automation and AI enablement. His expertise includes manufacturing execution systems, industrial data platforms, data governance, and the enablement of AI and advanced analytics. With more than 25 years of experience in operations, information technology, and quality management across the semiconductor industry, he combines deep technological expertise with a strong understanding of manufacturing processes and operational excellence.Marco Grafe is a Solution Specialist for Smart Manufacturing at ZEISS Digital Innovation, where he coordinates development activities related to Industry 4.0. His areas of expertise include modern manufacturing organizations, industrial data platforms, and digital twins. With more than 15 years of experience in mechanical and plant engineering and project work across the semiconductor, automotive, and pharmaceutical industries, he combines deep technological expertise with a strong understanding of industrial processes.

Coming Soon

Sousa, Veronique
Key Account Manager
CEA-Leti

Abstract
Coming Soon

Biography
Coming Soon

Powering the AI Era in Europe: From Semiconductor Innovation to Global Industrial Impact

Dauvé, Sébastien
CEO
CEA-Leti

Abstract
AI is entering a new era—one where the limits of computing are increasingly defined not only by algorithms, but by the technologies that power, connect and integrate them. The semiconductor industry is at the heart of this transformation. This keynote will explore how breakthrough innovation provided by European RTOs, from advanced silicon to heterogeneous integration and photonics, can unlock the next generation of AI systems while addressing the critical challenges of energy, scale and sustainability. It will also highlight the power of global collaboration to turn rapidly deep-tech innovation into industrial impact and shape the technological foundations of the AI era.

Biography
Sébastien Dauvé was named CEO of CEA-Leti effective on July 1, 2021, after more than twenty years of experience in microelectronics technologies and their applications, including clean mobility, medicine of the future, cybersecurity, and power electronics. Sébastien Dauvé started his career at the French Armament Electronics Center, where he worked on developing synthetic-aperture radar. In 2003, he joined CEA-Leti as an industrial transfer manager and supervised several joint research laboratories, in particular with the multinational Michelin. In 2007, Sébastien Dauvé became a laboratory manager, then head of an R&D department in the area of sensors applied to the Internet of things and electric mobility. During this time, he supported the dissemination of new technologies in industry, including the automotive industry (Renault), aeronautics, national defense (SAFRAN), and microchips with the industry leader Intel. He played an active role in the creation of start-ups in application fields ranging from health to infrastructure security, leading to dozens of new jobs. In 2016, he became Director of the CEA-Leti Systems Division. From sensors to wireless communication, Sébastien Dauvé has played an active role in the digital transformation, focused on coupling energy frugality and performance. He has made cross-disciplinary approaches central to innovation by harnessing the expertise of talented teams with diverse backgrounds. Their goal is to provide technological tools for meeting the major societal challenges of the future. Sébastien Dauvé is a graduate of the French Ecole Polytechnique and the National Higher French Institute of Aeronautics and Space (ISAE-SUPAERO).

HZO ferroelectric thin films and their applications to memory devices

Grenouillet, Laurent
Senior Expert
CEA-Leti

Abstract
The discovery of ferroelectricity in hafnia-zirconia-based (HZO) films, first published 15 years ago, could potentially change the (non-volatile) memory landscape. Indeed, HZO films are ferroelectric in the 5-10nm thickness range allowing low voltage operation, can be deposited in a three-dimensional configuration by Atomic Layer Deposition (ALD) to improve density, and are fully CMOS compatible, which potentially allow their introduction at any technological. In this talk, recent advancements in HZO-based memories will be reviewed, with a focus on FeRAM (Ferroelectric Random Access Memory) highlighting the opportunities but also the challenges at material, integration and design levels. The potential of HZO FeRAM in terms of applications will also be discussed.

Biography
Dr Laurent Grenouillet received the Engineer degree in physics in 1998 from the National Institute of Applied Sciences (INSA) in Lyon, France, and the PhD degree in electronic devices in 2001. From 2001 to 2009 he worked at CEA-Leti on Optoelectronics and Silicon Photonics. In 2009, he joined IBM Alliance in Albany, USA to contribute to the development of FDSOI technology and took part to the FDSOI technology transfer to Global Foundries (22FDX) in 2015. Back in France, he joined the Advanced Memory Device Laboratory at CEA-Leti where he worked on resistive switching memory devices. In 2018 he started to work on ferroelectric HfO₂-based memories (FeCaps, FeRAM, FTJs) and is now leading the Ferroelectric Memory group at CEA-Leti. Laurent Grenouillet authored or co-authored over 110 papers (conferences and journals) and has filed over 60 patents. He also serves as committee member in different memory-related conferences (IRPS, IMW, NVMTS and SSDM).

Opening Remarks by Session Chair

Berger, Pierre
MEMS Business Development Manager
CEA-Leti

Abstract
Coming Soon

Biography
Coming Soon

Opening keynote: Building the Physical Foundations of the AI Era

Tchagaspanian, Michael
EVP, Strategic Partnership
CEA-Leti

Abstract
Coming soon

Biography
Michael Tchagaspanian is now EVP Sales & Marketing at CEA-Leti since 2017. During his last 12 years at CEA-Leti, he launched collaborative programs with industrial partners in the field of smart sensing and imaging , embedded systems and integrated circuits. He manages several strategic developments with US Silicon Valley. Previously, he held the position of Business Development Manager for the Integrated Circuits and Embedded Systems Division, where he was previously head of the Image Sensor Design Laboratory, dedicated to intelligent integrated circuits for imaging applications and display. Advanced algorithms have been created and integrated into the circuit architecture for several applications (defense and security, smart home and building, medical). Prior to CEA, during the previous 11 years in the semiconductor industry, as ASIC design manager for ST Microelectronics and On Semiconductor, he built on-chip integrated circuits for radio frequency and management applications Energy. He has led strategic projects for automotive and mobile phone applications.

Reinventing the AI Compute Engine: Embedded Memory, 3D Integration and Beyond-CMOS Materials

Faynot, Olivier
GM of Silicon Component Division
CEA-Leti

Abstract
Coming soon

Biography
Olivier Faynot received the M.Sc and Ph.D. degrees from the Institut National Polytechnique de Grenoble, France in 1991 and 1995, respectively. His doctoral research was related to the characterization and modeling of deep submicron Fully Depleted SOI devices fabricated on ultrathin SIMOX wafers.He joined CEA (CEA-Grenoble, France) in 1995, working on Partially Depleted and Fully Depleted SOI technologies development in the frame of Industrial Partnerships.From 2008 to 2017, he managed various teams focussed on advanced CMOS, memories and 3D technology integration and was assigned on manufacturing sites to implement FDSOI technologies.During that period, he was engaged in the transfer to production of 28nm and 22nm FDSOI technologies with industrial partners. Those technologies are now available in production.From 2017 to 2019, he managed the Patterning department at CEA-LETI, within the Silicon Technology division.Since 2019, he is managing the whole Silicon Component division at CEA-LETI.He is author and co-author of more than 400 scientific publications in journals and international conferences, and was successively in the committees of the main international Semiconductors conferences like International Electron Device Meeting (IEDM), the symposium on VLSI Technology, the IEEE International SOI conference, the EUROSOI network, the Solid State Device and Materials (SSDM) conference and the International S3S conference.He received the ‘Général Férié’ award in 2012 and the ‘Electron d’Or’ award with CEA-Leti, ST Microelectronics and SOITEC in 2017.He has been elected as an IEEE Fellow in 2024 for leadership in CMOS technology development.

Rewiring AI Systems with Light: Silicon Photonics, Optical Interconnect and Co-Packaged Optics

Fellous, Cyril
GM of Optics and Photonics Division
CEA-Leti

Abstract
Coming soon

Biography
Cyril Fellous has joined CEA-Leti in 2024 as head of Optics and Photonics Division. He holds a PhD and Engineering degree in Physics and material science.Industry, business and technology enthusiast. he has developed a 25 years experience in high tech sector, enjoying many positions from process and Device engineer, R&D manager, quality manager, product and program manager and Business unit Director.Cyril has worked in various semiconductor companies like STMicroelectronics, Teledyne e2v, SOITEC.Cyril’s ambition is to develop long term partnerships, creating business opportunities and being customer focused.Within CEA-Leti he has the chance to lead a team of highly skilled experts and professionals providing breakthrough technologies and solutions to partners.Together we bring high differentiation in the image sensors, optical sensors, Silicon photonics, optical packaging and displays for sensing, imaging, IA, data communication, computing, AR/VR, health and we help our customers to transform these R&D technologies into industrial solutions.

Powering the AI Factory: Advanced Power Delivery, Thermal Management and Packaging

Clermidy, Fabien
GM of System Division
CEA-Leti

Abstract
Coming soon

Biography
Fabien Clermidy is currently heading the system Division of CEA-LETI. He was previously leading the digital architecture and IC design division.The main activities of his division spread from power modules development to hardware cybersecurity, including sensors system design and new telecommunication scheme. The main applicative domains are automotive, factory of future, energy, telecommunications, security and defense.Fabien holds a PhD, a thesis supervisor degree and is a CEA research director. He has published more than 100 papers including in the greatest conferences such as ISSCC, VLSI, DAC, DATE or IEDM. He is also author or co-author of 15 patents. Fabien is in the board of directors of the open Hardware Group leveraging on RISC-V open-source initiative

When Chips Start Talking with Light: Live Journey into Optical Network On Chip

Thonnart, Yvain
Chief Scientist, Digital Integrated Circuits and Systems Division
CEA-Leti

Abstract
Coming soon

Biography
Yvain Thonnart graduated from Ecole Polytechnique and Telecom Paris, France in 2005. He then joined the Technological Research Division of CEA, the French French Alternative Energies and Atomic Energy Commission, within the CEA-Leti institute until 2019, then within the CEA-List institute. He has led the development of several large research projects for on-chip communications, focusing on the maturation of novel concepts towards industrial adoption, such as communication between multiple voltage and frequency domains, 3D-stacked circuits, and optical on-chip interconnects. He is now a CEA fellow, and chief scientist for the digital ICs and systems division of CEA-List.

Inside the Drone Brain: Sensing, Positioning, Connectivity and Cybersecurity for Trusted Autonomy

Despesse, Philippe
Deputy Director of Programs, Systems Division
CEA-Leti

Abstract
Coming soon

Biography
Philippe Despesse is Industrial Partnerships Manager at CEA-Leti, bringing more than 25 years of experience across semiconductor technologies, product development, system innovation and industrial partnerships. He began his career at STMicroelectronics and ST-Ericsson, where he held engineering, marketing, business development and strategic partnership roles. Since joining CEA-Leti in 2015, he has contributed to technology programs spanning power electronics, energy management, connectivity, sensing and hardware cybersecurity. His work focuses on bridging semiconductor innovation and industrial applications, with a particular interest in next-generation drones, aerospace, mobility and autonomous systems, where efficiency, connectivity, sensing and security are key enablers.

Closing keynote: RESOLVE: Engineering Sustainable Compute for Europe

Lequepeys, Jean-René
CTO
CEA-Leti

Abstract
Coming soon

Biography
Jean-René Lèquepeys received an engineering degree in 1983 from CentraleSupélec, a top French graduate engineering school at Paris-Saclay University, France. He taught physics during 2 years in Ouarzazate, Morocco.He joined CEA, a French Research and Technology Office focusing on applied research, in Paris Saclay in 1985. He first worked at the laboratory of the Central Security Office, on the evaluation of means of detection and intrusion. Two years later, he was promoted head of this laboratory.In 1993, he moved to Grenoble, France, and joined the System Division of CEA-Leti. He worked on different projects in the field of image processing and telecommunication technologies. In particular, he was responsible for the "Telecom, Communicating Objects and Smart Card" programs from 1999 to 2004.In 2005, he took the responsibility of the Circuits Design Division at CEA-Leti (200 people). He launched new research activities at CEA such as a new laboratory in Aix-en-Provence, France, on the development of secured chips. In 2000, Jean-René Lèquepeys received the prestigious award from the french Société de l'Electricité, de l'Electronique et des technologies de l'information et de la communication (SEE) "Grand Prix de l'électronique Général Ferrié" for his work in the telecommunications field (he holds 15 patents).In 2010, he launched a new division at CEA focusing on Electronic Architectures, Integrated Circuit Design and Embedded Software. He established the structure on two sites (Paris and Grenoble) and led the division twice in his career.He rapidly got involved in the creation of the Silicon Components Division at CEA-Leti, and took the lead of it in 2011 managing 350 people. Division encompasses micro and nanoelectronics (SOI, nanodots, quantum, memories, 3D technologies, substrates), Micro Systems (sensor, actuator, radiofrequency components) and Power Components. He established the French Nano2022 Program for research funding in microelectronics.In 2019, he was appointed Chief Technology Officer of CEA-Leti, overseeing Science, relations with the European Commission, Industrial Partnership and Strategic Program Management in the scope of the institute (2,000 people, ~€350m budget). He took the responsibility of the Microelectronic Program at CEA level, spearheading technological and upstream research in the field of semiconductor technologies. For the past 2 years, he has been strongly involved in the CEA-Leti Next Gen FD-SOI project in the frame of France2030 and has played a key role in European chips Act pilot line promoting FD-SOI and Gate All Around technologies.Having dedicated his career to applied research, he is regularly invited as a keynote speaker in international semiconductor conferences.Jean-René is also Vice President of ACSIEL, a professional trade union gathering industrial companies in the French electronic value chain, member of the Board of EPOSS, the European Technology Platform on Smart Systems Integration, a member of the Board of AENEAS, the Association for Europoean NanoElectronics Activities, and an expert consultant for the European Commission and French Research Agency.

Panelist

Paing, Bruno
VP Europe
CEA-Leti

Abstract
Coming Soon

Biography
Coming Soon

Future Standards for Sustainability

Pain, Laurent
Sustainable Electronics Program Director
CEA Leti

Abstract
The semiconductor industry is pivotal for global digital transformation, with the ICT market projected to double by 2030, driven by advancements in AI, 5G, and cloud computing. Ensuring sustainable growth necessitates a transition to more resilient, resource-efficient, and circular manufacturing processes. Key challenges include reducing consumption of water, gas, and critical materials, minimizing the use of PFAS, and enhancing the circularity of effluents and waste.To tackle these challenges, the European program GENESIS, supported by the CHIPS Joint Undertaking and launched in May 2025, brings together 57 partners under the coordination of CEA-Leti. GENESIS focuses on developing and qualifying innovative materials and solutions to optimize resource efficiency, waste management, and the environmental performance of the semiconductor manufacturing value chain. Complementing GENESIS, CEA-Leti is now activating the SUBFAB LABS initiative in collaboration with the International SubFAB Research Labs (ISRL). This initiative aims to transform sub-fabrication operations by enhancing process optimization and end-of-life waste treatment. SUBFAB LABS emphasizes improving material efficiency, abatement strategies, and circular resource management, all while reducing operational costs and environmental impact.Together, GENESIS and SUBFAB LABS exemplify an integrated approach to semiconductor sustainability. They achieve this by replacing hazardous substances, deploying advanced monitoring technologies, optimizing the management of critical materials, and enhancing recycling and circularity. This presentation will show how these programs are paving the way for lower emissions and more sustainable semiconductor manufacturing, potentially guiding the establishment of future sustainability standards

Biography
Laurent Pain is a fellow expert in the field of semiconductors and lithography. He graduated from the Physics-Electronics-Materials engineering school of Grenoble in 1992 and earned his PhD for work on DUV resists. He joined CEA-Leti in 1996 to work on infrared technology. In 1999, he was assigned to STMicroelectronics to introduce 193nm and e-beam lithography new generation equipment.From 2008 to 2014, Laurent led CEA-Leti’s lithography laboratory, later managing business and partnership development for the CEA-Leti Silicon Technologies Division. In September 2023, he became the Sustainable Electronic Program Director, tasked with shaping CEA-Leti’s strategy and programs in eco-innovation and sustainability, building on decades of expertise in semiconductor processes, lithography, and technology leadership across industrial and research collaborations.

Boosting MEMS through technological development: from improved transduction to optomechanics

Sansa, Marc
Project Manager in Optomechanics
CEA, Leti

Abstract
Electrical microsensors (MEMS) have been gaining maturity and performance over the last 40 years, and they are nowadays ubiquitous in our everyday life. Recently, the integration of MEMS with silicon photonics gave birth to optomechanical MEMS (optically transduced microsensors), enabling a jump in performance in terms of readout sensitivity and frequency of operation. This combination opens the door to new sensing paradigms across various fields, and is rapidly maturing in terms of integration.In this talk I will present the advantages of optomechanics for high-efficiency sensing, and showcase how CEA-Leti’s developments have enabled novel applications in fields such as biosensing, environmental and biological monitoring, high-speed atomic-force microscopy (AFM) and precision timing with clocks.

Biography
Marc Sansa received his M.Sc. in Micro and Nanotechnologies from the Universitat Autònoma de Barcelona in 2009 and his Ph.D. in Electronic Engineering from the same institution in 2013. He joined CEA-LETI in 2014 as a research engineer and currently serves as a project manager at the Sensors and Actuators Laboratory. He is an expert in microelectromechanical systems (MEMS) and optomechanics, he has authored over 65 publications and holds more than 18 patents. His research focuses on developing novel MEMS technologies by leveraging multiphysical approaches and collaborative efforts among multidisciplinary teams and experts from diverse fields.

Bridging European Policy and Technical Standardization

Rüddenklau, Uwe

CEN/CENELEC

Abstract
coming soon

Biography
Uwe Rüddenklau is Head of Global Standardization Topics and Director of Standardization at Infineon Technologies AG, a major semiconductor company in Munich. He holds degrees in electrical engineering and marketing, and brings over 30 years of global experience in system engineering, sales, and technical marketing, particularly for RF solutions in consumer electronics and mobile applications. Uwe has held senior positions at Infineon, Lantiq, and Siemens, and actively contributes to international and European standardization bodies like IEC, ISO, CEN, CENELEC, and ETSI, where he chairs the CENELEC Technical Committee for semiconductors and trusted chips (CENELEC TC47X). Uwe is German speaker and expert in the International SDO IEC Technical committee (IEC TC47).He also engages with German government forums, standardization organizations such as DKE/VDE, DIN and industry associations such as BDI, BITKOM, and ZVEI, focusing on technical regulation and standardization for 5G, cybersecurity, and semiconductor technologies.

Panellist - What is missing for CHERI to be widely adopted?

Eftimakis, Mike

CHERI Alliance

Abstract
Panellist

Biography
Mike Eftimakis has an extensive background in the semiconductor and electronics industry with 30 years in senior technical and business roles. He has a rich history of innovation with companies like VLSI Technology, NewLogic, Arm and Codasip, and he started-up and led his own company. where he played pivotal roles in advancing technology and business strategies. His expertise ranges from chip design engineering and system architecture to product and company management, marketing and strategy, making him a key contributor to the growth and success of microelectronics organisations.In parallel to his VP Strategy and Ecosystem role at Codasip, he is the Founding Director of the CHERI Alliance, an industry association dedicated to promoting CHERI technology. This technology addresses the root causes of most current cyberattacks, contributing to a safer and more trustworthy World.

Coming Soon

Kinaret, Jari
Executive Director
Chips JU

Abstract
Coming Soon

Biography
Jari Kinaret was born in Finland and holds M.Sc. degrees in Theoretical Physics and Electrical Engineering from the University of Oulu in 1986 and 1987, respectively, and a Ph.D. in Physics from the Massachusetts Institute of Technology (MIT) in 1992. Prof. Kinaret has worked in various roles at research institutes and universities in Copenhagen, Denmark, and Gothenburg, Sweden. From 2013 to 2023, he served as the Director of the Graphene Flagship, a one-billion-euro research project dedicated to exploring the potential of graphene. In October 2023, Prof. Jari Kinaret assumed the role of Executive Director at Chips Joint undertaking (Chips JU), a European public-private partnership that supports research, development, innovation, and future manufacturing capacities in the European semiconductor ecosystem.

Chips JU as an enabler for Research In Advanced Packaging and 2.5D/3D Heterogeneous Integration

Chichkov, Anton
Head of Programmes
Chips JU

Abstract
Advanced packaging has emerged as a critical route for system scaling beyond monolithic SoC integration. Increasingly, performance, functionality and energy-efficiency gains are delivered through heterogeneous integration, chiplet-based architectures, and package–system co-design rather than transistor miniaturisation alone. In this context, advanced packaging, assembly, test, validation and reliability have become strategic capabilities for Europe’s semiconductor ecosystem.The ECSEL JU and, more recently, the Chips JU have made significant contributions to strengthening Europe’s Electronic Components and Systems (ECS) value chain, from collaborative research and innovation to pilot lines, industrial deployment and technology transfer. Through sustained investment, these programmes have supported the development of European capabilities in design, manufacturing, advanced packaging, inspection, validation, test and reliability, reinforcing Europe’s technological sovereignty and industrial competitiveness.This talk will provide an overview of how the sequence of R&I projects funded by ECSEL and Chips JU progressively contributed to the Europe's capabilities in advanced packaging and heterogeneous integration as well as in the area of validation, test and reliability.The presentation will also highlight the first tangible outcomes of the European Chips Act implementation through the Chips JU, including pilot lines, the Design Platform, Competence Centres, and emerging Quantum Pilot initiatives. Together, these actions are laying the foundations for a stronger European innovation ecosystem and for future industrial competitiveness in advanced semiconductor packaging and integration.

Biography
Anton Chichkov is currently Head of Programmes at Chips Joint Undertaking (Chips JU). Holding a PhD in Computer Science from the Technical University of Lisbon and a background in chip design and design for test, Anton Chichkov brings 37 years of experience in the electronic components and systems (ECS) sector. His career spans roles as a chip designer, test equipment manufacturing, researcher in an RTO, and a decade in semiconductor manufacturing, before joining ENIAC JU and now contribute to shaping Europe’s semiconductor ecosystem through Chips JU.

Europe's first semiconductor VC fund

Kromhof, Rene
Founding Partner
Cloudberry VC

Abstract
Introduction to Cloudberry VC: Europe's First Semiconductor-Dedicated VC FundEurope leads the world in semiconductor research yet captures a fraction of the value when that research becomes a company. Too many promising deep tech teams stall in the gap between the lab and a first commercial cheque, and most generalist funds are not built to underwrite hardware risk on physics, fabrication, and long development cycles.Cloudberry VC was founded to close that gap. As Europe's first venture fund dedicated to semiconductors, photonics, and advanced materials, we back founders at pre-seed and seed, the earliest and hardest stage to fund, and bring deep operator experience and strategic industry partners to help them reach the market. Our strategic LP base includes industry leaders such as GlobalFoundries and Radiant Opto-Electronics, giving portfolio companies direct access to manufacturing expertise, supply chain reach, and commercial relationships from day one.This talk introduces who we are, why a specialist fund matters for European deep tech, what we look for in a team and a technology, and how we work alongside founders from first cheque onward. It is aimed at founders, researchers, and partners building the next generation of European semiconductor companies.

Biography
René Kromhof is Founding Partner of Cloudberry VC, Europe's first venture fund dedicated to semiconductors, photonics, and advanced materials. He brings more than two decades in the semiconductor and consumer electronics industry to backing deep tech founders at the earliest stages.René spent seven years at ASML, where he worked at the heart of the lithography systems that underpin modern chipmaking. He later helped build Heptagon, a developer of optical sensing and micro-optics technology, through to its acquisition by ams AG in 2017. These experiences shaped his conviction that Europe's world-class semiconductor research deserves capital and partners that understand hardware.At Cloudberry VC, René invests at pre-seed and seed in founders building the next generation of European chip, photonics, and materials companies, backed by strategic industry partners including GlobalFoundries. He is based in Helsinki and works with founders across Europe to take ambitious technology from the lab to the market.

Ftrace on CHERI Linux - porting a fairly complex kernel subsystem

Kaiser, Martin

Codasip

Abstract
Codasip have ported the Linux kernel's tracing subsystem to CHERI. This talkprovides an overview of the current status and describes some of the challenges we met along the way.ftrace is another example where software could be ported to cheri withreasonable effort. The CHERI port uncovered several bugs in the existingcodebase.This session aims to raise awareness of the ongoing work and engage the audience for feedback, especially about missing functionality and potentialextensions of tracing for CHERI.

Biography
Martin Kaiser is a senior software engineer at Codasip.As a member of the operating systems team, he works on porting the Linux Kernelto CHERI. He has also contributed to the CHERI version of Qemu.

Valid, In-Bounds, and Wrong: Analysis of Fault Injection Attacks Against CHERI Capabilities

Thoma, Jan Philipp

Codasip

Abstract
Memory-safety vulnerabilities remain the root cause of a large share of real-world exploits, and CHERI (Capability Hardware Enhanced RISC Instructions) has become one of the most promising hardware answers, attracting significant interest from academia and industry. Against the software attacker it was designed for, CHERI's capability mechanism works nicely. Deployed devices, however, are frequently physically accessible, and a physical attacker can inject faults that go well beyond the fault model assumed during CHERI's development. Memory safety and fault resistance are orthogonal properties, which raises the question of whether CHERI's guarantees survive a fault attacker at all.We present the first systematic fault analysis of CHERI on RISC-V systems. We examine how instruction skips and bit flips affect capabilities and capability management instructions, and our threat analysis identifies which parts of the capability encoding are attractive targets and where the architecture already constrains the attacker. To evaluate generic CHERI-RISC-V systems, we built a functional fault simulator on top of Spike. With it, we demonstrate faults that violate CHERI's memory safety guarantees in simulation, and we assess countermeasures ranging from error-detecting capability encodings to fault-resistant control flow, including what each costs an implementer.

Biography
Jan Philipp ThomaJan Philipp Thoma is a security engineer at Codasip, where he works on CHERI-enabled RISC-V processor IP. His role includes threat modeling, supporting the architecture definition, and microarchitectural security analysis, with a current focus on the security properties of out-of-order cores that support capability-based memory safety.He received his doctorate from Ruhr University Bochum in 2024 under the supervision of Tim Güneysu, with a dissertation on hardware designs for secure microarchitectures. His research sits at the intersection of capability security, microarchitectural attacks, and hardware fault injection. His published work centers on cache and TLB side channels, transient execution attacks, and on architectural defenses against them.Maja MalenkoMaja Malenko works on CHERI RISC-V and microarchitectural security at Codasip. She is a CHERI Alliance Ambassador, and previously researched fault injection, side-channel attacks, and fine-grained memory isolation for embedded systems.Yan YanYan Yan works on CHE security at Codasip. Before joining Codasip, he worked as a researcher on cryptographic implementations focusing on side channel analysis.

CHERI Specification and Standardisation Update for RV64Y, RV32Y and CHERIoT

Kurd, Tariq

Codasip

Abstract
This talk will give the status of the standardisation process in RISC-V.It will cover the RV64LYA base ISA for Linux-capable application cores, and also RV32LYA for general purpose micro-controllers and embedded cores, and the highly specialised CHERIoT format.It will also include details of future extensions which are planned to improve the performance and/or security of RV64LYA cores.The talk will be written shortly before the deadline to relect the current status.The intention is to announce a ratification date of the RV64LYA base ISA and the relevant profile in the spring of 2027, and that the specification is already in a frozen state with upstreamed toolchains, simulators and tests etc. available for public use.

Biography
Tariq is Chief Architect and is a Distinguished Engineer at Codasip. He has over 30 years of experience in the silicon industry, and has worked for major companies such as NVIDIA, Broadcom, Huawei, and STMicroelectronics. He is an active participant in the RISC-V standards body, and a TSC member. He has ratified multiple RISC-V extensions. He has spent 5 years working on CHERI and aims to bring memory safety to mainstream computing.

Building Memory Safety into a DMA Engine with CHERI

Fletcher, Ben

Codasip

Abstract
DMA engines read and write memory independently of the CPU, and conventionally rely on an external mechanism - like an IOMMU - to police what they're allowed to touch. History shows that boundary is often incomplete, misconfigured, or simply not yet active when it matters, from early-boot DMA to malicious peripherals like those behind the Thunderclap attacks. CHERI takes a different approach: instead of policing access from outside, it makes the constraint part of what's handed to the device in the first place.This talk works through what that shift means in practice, building up from first principles. We start with the simplest possible DMA engine - programme source and destination registers, kick it off, wait for an interrupt - and show what changes when capabilities replace raw addresses: how they're delivered to the engine, how the engine constrains its own accesses to what it was given, and how cleanup on completion helps to deliver temporal safety. We then repeat the exercise for a more realistic engine driven by a linked list of descriptors, where the capabilities themselves must be chained safely through memory the engine doesn't fully control.Finally, we show this isn't just a paper exercise: Codasip is currently developing a CHERI-aware DMA engine internally, supporting both register-based and descriptor-based operation. Ahead of hardware, we've built a QEMU model of the engine, which we're using for early software development and to validate the architecture and software interface before committing to RTL.

Biography
Ben Fletcher is IP Engineering Director at Codasip, where he leads the CPU Core Architecture team and is currently working on architectures for CHERI-enabled out-of-order RISC-V CPU cores. He is also "CHERI in SoC" Work Group Lead at the CHERI Alliance, where his current work focuses on the practical system-level adoption of CHERI technology, including how CHERI-aware processors, interconnects, memories, and peripherals can be integrated into interoperable SoCs. Ben has more than 25 years of experience in semiconductor and SoC development, spanning architecture, design, verification, and software. Before joining Codasip, he held engineering leadership roles at Sondrel, an engineering management role at Imagination Technologies, and technical roles at Broadcom and Oxford Semiconductor.

AI-Powered X-ray Inspection for Advanced Packaging at Scale: Insights from Glass Panel and Wafer Inspection

Malin, Joscha
Director of Product Marketing for Software Solutions
Comet

Abstract
The global demand for high-end computing power, driven by AI, smartphones, IoT applications, high-performance computing, and emerging mobility solutions, continues to grow while simultaneously facing increasing miniaturization requirements. The semiconductor industry is urgently addressing these challenges through innovations such as advanced packaging, which in turn create new inspection requirements.As a result, the need for process control information is becoming increasingly critical to accelerate the introduction of new process nodes and products. At the same time, advanced packaging manufacturers are seeking non-destructive, automated inspection solutions that are fast enough to provide value within production environments, helping to increase yield and reduce waste at an early stage.This presentation will demonstrate how X-ray inspection, combined with AI-driven image analysis, can provide the critical process and quality data required for a wide range of advanced packaging applications involving glass panels and wafers.

Biography
Joscha Malin is the Director of Product Marketing for Software Solutions at the Systems Division of Comet that specializes in supplying X-ray and CT inspection solutions with a particular focus on the Semiconductor R&D and production sectors. In his role, Joscha oversees the division's software product portfolio, with the goal to enhance customer productivity by automation and empower them by data-driven insights derived from X-ray and CT image data. Joscha started his career with an Engineering diploma in Microelectronics from the Technical University Hamburg-Harburg. Over the years, he has worked in multiple roles within R&D in Semiconductor frontend design and system architecture, and within product management, with a consistent focus on image processing solutions.

SWIR Illumination for Sub-Surface and Backside Inspection in Advanced Packaging Metrology

Stacey, Duncan
Business Development Manager
CoolLED

Abstract
As advanced packaging continues to increase in complexity, optical inspection and metrology are facing new challenges in detecting defects hidden beneath the surface or on the backside of packaged assemblies. Conventional visible-light imaging often lacks the contrast and optical penetration needed to reliably reveal these defects, particularly in the presence of dense structures, mixed materials, and highly reflective interfaces.This presentation will discuss the role of short-wave infrared (SWIR) illumination in improving inspection and metrology capability for advanced packaging applications. In particular, it will examine how wavelength selection, angular illumination, polarization, and etendue influence image formation, optical throughput, and defect visibility. These factors will be considered in the context of common advanced packaging structures such as hybrid bonds, redistribution layers, micro-bumps, through-package features, and heterogeneous integration assemblies.The talk will describe how SWIR-based illumination can support both defect detection and quantitative metrology by improving contrast for sub-surface and backside features, enabling more robust segmentation and feature extraction, and improving measurement repeatability across different package materials and geometries. Practical considerations for calibration, system integration, and reproducibility will be addressed.Overall, the presentation will highlight how SWIR illumination can extend the reach of optical inspection and metrology in advanced packaging, increasing the visibility of defects that are otherwise difficult to detect using conventional imaging methods.

Biography
Gerard Whoriskey is the Chief Technology Officer at CoolLED, a position he has held since the company’s founding over 20 years ago. With a background in Electronic Engineering, Gerard’s journey into photonics began during a university KTP project investigating LED technology, the outcomes of which were instrumental in the formation of CoolLED and the introduction of the first commercial LED illumination solution for scientific applications. Over the course of his career, he has developed deep expertise spanning both electronics and optics, positioning him at the forefront of LED-based illumination innovation.

WalTIS: Wafer-Level Thermal Integration for Advanced Semiconductor Packaging

van Geelen, Andre
CTO
CoolSem Technologies

Abstract
The continuous increase in power density in modern semiconductor devices is placing unprecedented demands on thermal management at the package level. In RF, photonics, power electronics and compute, local power densities exceeding 10 W/mm² are increasingly common, while conventional substrates and package architectures often introduce thermal bottlenecks that limit device performance, reliability, and achievable integration density. Addressing these limitations requires a shift from package-level heat removal to thermal path engineering directly at the wafer level.CoolSem introduces a packaging approach in which the thermal management of semiconductor devices is addressed at the wafer level rather than only during package assembly. The concept focuses on integrating a thermally optimized carrier and insulating stack directly beneath active semiconductor layers, enabling efficient heat spreading while maintaining electrical isolation and compatibility with standard semiconductor fabrication processes.A central element of the CoolSem technology platform is WalTIS (Wafer-level Thermal Integration Stack), an integration architecture that combines a thermally conductive carrier with an electrically insulating layer stack to create a high-performance thermal path directly beneath active devices. WalTIS significantly shortens the thermal path between device junction and the heat-spreading substrate. Thermal modelling indicates that the WalTIS architecture can achieve up to a 10× reduction in junction-to-heatsink thermal resistance compared to state-of-the-art approaches based on thinned GaAs or GaN substrates mounted on regular heat spreaders. WaLTIS maintains electrical isolation and wafer-level manufacturability. The concept is compatible with a range of semiconductor technologies, including III–V RF devices, photonic components, and other high-power and high performance compute semiconductor platforms.From a packaging perspective, WalTIS represents a new class of engineered carrier in which conventional semiconductor substrates are replaced by a thermally optimized integration stack. This architecture enables improved heat extraction while preserving mechanical stability. By relocating key thermal management functions from the package level to the wafer level, the approach opens new integration strategies for high-power semiconductor systems.

Biography
Dr. André van Geelen has a PhD in Physics and is an experienced executive in the semiconductor and mobile markets. After several roles at Philips and JDS-Uniphase, he was part of the management team of the high tech startup III-V Photonics around 2000. In 2007, he founded EPCOS Netherlands via a spin-out from NXP semiconductors to generate antenna tuners for mobile. This company was acquired by Qualcomm in 2014. From 2015 onwards, he supported high tech start- and scale-ups in finding their strategic direction, acquiring startup capital and in building the company team and culture. In 2025, he recognized increasing issues around thermal management of high power chips and together with his co-founders started CoolSem Technologies.

Session Chair

de Koning Gans, Jan
Business Development Director
Cosmic Services

Abstract
Coming Soon

Biography
Coming Soon

The First Domino: How India Became the Launchpad for Micron Assembly & Test Modernization

Lobo, Francisco Almada
CEO
Critical Manufacturing

Abstract
Micron's India Assembly & Test facility was more than a greenfield manufacturing investment. It became the catalyst for a new, globally integrated approach to manufacturing transformation, establishing the foundation for future Assembly & Test operations worldwide.This session will explore how Micron leveraged the opportunity to design a modern digital manufacturing ecosystem from the ground up, connecting product lifecycle management (PLM), global master data authoring, automation, analytics, and operational processes around a manufacturing execution core built on Critical Manufacturing MES, unifying them into a single, scalable framework. Rather than deploying isolated solutions, the program adopted an end-to-end strategy that enabled common standards, accelerated deployment, and ensured consistency across the manufacturing value chain.Attendees will learn how India served as the proving ground for this vision, demonstrating how a globally aligned digital architecture, with a modern MES as the execution layer of the digital thread, can shorten time-to-ramp, improve operational readiness, and create a repeatable blueprint for future Assembly & Test expansion. The session will share key lessons learned from implementing a unified digital thread that connects engineering, manufacturing, and operations while balancing global governance with local execution.Key Takeaway: Modernizing manufacturing is not about deploying a new MES or automating individual processes. It is about establishing an integrated digital foundation that enables scalability, standardization, and agility across the enterprise.

Biography
Didier Chavet is the Senior Director and Global Head of Manufacturing IT at Micron Technology, leading the strategy, delivery, and operations of Manufacturing IT capabilities supporting Micron's worldwide semiconductor manufacturing network. With more than two decades of experience in the semiconductor industry, he is responsible for the technology platforms and operational systems enabling highly automated front-end and assembly & test manufacturing across Micron's global factories.Throughout his career at Micron, Didier has been at the forefront of digital transformation initiatives that have significantly advanced manufacturing automation, operational excellence, and factory intelligence. He played a pivotal leadership role in the development of Micron's vision for highly autonomous "Lights Out" manufacturing operations, helping drive the integration of advanced automation, manufacturing execution systems, and data-driven decision-making capabilities across the company's assembly and test operations.More recently, Didier has been leading Micron's Assembly & Test (AT) Modernization Program, one of the company's most strategic manufacturing transformation initiatives. This program is reimagining the technology foundation of Micron's Assembly & Test network through modernization of manufacturing platforms, standardization of global processes, and adoption of next-generation digital capabilities that improve scalability, resiliency, and operational agility.A strong advocate for innovation and emerging technologies, Didier also drives the incorporation of Artificial Intelligence and advanced analytics into manufacturing operations. Under his leadership, Manufacturing IT has accelerated the use of AI-powered solutions to enhance operational efficiency, predictive decision-making, automation, engineering productivity, and factory intelligence. His focus is on transforming data into actionable insights while enabling smarter, more autonomous manufacturing ecosystems.Having lived and worked across Asia, North America, and Europe, Didier brings a global perspective to technology leadership and organizational transformation. His international experience, coupled with deep expertise in semiconductor manufacturing and digital innovation, enables him to lead diverse global teams while delivering large-scale business and technology transformations that support Micron's continued growth and competitiveness.Francisco Almada Lobo is recognized as a top strategic thought leader and evangelist on digital transformation, specifically Industry 4.0, manufacturing operations and the factories of the future. He holds an MBA and an Electrical Engineering Degree from the University of Porto. He started his career in a CIM R&D Institute and joined Siemens Semiconductor in 1997. Throughout his tenures at Siemens, Infineon and Qimonda, he specialized in optimizing highly complex, discrete manufacturing operations. In 2004, he led the first migration of an MES system in a running high-volume facility. Francisco Almada Lobo holds various positions within the smart manufacturing and venture capital industries, including being a Member of the 200M Fund's Investment Committee, Executive Committee Member of SEMI Smart Manufacturing Technology, Member of the Forbes Technology Council and Advisor to many Industry 4.0 startups. Francisco Almada Lobo co-founded Critical Manufacturing in 2009 and has been CEO since 2010.

From Insights to Impact: Simulation-Enabled Determination of Actionable Fab Enhancement Measures

Lendermann, Peter
Chief Business Development Officer
D-SIMLAB Technologies Pte Ltd

Abstract
Bosch's 300 mm Dresden semiconductor fab is characterized by a highly diverse mix of ASICs, MOSFETs, and MEMS products in ramp up. This creates a production environment in which equipment and process releases as well as performance improvements constantly reshape factory capacity and performance. In such an environment, accurate prediction of wafer output and cycle time is challenging.In this presentation, we will describe how fab simulation overcomes this challenge by providing a digital twin of the dynamic production environment that can not only predict future performance but also explain it. By revealing the process steps, equipment groups, and operational constraints that limit factory performance, it makes current and future bottlenecks transparent. This enables derivation of actionable insights. Identified bottlenecks directly translate into targeted improvement measures whose impact on wafer output and cycle time can be quantified before implementation. Measures with the highest operational benefit can be prioritised accordingly. As such, by connecting forecasts, bottleneck identification, and actionable measures, fab simulation becomes the key enabler of continuous operational improvement. In this way simulation evolves from a forecasting tool into a decision support system that systematically drives wafer output growth and cycle time reduction throughout the fab ramp up.In the presentation, we will also describe how this has been realized jointly by Bosch and D-SIMLAB through the deployment of the D-SIMCON Dynamic Capacity and Material Flow (DCMF) Planner, the flagship module of the AI-enabled D-SIMCON Digital Twin suite for Semiconductor Manufacturing, and the kind of benefits that have been achieved so far.

Biography
Peter Lendermann is a Co-Founder and serves as the Chief Business Development Officer of D-SIMLAB Technologies, a Singapore-headquartered company providing AI-enabled, simulation-based decision support solutions for Capacity Planning and Production Flow Optimisation to Semiconductor Manufacturing companies. Prior to this he worked at the Singapore Institute of Manufacturing Technology where he led related R&D activities until spinning them off into D-SIMLAB. Peter has been engaged in the field of production logistics, supply chain management and related decision support technologies and solutions since the early 1990’s. He holds a PhD in Physics from Humboldt University in Berlin (Germany) and an MBA in International Economics and Management from SDA Bocconi in Milan (Italy).Korbinian Behrens specialises in capacity planning and fab optimization at the Bosch semiconductor fab in Dresden, Germany. Responsible for fab simulation in a 300 mm high-mix manufacturing environment, he develops simulation-based decision support capabilities for capacity planning, production flow optimisation and operational performance improvement. His focus is on applying simulation and data-driven methods to support manufacturing decisions and identify improvement opportunities across semiconductor production. He holds a German Diploma in Business Information Systems.

Platform Based Design Technology Co-optimization using 3DEXPERIENCE PLATFORM

Joshi, Smriti
Senior Manager Technical Solution - Semiconductor Industry
Dassault Systèmes

Abstract
Design-to-Technology Co-Optimization (DTCO) is a critical strategy for maximizing the performance, power, and manufacturability of semiconductor devices as process nodes continue to shrink to Angstrom era. DTCO involves the simultaneous optimization of both the design and technology parameters, ensuring that the design is well-aligned with the limitations and opportunities of the manufacturing process. This approach addresses the challenges of advanced semiconductor nodes by leveraging process-specific insights, such as Design for Manufacturability, Design for Testability, and Design for Yield. A platform-based DTCO framework further enhances these benefits by providing a unified environment that connects process technology development, simulation with requirements and manufacturing. Accurate CMP simulations are critical elements for DTCO. In this paper we will show how Chemical Mechanical Planarization can be improved using simulation.This paper further illustrates how the entire CMP environment can be visualized, modeled, and simulated within a unified platform, the 3DEXPERIENCE platform. The platform enables sustainable business innovation with systems engineering approach that integrates requirements, design, simulation, and manufacturing on a single platform. By connecting all stages of the development process, it enhances collaboration, ensures traceability, and enables faster, more efficient product realization. The platform-based design technology co-optimization approach brings following values1.Streamline BOM Management: implement strategies to efficiently manage and update Bills of Materials (logical, engineering, manufacturing, and process BOM), ensuring alignment with design changes and facilitating seamless integration with manufacturing processes 2.Accelerate Time-to-Market: through early-stage simulations and optimizations, reduce the risk of costly design iterations, thereby shortening development cycles and expediting product delivery 3.Enhance Design Robustness: utilize CMP modeling and simulation to predict and mitigate potential manufacturing defects such as dishing and erosion, ensuring that designs are resilient to process variations 4.Optimize Layout Efficiency: leverage DTCO principles to refine layout patterns, improving performance, power, and area (PPA) metrics while adhering to advanced process design rules. By providing such platform for DTCO improves cooptimization efficiency and accelerates advances node design innovation.

Biography
Smriti is currently working as a Solution Experience Senior Manager for Semiconductor Industry (High-tech) with Dassault Systèmes leading solution strategy. Prior she was responsible for understanding, consolidating and driving semiconductor technical solutions. She develops new solutions and provide enablement worldwide for semiconductor customers. She has over 14 years of R&D experience working with different foundries ST Microelectronics, Altis Semiconductor, X-FAB and research lab like CEA –LETI and Lip6 (U.P.M.C.).She received her Doctoral (Ph.D) degree in Nanoelectronics and Nanotechnolgy from INP Grenoble (France) in 2013.Manuel Joined Dassault Systèmes in 1986 and based in France. He is working as Semiconductor Industry Solution Experience Director. He brings over 35+ years of experience supporting Dassault Systèmes’ global customers in high-tech and automotive markets.He held various positions of responsibility in the development of Dassault Systemes solutions dedicated to the Electronics and semiconductor industry. Since 2011, he’s been in charge of the High Performance Semiconductor Solution Experience, dedicated to creating Virtual Twins of semiconductor devices.

Future Standards for Emerging Technologies, tbc

Ishihara, Ryoichi

Delft University

Abstract
Coming soon

Biography
Coming soon

Designing Sustainable, Energy-Efficient and High-Performance Semiconductor Fabs

Turtschan, Silvia
Dipl. Ing. (FH), Director
Drees & Sommer SE

Abstract
The performance of a semiconductor fab is shaped long before production begins. Early decisions on factory layout, utilities, energy and resource concepts, modularization, automation and future expansion determine how efficiently and resiliently a fab can operate throughout its lifecycle.This keynote explores an integrated approach to designing sustainable, energy-efficient and high-performance semiconductor fabs. It demonstrates how sustainability and operational efficiency can be embedded into fab planning through resource-efficient utility concepts, modular and scalable design, digital twins, automation and data-driven optimization. Particular attention is given to anticipating future disruptions, capacity expansions, changing equipment requirements and the challenges of both greenfield and brownfield environments.By considering the fab as an integrated production system from the outset, sustainability, cost efficiency, operational performance and long-term adaptability can be addressed together rather than as separate objectives.

Biography
coming soon

Application of Underfill and Benzocyclobutene in Advanced Flip Chip Technology for Packaging and Reliability in Terrestrial and Space Environments

Sur, Rajesh
Staff Product Engineer
Elevate Semiconductor

Abstract
Flip-chip technology is increasingly popular due to its low parasitics and compact package size, especially as traditional wire-bonded packages introduce higher parasitics. With the rise of artificial intelligence and the deployment of data centers in space, advanced packaging is essential for withstanding extreme atmospheric conditions and ensuring long-term reliability. Traditional flip-chip packaging has used both thin and thick polyimide, but both are prone to cracking over time. Benzocyclobutene (BCB) offers superior stress resistance and does not crack, making it a more reliable alternative. Effective use of BCB requires a tri-metal or under-bump metallurgy (UBM) layer; in my process, I used titanium, copper, and titanium, followed by BCB to open the vias for solder bump attachment. This paper outlines the BCB curing procedure, including the application and curing time before solder bumps are formed by electrochemical deposition. Electrochemical deposition is preferred because it produces more robust solder bumps than stenciling, which can fail during high-temperature operating life (HTOL) or temperature cycling. While some use reballing to continue testing, this is not standard practice in the Aerospace and Defense industry. The combination of BCB and UBM ensures solder balls remain secure during reliability stress testing.Solder bump composition is critical for process robustness. This paper provides a detailed analysis of the solder bump materials required to withstand the extreme conditions found in Aerospace and Defense applications. As data infrastructure expands into space, selecting the appropriate solder bump composition, BCB, and underfill materials is essential for long-term chip reliability. One of the main challenges for integrated circuit chips in space is the stress caused by angular velocity and momentum. This paper details the entire flip-chip process, including the use of Dexter Hysol, which helps maintain solder bump reliability under these conditions. I have conducted extensive HTOL and temperature-cycling tests in accordance with MIL-STD-883 standards, with tests running for over 4000 hours without any damage to the flip-chip structure.

Biography
Rajesh Sur is a Senior staff product engineer with Elevate Semiconductor. He earned a B.S.E.E. degree from MIT Manipal, an M.S.E.E. from University of Arkansas, Fayetteville, and an M.B.A. degree from Wake Forest University. Rajesh is a senior member of the IEEE. He currently holds 868 worldwide patents and is one of the most prolific inventors in the state of North Carolina He is the author of eleven technical books. Rajesh has 23 years’ experience as a senior product engineer, senior packaging engineer, and product engineering manager having previously worked at Texas Instruments, Freescale Semiconductor, Analog Devices and Qorvo.

Materials Matter: Enabling Advanced Packaging Performance at Scale

Parry, Gilbert
Director | Advanced Innovation & Technology
Entegris

Abstract
As advanced packaging becomes the primary path to system-level performance, success increasingly depends on how well materials and interfaces are controlled throughout the integration flow. The shift to heterogeneous integration, high-density interconnects, and advanced bonding schemes places new requirements on material purity, stability, and interaction at various technology nodes.Performance is now tightly linked to interface integrity, where contamination, defects, or variability can directly impact yield and long-term reliability. At the same time, increasing thermal loads and new architectures require materials with enhanced thermal conductivity, electrical performance, and compatibility with emerging integration schemes.Scaling these technologies from development to high-volume manufacturing introduces additional challenges in handling, cleaning, planarization, and process consistency – particularly with the transition toward larger formats such as panel-level packaging.Entegris supports this evolution through materials-driven solutions and process-enabling technologies spanning Cu deposition, cleaning, CMP, high-viscosity material handling, thermal management, contamination control, and filtration – ensuring that performance achieved at the design stage is preserved through industrial-scale manufacturing.

Biography
Gilbert Parry joined Entegris in 1995 as an application engineer in its semiconductor business. He then held various technical and product management positions in gas purification, liquid and specialty chemicals filtration.Over the past 20 years, Mr. Parry has been responsible for cross-divisional Business Development activities in a variety of industries, including energy production and storage, graphic arts, water treatment or life sciences. Now involved in analyzing semiconductor technology trends to guide the company's investments and research directions, M. Parry explores the opportunities presented by the most critical applications of Advanced Packaging, particularly those requiring new materials.Mr. Parry is a graduate engineer (Master of Science) in chemistry, polymers and materials from ECPM, Strasbourg, France.

Panel Discussion Moderator

Yang, Wenge
VP of Marketing
Entegris Inc.

Abstract
Panel Discussion Moderator

Biography
Wenge Yang, Ph.D.Vice President, Market StrategyDr. Yang joined Entegris in 2012 to serve as leader of Entegris Market Strategy. In his role, he is responsible for product and market strategy, market research and market trend analysis, strategic marketing, and maintenance of the company’s strategic technology roadmap. Prior to joining Entegris, Dr. Yang was an equity research analyst at Citigroup covering the semiconductor equip-ment and materials sector. He also served in various executive roles at Advanced Micro Devices, Tokyo Electron and two start-up companies. Dr. Yang received a Ph.D. in Materials Science and an MBA from Rensselaer Polytechnic Institute, a Master of Science degree in mechanical engineering from the New Jersey Institute of Technology and a Bachelor of Science degree in materials science and engineering from Shanghai Jiao Tong University.

Closing Remarks by Session Chair

Lee, Carlos
Director General
EPIC Photonics

Abstract
Coming Soon

Biography
Coming Soon

Beyond Performance: How the Semiconductor Industry and Ericsson Can Accelerate Decarbonization

Pozza, Genevieve
Networks Sales Strategy Manager & Sustainability Lead
Ericsson AB

Abstract
Artificial intelligence is driving a new wave of infrastructure investment, increasing demand for semiconductors and communications networks.As telecom networks become more energy efficient and operational emissions decline, a larger share of the carbon footprint will come from materials, components, and manufacturing. This makes the semiconductor supply chain an increasingly important part of telecom decarbonization.How can the semiconductor industry and Ericsson work together to reduce these emissions?This session explores practical opportunities how the semiconductor ecosystem can help accelerate decarbonization —from renewable energy and cleaner manufacturing to reliable product-level carbon data and innovation in materials and processes.Addressing these challenges requires collaboration across the entire ecosystem, from semiconductor manufacturers and technology suppliers to telecommunications providers and end customers.

Biography
Genevieve Pozza is a Strategy Manager & Sustainability Lead at Ericsson, where she drives the Business Area Networks environmental sustainability agenda and supports the company's ambition to achieve Net Zero emissions by 2040. Responsible for sustainability strategy execution, governance, performance management, and cross-functional transformation initiatives. With extensive leadership experience spanning strategy, product development, operational transformation, and commercial excellence, Genevieve helps drive the integration of sustainability, technology innovation, and business value creation across Ericsson's Networks operations.

Presentation by Ericsson

Möckelind, Per-Erik
Director of Strategic Technology
Ericsson AB

Abstract
Coming Soon

Biography
Per-Erik Möckelind is Director of Strategic Technology in Ericsson’s CTO Office. He began working with Ericsson in 1993 as a consultant on GSM radio base stations and has since held a range of technical expert and systems leadership roles. His work spans successive generations of mobile networks, including 6G, with a focus on digital hardware architecture for Ericsson’s radio access networks. He also leads engagement with the semiconductor ecosystem to foster joint innovation. Per-Erik holds an MSc from Linköping University and Case Western Reserve University.

Title withheld (paper under submission)

Jordan, Nils

Ericsson Security Research

Abstract
Abstract withheld due to the paper being under submission.

Biography
Nils Jordan is a MSc Cybersecurity student at KTH Royal Institute of Technology in Stockholm, Sweden, where he focuses on cybersecurity and especially software and systems security. He holds a BSc in IT-Security, providing him with a strong background in secure software and system design. During his internship at Ericsson Security Research, he contributed to developing an approach for complete and scalable temporal safety for CHERI application processors. This work introduced him to memory safety research and approaches for achieving memory safety through both software- and hardware-based solutions. His background in cybersecurity, combined with his practical research experience with CHERI, provides a solid foundation for investigating security challenges related to memory safety.

Opening Remarks by Session Chair

Kröhnert, Steffen
President & Founder
ESPAT-Consulting

Abstract
Session Chair

Biography
President & Founder @ ESPAT-Consulting, Dresden, Germany, since 2019, Advisor & Lead Consultant Europe - Advanced Packaging Technology @ Global Electronics Association / IPC, Subject Matter Expert - Advanced Packaging Technology @ SEMI Europe;Until June 2019, worked for 22 years in different Semiconductor Packaging, Assembly, and Test R&D, Engineering, and Management positions at large IDMs and OSATs in Germany and Portugal: Siemens Semiconductors, Infineon Technologies, Qimonda, NANIUM, Amkor Technology;In 2014 founded and since chaired or co-chaired an Industry Interest Group focusing on Packaging, Assembly, and Test manufacturing in Europe,Since 2016: Europe Chapter of SEMI-integrated Packaging, Assembly, and Test (SiPAT / ESiPAT) - Special Interest Group (SIG), later Technology Community (TC), Since 2026: Europe Chapter of Advanced Packaging and Heterogeneous Integration - Technology Coalition (APHI-TC) at SEMI;Authored or co-authored 23 patent filings and many technical papers in the field of Packaging Technology;Co-edited two textbooks about "Embedded and Fan-Out Wafer and Panel Level Packaging Technologies”;Active member of many technical and conference committees of IEEE EPS, SEMI, IMAPS, and EPoSS;IEEE EPS Program Director Region 8 (EMEA) and member of the Board of Governors;Holds an M.Sc. in Electrical Engineering and Micro Systems Technologies from the Technical University of Chemnitz, Germany.

Panelist

Zwegers, Arian
Deputy Head of Unit
European Commission

Abstract
Coming Soon

Biography
Arian Zwegers is the Deputy Head of Unit “Microelectronics and Photonics” at the European Commission, Directorate General for Communications Networks, Content & Technology. He received a Ph.D. from the Eindhoven University of Technology in the Netherlands for his contribution to the system architecting field. After his Ph.D., he worked for the Philips Electronics’ Centre for Manufacturing Technology, Baan Development, and PlatteConsult. In the Commission, he worked on enterprise interoperability, service engineering, the Future Internet Public-Private Partnership, the Digitising European Industry initiative, and now in the microelectronics and photonics area.

Unlocking Public Funding for Strategic Semiconductor Projects

Isabelle, Marc
CEO & Founder
european economics

Abstract
The semiconductor industry is one of the largest beneficiaries of public funding in the EU. This momentum is reinforced by the EU Chips Act 2.0 and IPCEI AST, which place semiconductor technologies and investments at the heart of Europe’s renewed industrial policy. Grants support R&D activities, first industrial deployment of breakthrough innovations, and first-of-a-kind manufacturing facilities across the value chain. Securing State aid and EU funding remains highly competitive and requires a clear understanding of available opportunities, processes and regulations. Based on several use cases, Marc Isabelle’s presentation will provide a practical first dive into public funding opportunities for the semiconductor industry in the EU.

Biography
Marc ISABELLE, engineer and PhD in Economics, is the founder and CEO of european economics.Marc is a recognised expert in the public funding of strategic projects. Since 2009, he has helped 210 companies secure €46 billion in public funding for more than 250 major projects. These initiatives tackle key societal challenges - including disruptive innovation, decarbonisation, resilience and infrastructure - across a wide range of industrial sectors including microelectronics, software, telecoms, automotive, energy and environment, batteries, pharmaceuticals and biotech.Through his extensive work with the European Commission and national authorities, Marc has actively contributed to shaping the methodologies and best practices used to assess public funding applications and their compatibility with EU regulations.

The Future of Europe's Industrial Policy

Haddaoui, Narjiss
Managing Director
european economics

Abstract
Europe is entering a new industrial cycle shaped by AI, computing power and strategic technologies. As globalisation gives way to resilience and sovereignty, semiconductors are becoming a foundation of Europe’s future competitiveness.This keynote will explore how Europe’s industrial policy is evolving to reduce dependencies, accelerate industrial scale-up and open new opportunities for ambitious technology leaders.

Biography
Narjiss Haddaoui is Managing Director at european economics, a leading consultancy specialised in State aid and European funding.A graduate of Paris Dauphine University with a Master’s in International Business, she has worked across aeronautics and nuclear industries before joining european economics in 2018.At european economics, Narjiss leads the firm’s strategic development and international expansion, strengthening its role as a bridge between public policy, finance, and industry.She brings a forward-looking perspective on how Europe can turn public funding into a driver of industrial competitiveness, decarbonisation and sovereignty.

Pantel Discussion Moderator

Schenk, Oliver
Member of the European Parliament, Rapporteur on the Chips Act 2.0
European Parliament

Abstract
Chips Act 2.0 and International Collaboration with Trusted Partners

Biography
As Europe moves towards the implementation of the Chips Act 2.0, strengthening international partnerships will be essential to building a more resilient, secure and competitive semiconductor ecosystem. Europe’s position across the semiconductor value chain depends not only on strengthening domestic capabilities, but also on deeper cooperation with trusted partners, including the US, Japan, Taiwan and South Korea.This session will examine how the Chips Act 2.0 can reinforce Europe’s strategic positioning and translate international partnerships into practical cooperation on supply chain resilience, technology, investment and innovation. It will also explore the role of initiatives such as ICOS in connecting European capabilities with trusted international ecosystems.

Panelist

Uhrmann, Thomas
VP of Sales
EV Group

Abstract
Panelist

Biography
Coming soon.

Leveraging Advanced Bonding Technologies to Enable Scalable Co-Packaged Optics Architectures

Brandl, Elisabeth
Business Development Manager
EVG

Abstract
Heavy data workloads have already driven the deployment of optical interconnects as a practical solution to the limitations of electronic data transfer. Especially with artificial intelligence (AI), the need for efficient data transfer is again immensely increased. Optical interconnects are now used in modern data centers and high-performance systems, enabling high-bandwidth, low-latency, and energy-efficient communication across chips and racks. Supported by advances in silicon photonics and system integration, these optical technologies have become a key enabler for scaling today’s large AI models and infrastructure.In this work, we present an overview of manufacturing approaches for silicon photonic components and their integration into various optical interconnect architectures. A particular emphasis is placed on advanced bonding techniques as an enabler for heterogeneous integration. We examine both die-to-wafer and wafer-to-wafer bonding strategies, highlighting their advantages: die-to-wafer bonding provides flexibility for selectively integrating high-performance components, while wafer-to-wafer bonding enables parallel, high-volume fabrication with improved uniformity and scalability. The discussed bonding technologies include temporary bonding, plasma-activated fusion bonding, oxide-free direct bonding, and hybrid bonding. Such methods enable the integration of diverse material systems, including III–V semiconductors for realizing efficient on-chip light sources, as well as thin-film lithium niobate for high-performance electro-optic modulation. By combining these materials with silicon photonics platforms, it becomes possible to leverage their complementary properties. III–V compounds offer high optical gain compared to Si, and lithium niobate has a high electro-optical efficiency. By integrating different material systems, the functionality and performance of integrated photonic circuits is significantly enhanced.By combining these advanced bonding techniques with scalable process flows, a versatile manufacturing toolbox is established, capable of supporting highly integrated, high-performance optical interconnect systems tailored to the stringent requirements of AI computing.

Biography
Elisabeth Brandl is business development manager at EV Group for temporary bonding and metrology. She holds a Master degree (DI) in technical physics from the Johannes Kepler University Linz specialized on nanoscience and - technology.Since 12 years she works at EVG and was, amongst other topics responsible for the UV laser debonding launch. She published several articles and papers in the field of temporary bonding and metrology.

Semiconductor Supply Chain Planning, Scheduling, and Execution in the Age of AI

Panyard, Crispin
Vice President of Sales Engineering
Eyelit Technologies

Abstract
The Panel will introduce how Melexis is planning their fabless supply chain, and how Lfoundry manages manufacturing execution in their high volume foundry. Eyelit Technologies will give an overview on how Agentic AI is quickly changing semiconductor Planning, Scheduling, and Executrion management. This will be followed by an open discussion where members of the audience can ask questions on the solutions presented, or their companies specific needs. The panel is comprised of Professionals from Melexis, Lfoundry, and Eyelit Technologies

Biography
Crispin Panyard is Vice President of Sales Engineering at Eyelit Technologies, where he leads the global team that shows how Eyelit's manufacturing software solves real production problems for its customers. He joined Eyelit in 2002 and spent nearly 25 years helping turn it from an OEM software supplier into an international leader in manufacturing automation. Over that time he built Eyelit's strategic sales and account management practice and developed its global partner channels. He has worked with leading manufacturers in semiconductor, aerospace and defense, medical device, and electronics, including Lfoundry, Raytheon (RTX), Northrop Grumman, L3Harris, MIT Lincoln Laboratory, Analog Devices, Medtronic, Skyworks, Tower Semiconductor, and Perkin Elmer, and Corning Inc.. Before Eyelit, he held client services, sales engineering, and training roles at Verid Technology and Brooks Automation/FASTech (now Applied Materials), and he has more than 30 years of experience in the industry. He has appeared on CNBC's World Business Review and been published in BusinessWeek and numerous other outlets.

Semiconductor Supply Chain Planning, Scheduling, and Execution in the Age of AI

Hosford, John
Director, Professional Services SIOP-A
Eyelit Technologies

Abstract
The Panel will introduce how Melexis is planning their fabless supply chain, and how Lfoundry manages manufacturing execution in their high volume foundry. Eyelit Technologies will give an overview on how Agentic AI is quickly changing semiconductor Planning, Scheduling, and Executrion management. This will be followed by an open discussion where members of the audience can ask questions on the solutions presented, or their companies specific needs. The panel is comprised of Professionals from Melexis, Lfoundry, and Eyelit Technologies.

Biography
John Hosford is Eyelit Technologies Director, Professional Services SIOP-A, overseeing the division’s; Consulting, Support Services, and Customer Satisfaction. Mr Hosford, with over 30 years of Operations Research experience, has been with Eyelit since 2003 where previously he served as Adexa’s COO responsible for all global operations. Prior to joining Adexa Mr Hosford spent 3 years at Lucent Technologies (OFS) where he was responsible for supply chain systems. Prior to that he retired from a career in the Navy during which he was an instructor at the Naval Postgraduate School specializing in Operations Research and Computer Science. Mr. Hosford holds a M.S. degree in Operations Research and completed all requirements (abd) for a PHD from the Naval Postgraduate School in California. He is also an active member of the Institute of Operations Research and Management Science (INFORMS).

Semiconductor Supply Chain Planning, Scheduling, and Execution in the Age of AI

Jain, Salil
CTO
Eyelit Technologies

Abstract
The Panel will introduce how Melexis is planning their fabless supply chain, and how Lfoundry manages manufacturing execution in their high volume foundry. Eyelit Technologies will give an overview on how Agentic AI is quickly changing semiconductor Planning, Scheduling, and Executrion management. This will be followed by an open discussion where members of the audience can ask questions on the solutions presented, or their companies specific needs. The panel is comprised of Professionals from Melexis, Lfoundry, and Eyelit Technologies.

Biography
Salil Jain is a seasoned technology founder with a proven record of building and scaling advanced manufacturing and smart-factory software solutions, focusing primarily on the semiconductor, precision electronics, and high-tech industries.

Autonomy Needs a Plan the Fab Can Trust: A Live Deployment of Dynamic Capacity Planning at Diodes

Potter, Jamie
CEO & Cofounder
Flexciton Ltd

Abstract
Most autonomous-fab roadmaps focus on data, connectivity, and automation. This talk focuses on decisions. Fab decisions sit in layers by time horizon: capacity planning (months), production planning (weeks), fab-wide scheduling (a day), and toolset scheduling (minutes).Autonomy comes from adding intelligence: connecting the layers, letting optimisation make decisions, with AI removing manual work and people setting objectives. Capacity sits at the top: plan it on static averages and the decisions below inherit the error, however good their optimisation. In a live deployment at Diodes' Greenock fab, a dynamic capacity model replaced the spreadsheet within three months, delivering weekly bottleneck foresight and plans in under an hour, not days.

Biography
Jamie co-founded Flexciton in 2016 and serves as CEO, driving the company's vision to optimise complex manufacturing and enable an autonomous factory. He led the commercialisation of Flexciton's cutting-edge technology within the semiconductor industry and expanded its global customer base across the US, Europe, and Asia. Under his leadership, the solution offering evolved into a comprehensive suite of autonomous technologies for planning and scheduling across front-end and back-end semiconductor manufacturing. Jamie is a founding member of the SEMI Smart Manufacturing Committee for Europe and has represented the UK deep tech sector to the government. An Oxford graduate (top of his year, Mathematics & Statistics), he was named to the Forbes 30 Under 30 list in 2018.

Beyond Glass: Flexiramics for Next-Generation RF and Thermal Substrates

Wynn, Andy
CEO
Flexiramics B.V

Abstract
Recent evaluations and early application trials have demonstrated that Flexiramics®, a European‑developed ceramic microfiber nonwoven reinforcement, can deliver measurable benefits in XY thermal spreading and RF/mmWave stability when integrated into advanced substrate and packaging materials. These results represent a new development in reinforcement architectures for high‑frequency and high‑thermal‑load electronics, offering an alternative to traditional woven glass fabrics.As devices move into the 28–110 GHz domain and thermal densities continue to rise, the limitations of glass‑reinforced dielectrics are becoming more pronounced. Woven glass introduces anisotropy, resin‑rich pockets, and local dielectric variation, all of which can affect signal uniformity and thermal performance. These constraints are increasingly visible in multilayer substrates, advanced packaging, and next‑generation RF systems.Flexiramics addresses these challenges through a continuous ceramic micro‑network that can be incorporated into existing polymer matrices and lamination processes.Recent test data and early customer evaluations indicate three key areas of impact:• XY thermal dissipation - application trials show that the ceramic network supports more efficient lateral heat spreading, helping reduce hotspot formation. This is designed to support improved thermal stability in high‑density architectures• RF/mmWave stability - initial RF measurements demonstrate stable dielectric behaviour across 30–110 GHz, with reduced sensitivity to local reinforcement effects. This is particularly relevant for communication, radar, sensing, and advanced packaging applications• Beyond glass - by eliminating woven‑fabric artifacts, Flexiramics provides a more uniform reinforcement environment. Early evaluations indicate more predictable electrical behaviour across the panel compared to glass‑based systemsBeyond technical performance, Flexiramics contributes to broader European strategic objectives. The platform is developed and manufactured within the EU, supporting regional supply‑chain resilience for advanced materials. Its scalable production approach enables both early‑stage prototyping and industrial‑scale deployment.The presentation will share new evaluation data, application examples, and insights from ongoing collaborations, illustrating how a new reinforcement architecture can help Europe advance toward more capable, efficient, and reliable electronic systems.

Biography
Andy is a technology leader with 30 years’ experience transformingnew technologies into successful global businesses. FormerCTO of Morgan Advanced Materials plc, $Billion FTSE 250multinational. Brings deep expertise in aligning innovationand business strategy across industries and geographies,including 6+ years based in China.​Led commercialization of $2B of new tech sales inrenewable energy, EVs, medical devices, semicon & more​Held senior exec roles (CTO, CEO, Board Director,Programme Director) with responsibility for global P&L,innovation, strategy, and major restructuringprogrammes​Built and scaled businesses internationally: launchedventures across Asia, built factories in China/ME/Asia,turned around US operations, and re-engineeredproduction lines worldwide​Entrepreneurship: Co-Founder of TTIP Talent, TTIPStrategy, PurEmissions, and BLOK Capital​Educator & thought leader: keynote speaker, MBA facultyat IE & Warwick Business Schools, and author ofTransforming Technology into Profit, Cracking theInnovation Code, and Building an Innovation Powerhouse.​

Beyond Glass: Flexiramics for Next-Generation RF and Thermal Substrates

Ivanovic, Ivana
Commercial Manager
Flexiramics B.V

Abstract
Recent evaluations and early application trials have demonstrated that Flexiramics®, a European‑developed ceramic microfiber nonwoven reinforcement, can deliver measurable benefits in XY thermal spreading and RF/mmWave stability when integrated into advanced substrate and packaging materials. These results represent a new development in reinforcement architectures for high‑frequency and high‑thermal‑load electronics, offering an alternative to traditional woven glass fabrics.As devices move into the 28–110 GHz domain and thermal densities continue to rise, the limitations of glass‑reinforced dielectrics are becoming more pronounced. Woven glass introduces anisotropy, resin‑rich pockets, and local dielectric variation, all of which can affect signal uniformity and thermal performance. These constraints are increasingly visible in multilayer substrates, advanced packaging, and next‑generation RF systems.Flexiramics addresses these challenges through a continuous ceramic micro‑network that can be incorporated into existing polymer matrices and lamination processes.Recent test data and early customer evaluations indicate three key areas of impact:• XY thermal dissipation - application trials show that the ceramic network supports more efficient lateral heat spreading, helping reduce hotspot formation. This is designed to support improved thermal stability in high‑density architectures• RF/mmWave stability - initial RF measurements demonstrate stable dielectric behaviour across 30–110 GHz, with reduced sensitivity to local reinforcement effects. This is particularly relevant for communication, radar, sensing, and advanced packaging applications• Beyond glass - by eliminating woven‑fabric artifacts, Flexiramics provides a more uniform reinforcement environment. Early evaluations indicate more predictable electrical behaviour across the panel compared to glass‑based systemsBeyond technical performance, Flexiramics contributes to broader European strategic objectives. The platform is developed and manufactured within the EU, supporting regional supply‑chain resilience for advanced materials. Its scalable production approach enables both early‑stage prototyping and industrial‑scale deployment.The presentation will share new evaluation data, application examples, and insights from ongoing collaborations, illustrating how a new reinforcement architecture can help Europe advance toward more capable, efficient, and reliable electronic systems.

Biography
Andy is a technology leader with 30 years’ experience transformingnew technologies into successful global businesses. FormerCTO of Morgan Advanced Materials plc, $Billion FTSE 250multinational. Brings deep expertise in aligning innovationand business strategy across industries and geographies,including 6+ years based in China.​Led commercialization of $2B of new tech sales inrenewable energy, EVs, medical devices, semicon & more​Held senior exec roles (CTO, CEO, Board Director,Programme Director) with responsibility for global P&L,innovation, strategy, and major restructuringprogrammes​Built and scaled businesses internationally: launchedventures across Asia, built factories in China/ME/Asia,turned around US operations, and re-engineeredproduction lines worldwide​Entrepreneurship: Co-Founder of TTIP Talent, TTIPStrategy, PurEmissions, and BLOK Capital​Educator & thought leader: keynote speaker, MBA facultyat IE & Warwick Business Schools, and author ofTransforming Technology into Profit, Cracking theInnovation Code, and Building an Innovation Powerhouse.​

Opening Remarks

Stephan, Jörg
Project Manager & Research Coordinator
Fraunhofer

Abstract
Coming Soon

Biography
Coming Soon

Novel Semiconductors for future Power Devices

Meissner, Elke

Fraunhofer Insitute for Integrated Systems and Device Technology

Abstract
Power electronics is increasingly shaped by novel semiconductor materials that enable higher efficiency, faster switching, and greater power density. Among these, gallium nitride (GaN) and SiC are already highly relevant for next-generation power devices. Ultra-wide-bandgap materials, are considered the next generation of semiconductor materials, offering even greater potential for advancing power density, high-temperature, and high-frequency opperation, with aluminum nitride (AlN) being an extremly promising candidate. AlN, gaining fast growing attention for future power devices. Although challenges remain, AlN has a strong potential to advance future power electronics and support disruptive innovation beyond GaN and SiC.

Biography
Dr. Meissner is an experienced senior professional active in the field of semiconductor materials development and crystal growth. She brings along a broad perspective across the entire value chain, from materials and device technology to applications in power modules and systems, with a particular focus on ultra-wide-bandgap semiconductor materials.After more than two decades as a researcher, she is today engaged in strategic planning at Fraunhofer IISB and represents the strategic business development for semiconductor materials and technology. At the same time, she is involved in fundamental research as a member of the Chair of Electron Devices at the University of Erlangen–Nuremberg.

Sustainable Microelectronics and the GENESIS project

Osten, Julia
Research Manager
Fraunhofer IPMS

Abstract
Sustainable microelectronics requires resource-efficient semiconductor manufacturing and circular process concepts. The goal of the Chips-JU project GENESIS is to develop new solutions for implementing such measures in European semiconductor factories. Activities by the consortium include reducing material consumption in wet processing and lithography, replacing critical materials, lowering process emissions, improving equipment energy efficiency, and developing greener manufacturing technologies. Recent results obtained by Fraunhofer IPMS together with other project partners include PFAS removal from wastewater, recycling of CMP slurries to reduce fresh material consumption, and recovery of high-purity solvents for reuse in semiconductor production. Together, these approaches support a more sustainable and resilient European semiconductor industry.

Biography
Julia Osten is a research manager working in Business Development at Fraunhofer IPMS in Dresden. She has been with the Fraunhofer-Gesellschaft since 2018, after previously working at HZDR. She has a PhD in Physics. Her work combines research management, strategic development and collaboration, with activities spanning topics such as microelectronics and resource-efficient technologies. In the Genesis Project she coordinates one work package.

Functional Silicon Interposers for 2.5D integration

Guhl, Conrad

Fraunhofer IPMS-CNT

Abstract
The ever-rising demand for computational power increase poses a great challenge, one solution is to combine multiple functions as chiplets with high I/O density employing a silicon interposer. The key to successful combination of chiplets in a system is high I/O density, thus small pitches approaching BEoL dimensions. Usage of silicon interposers with damascene based interconnect lines has the key benefit of a mature technology easily scalable to sub µm dimensions. Unfortunately, Silicon interposers with damascene based RDLs are comparably expensive. One industry reaction to the cost issue was miniaturization of Silicon interposers for cost savings, namely EMIB. Another possible consequence of the cost issue for Silicon interposers is to raise their value by integrating passive devices to realize a functional interposer.In the contribution we present the concept of integrated capacitors and resistor networks. By utilization of Silicon based production steps it is possible to integrate 3D capacitors in silicon interposers realizing capacity densities of up to 400nF/mm². As the capacitors move from a location next to active devices to directly below the active devices the wiring length can be reduces from several mm to few µm. The unique combination of close proximity high density capacity is crucial and allows to work e.g. without capacitor ladders.Advanced chiplet interconnection schemes like UCIe 3.0 and mobile hardware trends to lower switching voltages further increase the demand for integrated passive devices. To realize high data transfer rates like 64 GT/s in UCIe 3.0 impedance matched transmission lines are crucial. One way to realize these is integration of distinct passive devices. For ultra low power devices not only the operation voltage, but also the voltage tolerance is minimal. Such low tolerances are challenging to realize and demand a maximum capacity in ultimate proximity to the active devices. Both challenges can be tackled by functional silicon interposers.

Biography
Conrad Guhl:2009-2015 Bachelor & Master on Materials Science at Friedrich-Schiller-Universität Jena; Focus on metallic materials2015-2018 PhD in Materials Science at Technische Universität Darmstadt; XPS on battery cathode materials2019-2023 Scientist for Chemical Mechanical Polishing at Fraunhofer IPMS; Focus on design process interactions2024-open Group Leader Interconnect Technologies; work package leader in EU Chips act project “Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems”

Pilot-line implementation of advanced die-to-wafer integration based on hybrid and fusion bonding processes

Bickel, Steffen

Fraunhofer IZM-ASSID

Abstract
Advanced electronic packaging technologies enable next-generation system performance, driven by the increasing demands of AI, high-performance computing (HPC) and heterogeneous system integration. In this context, the APECS pilot line plays a central role in Europe by bridging the gap between research and industrial manufacturing, enabling the transfer of advanced packaging technologies into scalable and production-ready solutions. Fraunhofer IZM-ASSID contributes to this effort by developing and validating core process modules for chiplet integration. Focusing, on die-to-wafer (D2W) bonding technologies, this work presents a technology-driven evaluation of low-temperature fusion bonding using both TEOS and SiCN as well as hybrid bonding at an interconnect pitch of 10 µm. Die sizes range from 4 mm x 4 mm to 9 mm x 9 mm and their corresponding thickness from 775 µm down to 100 µm. Adressing critical processing challenges such as surface preparation, die handling and bonding yield with respect to high component throughput as well as introducing novel characterization techniques, the study is conducted by Fraunhofer IZM-ASSID in close collaboration with Fraunhofer IMWS. At first, the results point out the importance of precise process control on 300 mm wafer, paritcularly for dielectric deposition, chemical-mechanical polishing and the cleaning of singulated wafers. From a pilot-line perspective, the bonding yield for a given process is the most important metric. Therefore, densely populated 300 mm wafers were characterized by non-destructive methods. Only bonding areas exhibiting no detectable voids were considered for yield analysis. While bonding yields beyond 95% are obtainable using 4 mm dies for a given process-of-record (POR) flow, they drop distinctly in case of larger dies, thus requiring extensive adjustments and optimization, respectively. The presented work provides a significant contribution to the development and qualification of high-throughput fine-pitch D2W bonding processes as a key enabling technology for chiplet integration within the APECS pilot line framework.

Biography
Steffen Bickel received a diploma degree in materials science in 2011 and a PhD degree in electrical engineering in 2025, both from TU Dresden. In 2021, he joined Fraunhofer IZM-ASSID and currently manages research projects to further develop wafer level packaging technologies for quantum computing applications and bonding technologies for heterogeneous chiplet integration.

The Pervasive Intelligence With AI That Learns Inside the Sensor

Schmidt, Moritz
Co-Founder & CFO
GEMESYS GmbH

Abstract
Sensors are moving into grids, vehicles, factories and wearables. They produce more data than anyone can move, store or trust to the cloud. Most edge AI deals with this through inference only: a model is trained elsewhere, compressed, and run on the device (Level 3 of edge intelligence). Adapting that model to each site, machine or user still needs cloud training, labeled data and bandwidth. Learning on the microcontroller itself is held back by memory, energy and compute. GEMESYS takes a different route. Our CMOS-compatible analog processing unit learns directly at the sensor. An event-driven analog core processes the raw signal and does the learning, while the microcontroller keeps its job and runs only a small digital layer. The goal is to complement TinyML, not replace it, and to bring existing systems to Level 6, where training and inference both happen on the device. All within a microwatt-class power budget. Early evaluations on a hardware-accurate digital twin, using real sensor data from industrial pilots, are promising. They show the potential of analog learning at the sensor for edge intelligence that is private, adaptive and light on bandwidth. Next comes silicon. We are turning the digital-twin results into silicon validation, partner evaluation kits and larger customer pilots. We are also extending the concept to new uses, such as chips that monitor their own health, performance and lifetime. The presentation will introduce Level 6 edge intelligence and the analog learning layer, share what we learned from our pilots, and lay out the path to silicon. Stop by our booth at SEMICON Europa 2026 (Hall B0) to talk it through and see the demos.

Biography
Moritz Schmidt is Co-Founder and CFO of GEMESYS, a semiconductor startup based in Bochum, Germany. He has helped build the company from its origins as a research project at Ruhr University Bochum, with responsibilities spanning finance and business operations. Previously, he worked in management consulting at MHP, A Porsche Company, gaining experience in digital transformation. Further details about his professional background are available on LinkedIn https://www.linkedin.com/in/schmidtmo/

Coming Soon

Kneitz, Stefan

GlobalFoundries

Abstract
Coming Soon

Biography
Coming Soon

Topic Coming Soon

Horstmann, Manfred
General Manager & Senior VP
GlobalFoundries

Abstract
Coming Soon

Biography
Dr. Manfred Horstmann is General Manager and Senior Vice President at GlobalFoundries (GF) and has led the company's European manufacturing operations since October 2020, including the Dresden site, one of the world's most advanced and successful semiconductor manufacturing facilities.With nearly 30 years of experience in research, technology development, and semiconductor manufacturing, Dr. Horstmann is a leading voice for industrial semiconductor applications, European chip sovereignty, and Physical AI. Under his leadership, GlobalFoundries is investing a double-digit billion-euro amount in the expansion of its Dresden Fab - The SPRINT project is considered a European benchmark project for scalable, subsidized semiconductor capacity. As a physicist, Dr. Horstmann combines deep technical expertise with a strategic vision for the future of the European technology industry. The Dresden site employs more than 3,200 people from 47 nations, reflecting GlobalFoundries' strong international presence and commitment to innovation.

SignetOS: Designing a Secure and Fast Single-Address-Space Microkernel to Support Modern Workloads

Kressel, John

Google

Abstract
Most modern operating systems task the memory management unit (MMU) with dual responsibilities: managing virtual-to-physical memory translation and enforcing isolation. Relying on page tables for security incurs steep costs: fragmented address spaces, TLB pressure, expensive context switches, and complex inter-process communication (IPC). While CHERI capabilities can replace the MMU for robust, hardware-enforced isolation, existing systems are largely restricted to statically configured embedded domains or struggle to support rich, dynamic, general-purpose workloads within a single address space.In this talk, we present SignetOS: a CHERI microkernel that decouples memory translation from protection within a single 64-bit virtual address space and a single CPU privilege level. Rather than managing isolated address spaces, SignetOS retains the MMU solely for paging, enforcing all spatial and temporal boundaries via capabilities. Central to this design is the orthogonal decoupling of protection domains (compartments) from execution contexts (threads). Threads migrate across compartments via a lightweight domain switcher, reducing cross-domain security transitions to near-function-call overhead while eliminating page table switches, TLB flushes and message copying. To manage resources without complex resource managers, SignetOS governs access to system resources such as memory and CPU time through hierarchical quotas which can be used or sub-divided and delegated by the holder. SignetOS maintains a minimal, verifiable microkernel.SignetOS also enables efficient memory-sharing optimizations for modern template-based application cloning. Mainstream platforms like Android rely heavily on fork() and Copy-on-Write (CoW) via a zygote process to accelerate application startup, an optimization that conventionally depends on duplicate virtual address spaces so absolute pointers remain valid across clones. SignetOS brings these memory-sharing optimizations to a SASOS through a ""fork-less"" CoW primitive paired with relative addressing meaning that pre-warmed runtime templates can be cloned into new compartments with on-demand physical page sharing and no pointer fixups.We will present our system architecture, security guarantees, and current progress on SignetOS, demonstrating that CHERI capability-enforced security combined with a single address space offers a viable, highly performant foundation for modern workloads.

Biography
John Alistair KresselJohn Alistair Kressel is a student researcher at Google, researching single-address-space OSes and security with a particular focus on building secure and performant systems using CHERI. He is pursuing a PhD from the University of Manchester with a focus on the same topic.Murali VijayaraghavanFormal Methods and Security Researcher at Google.

PFAS, tbc

Mashiro, Supika

GSS Committee Chair

Abstract
Abstract coming soon

Biography
Coming soon

SEMI Global Standards Summit 2026"Future Standards in Focus: Innovation and Industry Readiness"

Mashiro, Supika
Advisor
GSS Program Committee Chair

Abstract
Now in its third edition, the Global Standards Summit (GSS) builds on the momentum of the past two events, providing a forum to identify potential areas for future standardization efforts.In a context of increasing complexity across the global semiconductor ecosystem, emerging technologies, regulatory requirements, and advanced research spur the need for effective standards development. The 2026 GSS will explore these current needs and contribute to shaping a roadmap for the next three to seven years.The GSS 2026 Panel discussion will explore AI in semiconductor manufacturing and its value chain and how SEMI Standard can promote AI adoption as well as be benefited from AI utilization.

Biography
With plasma etching process and equipment development engineering background, Ms. Mashiro has been active in SEMI Standards technical committees focusing on equipment-Fab integration enablers, such as EH&S, facilities, and physical interface specifications.She has been an active contributor to various SEMI EHS WGs including a leadership role in SEMI PFAS Initiative, a global technology community addressing PFAS supply chain challenges, as well as SIPS Japan regional PFAS WG.She is also active in IRDS (International Roadmap for Devices and Systems) and has been the co-chair of its Factory Integration focus team since 2016.

Raw Materials in Europe – Research and Innovation landscape

Rožkov, Andrej
Programme Manager and Call coordinator
Health and Digital Executive Agency (HaDEA), Raw Materials

Abstract
Microchips are made from specialized raw minerals sourced from global mining operations. Critical Raw Materials represent the essential mined minerals and metals—such as gallium, germanium, silicon, palladium, and rare earths — that are strictly required to manufacture microchips and semiconductors. In his session we present the portfolio of CRM research and innovation projects co-funded by European Union and managed by HADEA. We also present the funding opportunities for CRM topics under Horizon Europe program in 2027.

Biography
Dr. Andrej Rožkov is a Programme Manager at Health and Digital Executive Agency (HaDEA) "Raw Materials" in Brussels. He holds a PhD in Physics. Andrej has publications on ionising radiation metrology and radioanalytical chemistry. Andrej is managing research and innovation grants and is coordinating Horizon Europe calls for proposals.

Panellist - What is missing for CHERI to be widely adopted?

Cooper, Joshua

Hildebrand Technology Limited

Abstract
Panellist

Biography
Joshua Cooper is CEO and co-founder of Hildebrand, a UK technology company specialising in smart energy data and connected technologies. He has extensive experience using real-world energy data to help consumers, businesses and policymakers better understand energy usage.He has been involved in a range of energy innovation projects exploring how smart meter data can support energy efficiency, heat decarbonisation and the transition to low-carbon technologies. His work includes developing approaches that use actual household energy consumption to understand heating demand and model the impact of energy efficiency measures.

The evolvement of the largest and most complex structure built by humans and its influence on Power Semiconductors

Keller, Tobias
Vice President, Head of global Product Management, Portfolio & Marketing
Hitachi Energy Ltd

Abstract
The electrical power grid has been built up over decades and many previously isolated sub-grids are connected to each other. The integration of renewable energy sources now leads to a sharp increase in power semiconductors in the distribution network with technologically very interesting prospects.

Biography
Tobias Keller graduated in 2004, from University of applied science Aargau, the Electrical Engineering Faculty, with a degree in power electronics, thermodynamics and electrical machines. At the end of 2004, he joined ABB Excitation systems and Synchronizing equipment business (Turgi, Switzerland) and held various engineering position until 2008. He holds the first patent on MEGATROL, ABB’s smart power package solution for reliable starts of gas turbines or any synchronous machine and another patent quenching arc faults in excitation systems. In 2008 he became the Head of global Technology and Support for ABB’s Excitation systems and Synchronizing equipment business. Between 2009 and 2015 he was the Vice President global Products and Marketing ABB Excitation systems and Synchronizing equipment and High Power Rectifier business. Starting from 2016 until 2019 he held the Vice President position for Vehicle Integration Engineering business in ABB railway traction. Since April 2019, he is the Vice President of global Product Management in ABB Semiconductors (Lenzburg, Switzerland) now HITACHI ENERGY Semiconductors and a strong supporter of SiC used in power electronics based on his application know how from traction and industrial applications. Tobias is responsible for the global Product Management and Marketing of any Power Semiconductor from Hitachi Energy as well as responsible for BIMOS power semiconductors R&D (Chips and packages, Si and SiC). Tobias Keller is a senior member of IEEE (20127) and co-author of various papers.

Shaping the future of non-volatile memories with the MRAM Alliance

Lambinet, Gilles
CCO
Hprobe

Abstract
Over the past several decades, the semiconductor sector has been driven by Moore’s Law, continuously increasing transistor density to improve chip performance. With computational power of AI chips having grown much faster than memory bandwidth and data transfer efficiency, data centers may soon be choked by the demand and the cost of providing high performance data access. At the same time, software-defined vehicles with centralized, high-compute chip architectures, need more bandwidth, faster boot times and persistent data for performance, safety, updateability, and user experience. Memory, once considered a commodity, is now left, right, and center.Jump in MRAM! Magnetic Random Access Memory (MRAM) has become a compelling and widely deployed non-volatile memory technology across a growing range of applications spanning standalone and embedded products. With built-in persistence, near-infinite endurance, intrinsic robustness, faster read speed than DRAM, and better density than SRAM, MRAM is now poised to expand into next-generation automotive, storage and AI systems.MRAM however stands at a critical juncture. Despite technical readiness and availability at tier-1 foundries (TSMC, Samsung and GF leading the pack), adoption still faces hesitation. Fragmented efforts, slow standardization, and inconsistent messaging hinder progress. This triggered stakeholders across the whole value chain, from foundries to chip makers, IP vendors and system companies, equipment suppliers and leading universities/research centers, to join forces. SNIA's MRAM Alliance Special Interest Group (SIG) is designed to align the industry on key priorities, address real-world challenges, improve education and awareness, create standards when applicable, facilitate product implementation, and ultimately maximize end-system product benefits.Whether you're ready to deploy today or want to help shape what comes next, come hear what’s not to love about MRAM, and how the MRAM Alliance can shape the future.

Biography
Gilles Lambinet is an international sales and business development executive with more than 25 years of experience in high-technology industries. An engineer by background, he graduated from ENSAM Paris (École Nationale Supérieure d’Arts et Métiers) and holds an MBA from Purdue University. He is particularly passionate about emerging technologies and innovation and combines strong technical expertise with a proven track record in turning complex technologies into successful business opportunities. Throughout his career, he has worked with and for multiple technology companies, developing markets and driving international growth across diverse industries. His experience spans industrial automation, robotics, automotive, glass manufacturing, IT, utilities, digital technologies and semiconductors. A significant part of his career was spent at Hewlett-Packard, where he held international leadership positions across sales, marketing and supply-chain activities in EMEA. He subsequently moved into entrepreneurship and business development, supporting innovative technology companies in their go-to-market strategies and international expansion. His later activities covered emerging fields including cloud, IoT, digital transformation, data science and artificial intelligence.Today, as Chief Commercial Officer of Hprobe, he is focused on the semiconductor industry and advanced automated test equipment for magnetic devices. His current role places him at the forefront of a strategic high-tech ecosystem, working with semiconductor companies and technology partners worldwide.

From Pilot-Line Readiness to Trusted Deployment: A Cloneable Manufacturing Blueprint for European Semiconductor Resilience

Herfurth, Norbert
Research Manager
IHP GmbH - Leibniz Institute for High Performance Microelectronics

Abstract
Europe’s semiconductor ecosystem faces a deployment gap. RTOs and pilot lines are essential for developing new technologies, but many security-, safety- and long-lifecycle applications require something different: stable, auditable and repeatable manufacturing capacity at mature nodes, combined with advanced packaging, test and traceability.This contribution presents the European Reference Fab concept as a non-commercial manufacturing blueprint to close that gap: a cloneable 300-mm infrastructure model for 130 nm with an optional evolution path to 65 nm, integrating front-end manufacturing, packaging, chiplet integration, test, open design enablement and auditable process and data flows.The news is not another pilot line or a single national flagship fab. The proposed Reference Fab is an industrial deployment architecture. It defines how mature process modules, open PDKs/ADKs, documented tool flows, traceability mechanisms, MPW and small-series access, and packaging/test capabilities can be combined into a governed manufacturing environment. Clone sites could be implemented as front-end lines, assembly/test hubs or combined facilities, depending on regional and sectoral needs.The concept addresses several bottlenecks in semiconductor adoption. First, it provides a trusted manufacturing route for defence, critical infrastructure, automotive, industrial, med-tech and aerospace applications that do not necessarily require leading-edge nodes but do require long-term availability, provenance and auditability. Second, it creates an industrial endpoint for RTO and pilot-line results, helping promising technologies move from readiness to deployment. Third, it lowers access barriers for SMEs, start-ups and system integrators through open design kits, harmonised design interfaces and fair MPW/small-series schemes. Fourth, it embeds smart-manufacturing principles such as MES-based traceability, inline metrology, SPC/ML-assisted control, documented audit trails and secure data flows from design through manufacturing and final test.The presentation will outline the core architecture of the Reference Fab, the rationale for the 130 nm to 65 nm pathway, the role of packaging-first system integration, and the mechanisms by which open design enablement, auditable manufacturing and workforce development can support trusted electronics, supply-chain resilience and European semiconductor competitiveness.

Biography
Dr.-Ing. Norbert Herfurth is a research group leader, programme coordinator and semiconductor technologist with more than ten years of experience at the interface of microelectronics research, collaborative R&D programmes, open-source chip design, failure analysis and semiconductor strategy. He currently leads the Diagnostics, Sensors & Emerging Modules group at IHP – Leibniz Institute for High Performance Microelectronics in Frankfurt (Oder), Germany, where he is responsible for building and managing a newly established interdisciplinary unit with activities in diagnostics, sensors, photonic and emerging module technologies.His work combines technical depth in semiconductor devices and failure analysis with strategic programme leadership. Before taking on his current group-leader role, he initiated, structured and coordinated several publicly funded collaborative R&D projects in the field of open-source microelectronics, open PDKs and trusted electronics. He has contributed to the development and positioning of Europe’s open-source chip-design ecosystem, including work around IHP’s open 130 nm PDK activities and European discussions on open-source EDA, design access and semiconductor sovereignty.Norbert Herfurth earned his doctorate in electrical engineering from Technische Universität Berlin, where his research focused on semiconductor devices and silicon-level failure analysis. During his academic work, he operated and developed advanced diagnostic and failure-analysis methods, including photon-emission microscopy, thermal and optical techniques, probing methods and cleanroom-based experimental workflows. Since 2024, he has also been a lecturer at Technische Universität Berlin for the course “Debug of Integrated Circuits on Silicon Level”, which combines IC debug, failure analysis and hands-on diagnostic methods.In addition to his technical work, he has extensive experience in consortium building, project governance and strategic technology communication. He has led or coordinated multiple BMBF-funded collaborative projects, developed R&D work programmes, managed milestone- and review-driven project structures and worked with partners from research organisations, SMEs, industry, funding bodies and public-sector stakeholders. His current activities include the development of strategic concepts for open and trustworthy semiconductor ecosystems, especially where design enablement, manufacturing access, packaging, test, traceability and trusted electronics intersect.Norbert Herfurth is one of the contributors to the European Reference Fab / Transparent Reference Fab concept, a proposed open, cloneable manufacturing blueprint for trustworthy mature-node semiconductor production in Europe. In this context, he focuses on the connection between open design enablement, auditable manufacturing, trusted electronics, chiplet-aware system integration and the transition from pilot-line readiness to industrial deployment. He is also a founding member of the VDE ITG expert group on trustworthy electronics.His professional interest lies in translating complex semiconductor technology topics into actionable strategies for research, industry and policy stakeholders. This includes open PDKs and open EDA, trusted manufacturing, semiconductor resilience, system-level integration, failure analysis, photonic and electronic diagnostics, and the role of public-interest infrastructure in strengthening Europe’s semiconductor ecosystem.

Moderator

Vanhoutte, Tom
Partner - imec.xpand
imec

Abstract
Coming Soon

Biography
Tom Vanhoutte is founding partner of imec.xpand, an independently managed early stage and growth fund that invests in start-ups where knowledge, expertise, network and/or infrastructure of imec, the world-renowned semiconductor R&D center, plays a differentiating role in the success of the company. The two imec.xpand funds raised over 400 million EUR and are amongst the best performing venture capital funds globally.

Moderator

Van den Bosch, Anne
VP Strategic Public Policy & Invest for R&D Ecosystems
imec

Abstract
Coming Soon

Biography
Anne Van den Bosch is Vice President Strategic Public Policy & Invest for R&D Ecosystems at imec. She is responsible for imec's public research funding strategy, international academic research collaborations, and engagement in European and global R&D policy initiatives. With more than two decades of experience in research funding, innovation policy, and international technology partnerships, she plays a leading role in shaping collaborative research programs that support Europe's semiconductor and digital technology ambitions. Anne holds a PhD in Electrical Engineering from KU Leuven and serves in several European research and technology governance bodies, including being president of EASTRO.

Panelist

Miller, Andy
Department Director, 3D and Silicon Photonics Technology
imec

Abstract
Panelist

Biography
Andy Miller graduated from the University of Glasgow in 1995 with a Honours degree in Physics. He immediately started work as a process engineer at NEC Semiconductors (UK) Ltd in lithography. In 2000 he moved to Filtronic Compound Semiconductors Limited as lead lithography engineer. In 2008 he joined the Advanced Lithography program at IMEC, focused on alternative materials for Double Patterning.In 2009 he became the Team Leader for More Than Moore lithography development at imec, quickly expanding the team to include wafer level bonding, die bonding and metrology. In 2012 he took up the position of Group Leader for technology development within the 3D Integration program, becoming department Department Director for 3D and Si Photonics technology development at imec in 2020. Since 2026 he has been head of the 3D and Advanced Packaging Technology Office at IMEC.

Closing Remarks

Marent, Katrien
EVP & Chief Marketing and Communications Officer
imec

Abstract
Coming Soon

Biography
Katrien Marent has an engineering degree in microelectronics. She joined imec in 1992 as analog design engineer and specialized in design of low-noise readout electronics for high-energy physics. In 1999, she became press responsible and scientific editor at imec's business development division and was responsible for authoring and editing the research organization's numerous company technical documents and publications. In 2001, she was appointed corporate communications director at imec. Her responsibilities expanded in August 2007, when she got the position of external communications director including corporate, marketing and outreach communications. In October 2016, she became VP corporate, marketing and outreach communication. Since April 2020 she is Executive Vice President & Chief Marketing and Communications Officer and member of the executive board of imec.

Orchestrating a scalable AI revolution

Vandenameele, Patrick
CEO
imec

Abstract
Artificial intelligence is becoming the defining technology of our era, but its long-term impact depends on one critical challenge: scalability. As AI evolves toward complex, agentic systems operating from cloud to edge, demands on compute, memory, and connectivity are growing at an unprecedented pace. This keynote explores how sustaining the AI revolution requires innovation across the entire technology stack, from advanced CMOS and heterogeneous integration to photonic interconnects and system-level co-optimization. Looking further ahead, emerging paradigms such as quantum and brain-inspired computing may unlock new forms of efficient intelligence. Ultimately, scalable AI will not emerge from a single breakthrough, but from orchestrating a global ecosystem of technologies, disciplines, and innovators.

Biography
Patrick Vandenameele is Chief Executive Officer at imec - a globally recognized R&D center specializing in nanoelectronics and digital technologies - since April 1, 2026. His leadership underpins imec’s commitment to addressing market-driven application challenges while advancing its world-class technology platforms through targeted internal investments and external collaborations.Prior to this appointment as CEO, he served as Executive Vice President and Co-Chief Operating Officer at imec, where he was overseeing and shaping the organization's R&D strategy and its execution. In this position, Patrick was responsible for shaping and driving the center’s innovation agenda, ensuring the alignment of research initiatives with emerging market needs, partner priorities and technological frontiers. Previously, as chief portfolio officer at imec until early 2024, he spearheaded strategic initiatives spanning business development, portfolio management, and venture creation. Holding a PhD from KU Leuven, Patrick began his journey with imec in 1996, contributing to the wireless communications program. In 2000, he transitioned to entrepreneurship, founding and leading several deep-tech ventures, three of which were built on imec technology. Patrick also held senior positions at top semiconductor firms like Qorvo and Hisilicon/Huawei, leading 11 product launches and overseeing over 100 million units shipped. After returning to imec in 2017, Patrick has been instrumental in expanding imec’s venture development activities, working closely with the deep-tech venturing fund imec.xpand to strengthen imec’s position as a pioneer in technology-driven solutions.

What does an AI Workload actually need from silicon? imec's cross stack view

Latré, Steven
VP AI
imec

Abstract
As AI workloads increasingly dictate hardware requirements, the semiconductor industry needs a common, vendor-neutral language to connect process and packaging decisions to real-world AI performance. This talk introduces imec's AI Stack: a benchmarking platform and layered framework that maps AI workloads — from inference to training — down through system architecture, device integration, and ultimately to process and materials choices such as lithography parameters and node scaling. Drawing on early results, including a GPU total-cost-of-ownership analysis, we show how fab-level decisions ripple through to workload economics, and outline imec's ambition to build an open ecosystem where hardware and AI software communities can jointly optimise the stack.

Biography
Steven Latré is Vice President AI at imec, the worldwide leading research centre on semiconductors. In this role, he’s responsible for imec’s AI portfolio, focusing mainly on the intersection of hardware and software and how next generation AI workloads drive the semiconductor roadmap. Steven has a 20+ year career in AI, leading and scaling highly technical teams on the intersection of AI and hardware. Previously he was a professor in AI at the University of Antwerp, Chief AI Officer at OpenChip, a full stack chip player in HPC and AI, and was already previously Vice President AI at imec.

From Vision to Impact: Three Years of NanoIC Enabling Future Semiconductor Technologies

Holsteyns, Frank
VP R&D Unit Process & Modules
imec

Abstract
Three years after its launch, NanoIC grows into a collaborative European innovation ecosystem that accelerates the development of the chips of the future. Driven by a shared ambition to strengthen the semiconductor innovation and expand manufacturing capabilities, NanoIC brings together industrial and research partners around advanced technology platforms and infrastructure. By highlighting key achievements in Logic, Memory and Heterogeneous Integration, we showcase how collaborative R&D and shared infrastructure can accelerate innovation and reduce barriers to technology development. Engagement with companies, leveraging this new ecosystem, allows to jointly shape the next generation of semiconductor technologies together.

Biography
Frank Holsteyns has been serving as the VP of R&D at imec, leading the Unit Process and Module Department since July 1, 2023. Before stepping into this role, he was the director of the same department, where he managed various process-development-focused groups, including surface and interface processing, etch, thin film deposition, epitaxy, plating, chemical mechanical polishing, layer transfer, and assembly.Frank's journey at imec began in 2000, where he concentrated on wet cleaning research for semiconductor devices. His work in this area culminated in a PhD in Bio Engineering (surface chemistry) from KU Leuven, Belgium. In 2006, he transitioned to Lam Research AG in Villach, Austria, as a research scientist. There, he coordinated a university and research network focused on fluid dynamics, particularly cavitation, droplet impact, wetting, and dewetting.In 2012, Frank returned to imec, taking on the role of manager for the Surface and Interface Processing Group. In this position, he specialized in wet clean and etch processes, as well as isotropic dry etches.

Design enablement services: lowering the barrier for IC design companies

Hoofman, Romano
Strategic Development Director
imec

Abstract
As part of the EU Chips Act, the EU Chips Design Platform (EuroCDP) has been launched. EuroCDP's mission is to lower the barrier for fabless IC design companies, in particular startups. This will be done by lowering the technical barriers and the cost of the design process, plus in addition dedicated venture development together with private investors. EuroCDP is designed as a one-stop marketplace for startups, SMEs, and research teams, offering streamlined access to advanced design tools, manufacturing, IP, training, and funding.

Biography
Romano Hoofman is Strategic Development Director at imec since 2016. He is responsible for the coordination of both the EU Chips Design Platform and the EUROPRACTICE Service. In addition, his team is responsible for providing technology access and design enablement for the NanoIC pilot line, 2D-PL and SPINS (Quantum pilot line). He started his career in industry, where he worked as a Principal Scientist at Philips Research and later on NXP Semiconductors. He covered many different R&D topics, ranging from CMOS integration, advanced packaging, thin film batteries, photovoltaics and (bio)sensors. Romano received his PhD from the Technical University of Delft in 2000, where he investigated charge transport in semi-conducting polymers. He has authored more than 30 publications and holds more than 10 patents in various research areas.

Beyond Automotive: chiplets as the Foundation for Autonomous Edge Platforms

Sommer, Grit
Regional Managing Director
imec

Abstract
Edge High Performance Compute is becoming the “brain” of autonomous systems, enabling the rapid growth of L2+ and future autonomous mobility capabilities. However, the automotive industry faces a fundamental dilemma: compute requirements are increasing exponentially, driven by AI and advanced perception workloads, while the global automotive market remains relatively flat and cannot absorb the rising costs associated with leading-edge semiconductor technologies.Imec believes interoperable chiplet architectures provide the path forward. By decomposing complex system-on-chip designs into modular building blocks, chiplets enable heterogeneous integration of compute, AI, safety, and memory functions, each optimized on the most appropriate technology node. This approach improves scalability, yield, cost efficiency, supply-chain resilience, and platform reuse while supporting the transition toward software-defined vehicles.To accelerate adoption, imec is bringing together complementary initiatives across the chiplet value chain. The Automotive Chiplet Forum (ACF) aligns industry stakeholders around open, interoperable chiplet standards, while the Automotive Chiplet Program (ACP) advances pre-competitive research and technology development. Complementing these efforts, the new Chiplet Acceleration Center (CAC) at imec Germany supports design enablement, prototyping, and the path toward industrial deployment. Together, they help de-risk development, advance quality and reliability, and accelerate the transition from chiplet innovation to real-world automotive applications.Building on the success of ACP, imec is expanding its vision beyond automotive with the launch of the Autonomous Edge Chiplet Program (AECP), addressing shared compute needs across robotics, humanoids, aerospace, and security applications. Complemented by the development of a reference autonomous edge platform, this cross-industry strategy aims to accelerate innovation, reduce costs, strengthen resilience, and establish interoperable chiplets as the foundation for next-generation autonomous systems.

Biography
Dr. Grit Sommer is the Regional Managing Director of imec Germany, a position she has held since July 2026. With almost three decades of experience in the semiconductor industry, she is recognized as a strategic technology leader, transformative executive, and accomplished people manager, combining deep technical expertise with a strong track record of building high-performing global organizations. Prior to joining imec, Dr. Sommer spent 20 years with Infineon Technologies, where she held a series of international leadership positions across Germany and Singapore. Most recently, she served as Senior Director Global Product Engineering Digitalization, leading the digital transformation of end-to-end product engineering across a global network of manufacturing and R&D sites. In this role, she drove the adoption of advanced analytics and artificial intelligence, enabling significant improvements in product development efficiency, yield optimization, and quality management. Throughout her career, Dr. Sommer has successfully led multicultural teams across Europe, Asia, and the Americas, managing organizations with of up to 50 experts and influencing more than 1,000 employees worldwide. Her expertise spans semiconductor technology, advanced packaging, product engineering, manufacturing excellence, digitalization, and innovation management. She has consistently delivered business impact through strategic program leadership, operational excellence initiatives, and technology-enabled transformation. Before her tenure at Infineon, Dr. Sommer held research and leadership roles at the Fraunhofer Institute for Reliability and Microintegration (IZM), where she established and led advanced RF modelling and simulation activities and managed numerous industry and publicly funded research programs. Dr. Sommer holds a PhD (Dr.-Ing.) in Electrical Engineering and Computer Science from TU Berlin, specializing in RF modelling and design optimization. She also earned her Engineering Degree (Diplom-Ingenieur) in Electrical Engineering from TU Berlin with distinction. In addition to her executive responsibilities, she has served as a board member supporting the strategic development of Fraunhofer IZM and has contributed to industry governance and leadership selection processes. Driven by curiosity, innovation, and an entrepreneurial mindset, Dr. Sommer is passionate about advancing semiconductor technologies and strengthening Germany's role in the global microelectronics ecosystem.

Chips Act 2.0 and SSTS: Building Europe's Next Semiconductor Advantage

Shamuilia, Sheron
ESG Program Director
imec

Abstract
As Europe moves from capability creation to competitiveness, the success of Chips Act 2.0 will depend not only on research infrastructure, pilot lines and manufacturing capacity, but also on the intelligence, innovation and ecosystem collaboration required to sustain them. This presentation explores how imec's Sustainable Semiconductor Technologies & Systems (SSTS) program combines its Assess and Improve activities to create competitiveness intelligence across the semiconductor value chain. By connecting manufacturers, suppliers, researchers, system companies and emerging design ecosystems, SSTS helps address challenges related to sustainability, resilience, resource security and future design enablement. The presentation discusses how such ecosystem intelligence can contribute to Europe's long-term competitiveness and support the ambitions of Chips Act 2.0.

Biography
Sheron Shamuilia leads imec's ESG strategy, embedding sustainability across semiconductor R&D, operations, governance, and strategic partnerships. Her work focuses on positioning sustainability as a driver of responsible innovation, ecosystem resilience, circularity, and long-term value creation. With over 15 years of experience spanning the European Commission, corporate public affairs, and the semiconductor industry, including Cadence, she has worked at the intersection of technology, policy, innovation, and business strategy. Holding a Ph.D. in semiconductor physics, Sheron brings a unique combination of technology expertise, policy insight, and sustainability leadership, helping bridge research, industry, and government to accelerate sustainable innovation and competitiveness across the semiconductor ecosystem.

Orchestrating a scalable AI revolution

Van den hove, Luc
Chairman
imec

Abstract
Artificial intelligence is becoming the defining technology of our era, but its long-term impact depends on one critical challenge: scalability. As AI evolves toward complex, agentic systems operating from cloud to edge, demands on compute, memory, and connectivity are growing at an unprecedented pace. This keynote explores how sustaining the AI revolution requires innovation across the entire technology stack, from advanced CMOS and heterogeneous integration to photonic interconnects and system-level co-optimization. Looking further ahead, emerging paradigms such as quantum and brain-inspired computing may unlock new forms of efficient intelligence. Ultimately, scalable AI will not emerge from a single breakthrough, but from orchestrating a global ecosystem of technologies, disciplines, and innovators

Biography
Luc Van den hove is President and CEO of imec since July 1, 2009. Before he was executive vice president and chief operating officer. He joined imec in 1984, starting his research career in the field of silicide and interconnect technologies. In 1988, he became manager of imec’s micro-patterning group (lithography, dry etching); in 1996, department director of unit process step R&D; and in 1998, vice president of the silicon process and device technology division. In January 2007, he was appointed as imec's EVP & COO. Luc Van den hove received his PhD in electrical engineering from the KU Leuven, Belgium.In 2023, he was honored with the Robert N. Noyce medal for his leadership in creating a worldwide research ecosystem in nanoelectronics technology with applications ranging from high-performance computing to health.In 2025, he received an honorary distinction from the Flemish Community in recognition of his impressive role in strengthening Flanders as a leading innovative region. He has authored or co-authored more than 200 publications and conference contributions.Starting in April 2026, he took on a new role as Chair of imec’s Board of Directors.

Enabling scalable III-V technology for RF and photonics applications at IMEC: Opportunities and challenges

Vais, Abhitosh
Principal member of technical staff
Imec

Abstract
III-V semiconductor-based devices, in particular InP Heterojunction Bipolar Transistors (HBTs), are a strong contender for next generation high speed communication systems. In this presentation, motivation for the upscaling of III-V technology on to 200/300mm Si platforms is presented. A comparison of various options for such III-V on Si technology are described. The challenges in the way to achieve its integration into existing CMOS platform and possibilities to overcome them are shown. IMEC’s path to enable a CMOS compatible III-V-on-300mm Si technology with the most recent results are demonstrated.

Biography
Abhitosh Vais received the Ph.D. degree in applied physics from the KULeuven, Belgium in 2016 for his work on III-V MOS devices and defect characterization. He was an Eramus-mundus scholar during 2010-2012, working on MSc in nanoscience and nanotechnology at KULeuven, Belgium and Chalmers Technology, Sweden. He joined IMEC, Belgium, in 2016, where he is a principal member of technical staff and leads the development of III-V on Si technology for advanced RF applications. Dr. Vais has authored or co-authored 60+ technical journal papers and conference publications and several patents.

Opening Remarks by Session Chair

Malinowski, Pawel
Portfolio Manager
imec

Abstract
Coming Soon

Biography
Coming Soon

Better Tool Qualification Decisions with Optimization

Azizi, Shima
Data Scientist II
INFICON Inc

Abstract
As process complexity increases and tool fleets grow more specialized, qualification management has become one of the most capacity-intensive and least-optimized planning problems in semiconductor manufacturing. Tools must be qualified for specific capabilities through dedicated tests that consume production capacity. Manual management is complex and often suboptimal resulting in over-qualification that wastes capacity, or under-qualification that creates bottlenecks and missed delivery targets. In collaboration with X-FAB, INFICON developed the Tool Qualification Optimizer (TQO) to address this problem through automated, optimization-driven decision making.TQO automates three interconnected decisions: which tools should be qualified for which capabilities, how WIP should be distributed across available tools, and when qualifications should occur. It operates over a configurable multi-period planning horizon, carrying unprocessed demand forward across time buckets and adapting decisions as conditions evolve.The optimization pipeline combines Linear Programming and Mixed-Integer Linear Programming in a multi-step approach: determining minimum tool counts per capability through workload balancing, making binary qualification decisions that account for qualification time costs and tool diversification requirements, and allocating WIP using priority-weighted optimization based on lot urgency and due-date proximity.TQO is deployed in a production fab, integrating with the factory data warehouse to ingest tool states, WIP snapshots, and qualification expiration data automatically. Benchmarked against a qualify-all baseline, qualification reductions of 10 to 40% were observed, directly recovering capacity previously lost to unnecessary qualification runs. Consistent coverage also reduces excursion risk from lapsed qualification, protecting yield. Recommendations are generated in minutes, with consistent decision logic across shifts and operators.

Biography
Shima Azizi, Ph.D., is a Data Scientist at INFICON, where she develops advanced analytics and optimization solutions to improve operational performance and support data-driven decision-making in fabs. Over the past two years, she has focused on developing optimization-based products for semiconductor manufacturing, leveraging linear programming, mixed-integer programming, and metaheuristic approaches to automate and enhance fab operations and planning decisions. Prior to joining INFICON, Dr. Azizi served as an Assistant Professor of Business Analytics at St. John’s University, where she taught analytics courses and conducted research on developing advanced analytics solutions for real-world challenges. She earned her Ph.D. in Operations Management from Worcester Polytechnic Institute (WPI). Her expertise spans operations research and data science, with applications in semiconductor manufacturing, healthcare, humanitarian operations, and sustainability. Dr. Azizi is passionate about translating complex fab challenges into practical solutions that help make semiconductor manufacturing more predictable, efficient, and productive.< div class="simple-translate-system-theme" id="simple-translate" >< div >< div class="simple-translate-button isShow" style="background-image: url("chrome-extension://cllnohpbfenopiakdcjmjcbaeapmkcdl/icons/512.png"); height: 22px; width: 22px; top: 38px; left: 0px;" ></div>< div class="simple-translate-panel " style="width: 300px; height: 200px; top: 0px; left: 0px; font-size: 13px;" >< div class="simple-translate-result-wrapper" style="overflow: hidden;" >< div class="simple-translate-move" draggable="true" ></div>< div class="simple-translate-result-contents" >< p class="simple-translate-result" dir="auto" ></p>< p class="simple-translate-candidate" dir="auto" ></p></div></div></div></div></div>

Behnke’s Rule of n: How Factory Scale Shapes Semiconductor Company Performance

Behnke, John
General Manager Smart Manufacturing
INFICON Inc.

Abstract
John will present his recently published “Behnke’s Rule of n,” a framework that explains the core industrial engineering drivers behind some of the biggest shifts in the semiconductor industry over the past 25+ years. The rule can be summarized simply: a semiconductor factory’s size and scale have a dramatic impact on its achievable KPIs. The underlying physics are straightforward. Understanding them unlocks powerful insights for industry and policy leaders. John will explore how the rule applies across an entire organization, from in-fab tool and product groups to multi-site manufacturing optimization. He will also share how companies that have mastered these principles have outpaced industry growth, and how smaller, niche players can use the rule to sharpen their performance and improve their odds of profitable growth.

Biography
Mr. Behnke has over 40 years of semiconductor industry experience. As the GM of INFICON’s FPS Product Line and Head of its IMS Marketing team, John leads a global team that develops and deploys Smart Manufacturing software and hardware solutions which improve factories performance. INFICON’s comprehensive Digital Twin of a factory enables advanced Factory Scheduling, optimized WIP movement and other advanced capabilities.He is also a Co-Chair of the Semi North America Smart Manufacturing Chapter as well as a founding member of Semi’s Smart Global Executive Committee. Prior to his current role at FPS John served as: the President of Novati Technologies, SVP and GM of the Semiconductor Group at Intermoleculor, CVP for Front End Manufacturing and Tech Transfers at Spansion and Director of Operations at AMD's Austin Fab 25

Coming Soon

Recklies, Joerg
Executive Vice President Frontend
Infineon

Abstract
Coming Soon

Biography
Coming Soon

Session Chair

Grassmann, Andreas
Vice President
Infineon Technologies

Abstract
Coming Soon

Biography
Coming Soon

We power AI from grid to core

Kessler, Angela
Senior Principal Engineer Package Concepts
Infineon Technologies

Abstract
We are all part of a technological revolution driven by AI, which is gaining momentum unpredictably. AI not only has the potential to significantly change our daily lives through digital assistants, financial services or programming new ways, but it also transforms and reshapes every part of the computing market. The heart of this transformation is the enormous power requirement of AI technologies.To meet accelerating AI compute demand, next generation processors will need 2–4 kW per GPU, pushing rack power toward 1 MW+ by 2030. Increasing GPU cluster densities demands new power architecture designs that boost efficiency, thermal performance, and power delivery density while ensuring high reliability.Today’s AI racks use 1‑phase PSUs to create a 50 V bus that is distributed to the compute trays and will support up to 250kW rack power. IBCs and high‑density DC‑DC stages supply <1 V GPU core power, making optimized conversion essential as currents rise into the thousands of amps.Electricity and cooling are the major lever affecting GPU infrastructure TCO, often more impactful than minor differences in hardware acquisition costs. Even a seemingly small efficiency drop in a large GPU cluster translates to substantial financial impact. A reduction in cooling costs can be achieved not only through high efficiency but also through effective cooling due to a low Rth of the components.This talk presents the path from grid to core for powering AI with focus on DC-DC power modules and their thermal management.

Biography
Angela Kessler has been with Infineon Technologies AG since 2000. After completing her diploma in Chemistry in Göttingen, she received her PhD in Physical Chemistry at the University of Regensburg. She has worked in package development for Power and Sensor Systems, Automotive, and Green Industrial Power divisions. Her current focus is on concepts for energy-efficient packages with high power densities, for power delivery from the grid to the processor core for AI and data centers.

To be announced

Sebastian, Ina
Vice President R&D&I Policy
Infineon Technologies AG

Abstract
To be announced

Biography
Ina Sebastian is Vice President for Research and Innovation Policy at Infineon Technologies AG in Germany. She is involved in shaping research programmes on German and European level. The EU Framework Programme for Research and Innovation and the EU Chips Act are part of her expertise.Her second mainstay is various digital topics, such as artificial intelligence, data and microelectronics.She holds a PhD in physics. After she has finished her studies, she worked amongst other things as innovation manager, and as expert for publicly funded programmes and external collaborations at Siemens Corporate Research. She was temporarily seconded as personal advisor to the President of the German acatech (National Academy of Science and Engineering) before taking on her current role at Infineon.

Challenges of Digital Transformation in an Established Semiconductor Factory

Jentzsch, Julia

Infineon Technologies Dresden AG & Co. KG

Abstract
Through a digital transformation project at Infineon’s Dresden site, our goal is to implement a coordinated, holistic digitalization strategy for the site. This involves fundamentally rethinking the organization, processes, and collaboration. The focus is not only on the technical implementation of individual projects, but rather on supporting employees through the transformation phase by further developing their work methods and adapting and introducing new business processes.

Biography
Julia Jentzsch has been with Infineon Dresden since 2011. After holding positions in industrial engineering, implementing automation projects, and maintenance manager, she has led the Digital Transformation Dresden department since 2025. Her focus is on the successful implementation of digital transformation project at Infineon Dresden.

Powering AI - Infineon's Smart PowerFab

Thyssen, Norbert
Senior Director R&D Technology
Infineon Technologies Dresden AG & Co.KG

Abstract
The Power Management application field is driven by several market changes. Ai-Server do develop new power bus configurations and independant electrical machines, e.g. cars and humanoids need smart power configurations. Giving some insight on these developments and the consequences on technology needs will be connected to the newest Smart Power Fab in Dresden of Infineon, shwing how this will contrinute. The talk tries to show how dynamic and fast market changes search for a supply chain set-up that is able to deliver solutions.

Biography
- PhD in Physics (Diplom: RWTH Aachen / PhD: Research Center Jülich and University of Erlangen)- 28 years of experience in semiconductor technologies with focus in Research & Development & Innovation in a manufacturing environment on 200mm and 300mm- experienced in custoer partnership and joined projects with many partners in the European context- Technology Knwoledge: DRAM. embedded Flash, BCD, MEMS, Optics, Sensors, Power, Smart Power, embedded Poser)

High-Speed AFM Metrology for Advanced Packaging: Enabling High-Yield Hybrid Bonding at Sub-Micron Pitch

Haspel, Dan

Infinitesima

Abstract
Advanced packaging has become a primary driver of semiconductor performance, with hybrid wafer bonding emerging as the key enabler of 3D integration. As bonding pitches scale toward sub-1-micron dimensions, the process window tightens: copper pad recess, dielectric roughness, and wafer-scale flatness must all be controlled simultaneously to achieve void-free, high-yield bonding interfaces. This creates a metrology “blind spot” – the need to capture sub-nanometre roughness and millimetre-scale topography across an entire wafer without sacrificing high-volume manufacturing (HVM) throughput. Atomic Force Microscopy (AFM) has long been the gold standard for 3D surface resolution, but its historic speed constraints have confined it to R&D. This paper presents a paradigm shift in in-line process control using the Metron®3D, a hybrid optical-AFM system. Combined with a high-speed wafer stage and surface detection, it enables dense sampling across full 300 mm wafers at speeds compatible with mass production – measuring copper pad recess with picometre repeatability at throughputs exceeding 60 wafers per hour under standard sampling plans. We demonstrate that a single high-speed AFM platform can deliver comprehensive, multi-scale characterisation – from local copper dishing and dielectric roughness to macro-scale wafer topography – at sub-nanometre precision. This makes it ideally suited to pre-bonding characterisation of post-CMP wafers, ensuring interfaces meet the stringent requirements for high yield hybrid bonding. Results from a 3D integration development partner will be presented, proving that the multi-scale data density of high-speed AFM is essential to securing bonding interfaces in advanced semiconductor manufacturing. By moving AFM out of the R&D lab and onto the production line, this approach closes the metrology gap that today constrains hybrid-bonding yield – accelerating the cost-effective scaling of 3D-integrated devices for the AI and high-performance-computing era.

Biography
Dan Haspel is Product Manager at Infinitesima Limited, the UK company behind Rapid Probe Microscopy (RPM) — a breakthrough nanoscale metrology technology enabling true 3D imaging for next-generation semiconductor manufacturing.With a PhD in Materials Science from Loughborough University and a background spanning Oxford Instruments and academic research, Dan brings together deep technical knowledge and commercial expertise to drive Infinitesima's product strategy. He works closely with semiconductor manufacturers, research institutions, and industry partners to translate cutting-edge science into real-world solutions.Dan is passionate about bridging the gap between complex technology and the people who use it — from advanced metrology to the practical adoption of modern digital tools within high-tech organisations.

NEMS-Based Inertial Sensors: Enabling Navigation-Grade Performance for High-Volume Autonomous Applications

Robert, Philippe
CEO
INGAGE

Abstract
Reliable navigation remains a critical challenge for autonomous systems operating in environments where GNSS signals are unavailable or degraded. From autonomous vehicles and drones to industrial robots, accurate positioning requires inertial sensors capable of maintaining navigation performance during extended GNSS outages.While MEMS inertial sensors have become ubiquitous thanks to their compact size, low power consumption and low manufacturing cost, their performance remains insufficient for many navigation-grade applications. Conversely, existing high-end inertial solutions deliver the required accuracy but are often too bulky and expensive for deployment in high-volume markets.This presentation introduces a new generation of MEMS inertial sensors based on ultra-sensitive nano-strain-gauge transduction technology. Developed over more than 15 years of research at CEA-Leti and protected by an extensive patent portfolio, this breakthrough sensing approach significantly enhances the detection of mechanical motion and enables performance levels beyond the limits of conventional capacitive MEMS technologies.The talk will present the fundamental principles of nano-strain-gauge sensing, its integration into MEMS accelerometers and gyroscopes, and the expected benefits in terms of bias stability, noise performance, scale-factor stability and overall inertial navigation accuracy. Particular attention will be given to the challenges associated with transferring advanced laboratory technology into a manufacturable industrial solution compatible with high-volume semiconductor processes.The presentation will also provide an overview of the technology industrialization roadmap pursued by iNGage, a fabless Deeptech company founded in 2025 to bring this innovation to market. By combining navigation-grade performance with MEMS scalability, nano-strain-gauge inertial sensors have the potential to unlock a new generation of cost-effective navigation systems for autonomous mobility, robotics and other demanding positioning applications.

Biography
Philippe Robert is CEO and co-founder of iNGage, a deeptech startup developing a new generation of high-performance MEMS sensors. He holds a PhD in Microtechnologies and began his career at the startup SILMAG, developing advanced magnetic sensor technologies for data storage, before joining THALES to work on high-end MEMS inertial sensors for aerospace and defense applications.He joined CEA-Leti in 2001, where he held successive leadership roles, including Head of the MEMS Sensors Laboratory and Head of the Microsystems Department (120+ people), before leading Business Development for Microsystems.In 2025, he founded iNGage as CEO & CTO, leading corporate strategy, fundraising, and execution.He has authored over 50 scientific publications and holds more than 60 patents, including more than 20 related to the M&NEMS architecture at the core of iNGage’s innovation.Philippe also contributes to the international MEMS community through expert evaluations (HCERES, EIC) and leadership roles in major conferences such as IEEE MEMS, IEEE Transducers, and Eurosensors.

Ultra miniaturized rechargeable solid-state micro battery technology for new generation of implantable medical devices

Andreucci, Philippe
Chief Executive Officer
Injectpower

Abstract
Powering the Future of Digital Health: Ultra-Miniaturized All-Solid-State Microbatteries for Next-Generation Implantable Medical DevicesThe rise of digital health and personalized medicine has fueled an unprecedented demand for autonomous, smart implantable medical devices (IMDs). Monitoring and treating chronic pathologies—such as glaucoma in ophthalmology, intracranial pressure in neurosurgery, or arrhythmia in cardiology—require continuous, highly reliable physiological data tracking. However, traditional battery technologies represent a critical bottleneck, as their size, rigid form factors, and chemical leakage risks severely limit the miniaturization and safety of long-term implants.This paper introduces INJECTPOWER’s breakthrough energy solutions based on wireless rechargeable, all-solid-state microbatteries tailored specifically for high-density, ultra-miniaturized IMDs. Leveraging over 20 years of foundational R&D at CEA-Leti and protected by a robust portfolio of more than 40 patents, these microbatteries achieve dimensions as thin as a human hair while delivering unrivaled volumetric energy density and hermetic safety.By eliminating liquid electrolytes, this all-solid-state chemistry eliminates the risk of toxic leakage, ensuring high biocompatibility and excellent thermal stability during wireless charging cycles (such as RF or inductive powering). This technology enables a new paradigm of completely autonomous, micro-scaled implants capable of providing continuous, representative medical data over years of implantation.We will present the electrochemical performance, cycling stability, and integration architecture of these microbatteries. Finally, we will discuss the scaling-up strategy and industrial roadmap within the framework of the European IPCEI Health (Tech4Cure) program, leading toward a first certified commercial product on the market by 2029.

Biography
Philippe AndreucciCo-founder & CEO of INJECTPOWER | Deep Tech Entrepreneur & Board MemberBiographyPhilippe Andreucci is a seasoned deep-tech entrepreneur and executive leader with over 25 years of experience driving breakthrough innovations from laboratory research to global markets. Throughout his career, he has successfully operated at the intersection of micro-technologies, nanosystems, and life sciences, combining strong technical expertise with a proven track record in fundraising, corporate governance, and international business development.Philippe began his leadership journey at CEA-Leti, a world-renowned microelectronics research institute, where he served as Head of Nanosystems Programs. During this tenure, he co-founded the Alliance for Nanosystems VLSI—a prestigious, multi-year international research collaboration between the CEA and the California Institute of Technology (Caltech), established alongside Professor Michael Roukes.Driven by an entrepreneurial vision, Philippe transitioned from institutional leadership to venture creation. He co-founded and led APIX Analytics, a company specializing in miniaturized gas chromatography systems for industrial and environmental applications. Under his leadership as CEO, APIX successfully industrialized its technology, raised significant venture capital and additional fundings, and established a strong international footprint.Following this success, Philippe co-founded INJECTPOWER in 2020, a pioneering deep-tech company disrupting the implantable medical device sector. The company manufactures ultra-miniaturized, wireless rechargeable all-solid-state microbatteries that provide autonomy to a new generation of monitoring and treatment solutions for chronic diseases (such as glaucoma, cardiovascular, and neurological disorders). Under his guidance, INJECTPOWER secured a strategic position within the prestigious European IPCEI Health (Tech4Cure) program, established key commercial partnerships in the US, and is currently on track for its first product certification by 2029.An active figure in the tech ecosystem, Philippe serves as a Board Member for several high-growth startups, where he provides strategic counsel on corporate scaling, venture financing, and intellectual property management.Core ExpertiseDeep Tech Entrepreneurship & Leadership: Proven ability to build, fund, and scale companies with highly complex, hardware-and-software integrated technologies.International Ecosystem Building: Established track record of forging high-level academic and industrial alliances between Europe and the United States (e.g., Caltech, US clinical partners).Venture Capital & Corporate Finance: Expert in structuring mixed financing strategies, combining multi-million dollar equity rounds (VC) with non-dilutive sovereign funding (IPCEI, state grants).Governance & Advisory: Experienced board member guiding early-stage and scaling startups through critical pivots, IP valorization, and growth phases.Vision Statement: "Miniaturized, reliable energy is the true gateway to tomorrow's digital health. By giving implantable devices the power to monitor chronic conditions autonomously, we are shifting medicine from reactive treatments to proactive, life-saving data intelligence."

Beyond Silicon Photonics: Next-Generation Multi-Material Integration through Photonic Heterogeneous Integration (PHI)

Luo, Xianshu
Head, Silicon Photonics, A*STAR Institute of Microelectronics, Singapore | Vice President, National Semiconductor Translation and Innovation Centre (NSTIC), Singapore
Institute of Microelectronics, A*STAR

Abstract
As demand for higher bandwidth, faster data movement, and greater computing performance continues to grow, silicon photonics alone is becoming insufficient to meet the requirements of future AI, data-center, communication, and sensing systems. Photonic Heterogeneous Integration (PHI) addresses these challenges by combining the strengths of multiple material platforms, including III-V semiconductors for efficient light generation, silicon nitride (SiN) for ultra-low-loss routing, lithium niobate for high-speed modulation, and silicon for large-scale integration and manufacturing.By leveraging the unique advantages of each material within a unified platform, PHI enables photonic integrated circuits that deliver higher performance, enhanced functionality, and improved scalability beyond what is achievable with silicon alone. This presentation will highlight recent breakthroughs in PHI technologies, key device demonstrations, and semiconductor-compatible manufacturing pathways that are accelerating the deployment of next-generation optical interconnects, AI infrastructure, and advanced sensing systems. The talk will also discuss how multi-material integration is shaping the future of photonic integrated circuits and enabling the transition toward 400 Gb/s-per-lane and beyond.

Biography
Dr. Luo received his Ph.D. in Electrical and Computer Engineering from The Hong Kong University of Science and Technology in 2010, specializing in silicon photonics. He began his career at A*STAR Institute of Microelectronics, focusing on silicon photonic integrated circuits (Si-PICs) and heterogeneous optoelectronic integration. In 2017, he co-founded Advanced Micro Foundry, leading the development of silicon photonics integration platforms and Process Design Kits (PDKs). He returned to IME in 2023 as Principal Scientist and, in 2024, was appointed Head of the Photonics & Sensors Department at IME and Vice President of Silicon Photonics Platform Technology at National Semiconductor Translation and Innovation Centre, where he leads next-generation silicon photonics heterogeneous integration.Dr. Luo is a Fellow of Optica, Senior Member of IEEE, Lifetime Member of SPIE, and member of PMI. He serves on the editorial boards of leading photonics journals and has previously held editorial positions across both academic and industry-focused publications. He is also actively involved in the international photonics community through conference leadership, technical program committees, and peer-review activities. Dr. Luo has authored or co-authored more than 200 publications, contributed to 5 book chapters, and holds over 30 patents in photonics and optoelectronics.

Presenting Use Cases of Semiconductor-X Impacting the Landscape of Standards for Supply Chain Data Exchange

Gossner, Harald
Senior Principal Engineer
Intel

Abstract
The presentation is highlighting the use cases of traceability and sustainibility reporting like PCF which have been developed as part of the German data ecosystem project Semiconductor-X. A cross industry domain data exchange has been demonstrated and a alignment with chemical suppliers and IC customers is initiated. In the next step a global standardization is seeked to enable a seamless operation across the global semiconductor industry.

Biography
Harald Gossner holds the position of a Senior Principal Engineer at Intel. He received his diploma degree in physics from Ludwig-Maximilians-University, Munich in 1990 and his PhD in electrical engineering from Universität der Bundeswehr, Munich in 1995. For 15 years he has worked on the development of electrostatic discharge (ESD) protection concepts with Siemens and Infineon Technologies. In 2011 he joined Intel leading the system ESD robustness development for Intel products.He is the co-founder and co-chair of the Industry Council on ESD Target Levels representing more than 60 companies including all leading semiconductor manufacturers. He is President Emeritus of the EOS/ESD Association, Rome, NY, IEEE Fellow and editor of IEEE Electron Device Letters.In his role as technology advisor, he is member of the industry advisory boards of the Bavarian Government and of several Fraunhofer institutes. Since 2024 he is leading the project Semiconductor-X, coordinating the development of a dataspace for a resilient supply chain of semiconductors for Europe. He is also responsible for Intel’s activities to build-up a design ecosystem of innovative designs in digital leading edge technologies in Europe.

Presenting Use Cases of Semiconductor-X Impacting the Landscape of Standards for Supply Chain Data Exchange

Benedikt, Stefan

Intel

Abstract
The presentation is highlighting the use cases of traceability and sustainibility reporting like PCF which have been developed as part of the German data ecosystem project Semiconductor-X. A cross industry domain data exchange has been demonstrated and a alignment with chemical suppliers and IC customers is initiated. In the next step a global standardization is seeked to enable a seamless operation across the global semiconductor industry.

Biography
Harald Gossner holds the position of a Senior Principal Engineer at Intel. He received his diploma degree in physics from Ludwig-Maximilians-University, Munich in 1990 and his PhD in electrical engineering from Universität der Bundeswehr, Munich in 1995. For 15 years he has worked on the development of electrostatic discharge (ESD) protection concepts with Siemens and Infineon Technologies. In 2011 he joined Intel leading the system ESD robustness development for Intel products.He is the co-founder and co-chair of the Industry Council on ESD Target Levels representing more than 60 companies including all leading semiconductor manufacturers. He is President Emeritus of the EOS/ESD Association, Rome, NY, IEEE Fellow and editor of IEEE Electron Device Letters.In his role as technology advisor, he is member of the industry advisory boards of the Bavarian Government and of several Fraunhofer institutes. Since 2024 he is leading the project Semiconductor-X, coordinating the development of a dataspace for a resilient supply chain of semiconductors for Europe. He is also responsible for Intel’s activities to build-up a design ecosystem of innovative designs in digital leading edge technologies in Europe.

Analysis of Industry Responses

Kaesen, Florian
Director Value Chain Integration
Intel Germany

Abstract
The semiconductor industry's cyclicality and stakeholder behavior represent classic supply chain challenges. In today's landscape of persistent manufacturing and material capacity constraints, analysing and forecasting customer and supplier behavior is increasingly complex. Historically, the industry responded to shortages by inflating demand at each node of the supply chain to secure allocation—a practice that often exacerbated instability.This presentation explores alternative, data-driven strategies to optimize output from both supplier networks and internal manufacturing operations. Utilizing real-world data and real world experiences, we will analyze the potential benefits and practical limitations of these strategies, identify opportunities for future improvements for a pathways toward more resilient value chain integration.

Biography
Physicist by education and a supply chain professional by passion, Florian leads at team of supply chain experts at Intel Corporation, spearheading digital modernization across complex global supply chain ecosystems. He focuses on integrating internal and external manufacturing, enterprise architecture alignment, the practical adoption of artificial intelligence and operational excellence.

Moderator - What is missing for CHERI to be widely adopted?

Bennison, Christopher

IoT Security Foundation

Abstract
Moderator for panel discussion.

Biography
Chris Bennison is Operations Manager at the IoT Security Foundation (IoTSF), where he works to promote better security practices across the connected-device and IoT industry.Chris has been involved with IoTSF since 2022, working with technology companies, security professionals, manufacturers and other industry stakeholders to develop and promote practical approaches to IoT security. His work spans industry engagement, membership, events, communications and the development of initiatives addressing emerging security challenges and regulation.Chris is particularly focused on bringing together industry and security communities to turn complex technical and regulatory issues into practical guidance for organisations developing and deploying connected technologies.

Prompt or Perish? How AI is Revolutionising Skills, Hiring & Workplace Ethics

Filip, Diana
Deputy CEO
JA Europe

Abstract
Coming soon

Biography
Diana Filip is a C-level executive and technology leader who has been with JA Europe since 2004, currently serving as Deputy CEO & Chief Development Officer. With 25+ years of experience across entrepreneurship, digital transformation, education, innovation, and youth employability, she drives European-scale growth, governance, capital mobilisation, and AI-enabled transformation. She began her career as a digital marketing entrepreneur before moving into European leadership. With a background in Informatics, she leads Code Week, the EU’s largest digital skills initiative, and created the EU’s first forward-looking AI & Entrepreneurship programme, recognised by the World Economic Forum among its Top 8 Global Best Practices. She has scaled complex, multi-country organisations, mobilised €250M+ in capital, and led Boards and executive teams with accountability for strategy, capital allocation, performance, and institutional credibility. A recognised thought leader at the intersection of AI, technology, skills, policy, and societal transformation, Diana operates across European institutions, business, education, and technology ecosystems. She serves on the boards of Global Women TechLeaders and Rise and Lead Women and holds an MBA from Vlerick Business School and executive certificates from Harvard University.

“Glass” as the Next Generation Compute Module Substrate - Replace silicon wafers? -

Yokouchi, Kishio
Head
Japan Jisso-Interconnect Solutions Laboratory

Abstract
The packaging architecture of computing systems is undergoing a fundamental transition. Whereas semiconductor integration pursued monolithic System-on-Chip scaling, current AI compute modules increasingly adopt heterogeneous integration, in which multiple logic chiplets and stacked memory devices are reassembled on an interposer substrate. This shift is driven by the growing complexity of advanced IC fabrication, yield constraints, reticle size limitations, and the demand for scalable system architectures.At the same time, there's a growing need for faster and higher-capacity data exchange between compute dies and high-bandwidth memory (HBM). To achieve higher bandwidth, lower latency, and better energy efficiency, we need ultra-short, high-density connections that are closer to on-chip wiring characteristics rather than traditional package-level interconnects.Consequently, future interposer substrates must evolve beyond passive electrical redistribution layers. They will be required to provide fine-pitch electrical routing, support high-frequency and broadband signaling, and ultimately accommodate optical interconnects for energy-efficient communication at system scale.The interposer substrate that interconnects the compute die and memory requires fine, high-density wiring and bonding over the shortest distances, similar to the internal wiring of IC dies. It also needs to support high-frequency and wideband connections, including optical wiring. Regarding glass substrates, which are attracting attention as compute module substrates, we’ll discuss what should be considered in light of future changes in IC die structures and processes, as well as how to form electrical and optical active circuits on glass substrates to support optical wiring and silicon photonics.

Biography
Dr. Kishio Yokouchi is now a Head of Japan Jisso-Interconnect Solution Laboratory (J2IS), R&D consulting company. Also, he is a Visiting Professor of Materials & Surface Engineering Research Institute, Kanto Gakuin University.He received his Ph. D. in thermal management engineering from the Osaka University in 2009.He has been leading on development of electronic interconnect technologies for HPCs on 46 years. In 1979, Dr. Yokouchi joined FUJITSU Laboratories Ltd., where he has been mainly engaged in R&D on D2D interconnect technologies for supercomputers, such as the world’s first copper co-fired LTCC, Ultra-fine pitch thin film 2.5D circuit boards, and also, phase change liquid cooling technologies.From 2000, Dr. Yokouchi was the director of the Advanced Optoelectronics Technology Dept. of FUJITSU Laboratories of America Inc., where he directed R&D work on monolithic co-packaged optical integration technologies. From 2005, he has been a deputy general manager of the Device & Materials Laboratories, FUJITSU Laboratories. In 2007, He joined FUJITSU Interconnect Technologies, Ltd. (Now FICT) as a Vice president of R&D.Dr. Yokouchi has been also contributing on world major societies of electronics packaging technologies, such as IEEE EPS, IMAPS, and JIEP.He is the author or co-author of 55 technical presentations and publications, and invented or co-invented 72 U.S. and over 100 Japanese patents. He co-authored three technical books.

Power semiconductor trends in AI data centers

Menon, Janardan
Managing Director
Jefferies

Abstract
Data centre power demand is projected to sharply rise over the next five years, pushing power grids beyond their limits. There is a widening gap between the power requirement from forecasted AI accelerator shipments and the ramp of power supply by energy providers, with the gap estimated to be over 100% in North America by 2028. This gap is already a concern for financial markets and a cause for recent pressure on semiconductor shares. The industry is working on multiple approaches to address this growing power demand for AI, which includes finding alternative sources of power as well as reduce power losses. This includes: 1. Behind The Meter power generation which is predicted to grow at 48% CAGR in North America alone from 1.2GW in 2025 to 8.5GW in 2030.2. The transition to 800V HVDC transmission using power sidecars from 2028 and subsequently with Solid State Transformers and Solid State Circuit Breakers from around 2030, which helps reduce transmission losses within the data centre. 3. The transition to Vertical Power Delivery to the AI accelerator/GPU which is already underway and helps reduce power losses on the GPU board itself. The power delivery to the AI accelerator/GPU is expected to further transition to Substrate Integrated Voltage Regulator Modules by the end of the decade, further reducing power losses. 4. The increasing use of SiC and GaN to replace both silicon-based devices as well as electro-mechanical components to further help reduce power conversion losses. The presentation examines the impact of these constraints and transitions in data centre power supply and their potential impact on the semiconductor industry, especially for providers of power semiconductor solutions and associated equipment.

Biography
Janardan Menon has been covering the semiconductor and technology hardware sectors for 33 years. He worked as an analyst with the Gartner Group in Singapore, before moving to Dresdner Kleinwort in Hong Kong in 1997 where he headed up the Asian technology research team. He started covering European semiconductor stocks from 2002 at Dresdner Kleinwort. In 2009 he joined Liberum Capital where he focused on UK mid-cap technology stocks as well as the large cap European tech sector. He joined Jefferies as a Managing Director and analyst in 2021. Over the past 30 years Janardan has consistently remained a well respected and top ranked analyst in the semiconductor and Tech Hardware sectors.

CheriBSD on RISC-V VP++: A fast virtual prototype for latest RVY 0.9.9

Hinterdorfer, Andreas

Johannes Kepler University (JKU) Linz

Abstract
We present RISC-V VP++, an open-source virtual prototype for exploring and evaluating RISC-V systems with CHERI support. While the platform has supported earlier CHERI ISA versions, it has now been brought up to the latest RVY specification (0.9.9), enabling experimentation with the current state of CHERI RISC-V. The updated implementation covers all architectural changes introduced by RVY0.9.9 and has been validated against QEMU using TestRIG. The differential comparison between the two independently developed platforms (QEMU vs. RISC-V VP++) provides strong confidence in their agreement on the implemented instruction semantics, capability handling, privilege mechanisms, memory behavior and CHERI protection. These validations not only strengthen RISC-V VP++, but also QEMU's confidence in conformance with the latest RVY specification.In contrast to high-level emulators such as QEMU, RISC-V VP++ is designed as an extensible transaction-level virtual prototype. Its SystemC/TLM-based architecture exposes ISS and platform behavior at a level suitable for architectural experimentation, instrumentation, hardware/software co-simulation and rapid evaluation of new extensions. At the same time, its simulation performance is sufficient to boot the full-scale, general-purpose CheriBSD operating system and interact with it at near real-time speeds, making full-system experimentation practical rather than limited to small bare-metal workloads. Running CheriBSD demonstrates that the implementation extends well beyound individual instruction semantics. This confirms the entire hardware/software stack agrees on capabilities usage, virtual memory and trap handling, when firmware is exercised in a realistic full-system environment. We demonstrate RISC-V VP++ running the latest CheriBSD on RVY 0.9.9, booted through OpenSBI.The demonstration includes interactive use of the operating system and examples of CHERI capability enforcement. It also highlights how the virtual prototype can be used to inspect and modify architectural behavior in ways that are difficult or impossible to achieve on real hardware. This includes selectively relaxing CHERI protection at runtime for controlled debugging. This feature allows revisiting the work on counterfactual execution to evaluate the effectiveness of CHERI protection, now using RVY 0.9.9 in a full operating-system environment [1].By combining support for the latest RVY specification, validated architectural behavior, and full-system CheriBSD execution, RISC-V VP++ provides a practical platform for cutting-edge experiments with the rapidly evolving CHERI RISC-V ecosystem. Because the complete platform runs in software on conventional host systems, researchers can experiment with latest CHERI RISC-V without access to dedicated CHERI hardware, FPGA infrastructure, or an RTL simulation environment. As an open-source project, RISC-V VP++ therefore significantly lowers the barrier to entry for researchers and potential CHERI adopters.References:[1] Distinguishing Exploit Failure from Effective CHERI Protection on RISC-V, Andreas Hinterdorfer, Manfred Schlägl, Daniel Große, RISC-V Summit Europe 2026

Biography
Andreas Hinterdorfer is a PhD student and research assistant at the Institute for Complex Systems (ICS), JKU Linz, under the supervision of Prof. Daniel Große. He received his MSc in Electronics and Information Technology with distinction in 2025 and subsequently worked as embedded software engineer at blue-zone GmbH Austria. His research focuses around hardware/software co-simulation, virtual prototyping and processor verification. He began working on CHERI during his master thesis and continues to research CHERI-enabled RISC-V systems, with a particular focus on virtual prototypes and validation.

From Automation to Autonomy: Building the Dark Factory with Physical AI and Intelligent Robot Orchestration

Jang, Young Jae
Professor
KAIST

Abstract
The semiconductor industry is entering a new era of manufacturing, moving beyond traditional automation toward fully autonomous operations. As semiconductor fabs become increasingly complex, conventional Material Control Systems (MCS) and equipment-level automation alone are no longer sufficient to achieve the flexibility, intelligence, and operational efficiency required for the next generation of manufacturing.This keynote introduces a new vision of the Dark Factory, where Physical AI continuously monitors factory conditions, coordinates heterogeneous robots and manufacturing equipment, and dynamically optimizes operations with minimal human intervention.At the center of this transformation is KAIROVERSE, an AI-powered robot orchestration platform designed to integrate and intelligently control diverse material handling systems, including Overhead Hoist Transport (OHT), Autonomous Mobile Robots (AMRs), and other robotic systems, within a unified factory-wide operational architecture. By combining intelligent material handling control, real-time decision-making, simulation, and AI-driven optimization, KAIROVERSE enables a transition from isolated automation systems to coordinated, autonomous factory operations.The presentation will also highlight practical applications and lessons learned from deployments of selected technologies in large-scale semiconductor and automotive manufacturing facilities, demonstrating how intelligent orchestration can improve material flow, operational flexibility, and factory-wide coordination.Ultimately, this keynote presents a broader perspective on Physical AI: the factory itself can be viewed as a massive, interconnected robotic system, where intelligence extends beyond individual machines to the autonomous operation of the entire manufacturing ecosystem.

Biography
Young Jae Jang received his Ph.D. in Mechanical Engineering from the Massachusetts Institute of Technology (MIT) in 2007, and dual M.S. degrees in Mechanical Engineering and Operations Research from MIT in 2001. He earned his B.S. in Aerospace Engineering from Boston University in 1997. He is currently a Professor in the Department of Industrial and Systems Engineering at the Korea Advanced Institute of Science and Technology (KAIST) and the Founding Director of the Center for KAIST Manufacturing Physical AI, where he leads research on next-generation autonomous manufacturing systems. In parallel, he is the CEO and Co-founder of DAIM Research Corp., the leading startup commercializing AI-based manufacturing powered by Physical AI technology. DAIM’s platforms have been successfully deployed by major global manufacturers, including Samsung Electronics, LG Electronics, SK On, and LG Energy Solution, demonstrating large-scale industrial adoption and real-world impact.

Quantum-Safe Silicon: From Chips to Cyber-Resilient Systems

K. Marnerides, Angelos
Asst. Professor of Cyber-Physical Systems Security
KIOS Research and Innovation Centre of Excellence at the University of Cyprus

Abstract
The transition to post-quantum cryptography is rapidly becoming a hardware–software co-design challenge. This talk will present ongoing activities within the EU-funded FOCAL project, focusing on crypto-agile architectures, hardware acceleration, trusted execution and programmable edge-to-cloud platforms for practical PQC deployment. Particular emphasis will be placed on how these technologies intersect with the semiconductor ecosystem and can enable scalable, high-performance and quantum-safe systems across automotive, communications and critical infrastructures.

Biography
Prof. Angelos K. Marnerides, Asst. Professor of Cyber-Physical Systems Security at the department of Electrical & Computer Engineering and Faculty Member at the KIOS Research and Innovation Centre of Excellence at the University of Cyprus. He is a Senior Member of the IEEE, has secured over €15M in research and innovation funding, and currently coordinates the €5.8M COCOON and €6.4M FOCAL Horizon Europe projects, while also contributing to European Defence Fund projects. His work bridges advanced cybersecurity research with real industrial, critical-infrastructure and defence applications, including on-going and past collaborations with BAE Systems, Raytheon, Fujitsu, NCSC, GCHQ and the UK Ministry of Defence as well as other EU security and defence agencies. He is also a directly appointed member of the Council for the Cypriot Defence Industry, advising the President of the Republic of Cyprus on defence-industry matters.

Coming Soon

Barnett, Richard
Director Etch Product Management
KLA

Abstract
Coming Soon

Biography
Coming Soon

Latest developments in MVD® Anti-Stiction Coatings for MEMS Manufacturing

Hammond, Paul
Senior Director & General Manager Release Etch Division
KLA

Abstract
Coming Soon

Biography
Paul Hammond has been Sr Director and GM of the Release Etch Division since 2005, with responsibility for the etch release (Primaxx HF & XACTIX XeF₂) and MVD product lines. Prior to the acquisition of Primaxx in 2005 by SPTS, Mr Hammond was VP Sales and Marketing, having joined the company in 2002. Prior to SPTS, from 1995 to 2002 Paul was President of American Tech Manufacturing Corp, a manufacturer of high-speed IC inspection and conditioning equipment. Previous roles also included Director of Sales and Marketing at Sono-Tek Corporation, selling ultrasonic coating equipment for many different process applications into a variety of industries. Paul started his career in the semiconductor industry with Cambridge Instruments Group where he held a number of positions including Business Unit Manager for the Crystal Growth and MOCVD division. Educated in the United Kingdom, Paul graduated with a BS in Applied Physics from Brunel University in London. He is currently based out of the company’s Allentown, PA facility.

The myth of troubleshooting

Messinger, Lior
CEO
Korra.ai

Abstract
The pitch is familiar by now: troubleshooting is what keeps tools down, and AI will finally shorten MTTR. It is a compelling story. It is also two claims stacked on top of each other, and neither has been examined closely.The first is empirical. How much of a technician's working day is actually spent troubleshooting? Measured against the full picture of setup, qualification, PM, documentation, handoffs and procedure execution, the answer is a much smaller fraction than the industry's attention would suggest. The second is a matter of judgment. Even where troubleshooting does happen, it is the worst possible place to point a probabilistic system. It is the moment with the least tolerance for a confident wrong answer, the least structured input, and the highest cost of being subtly plausible instead of correct.This talk argues that AI has been aimed at the most visible problem in the fab rather than the most valuable one, and presents an alternative: grounding AI in what the organization already knows, and separating diagnosis from procedures. We will enhance and present methods needed for real world use cases.

Biography
Lior Messinger is the founder and CEO of Korra.ai, an AI company building knowledge retrieval systems for industrial environments where the data cannot leave the building. Korra's platform runs fully on-premises and air-gapped, and is deployed in production across semiconductor manufacturing and field service operations. Lior has spent 35 years building software in high-consequence environments. He previously led physics and AI development for flight simulators and video games. He founded Korra in 2020 to let AI understand technical procedures using documentation text, visuals, and historical data.

LittleCHERI: Ultra-Fine-Grain Compartmentalization using Secure Stack-Sharing on CHERI Capability Machines

Storme, Elias

KU Leuven

Abstract
CHERI capability machines provide good support for low-overhead enforcement of spatial memory safety and compartment isolation. However, compartment granularity and temporal stack safety remain constrained by the use of per-compartment stacks, a trusted intermediary switcher and/or compressed representability of precise stack capabilities. Theoretical support for secure stack sharing between distrusting compartments is strong but ignores practical concerns, and hence has not been implemented or evaluated.We contribute LittleCHERI: a prototype secure calling convention that makes ultra-fine-grain compartmentalization viable on CHERI-RISC-V through secure stack sharing. LittleCHERI employs recently-proposed uninitialized and indirect sentry capabilities and contributes particularly a novel Reserve Stack technique that reconciles precise stack capabilities with capability compression. Benchmarks of our Clang/LLVM implementation show that LittleCHERI offers realistic overheads wrt. execution speed, stack pressure, and binary size, demonstrating that ultra-fine-grain compartmentalization is feasible on general capability machines.

Biography
Elias Storme is a PhD researcher at KU Leuven, working under the supervision of Dominique Devriese. His research focuses on the practical aspects of secure calling conventions, exploring the gaps between formal security results and real-world applications. Passionate about systems research, Elias aims to put novel security techniques into practice.

Topic Coming Soon

Bourke, Michelle
Mng Dir, Specialty Technologies and Strategic Marketing
Lam Research

Abstract
Coming Soon

Biography
Michelle Bourke received her B.Sc. degree in Optoelectronics and Laser Engineering from Heriot-Watt University in Scotland, UK. Subsequently she joined the Defence Evaluation and Research Agency (DERA), where she worked on advanced processing methods for GaAs/AlGaAs optoelectronic devices. In 1997 she entered the semiconductor capital equipment industry as a technologist and has since accrued more than 25 years of experience in semiconductor technology, strategy, and new product development. She is a specialist in fabrication technologies for MEMS, Power Devices, RF Electronics and Optoelectronics.Michelle is a frequent presenter at leading industry forums and also serves on many committees and industry councils. In November of 2018, she was inducted into the Semi MEMS and Sensors Industry Group Hall of Fame and in 2020 she was a Silicon Valley YWCA Tribute to Women Honoree. Michelle is currently Chair of the Semi MEMS Manufacturing Working Group, Co-chair of the Semi MEMs Standards Committee and a Director on the Transducers Research Foundation Board where she is the Chair of Fund Raising and Development Committee.Michelle joined Lam Research in 2015 and is currently Managing Director of Specialty Technologies and Strategic Marketing in Lam’s Corporate Strategy Group.

Semiconductor Supply Chain Planning, Scheduling, and Execution in the Age of AI

Abissini, Alessandro
Manufacturing Application Manager
LFoundry

Abstract
The Panel will introduce how Melexis is planning their fabless supply chain, and how Lfoundry manages manufacturing execution in their high volume foundry. Eyelit Technologies will give an overview on how Agentic AI is quickly changing semiconductor Planning, Scheduling, and Executrion management. This will be followed by an open discussion where members of the audience can ask questions on the solutions presented, or their companies specific needs. The panel is comprised of Professionals from Melexis, Lfoundry, and Eyelit Technologies

Biography
Alessandro Abissini is the Manufacturing Application Manager at LFoundry, bringing 20 years of ICT experience in the semiconductor industry. Starting his career in software development and support at Micron, he now leads the division overseeing the fab's MES, APS, and Factory Automation.

Panellist - What is missing for CHERI to be widely adopted?

Orensanz Martinez, Javier

lowRISC

Abstract
Panellist

Biography
Javier is the CEO of lowRISC, a non-profit with a mission to make open silicon a commercial reality, who runs active projects on secure and memory safe hardware. Previously, he was a VP and General Manager at Arm for over 8 years. Javier has worked in the semiconductor industry for over 25 years.

Magnetocalorics: Next-Generation Cooling for Semiconductors

Dubois, Remi
COO
Magnoric

Abstract
Magnoric is developing a new generation of cooling systems based on the magnetocaloric effect, replacing conventional vapor-compression technology with a solid-state thermodynamic cycle.Our technology operates without refrigerant gases and combines high energy-efficiency potential with silent, vibration-free operation and reduced maintenance requirements.Magnoric has already developed and validated pre-series cooling platforms from a few hundred watts to more than 1 kW and is now scaling the technology toward higher-power applications.For the semiconductor industry, magnetocaloric cooling opens new opportunities for efficient thermal management, process cooling and heat recovery. This presentation will introduce Magnoric’s technology, its latest developments and its potential for next-generation semiconductor manufacturing applications.

Biography
Rémi Dubois is Chief Operating Officer at Magnoric, a French deep-tech company developing magnetocaloric cooling technologies. He is responsible for operations, business development and the industrialization of Magnoric’s technology, working closely with industrial partners across cooling, energy and advanced manufacturing applications.

Leading the Transition - Cleanroom Filtration without added PFAS.

Spehl, Frank
Principal Expert Air Filtration
MANN+HUMMEL

Abstract
The semiconductor industry is under increasing pressure to eliminate substances of concern from manufacturing ecosystems while maintaining the highest standards of contamination control. PFAS chemicals are becoming a growing focus of regulators and sustainability programs worldwide.This presentation showcases how advanced air filtration technology can support the industry's transition toward more sustainable cleanroom operations. Through extensive laboratory and field validation, attendees will learn how filtration products designed without added PFAS chemistry deliver the same trusted performance in efficiency, energy consumption, pressure drop, and lifetime as traditional solutions.The session will discuss regulatory drivers, lessons learned during product development, and practical strategies for implementing technologies without added PFAS in semiconductor facilities. Participants will leave with a clearer understanding of how sustainability and cleanroom performance can be achieved together.

Biography
Frank Spehl, Principal Expert Air Filtration Solutions at MANN+HUMMEL, brings more than 35 years of experience in air filtration and cleanroom technology. Prior to his current role, he led R&D activities in air filtration, driving the development of innovative filtration technologies and solutions. His expertise spans sustainable filtration concepts, energy-efficient manufacturing environments, contamination control, and advanced solutions for highly regulated industries, including semiconductors, microelectronics, and other high-tech manufacturing sectors.

'Prompt or Perish? How AI is Revolutionising Skills, Hiring & Workplace Ethics'. In the Abstract field, please enter 'Coming Soon' or 'Panelist'

Barberis, Riccardo
Regional President Northern Europe & France
ManpowerGroup

Abstract
Panelist

Biography
Riccardo Barberis was appointed Regional President, Northern Europe in May 2021, and in January 2025 expanded his responsibilities to include France, ManpowerGroup's largest market in the region. In this role, Barberis oversees all of ManpowerGroup's brands and offerings across the region – Manpower, Experis, and Talent Solutions. Barberis will lay the path to further accelerate ManpowerGroup's diversification, digitization, and innovation plans, creating even more value for clients and candidates and strengthening our performance in the region.​Riccardo joined ManpowerGroup in 1998 and has held numerous leadership positions in Europe and Latin America, most recently as country manager for ManpowerGroup Italy. With more than 25 years of experience including many international roles his deep industry knowledge and passion for a client-first, candidate-centric approach consistently delivers superior results.An accomplished executive, Riccardo holds an Executive MBA from Bocconi University (Milan), has completed management programs at INSEAD and speaks five languages. Currently serving as Board Member of Junior Achievement Europe, he has previously held positions as Vice President of the Italian Industry Association (Assolavaro) and President of ManpowerGroup's Human Age Institute. Riccardo lives with his family in Paris.

Europe's Semiconductor Moment: Turning AI Disruption into European Opportunity

Pfingstag, Philipp
Partner
McKinsey & Company

Abstract
Artificial intelligence is transforming the global semiconductor industry, with the market potentially more than doubling to $2.3 trillion by 2030. This unprecedented growth creates significant opportunities for Europe. With world-leading semiconductor equipment companies, cutting-edge research, and a strong industrial base, Europe has the foundations to play a pivotal role in the AI era. This presentation explores Europe's unique competitive strengths, and how Europe can seize this moment to build a lasting competitive advantage in the global semiconductor industry.

Biography
​Philipp Pfingstag is a Partner at McKinsey based in Stuttgart.​Since joining the firm in 2018, Philipp has served clients mostly in semiconductor on multiple topics with a focus on capacity expansion.Philipp holds a Ph.D. in Technology and Innovation Management from the Technical University of Munich and a M.Sc. in Chemistry and Business Studies from the University of Zurich. During his doctoral studies, Philipp spent several months at the Massachusetts Institute of Technology.

Semiconductor Supply Chain Planning, Scheduling, and Execution in the Age of AI

Hoorelbeke, Pieter
Business Operations Program Manager
Melexis

Abstract
The Panel will introduce how Melexis is planning their fabless supply chain, and how Lfoundry manages manufacturing execution in their high volume foundry. Eyelit Technologies will give an overview on how Agentic AI is quickly changing semiconductor Planning, Scheduling, and Executrion management. This will be followed by an open discussion where members of the audience can ask questions on the solutions presented, or their companies specific needs. The panel is comprised of Professionals from Melexis, Lfoundry, and Eyelit Technologies.

Biography
Pieter Hoorelbeke is Business Operations Program Manager at Melexis, where he steers the digital supply chain roadmap within Business Operations and manages strategic projects in fabless supply chain planning and transformation. Since joining Melexis in 2010, he has served as Supply Chain Process Owner Back Office and Supply Chain Planning Business & Solution Architect leading the design and implementation of supply chain planning automation (MIPS), and related ERP integration initiatives. Pieter holds a Master’s degree in Applied Economics from the Catholic University of Leuven (Katholieke Universiteit Leuven), a graduate certificate Supply Chain Management (Bruges Business School) and is APICS certified as both a Certified Supply Chain Professional (CSCP) and Certified in Production & Inventory Management (CPIM).

Chips Act 2.0: How can Europe turn semiconductor excellence into investment, scale and resilience?

Schenk, Oliver

Member of the European Parliament

Abstract
Europe has many of the ingredients for semiconductor leadership: world-class research, strong industrial clusters and global champions in critical parts of the value chain. Yet too often, Europe struggles to turn these strengths into investment, scale and new industrial capacity. As the European Parliament begins to shape its position on Chips Act 2.0, the debate must therefore go beyond individual fabs, funding targets and market shares. The real challenge is to build a stronger European semiconductor ecosystem: connecting clusters across borders, bringing research faster to market, mobilising private investment and developing capabilities where strategic dependencies remain. With AI transforming the global geopolitical landscape at unprecedented speed, Europe must decide where it wants to lead, where it needs greater resilience and what it will take to remain a strong global technology player. Chips Act 2.0 is an opportunity to make those strategic choices.

Biography
Oliver Schenk has been a Member of the European Parliament since 2024 and serves as rapporteur in the Committee on Industry, Research and Energy for the Chips Act 2.0. In this role, he is leading the Parliament’s work on Europe’s future semiconductor policy. Before entering the European Parliament, he served from 2017 to 2024 as a Minister of State in Saxony and Head of the Saxon State Chancellery, including responsibility for European and federal affairs. Over the course of his career, he has held senior positions in both state and federal government, including in the fields of policy planning, digitalisation and technology. His work focuses on strengthening Europe’s industrial competitiveness and technological resilience.

Pantel Discussion Moderator

Ernst, Benedikt
Senior Vice President
Merck Group

Abstract
Chips Act 2.0 and International Collaboration with Trusted Partners

Biography
As Europe moves towards the implementation of the Chips Act 2.0, strengthening international partnerships will be essential to building a more resilient, secure and competitive semiconductor ecosystem. Europe’s position across the semiconductor value chain depends not only on strengthening domestic capabilities, but also on deeper cooperation with trusted partners, including the US, Japan, Taiwan and South Korea.This session will examine how the Chips Act 2.0 can reinforce Europe’s strategic positioning and translate international partnerships into practical cooperation on supply chain resilience, technology, investment and innovation. It will also explore the role of initiatives such as ICOS in connecting European capabilities with trusted international ecosystems.

Advanced Packaging: Redefining the New Front End Through Materials Innovation

Ernst, Benedikt
SVP and Head of Strategy and Transformation
Merck KGaA

Abstract
As semiconductor demand driven by AI continues to increase and traditional scaling methods near their limits, the trends toward advanced chip architectures and 3D densification are accelerating. The traditional boundary between front-end wafer fabrication and back-end assembly is increasingly blurring. Advanced packaging has become the “new front end,” where performance, power efficiency, yield, and reliability are determined by processes and materials that increasingly resemble those used in the most advanced logic manufacturing environments, powered by the same fundamentals.Feature sizes in advanced packaging are still relatively large today, but hybrid bonding is changing, driving miniaturization and complexity. It must be approached with the same level of process control, materials sophistication, metrology, and systems understanding that have defined front-end semiconductor manufacturing for decades. Merck’s integrated materials-and-systems solutions will be at the heart of it.Europe has a unique opportunity to establish a strong position in advanced packaging. Building on its world-class semiconductor ecosystem—including leaders in equipment, process technologies, and innovation. Europe is well positioned to accelerate the next wave of semiconductor advancement through advanced packaging technologies.In this keynote, Merck will share its perspective on how materials innovation is becoming a key enabler of advanced packaging growth. Critical materials including CMP slurries, cleaning solutions, thin-film deposition materials, and other specialty chemistries must now address challenges.We will explore how front-end manufacturing experience provides a critical foundation for solving advanced packaging challenges, what differentiates packaging materials development from traditional front-end applications, and how collaborative innovation across the European semiconductor ecosystem can create a sustainable competitive advantage. As advanced packaging becomes a strategic driver of semiconductor performance, Europe has a timely opportunity to shape its future, and materials innovation will be at the center of that journey.

Biography
Benedikt Ernst is the SVP and Head of Strategy and Transformation at the Electronics business of Merck KGaA, Darmstadt, Germany. As a member of the Electronics Executive Committee, he is responsible for the end-to-end strategic development and transformation of the business sector, encompassing market competitive intelligence, strategic roadmap, business transformation programs, and business and portfolio development. He joined Merck KGaA, Darmstadt, Germany in 2006, and has had various management positions. Since 2018, he has been heading Strategy and Business Development for Electronics and Semiconductor. Before he was Commercial Director for the Semiconductor business and Head of Packaging Business Field. Benedikt Ernst studied physics at the Technical University of Munich and at the Max Planck Institute of Plasma Physics.

Accelerating Materials Discovery for the Semiconductor Industry

Jatsch, Anja
Head of Materials Innovation Pipeline
Merck KGaA

Abstract
As semiconductor technologies advance, materials must deliver increasingly complex combinations of performance, reliability, manufacturability, and sustainability. At the same time, new device architectures and growing process complexity are shortening development and qualification cycles. New materials are therefore becoming an increasingly important lever for future semiconductor performance, while the scientific and experimental design spaces continue to expand. The challenge is not only to discover new materials, but to accelerate the full innovation process from material design through experimentation, characterization, process optimization, and integration.The effective use of AI in materials R&D depends on accessible, structured, and connected scientific data. Digital laboratory infrastructure, consistent data capture, instrument connectivity, and integrated workflows provide the foundation to make experimental information usable. Building on this, modeling, AI, automation, and data analytics can support better experimental decisions, explore larger design spaces, and shorten learning cycles by combining scientific understanding with data-driven and increasingly predictive approaches.We will share its perspective on how materials R&D can evolve from fragmented workflows toward connected, data-enabled, and predictive innovation environments. We will discuss how materials and process expertise, digital infrastructure, computational methods, and experimentation can be combined into integrated learning loops. Real use cases from semiconductor materials R&D will illustrate how these principles can accelerate materials innovation.The presentation will also highlight how Europe can build on its scientific excellence, R&D infrastructure, industrial capabilities, and collaborative ecosystem to advance materials innovation. Connecting internal R&D capabilities with research and industry partnerships can help translate scientific advances into industry-relevant solutions and strengthen Europe’s contribution to future semiconductor technologies.

Biography
Anja Jatsch, Head of Materials Innovation Pipeline within the Chief Technology Office of the Electronics Business of Merck KGaA, Darmstadt, GermanyAnja Jatsch is Head of Materials Innovation Pipeline at Electronics Business of Merck KGaA, Darmstadt, Germany, where she leads the development and advancement of new material platforms with a strong focus on semiconductor materials and technologies. Her work centers on accelerating materials innovation by combining deep materials science with portfolio strategy, digitalization, AI, and external collaboration.She has more than 16 years of experience in Electronics R&D and innovation leadership. Before taking on her current role, she held several leadership positions in Optronics, including Head of Material Research and Head of Early Innovation, where she worked across OLED materials, display technologies, and emerging Optronics-related fields.Anja holds degrees in chemistry and business administration and economics and has a scientific background in organic chemistry and advanced materials.

Coming Soon

Latawiec, Pawel
CTO
Metalenz

Abstract
Coming Soon

Biography
Coming Soon

The First Domino: How India Became the Launchpad for Micron Assembly & Test Modernization

Chavet, Didier
Senior Director & Global Head of Manufacturing IT
Micron Technology

Abstract
Micron's India Assembly & Test facility was more than a greenfield manufacturing investment. It became the catalyst for a new, globally integrated approach to manufacturing transformation, establishing the foundation for future Assembly & Test operations worldwide.This session will explore how Micron leveraged the opportunity to design a modern digital manufacturing ecosystem from the ground up, connecting product lifecycle management (PLM), global master data authoring, automation, analytics, and operational processes around a manufacturing execution core built on Critical Manufacturing MES, unifying them into a single, scalable framework. Rather than deploying isolated solutions, the program adopted an end-to-end strategy that enabled common standards, accelerated deployment, and ensured consistency across the manufacturing value chain.Attendees will learn how India served as the proving ground for this vision, demonstrating how a globally aligned digital architecture, with a modern MES as the execution layer of the digital thread, can shorten time-to-ramp, improve operational readiness, and create a repeatable blueprint for future Assembly & Test expansion. The session will share key lessons learned from implementing a unified digital thread that connects engineering, manufacturing, and operations while balancing global governance with local execution.Key Takeaway: Modernizing manufacturing is not about deploying a new MES or automating individual processes. It is about establishing an integrated digital foundation that enables scalability, standardization, and agility across the enterprise.

Biography
Didier Chavet is the Senior Director and Global Head of Manufacturing IT at Micron Technology, leading the strategy, delivery, and operations of Manufacturing IT capabilities supporting Micron's worldwide semiconductor manufacturing network. With more than two decades of experience in the semiconductor industry, he is responsible for the technology platforms and operational systems enabling highly automated front-end and assembly & test manufacturing across Micron's global factories.Throughout his career at Micron, Didier has been at the forefront of digital transformation initiatives that have significantly advanced manufacturing automation, operational excellence, and factory intelligence. He played a pivotal leadership role in the development of Micron's vision for highly autonomous "Lights Out" manufacturing operations, helping drive the integration of advanced automation, manufacturing execution systems, and data-driven decision-making capabilities across the company's assembly and test operations.More recently, Didier has been leading Micron's Assembly & Test (AT) Modernization Program, one of the company's most strategic manufacturing transformation initiatives. This program is reimagining the technology foundation of Micron's Assembly & Test network through modernization of manufacturing platforms, standardization of global processes, and adoption of next-generation digital capabilities that improve scalability, resiliency, and operational agility.A strong advocate for innovation and emerging technologies, Didier also drives the incorporation of Artificial Intelligence and advanced analytics into manufacturing operations. Under his leadership, Manufacturing IT has accelerated the use of AI-powered solutions to enhance operational efficiency, predictive decision-making, automation, engineering productivity, and factory intelligence. His focus is on transforming data into actionable insights while enabling smarter, more autonomous manufacturing ecosystems.Having lived and worked across Asia, North America, and Europe, Didier brings a global perspective to technology leadership and organizational transformation. His international experience, coupled with deep expertise in semiconductor manufacturing and digital innovation, enables him to lead diverse global teams while delivering large-scale business and technology transformations that support Micron's continued growth and competitiveness.Francisco Almada Lobo is recognized as a top strategic thought leader and evangelist on digital transformation, specifically Industry 4.0, manufacturing operations and the factories of the future. He holds an MBA and an Electrical Engineering Degree from the University of Porto. He started his career in a CIM R&D Institute and joined Siemens Semiconductor in 1997. Throughout his tenures at Siemens, Infineon and Qimonda, he specialized in optimizing highly complex, discrete manufacturing operations. In 2004, he led the first migration of an MES system in a running high-volume facility. Francisco Almada Lobo holds various positions within the smart manufacturing and venture capital industries, including being a Member of the 200M Fund's Investment Committee, Executive Committee Member of SEMI Smart Manufacturing Technology, Member of the Forbes Technology Council and Advisor to many Industry 4.0 startups. Francisco Almada Lobo co-founded Critical Manufacturing in 2009 and has been CEO since 2010.

Building a Network Security Product on CHERI: Early Insights

Atkins, Martin

Mission Critical Applications Limited

Abstract
Routers occupy a uniquely privileged position in every network — they see, and can redirect, almost every packet that passes through. Their management interfaces are consistently among the most attacked surfaces in networking, and 2026 has already brought a string of serious disclosures affecting major vendors. Compromise of a router's management interface can have consequences well beyond the device itself, across enterprise, telecoms and national-infrastructure networks alike.We are a UK SME building a hardware-enforced security appliance to address this problem, using CHERI on Arm Morello with a defined path to CHERI-RISC-V. Our premise is simple: a device trusted to guard a network's most sensitive interface must itself be measurably more robust than the system it protects.In this talk we will share why we believe CHERI's memory-safety and compartmentalisation guarantees are particularly well suited to problems of this kind, the practical realities of building a commercial product on a CHERI-compatible platform, and the open question of what should count as credible evidence that a security product is trustworthy, rather than merely marketed as such. We're also keen to compare notes with others in the CHERI community bringing CHERI-based products from research prototype toward commercial deployment, particularly around platform choices and evidencing trust to non-technical stakeholders.This is an early-stage project, and we see CHERITech'26 as a chance to engage the community as our work develops.

Biography
Dr Martin AtkinsDr Martin Atkins is Technical Director at Mission Critical Applications Limited, a UK SME specialising in high-integrity, safety-critical systems across aerospace, telecoms, automotive and defence. He holds a DPhil in Computer Science and a BA in Mathematics from the University of York. His interest in hardware capability systems predates CHERI itself, dating back to post-doctoral work on the Ten15 and Flex capability architectures at the Royal Signals and Radar Establishment. He was technical lead on MCA's work within the Digital Security by Design (DSbD) Technology Access Programme and the subsequent DASA-funded "CHERI within Defence and Security" programme, exploring seL4 on Arm Morello. He specialises in rapid prototyping, test harnesses and open-source safety-critical development.Dr Divya AtkinsDr Divya Atkins is Managing Director of Mission Critical Applications Limited, a UK SME specialising in high-integrity, safety-critical systems across aerospace, telecoms, automotive and defence. She holds a BSc from Mount Carmel College, Bangalore University, a BE in Computer Science from the Indian Institute of Science, an MSc in Computing from Balliol College, Oxford, and a DPhil from the University of York. She has led MCA for over 25 years, with a research background in formal methods and industrial software engineering standards. She was project lead on MCA's work within the Digital Security by Design (DSbD) Technology Access Programme and the subsequent DASA-funded ""CHERI within Defence and Security"" programme, with a particular interest in computer and network security.

Building a Network Security Product on CHERI: Early Insights

Atkins, Divya

Mission Critical Applications Limited

Abstract
Routers occupy a uniquely privileged position in every network — they see, and can redirect, almost every packet that passes through. Their management interfaces are consistently among the most attacked surfaces in networking, and 2026 has already brought a string of serious disclosures affecting major vendors. Compromise of a router's management interface can have consequences well beyond the device itself, across enterprise, telecoms and national-infrastructure networks alike.We are a UK SME building a hardware-enforced security appliance to address this problem, using CHERI on Arm Morello with a defined path to CHERI-RISC-V. Our premise is simple: a device trusted to guard a network's most sensitive interface must itself be measurably more robust than the system it protects.In this talk we will share why we believe CHERI's memory-safety and compartmentalisation guarantees are particularly well suited to problems of this kind, the practical realities of building a commercial product on a CHERI-compatible platform, and the open question of what should count as credible evidence that a security product is trustworthy, rather than merely marketed as such. We're also keen to compare notes with others in the CHERI community bringing CHERI-based products from research prototype toward commercial deployment, particularly around platform choices and evidencing trust to non-technical stakeholders.This is an early-stage project, and we see CHERITech'26 as a chance to engage the community as our work develops.

Biography
Dr Martin AtkinsDr Martin Atkins is Technical Director at Mission Critical Applications Limited, a UK SME specialising in high-integrity, safety-critical systems across aerospace, telecoms, automotive and defence. He holds a DPhil in Computer Science and a BA in Mathematics from the University of York. His interest in hardware capability systems predates CHERI itself, dating back to post-doctoral work on the Ten15 and Flex capability architectures at the Royal Signals and Radar Establishment. He was technical lead on MCA's work within the Digital Security by Design (DSbD) Technology Access Programme and the subsequent DASA-funded "CHERI within Defence and Security" programme, exploring seL4 on Arm Morello. He specialises in rapid prototyping, test harnesses and open-source safety-critical development.Dr Divya AtkinsDr Divya Atkins is Managing Director of Mission Critical Applications Limited, a UK SME specialising in high-integrity, safety-critical systems across aerospace, telecoms, automotive and defence. She holds a BSc from Mount Carmel College, Bangalore University, a BE in Computer Science from the Indian Institute of Science, an MSc in Computing from Balliol College, Oxford, and a DPhil from the University of York. She has led MCA for over 25 years, with a research background in formal methods and industrial software engineering standards. She was project lead on MCA's work within the Digital Security by Design (DSbD) Technology Access Programme and the subsequent DASA-funded ""CHERI within Defence and Security"" programme, with a particular interest in computer and network security.

Application of SnAg and Nano-Porous Cu Structures for Advanced Micro-Bump Pattern and Their Properties

Tatsumi, Koji
Manager
Mitsubishi Materials Tools Europe GmbH

Abstract
As semiconductor devices continue to demand higher integration density, fine-pitch micro-bump interconnects have become increasingly important in advanced packaging technologies. Although SnAg solder bumps are widely used for flip-chip bonding, their application to ultra-fine pitch structures is limited by strict requirements for electroplating control and assembly precision. In particular, ensuring bump height uniformity and reliable bonding at micrometer-scale dimensions remains a significant challenge.In this study, a novel micro-bump structure consisting of nanoporous copper coated with a SnAg passive layer (NP-Cu/SnAg) is proposed to address these limitations. The nanoporous Cu framework provides low-temperature sintering capability and mechanical compressibility, enabling effective absorption of bump height variations during bonding. Furthermore, the SnAg coating improves the structural stability of nanoporous Cu, preventing dissolution during processing.Micro-bump test structures with diameters of approximately 10 µm and pitches of 20 µm were fabricated using electroplating techniques. Both conventional SnAg and NP-Cu/SnAg bumps were successfully formed and evaluated through morphological observation and bump height measurement. The NP-Cu/SnAg bumps exhibited excellent height uniformity, with variations below 2 µm, and their compressible structure enabled complete bonding even under fine-pitch conditions.Electrical and reliability performance were assessed using daisy-chain resistance measurements and thermal cycling tests. The NP-Cu/SnAg bumps demonstrated lower initial electrical resistance compared to conventional SnAg bumps. Additionally, while the resistance of SnAg bumps increased after thermal cycling, NP-Cu/SnAg bumps maintained stable electrical characteristics, indicating superior thermal reliability.These results confirm that NP-Cu/SnAg micro-bump structures provide improved process tolerance, enhanced electrical performance, and robust reliability. Therefore, they represent a promising solution for next-generation semiconductor packaging requiring ultra-fine pitch and high-performance interconnects.

Biography
After majoring in chemistry at university, I joined Mitsubishi Materials Corporation in 2011. I spent ten years engaged in the development of SnAg plating chemicals for semiconductor Advanced packaging. During this period, I also provided technical support to customers across Asia, as well as in Europe and the United States, contributing to the expansion and optimization of plating technologies in global markets.I subsequently worked in a corporate planning role at the company’s headquarters for three years, where he was involved in business strategy and organizational initiatives.Since June 2025, I have been based in Germany, serving as a manager responsible for European marketing and business development, actively driving growth and strengthening the company’s presence in the region.

Advancing Copper Metallization for Reliable RDL Scaling in Next-Generation Packaging

Stubbe, Jessica
Manager Global Applications Engineering Semiconductor ECD
MKS | Atotech

Abstract
Redistribution layers (RDLs) are a key enabler of advanced semiconductor packaging, supporting high-density routing, heterogeneous integration, and reliable interconnection between package levels. As package architectures become more complex, die and package sizes continue to increase, and the industry transitions from wafer-level to panel-level manufacturing, the reliability of electroplated copper is becoming increasingly critical to long-term device performance. These trends place greater demands on copper interconnects, which must withstand elevated thermomechanical and electrical stresses while maintaining consistent material properties across increasingly large substrates.This presentation examines how copper plating chemistry and deposit quality influence RDL reliability. Particular emphasis is placed on the relationship between impurity incorporation, copper microstructure, grain boundary characteristics, and key failure mechanisms, including thermomechanical cracking and electromigration. Additive incorporation during plating can significantly affect grain structure evolution and defect formation, ultimately influencing the material's response to thermal and electrical stress.By linking electrochemical deposition, copper microstructure, and reliability performance, this presentation demonstrates how optimized copper plating processes can enable reliable RDL integration and support the increasing performance, scalability, and lifetime requirements of next-generation advanced packaging technologies.

Biography
Dr. Jessica Stubbe is Manager Global Applications Engineering Semiconductor ECD at MKS | Atotech. She leads the global semiconductor applications team and is responsible for application development, customer support, process optimization, and technology deployment for advanced semiconductor packaging. Her work focuses on electrochemical deposition (ECD) processes including Cu pillar, RDL, TSV, hybrid bonding, and next-generation packaging applications. Dr. Stubbe works closely with leading semiconductor manufacturers worldwide to develop plating solutions for advanced packaging technologies and future integration concepts.

Innovation in MEMS-industry, where do we come from and where are we going

Vilenius, Tommi
Senior Manager, Business Development Automotive
Murata Electronics Oy

Abstract
Small reflexion on how has innovation in MEMS business changed over the past 30 years. Starting from innovating how to realize a function on silicon, then how to make it for less than $100 and miniaturizing the sensors to fit inside a smartphone.What is MEMS innovation today and how we need to innovate in future to create value for the whole supply chain & industry.

Biography
Tommi Vilenius has been working in Automotive MEMS business for 30 years in various roles from R&D, Quality, Testing and Customer interface. Currently Mr Vilenius is focusing on new automotive applications for inertial MEMS and fitting together physical MEMS devices to ever improving capabilities of data processing & AI.

Co-Designed and Co-Packaged Thermal Solutions for Advanced Semiconductor Packaging

Martin, Henry Antony
Research Scientist
Netherlands Organization for Applied Scientific Research (TNO)

Abstract
Wide-Bandgap (WBG) power semiconductors, such as Silicon Carbide (SiC) MOSFETs, Schottky diodes, and Gallium Nitride (GaN) transistors, are widely adopted in electric vehicles for power conversion and inversion. While traditional surface-mount package architectures feature a thermal metal slug on the PCB side, the industry is quickly shifting towards Top-Side Cooling (TSC) and Dual-Side Cooling (DSC) layouts to bypass the thermal bottlenecks of conventional circuit boards. Some prominent examples of surface-mount top-side cooled SiC MOSFETs are STMicroelectronics’ HU3PAK™ and the standardized QDPAK platform adopted by Bosch, Infineon, and Nexperia.However, TSC and DSC platforms still rely on external liquid-cooled heatsinks, complex Thermal Interface Material (TIM) management, and substantial coolant volumes. In contrast, the ACEPACK™ DRIVE power module from STMicroelectronics integrates liquid cooling directly onto the pin-fin baseplate structure, achieving a very low junction-to-fluid thermal resistance of 0.1 K/W. This cooling-integrated power module highlights the industry's critical point, which is the need to move beyond conventional heatsink-based cooling approaches and adopt thermal management as an integral co-designed element of the package architecture.This presentation introduces a portfolio of co-designed and co-packaged thermal technologies currently under development at CITC (part of TNO). Thermal management is a multi-domain challenge governed by device architecture, power density, and transient operational characteristics, with different classes of electronic systems exhibiting fundamentally distinct thermal behaviors.Four complementary integrated thermal solution classes will be presented:1. Thermal Spreading: For devices suffering from highly localized hotspots and steep thermal gradients, advanced thermal spreaders based on diamond and Cu-diamond composites are being integrated to redistribute heat spatially before it reaches the cooling interface.2. Thermal Dissipation: For systems operating at extreme power densities, near-chip microfluidic cooling architectures are being integrated directly within the package to enable efficient heat extraction while minimizing coolant consumption.3. Thermal Regulation: For transient and pulsed workloads, Phase Change Materials (PCM) based thermal buffers are being investigated to temporarily absorb thermal peaks and reduce temperature swings.4. Adaptive Thermal Dissipation: Finally, adaptive thermal dissipation concepts based on shape-change materials are being explored to dynamically regulate cooling performance and coolant flow in response to changing thermal loads.The presentation will provide an overview of integration strategies, packaging architectures, and application spaces associated with each technology, illustrating how thermal spreading, heat removal, thermal buffering, and adaptive cooling can be combined to address the increasingly diverse thermal requirements of next-generation semiconductor packages.Ultimately, this work provides attendees with a practical framework for selecting and co-designing thermal solutions based on power density, hotspot characteristics, and transient operating conditions.

Biography
Henry A. Martin is a Research Scientist at the Chip Integration Technology Center (CITC), which is part of the Netherlands Organization for Applied Scientific Research (TNO).He holds an MSc in Mechanical Engineering from Eindhoven University of Technology (TU/e) and a PhD in Electrical Engineering from Delft University of Technology (TU Delft).His research focuses on heterogeneous integration, advanced packaging, and integrated thermal management.

Industry Keynote

Nordmann, Arne
VP Technology & Innovation
Neura Robotics

Abstract
Coming Soon

Biography
FileCommentsViewingThere is nothing to undo.Dr.-Ing. Arne Nordmann received his PhD in Software Engineering for robotic systems in 2015. From 2015 to 2022, he worked at Bosch Corporate Research on system engineering projects in both robotics and highly automated driving. Since 2022, he has served as Vice President Technology & Innovation at NEURA Robotics, overseeing software and hardware development as well as system integration across all robotic platforms.

Topic Coming Soon

Traverso, Andrew
Chief Scientist
Neurophos Inc.

Abstract
Coming Soon

Biography
Coming Soon

Design and Manufacturing by NIL of a Meta-Optics Camera

Kamino, Brett
Manager Business Development and Strategy
NIL Technology

Abstract
Meta-optics are emerging as a powerful technology platform for next-generation imaging and sensing systems, enabling optical performance and form factors that are difficult to achieve with conventional refractive optics. By controlling light through engineered nanoscale structures, meta-optics offer new opportunities for applications such as augmented reality, eye tracking, machine vision, and advanced optical sensing. However, translating these high-performance designs into scalable, manufacturable products still remains an open challenge.This presentation will describe how NIL Technology (NILT) addresses this challenge through meta-optics lens architectures and a manufacturing platform built for industrial-scale production. As a dedicated meta-optics foundry, NILT provides a complete pathway from prototyping to high-volume manufacturing, supported by vertically integrated capabilities including electron beam lithography, nanoimprint lithography, etch processing, metrology, testing, and optical integration.The presentation will examine the relationship between design, manufacturing, and optical performance, demonstrating how mature design-for-manufacturing methodologies enable close agreement between simulation, prototype results, and volume production. NILT's nanoimprint-based manufacturing approach is critical to achieving state-of-the-art performance in scalable meta-optics products. Using this unique manufacturing process, NILT has demonstrated excellent process stability, wafer-to-wafer reproducibility, and scalability to production volumes in the millions of units.A case study of the commercially available metaEye™ ultra-compact eye-tracking camera will highlight how meta-optics can reduce system size, improve thermal stability, simplify optical assemblies, and deliver robust imaging performance in demanding real-world environments.Finally, the presentation will outline NILT's foundry model for commercializing meta-optics. NILT's mature and proven design rules for meta-optical elements ensure predictable optical performance from initial design through prototyping to high-volume production. Adding to this are NILT’s open-access module architectures, which enable customers to build custom meta-optic modules based on proven designs. Whether customers bring their own designs, want to customize module solutions based on NILT’s architectures, or seek a complete custom solution, NILT provides the infrastructure and manufacturing expertise required to take meta-optical products from concept to volume production.

Biography
Brett Kamino is Manager, Business Development and Strategy at NILT, where he works on commercializing meta-optics technology. Brett has a background in thin-film semiconductors, next-generation solar cells, and nanophotonics, and has spent his career working across both the technical and commercial sides of emerging technology, first developing the underlying technology and now focusing on the business strategy, partnerships, and market positioning needed to bring it from the lab to commercial products.

Key building blocks for sustainable 6G networks (draft)

Kaib, Harry
Sustainability and Communication Manager
Nokia Solutions and Networks GmbH & Co. KG

Abstract
The presentation will cover energy‑aware radio units and power amplifiers, AI‑native baseband platforms for intelligent RAN, and smart software to reduce network power consumption while preserving performance and security (draft)

Biography
• Advocate for telecom's positive impact on people and planet.• Over 30 years' experience in telecommunications in Europe, South America, and China in R&D, Business Development, Sales & Marketing.• Dipl.-Ing. (FH) Allgemeine Elektrotechnik• Dipl.-Wirt.Ing. (FH) Marketing (post-grad)• Currently leads Sustainability and Communication, IPCEI ME/CT, Nokia Germany.

Sovereign AI at the Edge: Heterogeneous, Decentralised and Collaborative Compute

Kanjo, Eiman
Head of Smart Sensing Lab
Nottingham Trent University

Abstract
Moving AI into the physical world requires heterogeneous systems in which specialised units handle perception, communication, actuation and learning. Beyond existing specialised accelerators and memory-centric designs, the challenge is to coordinate these units across chips and edge devices while minimising data movement. This talk will explore hybrid, decentralised and collaborative architectures combining digital, analogue and neuromorphic computing, low-precision inference, high-precision processing and on-device learning to support sovereign TinyML, edge AI and physical AI.

Biography
Professor Eiman Kanjo is Professor of TinyML and Head of the Smart Sensing Lab at Nottingham Trent University, and Honorary Provost Visiting Professor at Imperial College London. She directs three major initiatives: the EPSRC TinyML Network, the EPSRC GREEN+ Network and the forthcoming TinyML UK Network. She also serves on the EPSRC ICT Strategic Advisory Team and is a public lecturer at the Royal Institution. She was named one of the Top 50 Women in Engineering by the Women’s Engineering Society, received the Edge AI Foundation Outstanding Educator Award in 2025, and received a Turing Network Development Award in 2022. Earlier in her career, she held research roles at the University of Cambridge and the University of Nottingham.

Scaling Advanced Packaging for the AI Era: Precision Manufacturing from Development to Volume Production

Golabchi, Ali
Product Leader, Novanta Precision Beam Steering
Novanta

Abstract
The rapid adoption of AI, chiplet architectures, and high-bandwidth memory is reshaping what advanced packaging has to deliver. As package sizes grow and interconnect densities increase, manufacturers face mounting pressure to maintain alignment accuracy, process repeatability, and yield, all while preparing for high-volume production.Technical feasibility is no longer the finish line. Manufacturers must also establish stable process windows, control critical feature quality, and scale output without introducing the variability that erodes yield and long-term manufacturability.This presentation explores how precision laser-based manufacturing supports the transition from development to production across substrate processing, micro-via formation, and interposer manufacturing. It looks at the manufacturing considerations associated with evolving package architectures and at why integrated control across beam delivery, motion systems, and process monitoring increasingly determines whether a process scales. Where laser source, scanning, and controls are engineered together rather than assembled from separate suppliers, process variation is easier to characterize and easier to hold.Drawing on production experience across semiconductor and electronics manufacturing, the session covers practical approaches to improving consistency, reducing process variation, and supporting scalable throughput. It also addresses how engineer-to-engineer collaboration between technology partners, equipment manufacturers, and semiconductor producers accelerates process qualification and reduces implementation risk.As advanced packaging becomes more central to AI system performance, precision, repeatability, and scalability at the process level will determine how quickly new architectures reach volume.

Biography
Ali Golabchi is Product Leader for Novanta’s Precision Beam Steering technologies, where he leads product strategy and growth for semiconductor manufacturing, photonics, and advanced industrial applications. He brings more than a decade of experience across precision metrology, optical systems, laser processing, and motion control technologies, spanning engineering, systems development, and commercial roles. Before joining Novanta, he held engineering positions at Olympus and Zygo Corporation, working on advanced imaging, metrology, and photonics-based solutions. He holds B.S. and M.S. degrees in Electrical Engineering from Northeastern University and is currently pursuing an MBA at Babson College.

Opening Keynote presentation

Bongers, Bas
Director of Sustainable Manufacturing (and Director of Renewable Energy)
NXP Semiconductors

Abstract
Coming soon

Biography
Coming soon

A Design-Enabled Advanced Packaging Ecosystem for Heterogeneous Integration and Co-Packaged Optics

Jampana, Gayathri
Associate Director, Business Development
NY Creates

Abstract
Rapid growth in data generation and consumption continue to drive unprecedented bandwidth and energy-efficiency requirements. This has accelerated the need for innovations in advanced packaging and co-packaged optics (CPO). Access to these technologies is limited to volume manufacturers with narrow ranges of high-maturity processes and products. There is a need to access to cutting-edge, advanced packaging technologies for R&D, that are rapidly scalable, in manufacturing-relevant conditions. The New York Center for Research, Economic Advancement, Technology, Engineering and Science (Creates) and American Institute for Manufacturing Integrated Photonics (AIM Photonics) fill this need together by offering practical frameworks through five focus areas: interposers and custom 3DICs; hybrid bonding; wafer-level packaging; CPO; and test, assembly and packaging services. Key technologies are 300mm silicon interposer platforms, TSV integration (down to 1×10μm), and multiple 3D stacking approaches. Chip-level integration alongside wafer-level bonding allows designers to prototype across a wide range of interconnect densities and performance regimes. Hybrid bonding enables ultra-fine-pitch interconnects with orders-of-magnitude improvements in density over bump-based methods, while reducing energy consumption. Current development spans pitches down to 0.5μm with planned extensions to die-to-wafer integration. Wafer-level packaging capabilities further enhance prototyping by supporting fine-pitch bumping (<25μm), RDL for wafer-level fan-out, and TCB integration. CPO is emerging as a critical architecture for delivering low-power, high-bandwidth performance in the datacenter and beyond by tightly integrating electronics and photonics within the package. AIM Photonics supports this transition through multiple photonic integrated circuit platforms and a range of photonic packaging capabilities, including electronic-photonic interposers, on-chip laser integration, detachable fiber array units, and low-loss optical coupling strategies. Central to the AIM Photonics ecosystem is design enablement through PDKs and ADKs, linking device, package, and test considerations within a unified framework. Together, these capabilities establish a design-enabled prototyping environment that accelerates cycle time, reduces integration risk, and provides a scalable bridge from concept to deployment for next-generation advanced packaging systems at Creates’ Albany NanoTech Complex.

Biography
Dr. Colin McDonough is Manager for 3D & Heterogeneous Integration for the American Institute for Manufacturing Integrated Photonics (AIM Photonics) at the New York Center for Research, Economic Advancement, Technology, Engineering and Science (Creates) in Albany, NY. Colin specializes in 3D integration and advanced packaging, with a particular focus on silicon photonics and interposer technologies. He has lead development efforts in TSV fabrication, wafer-to-wafer direct bonding for electro-optic heterogeneous integration, and on-chip laser integration. Colin earned his Ph.D. in Nanoscale Science & Engineering in 2011 at the University at Albany, State University of New York and is a Senior Member of IEEE.Dr. Erin Lavigne is a senior leader in the semiconductor industry with more than 15 years’ experience spanning technologies, businesses, and continents. Erin began her career at IBM developing leading-edge advanced patterning and metrology solutions for IBM’s high-end server products. From there, she moved to a role in Leading-Edge Product Management at GlobalFoundries, where she drove their technology and customer strategy for their 14/12nm FinFET programs. Most recently, Erin was at Meta developing innovative process engineering and integration for advanced displays for AR/VR/MR applications. Throughout this journey, Erin has led multidisciplinary teams spanning Europe and the USA. In her current role at NY Creates, she has returned to her roots, leading the technology strategy and partnerships ecosystem for NY Creates’ EUV and Advanced Patterning Center, Design Enablement Ecosystem and Advanced Packaging in Albany, NY.Gayathri Jampana is currently working as Associate Director in Business Development team for Advanced Packaging at NY Creates. She started her career in Advanced Packaging as Graduate Research Assistant at University of Arkansas fabricating a 100 micron interposer at HiDEC Fab. After graduation, she was hired by Brewer Science as Associate Applications Engineer developing processes for WaferBOND materials. After that, Gayathri was hired at SUSS Microtec as Applications engineer for XBS300 Wafer Bonding tool and developed process flows for different temporary wafer bonding materials. She moved to Canada and worked as Program Manager at TechInsights before starting at NY Creates.

Opening Remarks by Session Chair

Holmberg, Heikki
R&D Director
Okmetic

Abstract
Coming Soon

Biography
Coming Soon

Next-Generation Optical Switching and AI Infrastructure

Aguilar, Keith Eric
CEO
Omnitron Sensors

Abstract
The rapid growth of AI is creating new requirements for high-bandwidth, energy-efficient connectivity and placing increasing pressure on conventional electrical network architectures. Optical circuit switching offers a path toward more scalable infrastructure, but achieving the required optical performance, reliability, and manufacturability presents significant MEMS design and fabrication challenges.Omnitron is addressing these challenges through a proprietary 3D MEMS fabrication platform and large-aperture mirror arrays with in-situ feedback control. The technology enables high-performance optical switching while supporting flatter network topologies, lower interconnect power consumption, and reduced infrastructure cost. This presentation will explore the MEMS innovations behind the platform and how advanced microfabrication can enable a new generation of optical switching systems for AI infrastructure.

Biography
Eric Aguilar is the CEO and co-founder of Omnitron Sensors, where he leads the development of next-generation MEMS technologies for AI infrastructure and autonomous systems. His career spans more than two decades in advanced sensing and semiconductor innovation, including leadership roles at Google X, where he led avionics development for autonomous delivery drones, and Tesla, where he led firmware and sensor integration for Model 3. Earlier in his career, Eric developed advanced sensors for U.S. Navy research laboratories and defense programs before joining Lumedyne, whose technology was later acquired by Google. Today, he leads Omnitron’s commercialization of breakthrough MEMS technology designed to enable the next generation of optical networking for hyperscale AI data centers.

Enabling AI at the Intersection of Advanced Packaging and Silicon Photonics

Kryman, Timothy
Sr. Dir. Product Mktg.
Onto Innovation

Abstract
Artificial intelligence is driving unprecedented demand for computing performance, memory bandwidth, and energy-efficient data movement, forcing the semiconductor industry to rethink both device architectures and package integration. Silicon photonics and advanced packaging have emerged as foundational enabling technologies for next-generation AI systems, providing the bandwidth density, power efficiency, and heterogeneous integration needed to scale future AI infrastructure. As these technologies build on existing methodologies and move from development into high-volume manufacturing, process control becomes a critical determinant of yield, reliability, and cost. This presentation examines the evolving metrology and inspection challenges across emergent silicon photonics for AI and advanced packaging ecosystems, including waveguide geometry, refractive index control, facet and V-groove characterization, microlens inspection, die warpage, hybrid bonding, TGV structures, optical alignment, and defect detection. Drawing on real manufacturing applications, we highlight how Onto Innovation's portfolio of optical, dimensional, materials, and defect inspection solutions resides at the intersection of these enabling technologies allowing customers to address these challenges, accelerate yield learning, and bring AI-enabling technologies to market with greater confidence and productivity.

Biography
Timothy Kryman is Senior Director of Product Marketing at Onto Innovation, where he leads strategic product positioning and market development for advanced semiconductor process control solutions. With more than 25 years of experience in semiconductor manufacturing, metrology, inspection, and advanced packaging, he works closely with leading logic, memory, and photonics manufacturers worldwide. Timothy has played a key role in driving adoption of innovative process control technologies that enable AI, silicon photonics, heterogeneous integration, and advanced packaging. He is recognized for his expertise in connecting technology innovation with market and business strategy.

Panellist - What is missing for CHERI to be widely adopted?

Ravishankar, Manu

PA Consulting

Abstract
Panellist

Biography
Manu Ravishankar is a Principal Consultant at PA Consulting, where he leads innovation, strategy and delivery programmes across cybersecurity, digital infrastructure and critical national infrastructure. He led the design and establishment of the UK's CHERI Secure by Design Managed Deployment Programme and now serves as its Programme Delivery Lead, bringing together government, industry and technology partners to support the deployment and adoption of CHERI-enabled technologies. His work focuses on scaling emerging technologies from research and development into real-world deployment and commercial adoption.

Integration of III-V semiconductor devices with photonic integrated circuits for large-scale manufacturing of photonic modules

Obara, Karol
Project Lead
PHIX Photonics Assembly

Abstract
Photonic integration and assembly are complex, multi-disciplinary processes that play a vital role in ensuring the correct functioning, reliability, and commercial viability of photonic integrated circuits (PICs). Semiconductor devices based on III-V materials play a key role in terms of emission, modulation, amplification, and detection of optical signals across multiple wavelength bands. During this talk, we will present different approaches for enabling co-integration between PICs fabricated in various material platforms and III-V semiconductor devices, allowing delivery of photonic modules compatible with large-scale manufacturing.

Biography
Karol Obara is a project leader at PHIX Photonics Assembly, the Netherlands, responsible for leading research and innovation projects in the field of photonics integration. Prior to joining PHIX in 2021, in the period from 2018 to 2021, he worked in the area of optical encoders at Renishaw, the United Kingdom. Karol holds a bachelor’s degree (BScEng) and a master’s degree (MScEng) from the Wrocław University of Science and Technology, Poland, in the field of Electronics and Telecommunication with specialization in Photonics.

From Recognition to Industrial Leadership: Scaling Integrated Photonics in Europe

Brinkhoff, Eelko
CEO
PhotonDelta

Abstract
Europe has built a world-leading position in integrated photonics, with strong capabilities across III-V technologies and complementary photonic integration platforms. The European Commission’s proposed revision of the EU Chips Act marks an important milestone: Photonic Integrated Circuits (PICs) are explicitly recognised as a strategic semiconductor technology within Europe’s future semiconductor strategy. Recognition, however, is only the starting point. Europe’s challenge is now to translate its technological leadership into industrial scale, market adoption and long-term global competitiveness.This presentation will outline what is needed to make that transition: moving beyond research excellence towards industrialisation and commercial deployment; creating viable pathways to scalable manufacturing; expanding and upgrading existing European production capacity; and strengthening the complete value chain from materials and substrates to PIC manufacturing, electronic-photonic integration, advanced packaging, testing, components and systems.The revised EU Chips Act provides an opportunity to turn decades of European research, investment and innovation into lasting industrial leadership. The next phase is not simply about making more photonic chips in Europe, but about building a globally competitive European industry around them.

Biography
Eelko Brinkhoff (CEO) is CEO of PhotonDelta, where he leads the mission to accelerate the growth and maturity of the integrated photonics industry in the Netherlands and Europe. With more than 25 years of experience in economic development, internationalisation and foreign direct investment, he brings a strong network across business, government, knowledge institutes and universities.Before joining PhotonDelta in February 2024, Eelko was Managing Director Internationalisation at the Brabant Development Agency (BOM). He is committed to building a globally recognised photonic chip ecosystem that turns Dutch and European innovation into scalable applications in areas such as datacom, telecom, healthcare, quantum technology, robotics, sustainable agriculture and autonomous mobility.

Coming Soon

José Carimatto, Augusto
Head of IC Design
Pi Imaging Technology

Abstract
Coming Soon

Biography
Coming Soon

How to enable ‘semiconductorization’ of photonic chip packaging ?

Dorrestein, Sander
Program Manager Integrated Photonics
PITC

Abstract
The photonics industry has successfully demonstrated the performance potential of photonic integrated circuits. Today, however, the challenge is no longer the chip itself. It is how to package, connect, and manufacture photonic systems at the scale demanded by emerging AI and data-centric applications.This keynote examines how advanced packaging technologies can transform photonics from a specialized technology into a mainstream manufacturing platform. Drawing inspiration from the semiconductor industry, new approaches based on interposers, redistribution layers, panel-level processing, and pluggable optical interfaces are enabling a step change in scalability, performance, and cost.This keynote talk will present a vision for highly manufacturable photonic systems where optical and electrical interconnections are integrated into modular packaging platforms, dramatically reducing assembly complexity while enabling high-density integration. Key developments in low-loss optical coupling and semiconductor-compatible assembly approaches will be highlighted, together with their implications for future co-packaged optics.As the industry moves from innovation to industrialization, packaging will define the pace of photonics adoption. This keynote explores why packaging has become the critical enabler for the next generation of photonic products and systems.

Biography
Sander is Program Manager Integrated Photoncis at PITC - Photonics Integration Technology Center (part of TNO) based in The Netherlands. Sander has a Bachelor degree in mechanical engineering, with special interest and broad experience in bonding and joining applications in both micro-electrical and micro-optical packaging.Sander has a proven track record of developing bonding and joining processes which are currently used in production for consumer, medical, industrial and automotive applications.

Towards Global Fab Scheduling

Knopp, Sebastian
CTO
Planimize

Abstract
The Planimize Schedule Optimizer can now provide real-time schedules for any work center in a fab, offering a single optimization engine that is easier to maintain than dedicated dispatching or scheduling tools. Relying solely on Planimize software, with no third-party solver, it considers all complex operational constraints while simultaneously optimizing many conflicting objectives. The software has been in operation since 2023, generating schedules within minutes in fully automated 300mm front-end fabs in Europe. In this talk, we present some of our latest developments on cluster tool scheduling and preview a new tool, the Global Fab Scheduler, which builds on the genericity of the Planimize Schedule Optimizer to optimize the entire fab rather than individual work centers.

Biography
Sebastian Knopp co-founded the company Planimize in 2021 where he currently serves as CTO, focusing on the development of optimization software to enhance factory efficiency. He completed his PhD Thesis on scheduling in semiconductor manufacturing (St-Etienne, France, 2016) and has a degree in computer science (Karlsruhe, Germany, 2006). Before founding Planimize, he worked at different companies on optimization software in the domains of logistics and education.Stéphane Dauzère-Pérès is Professor at Mines Saint-Etienne in its site of Gardanne, France. He received the Ph.D. degree from Paul Sabatier University in Toulouse, France, in 1992 and the H.D.R. from Pierre and Marie Curie University, Paris, France, in 1998. He was a Postdoctoral Fellow at M.I.T., U.S.A., in 1992 and 1993, and Research Scientist at Erasmus University Rotterdam, The Netherlands, in 1994. He has been Associate Professor and Professor from 1994 to 2004 at the Ecole des Mines de Nantes, France. His research interests broadly include modeling and optimization of operations at various decision levels (from real-time to strategic) in manufacturing and logistics, with a special emphasis on production planning (lot sizing) and scheduling, and on semiconductor manufacturing. He has published more than 120 papers in international journals and has contributed to more than 300 communications in national and international conferences. Stéphane Dauzère-Pérès has coordinated numerous academic and industrial research projects, including 4 European projects and 31 industrial (CIFRE) PhD theses. He was runner-up in 2006 of the Franz Edelman Award Competition, and won the Best Applied Paper of the Winter Simulation Conference in 2013, the EURO award for the best theory and methodology EJOR paper in 2021, and the EURO award for the best review EJOR paper in 2026.

Towards Global Fab Scheduling

Dauzère-Pérès, Stéphane

Planimize

Abstract
The Planimize Schedule Optimizer can now provide real-time schedules for any work center in a fab, offering a single optimization engine that is easier to maintain than dedicated dispatching or scheduling tools. Relying solely on Planimize software, with no third-party solver, it considers all complex operational constraints while simultaneously optimizing many conflicting objectives. The software has been in operation since 2023, generating schedules within minutes in fully automated 300mm front-end fabs in Europe. In this talk, we present some of our latest developments on cluster tool scheduling and preview a new tool, the Global Fab Scheduler, which builds on the genericity of the Planimize Schedule Optimizer to optimize the entire fab rather than individual work centers.

Biography
Sebastian Knopp co-founded the company Planimize in 2021 where he currently serves as CTO, focusing on the development of optimization software to enhance factory efficiency. He completed his PhD Thesis on scheduling in semiconductor manufacturing (St-Etienne, France, 2016) and has a degree in computer science (Karlsruhe, Germany, 2006). Before founding Planimize, he worked at different companies on optimization software in the domains of logistics and education.Stéphane Dauzère-Pérès is Professor at Mines Saint-Etienne in its site of Gardanne, France. He received the Ph.D. degree from Paul Sabatier University in Toulouse, France, in 1992 and the H.D.R. from Pierre and Marie Curie University, Paris, France, in 1998. He was a Postdoctoral Fellow at M.I.T., U.S.A., in 1992 and 1993, and Research Scientist at Erasmus University Rotterdam, The Netherlands, in 1994. He has been Associate Professor and Professor from 1994 to 2004 at the Ecole des Mines de Nantes, France. His research interests broadly include modeling and optimization of operations at various decision levels (from real-time to strategic) in manufacturing and logistics, with a special emphasis on production planning (lot sizing) and scheduling, and on semiconductor manufacturing. He has published more than 120 papers in international journals and has contributed to more than 300 communications in national and international conferences. Stéphane Dauzère-Pérès has coordinated numerous academic and industrial research projects, including 4 European projects and 31 industrial (CIFRE) PhD theses. He was runner-up in 2006 of the Franz Edelman Award Competition, and won the Best Applied Paper of the Winter Simulation Conference in 2013, the EURO award for the best theory and methodology EJOR paper in 2021, and the EURO award for the best review EJOR paper in 2026.

From Back-End Commodity to Performance Driver: The Strategic Role of Advanced Semiconductor Packaging in Automotive and ADAS Systems

Paul, Marco
Senior Expert | Automotive External
Porsche Consulting

Abstract
Advanced semiconductor packaging has emerged as a critical bottleneck and differentiator in the global semiconductor industry at a time when demand for compute, bandwidth, and energy efficiency is rising across multiple sectors. While front-end scaling is slowing and becoming increasingly capital-intensive, advanced packaging enables continued system-level performance gains through heterogeneous integration, chiplets, and multi-die architecture.From a macroeconomic perspective, this shift intersects with several structural trends:• the global race for semiconductor competitiveness and supply-chainresilience,• increasing geopolitical concentration of advanced packaging capacity,• and accelerating digitalization of industries such as automotive, AI, andindustrial automation.In automotive in particular, the transition toward software-defined vehicles and higher levels of driver assistance concentrates computing power into fewer, more capable electronic control units. This amplifies the importance of packaging technologies that can deliver high bandwidth, low latency, robust thermal behavior, and automotive-grade reliability—making advanced packaging a strategic topic not only for engineers, but also for executives responsible for sourcing, operations, and long-term competitiveness.

Biography
Marco Paul is a Senior Expert at Porsche Consulting, specializing in semiconductor strategy, innovation and industrialization. His work spans smart-factory transformation, emerging semiconductor technologies - including wide-bandgap semiconductors and advanced packaging - and the semiconductor requirements of AI-enabled physical systems in automotive and robotics. He represents Porsche Consulting on SEMI Smart Manufacturing and has authored industry perspectives on semiconductor strategy, silicon carbide and advanced packaging. Marco holds an M.Eng. in Mechanical Engineering and an Executive MBA and combines technical depth with a strategic perspective on translating emerging technologies into scalable industrial and business impact.Jonas Altmann is a Senior Manager at Porsche Consulting specializing in technology strategy, R&D transformation, and innovation-driven operating model design. His expertise spans corporate technology strategies, organizational transformations, technology ecosystems, and international partnerships. With extensive experience across the automotive industry, China, and Southeast Asia, he focuses on innovation ecosystems, technology partnerships, and the development of future-ready R&D organizations and operating models. Jonas participates in the SEMI Global Automotive Advisory Council and holds an M.Sc. in Aerospace Engineering, combining deep technical expertise with broad experience in technology.

From Back-End Commodity to Performance Driver: The Strategic Role of Advanced Semiconductor Packaging in Automotive and ADAS Systems

Altmann, Jonas
Senior Manager | Development & Technology
Porsche Consulting GmbH

Abstract
Advanced semiconductor packaging has emerged as a critical bottleneck and differentiator in the global semiconductor industry at a time when demand for compute, bandwidth, and energy efficiency is rising across multiple sectors. While front-end scaling is slowing and becoming increasingly capital-intensive, advanced packaging enables continued system-level performance gains through heterogeneous integration, chiplets, and multi-die architecture.From a macroeconomic perspective, this shift intersects with several structural trends:• the global race for semiconductor competitiveness and supply-chainresilience,• increasing geopolitical concentration of advanced packaging capacity,• and accelerating digitalization of industries such as automotive, AI, andindustrial automation.In automotive in particular, the transition toward software-defined vehicles and higher levels of driver assistance concentrates computing power into fewer, more capable electronic control units. This amplifies the importance of packaging technologies that can deliver high bandwidth, low latency, robust thermal behavior, and automotive-grade reliability—making advanced packaging a strategic topic not only for engineers, but also for executives responsible for sourcing, operations, and long-term competitiveness.

Biography
Marco Paul is a Senior Expert at Porsche Consulting, specializing in semiconductor strategy, innovation and industrialization. His work spans smart-factory transformation, emerging semiconductor technologies - including wide-bandgap semiconductors and advanced packaging - and the semiconductor requirements of AI-enabled physical systems in automotive and robotics. He represents Porsche Consulting on SEMI Smart Manufacturing and has authored industry perspectives on semiconductor strategy, silicon carbide and advanced packaging. Marco holds an M.Eng. in Mechanical Engineering and an Executive MBA and combines technical depth with a strategic perspective on translating emerging technologies into scalable industrial and business impact.Jonas Altmann is a Senior Manager at Porsche Consulting specializing in technology strategy, R&D transformation, and innovation-driven operating model design. His expertise spans corporate technology strategies, organizational transformations, technology ecosystems, and international partnerships. With extensive experience across the automotive industry, China, and Southeast Asia, he focuses on innovation ecosystems, technology partnerships, and the development of future-ready R&D organizations and operating models. Jonas participates in the SEMI Global Automotive Advisory Council and holds an M.Sc. in Aerospace Engineering, combining deep technical expertise with broad experience in technology.

Closing Remarks

Notarnicola, Giovanni
Partner and Head of Semiconductor Industry
Porsche Consulting S.r.L.

Abstract
Coming Soon

Biography
Coming Soon

Closing Remarks

Hansen, Uwe
VP Power Component Development
Robert Bosch GmbH

Abstract
Coming Soon

Biography
Coming Soon

Standards for Compound Semiconductors: Balancing Speed, Maturity, and Technical Understanding

Schoser, Siegmar
Director Cooperations
Robert Bosch GmbH

Abstract
Over the past five years, compound semiconductor technologies, particularly silicon carbide (SiC) MOSFETs, have gained significant market share and are expected to continue their strong growth. Driven by electrification, energy efficiency, and high-performance power electronics applications, SiC has become a key technology for automotive and industrial systems. At the same time, SiC products in 2026 and beyond remain fundamentally different from established silicon technologies with respect to product maturity, material behavior, process understanding, degradation mechanisms, and supply-chain structure. Learning cycles are still fast and not yet at the flat end of the S-curve.This creates a critical challenge for standardization. Many existing semiconductor standards were developed in a silicon-dominated environment and are not yet fully adapted to the specific characteristics of SiC and other wide-bandgap materials. Examples can be found in raw-material characterization, wafer marking (e.g. SEMI T5), defect inspection (e.g. SEMI M83-0820), and reliability validation. SiC specific standard SEMI M55 covers polished monocrystalline SiC wafers, but explicitly recognizing the weakness that additional physical, electrical, and bulk properties may be required for a complete purchase specification.Reliability validation faces a similar situation. SiC power devices exhibit additional aging and degradation mechanisms compared with silicon, including bipolar degradation and gate-related instabilities. These mechanisms are still subject to ongoing research, and mature acceleration models are not yet always available to translate mission-profile stress into robust qualification test conditions. In contrast, users have valid expectations that standards protect them from reliability risks during the expected life of a product.Even if cause-effect relations are understood by some players in the industry, particularly by implementing a good traceability from raw material to finishes goods, they might keep it confidential to gain a temporary competitive advantage. Only after several years, when multiple players have undergone the same learning cycles, this know-how gets public and can be used for the definition of standards. This slows down the development of new or the update of existing standards. At the same time, scientific contributors are lacking the required mass production experience to provide sufficient knowledge and compensate the hesitation of industrial contributors.As a result, the industry must avoid two risks: defining standards too late, which may slow global alignment, and defining overly prescriptive standards too early, which may lead to misleading test requirements, unnecessary cost, or requirements not clearly linked to real application risk.One approach to overcome this problem could be to use SEMI “Guide” documents as temporary solutions in the sense of ‘best practice’ which describes best-known-methods, provide practical direction without over-specifying immature requirements. This approach can help the industry move from shared terminology and pre-competitive engineering consensus toward durable global specifications.Standardization for emerging materials such as SiC must balance speed with technical maturity. Premature standardization can create misleading requirements, while structured pre-standards collaboration, guide documents, and traceability-based learning can accelerate the path toward robust, globally accepted SiC standards.

Biography
After graduation in physics at the University of Konstanz and obtaining a doctoral degree from the University of Augsburg, Siegmar Schoser joined the Robert Bosch GmbH in 1998. With a broad field of experience in various positions in MEMS manufacturing, automotive customer project management for parking assist systems, senior management of ECU development for door and tailgate modules as well as blower controller electronics, he joined the power semiconductor and power module area of Bosch in 2012. Today he is directing a project team on cooperation and external sourcing with a strong focus on silicon carbide related topics.

PFAS Whitepaper

Bierwagen, Jakob
Teamleiter Forward Material Compliance for Semiconductors
Robert Bosch GmbH

Abstract
The semiconductor industry is facing increasing regulatory attention on PFAS while simultaneously enabling many of the technologies that support Europe's digital and green transition. This presentation provides an overview of the PFAS White Paper developed by the European Semiconductor Alliance, outlining the role of PFAS in semiconductor manufacturing, ongoing innovation efforts to reduce dependency where technically feasible, and the potential implications of future regulatory measures.The presentation will discuss how the semiconductor value chain is addressing PFAS-related challenges, the importance of maintaining technological feasibility and supply chain resilience, and the need for science-based, risk-driven regulatory approaches. It will also highlight key messages and recommendations from the White Paper, intended to support a constructive dialogue between industry, policymakers, and other stakeholders on the future of PFAS regulation in Europe.

Biography
Dr. Jakob Bierwagen is a semiconductor environmental and regulatory compliance expert at Robert Bosch GmbH in Reutlingen, Germany. He specializes in material compliance, environmental regulations, and sustainable semiconductor manufacturing. He currently serves as Chair of the Environmental, Health and Safety (EHS) Working Group of the European Semiconductor Industry Association (ESIA) and represents industry interests in discussions on environmental and chemical regulation affecting the semiconductor sector.Dr. Bierwagen works closely with the European Commission, Member State authorities, and industry stakeholders on the development of appropriate environmental requirements for semiconductor manufacturing, including the ongoing STM-BREF (Semiconductor BREF) process under the Industrial Emissions Directive. His work focuses on balancing environmental objectives with technological feasibility, innovation, and the global competitiveness of the European semiconductor industry.In addition, he is a member of the PFAS Working Group of the European Semiconductor Alliance, contributing to the development of the Alliance’s PFAS White Paper. He has also provided semiconductor industry input on behalf of Bosch to the GENESIS Consortium in support of discussions on PFAS and future regulatory approaches.For today's topic, Dr. Bierwagen brings both an industry and policy perspective, combining practical semiconductor manufacturing experience with active engagement in European regulatory and sustainability initiatives.

From Insights to Impact: Simulation-Enabled Determination of Actionable Fab Enhancement Measures

Behrens, Korbinian

Robert Bosch Semiconductor Manufacturing Dresden GmbH

Abstract
Bosch's 300 mm Dresden semiconductor fab is characterized by a highly diverse mix of ASICs, MOSFETs, and MEMS products in ramp up. This creates a production environment in which equipment and process releases as well as performance improvements constantly reshape factory capacity and performance. In such an environment, accurate prediction of wafer output and cycle time is challenging.In this presentation, we will describe how fab simulation overcomes this challenge by providing a digital twin of the dynamic production environment that can not only predict future performance but also explain it. By revealing the process steps, equipment groups, and operational constraints that limit factory performance, it makes current and future bottlenecks transparent. This enables derivation of actionable insights. Identified bottlenecks directly translate into targeted improvement measures whose impact on wafer output and cycle time can be quantified before implementation. Measures with the highest operational benefit can be prioritised accordingly. As such, by connecting forecasts, bottleneck identification, and actionable measures, fab simulation becomes the key enabler of continuous operational improvement. In this way simulation evolves from a forecasting tool into a decision support system that systematically drives wafer output growth and cycle time reduction throughout the fab ramp up.In the presentation, we will also describe how this has been realized jointly by Bosch and D-SIMLAB through the deployment of the D-SIMCON Dynamic Capacity and Material Flow (DCMF) Planner, the flagship module of the AI-enabled D-SIMCON Digital Twin suite for Semiconductor Manufacturing, and the kind of benefits that have been achieved so far.

Biography
Peter Lendermann is a Co-Founder and serves as the Chief Business Development Officer of D-SIMLAB Technologies, a Singapore-headquartered company providing AI-enabled, simulation-based decision support solutions for Capacity Planning and Production Flow Optimisation to Semiconductor Manufacturing companies. Prior to this he worked at the Singapore Institute of Manufacturing Technology where he led related R&D activities until spinning them off into D-SIMLAB. Peter has been engaged in the field of production logistics, supply chain management and related decision support technologies and solutions since the early 1990’s. He holds a PhD in Physics from Humboldt University in Berlin (Germany) and an MBA in International Economics and Management from SDA Bocconi in Milan (Italy).Korbinian Behrens specialises in capacity planning and fab optimization at the Bosch semiconductor fab in Dresden, Germany. Responsible for fab simulation in a 300 mm high-mix manufacturing environment, he develops simulation-based decision support capabilities for capacity planning, production flow optimisation and operational performance improvement. His focus is on applying simulation and data-driven methods to support manufacturing decisions and identify improvement opportunities across semiconductor production. He holds a German Diploma in Business Information Systems.

Powering Europe’s Semiconductor Future: Energy Intelligence for Resilient, Sustainable Growth

Godemel, Frederic
Executive Vice President Energy Management
Schneider Electric

Abstract
Europe’s semiconductor industry is entering a defining era. Demand for advanced chips is accelerating alongside AI, electrification and digitalisation, while manufacturers must strengthen resilience, expand capacity and deliver on ambitious sustainability goals. Meeting these priorities requires more than additional power. It requires a smarter approach to how energy is generated, distributed and managed, from the grid to the fab.In this keynote, Frédéric Godemel will explore how the convergence of electrification, automation, digitalisation and AI is reshaping the energy landscape and creating new opportunities for industry. He will examine the growing relationship between the grid, AI factories and semiconductor manufacturing, and how Energy Intelligence can help turn growing energy complexity into competitive advantage.By combining connected hardware, software-defined architectures, data, AI, services and deep domain expertise, energy systems can become more visible, intelligent and responsive. For fabs, that means improving efficiency, reliability and operational performance while reducing emissions. Frédéric will also highlight why collaboration across the semiconductor, technology and energy ecosystems will be essential to building Europe’s future industrial capacity: resilient, efficient and sustainable by design.

Biography
Shaping the New Energy Landscape Frédéric's remit covers today's most urgent energy priorities, from meeting rising energy demand to strengthening energy security and sustainability. Responsible for over 80% of Schneider Electric's business, he and his teams deliver end-to-end solutions, advancing energy technology across infrastructure, data centers, buildings, and homes. Energy intelligence for efficiency, resilience, and sustainability By bringing together electrification, automation, digitalization and AI, Frédéric is unlocking "energy intelligence” to deliver measurable outcomes. Revolutionary technology released under his leadership includes: SM AirSeT, the first SF₆-free switchgear, eliminating a major greenhouse gas without compromising performance, reliability, or safety. One Digital Grid, a unified, AI-enabled platform helping utilities reduce outage penalties by up to 20%. The world’s first fully Software-Defined medium-voltage architecture enabling up to 3× faster ordering and manufacturing, up to 2× faster commissioning, zero-downtime upgrades, and up to 30% lower direct carbon emissions. Frédéric also oversaw the launch of Schneider Electric's global Impact Buildings Program, leveraging its own EcoStruxure™ solutions in Schneider offices worldwide. The program launched with The NEST in Dubai, delivering a projected 37% reduction in energy consumption, followed by the Winthrop Center in North America. In the data center space, Frédéric helps customers balance increasing compute demand with the need for greater efficiency and resilience. Today, Schneider’s technologies and expertise are trusted by 95% of the world's hyperscale data center operators. Accelerating progress through collaborationWith more than three decades of global industry experience, Frédéric knows that the new energy landscape won't be built in isolation. As Co-Chair of the Bloomberg Energy Tech Coalition, he convenes decision makers and experts worldwide to accelerate the adoption of demand-side technologies that drive greater energy efficiency.

Panelist

Jozic, Robert
SVP Disruption
Schwarz Digits

Abstract
Coming Soon

Biography
Robert Jozic leads Schwarz Digits Disruption, where he is responsible for identifying, developing future technologies, and building new digital business fields for the Schwarz Group (Lidl & Kaufland). Since joining the Group in 2016, he has held several key leadership positions, driving the creation and scale of strategic new ventures such as Retail Media and the AI Gigafactory, as well as leading the digital strategy, eco-system and digital business model sections of Schwarz Digital.Robert is a permanent member of the supervisory board of the German Research Center for Artificial Intelligence (DFKI) since 2018, a member of the board of DIGITALEUROPE, and a member of the Board of Trustees (Kuratorium) at the Max Planck Institute for Informatics. He started his career at an international strategy consultancy in 2001 and founded his own enterprise in 2005 for analytics and data mining. He participated in several start-ups and was managing partner at KPS. He studied Computer Science and Business Administration.

Writing applications for CHERIoT in Rust

Marangoni, Edoardo

SCI Semiconductor

Abstract
The project to make Rust work on the CHERIoT platform has been ongoing for a bit more than one year. In this year we have achieved many results, starting from compiling parts of the standard library to CHERIoT. While this initial work is fundamental, writing firmware for the CHERIoT platform requires specific features to be exposed to users: for example, how can one derive a valid capability that points to an MMIO-bound area of memory in pure Rust? How can one write a compartment in pure Rust? What about a shared library? We are now approaching a state where all the basic features to write firmware for CHERIoT in pure Rust are available, and the objective of this talk is to showcase these new features, and how they answer the questions above. Some of these features are CHERIoT-specific, while others are adaptable to every other CHERI platform. To this end, we will show multiple examples, each one explaining how to use the feature in case and how it works under the hood. The first example will show how to derive valid MMIO-bound capabilities using the `cheriot_mmio` attribute: we will show how to write a driver for the LCD on the ICENI MPW1 board in pure Rust. The second example will show how to declare and define statically-sealed values in Rust with the `cheriot_sealed` attribute, writing an interface for the CHERIoT-RTOS allocator in Rust. This example will also show how to use the API to dynamically allocate new sealed capabilities. The third and final example will show how to declare compartments in Rust with the `cheri_compartment` attribute and how to handle errors in Rust. This example will also show how to design security boundaries with compartments working on real-world CVEs that have affected Rust crates.

Biography
Edoardo has been working on compilers for the majority of his professional career. After working in the Wasm space, he joined SCI Semiconductor and started working on the Rust-on-CHERIoT project since its beginning. He has been involved with every aspect of it, ranging from technical tasks such as adding the CHERIoT target to organising work for the team and communicating about the project to make it more visible.

Connecting Technology and Society: SCREEN’s Vision for the Next Generation of Semiconductors

Goto, Masato
Representative Director, President and CEO
SCREEN Holdings Co., Ltd.

Abstract
As AI and digital transformation accelerate demand for high-performance and sustainable semiconductor technologies, the industry faces unprecedented challenges in terms of power consumption, manufacturing complexity, and innovation speed.In this keynote, Masato Goto, President and CEO of SCREEN Holdings Co., Ltd., will discuss how SCREEN Semiconductor Solutions Co., Ltd. is addressing these challenges through strategic partnerships and by developing advanced semiconductor manufacturing technologies.SCREEN’s growth strategy builds on its leadership in semiconductor manufacturing equipment while expanding its role in advanced packaging solutions for the AI era and its commitment to enable next-generation device architectures through innovations in wafer cleaning, lithography-related processes, wafer-to-wafer bonding, and panel-level packaging.Global R&D collaborations with leading semiconductor innovation centers, including imec and CEA-Leti in Europe, provide the foundation for both cutting-edge innovation and sustainability solutions aimed at resource-efficient semiconductor manufacturing.

Biography
Masato Goto is the Representative Director, President and Chief Executive Officer of SCREEN Holdings Co., Ltd.He joined Dainippon Screen Mfg. Co., Ltd. (now SCREEN Holdings) in 1990. He was stationed in the United States from 1995 to 2001, and in Europe from 2001 to 2009. During these 14 years overseas, he engaged in field engineering, helping clients achieve stable operation and improve productivity at their production sites, primarily through equipment setup and onsite maintenance.After returning to Japan, he became the general manager of the production department, in charge of ensuring a stable supply of equipment to clients. From 2011, he served executive officer, senior executive officer, and vice president of Semiconductor Equipment Company, in series.In 2019, he became the president of SCREEN Semiconductor Solutions. Utilizing the knowledge and experience accumulated over the years and with strong leadership, he continuously led sales to record highs.In 2024, he was appointed the head of corporate strategy at SCREEN Holdings. For over a year, he led the portfolio management of group businesses.He has served in his current role since June 2025.

Toward Autonomous Manufacturing: The Path from AI-Assisted Analytics to "Human in the loop" Agentic AI

Tropsa, Sean
Head of Technical Solutions, Growth Markets
Seeq Corporation

Abstract
As AI begins to meaningfully integrate into manufacturing operations, many companies are looking to get beyond deploying a basic chat bot. LLM Models are also advancing far quicker than they can be vetted for security concerns. In this session, Seeq will show how the Seeq Analytics and AI platform enables manufacturers to roll out scalable, trustable agentic AI workflows that are user customizable but purpose built for manufacturing environments. In practice, Intel has scaled the Seeq Platform and Agentic AI integrations within their ecosystem across their fabs to implement AI workflows allowing for faster time to detection as well as resolution for a given anomaly detected in the software, saving an estimated 7.5 million dollars through the platform roll out.

Biography
Sean Tropsa began his career as an engineer in the semiconductor manufacturing industry, where he developed expertise in analyzing large data sets with an emphasis on root cause analysis and process optimization. In his current role as the Head of Technical Solutions, Growth Markets, Sean leverages this background to help subject matter experts in the Semiconductor Industry apply Seeq to derive actionable insights from their data to meet sustainability goals, while improving reliability, yield, and quality. Sean holds both BS and MS degrees in Chemical Engineering from Arizona State University.

Opening Remarks

Manocha, Ajit
President and Chief Executive Officer
SEMI

Abstract
Coming Soon

Biography
Ajit Manocha is the president and CEO of SEMI, the global industry association serving the semiconductor and electronics manufacturing and design supply chain. Throughout his career, Manocha has been a champion of industry collaboration as a critical means of advancing technology for societal and economic prosperity. In his leadership role at SEMI, Manocha has broadened the association’s scope to fuel industry growth and foster collaboration on challenges such as geopolitical and sustainability concerns, the talent gap and supply chain disruptions. He has driven SEMI to evolve with the global microelectronics ecosystem as it rapidly expands to support smarter, connected applications based on artificial intelligence, machine learning and other disruptive technologies. Manocha was formerly CEO at GlobalFoundries. Prior to this, he held the role of Executive VP of worldwide operations at Spansion and earlier served as Executive VP and chief manufacturing officer (chief operations officer) at Philips Semiconductors. He began his career at AT&T Bell Laboratories as a research scientist and was granted more than a dozen patents related to semiconductor manufacturing processes that served as the foundation for modern microelectronics manufacturing. He has served on the boards of SEMI, the Semiconductor Industry Association (SIA) and Global Semiconductor Alliance (GSA). Manocha has overseen the formation of more than 20 joint ventures and M&As over his career. Out of these, some of the most noteworthy are the manufacturing JV between AT&T and Cirrus Logic, the foundry JV SSMC between Philips Semiconductors and TSMC, the back-end JV Suzhou ASEN Semiconductors between Philips Semiconductors and ASE, and the spinoff of Philips Semiconductors (now NXP Semiconductors) from Royal Philips Electronics. Manocha served on President Obama’s committees for “Advanced Manufacturing Partnerships” and the President’s Council of Advisors on Science & Technology (PCAST). Manocha holds the rare distinction of being inducted into two Hall of Fames. In 2021, VLSIresearch (now TechInsights) added Manocha to its Semiconductor Industry Hall of Fame for his leadership of SEMI efforts to address geopolitical trade tensions as well as for his initiative in navigating the many challenges of the COVID-19 pandemic impacting SEMI and the microelectronics industry. In 2020, Manocha was inducted into the Silicon Valley Engineering Hall of Fame, and VLSIresearch named him an “All Star of the Semiconductor Industry” for his visionary leadership in 2019 to restructure SEMI to represent the expanded electronics supply chain.

From AI Demand to Fab Reality: Investment, Capacity, and Manufacturing Outlook

Tseng, Clark
Sr. Director
SEMI

Abstract
AI is reshaping the semiconductor growth cycle and pushing manufacturing investment to a significantly higher level. However, the impact extends well beyond leading-edge logic. Memory expansion, technology migration, advanced packaging, and continued investment in mature-node and specialty manufacturing are broadening the next fab investment cycle.This presentation will examine SEMI’s latest outlook for global fab investment, equipment spending, installed capacity, and technology migration, highlighting how AI-driven demand is translating into manufacturing requirements across logic, DRAM, NAND, and specialty technologies. It will also look at the continued importance of 200mm and smaller-wafer manufacturing, where power, analog, compound semiconductors, MEMS, and other specialty applications continue to support substantial investment.The presentation will conclude with a regional perspective on Europe, examining how new fab investment, supply-chain resilience initiatives, and Europe’s strengths in automotive, industrial, power, and specialty semiconductor manufacturing position the region within the next global investment cycle.

Biography
Clark Tseng is Senior Director of Market Intelligence at SEMI, where he leads the development and execution of global market intelligence strategies covering the semiconductor manufacturing supply chain. He oversees SEMI’s market research portfolio and global research partnerships, providing analysis and forecasts on fab investment, capacity, equipment, materials, and semiconductor manufacturing trends.Clark has extensive experience analyzing the semiconductor industry across foundry, IDM, memory, fabless, and OSAT markets, with a particular focus on manufacturing investment, technology transitions, and regional supply-chain dynamics.Before joining SEMI, Clark held strategic and analytical roles at leading technology companies. At MediaTek, he served as Deputy Director of the Computing, Connectivity, and Metaverse Business Group, providing market intelligence and competitive analysis across computing, connectivity, automotive, and emerging technology markets. Previously, he was Division Manager for Strategy and Business Development at Qimonda, where he led market and competitive intelligence activities for the Asia-Pacific region. He began his career as an analyst at IDC, covering semiconductor, flat-panel display, and telecommunications markets.Clark holds a Bachelor of Business Administration and a Bachelor of Arts in International Relations from National Chengchi University in Taiwan.

Opening remarks by session chair

Michalopoulou, Eleni
Program Manager, Sustainability and Innovation
SEMI

Abstract
Aligning climate ambition, regulatory readiness and industry performance This session explores how sustainability, climate priorities, and EHS considerations are increasingly shaping semiconductor manufacturing and operations across Europe. Industry experts will share practical approaches and collaborative initiatives that support regulatory compliance, reduce environmental impact, and strengthen the resilience of the semiconductor ecosystem. Climate Strategy and Decarbonisation Pathways EHS and Regulatory Readiness Circularity and Resource Efficiency

Biography
Eleni Michalopoulou is a Program Manager for Sustainability Innovation at SEMI Europe, working to strengthen Europe's semiconductor ecosystem through collaborative innovation, sustainability initiatives, and strategic EU projects. She brings together industry, research, and policy stakeholders to address challenges related to climate, circularity, skills, and technological competitiveness.

SEMI Global Standards Summit 2026"Future Standards in Focus: Innovation and Industry Readiness"

Trio, Paul
Director
SEMI

Abstract
Now in its third edition, the Global Standards Summit (GSS) builds on the momentum of the past two events, providing a forum to identify potential areas for future standardization efforts.In a context of increasing complexity across the global semiconductor ecosystem, emerging technologies, regulatory requirements, and advanced research spur the need for effective standards development. The 2026 GSS will explore these current needs and contribute to shaping a roadmap for the next three to seven years.The GSS 2026 Panel discussion will explore AI in semiconductor manufacturing and its value chain and how SEMI Standard can promote AI adoption as well as be benefited from AI utilization.

Biography
With plasma etching process and equipment development engineering background, Ms. Mashiro has been active in SEMI Standards technical committees focusing on equipment-Fab integration enablers, such as EH&S, facilities, and physical interface specifications.She has been an active contributor to various SEMI EHS WGs including a leadership role in SEMI PFAS Initiative, a global technology community addressing PFAS supply chain challenges, as well as SIPS Japan regional PFAS WG.She is also active in IRDS (International Roadmap for Devices and Systems) and has been the co-chair of its Factory Integration focus team since 2016.

Welcome & Introductions

van Bilsen, Matthieu
Sr. Advisor
Semi

Abstract
Hosting session; - welcoming the audience & guest speakers- introducing guest speakers- Q&A and Closing

Biography
Matthieu van Bilsen is Senior Advisor to the SEMI Supply Chain Initiative.Previously, he was Global Executive Partner at IBM Consulting, bringing over 40 years of international leadership experience in the High-Tech and Manufacturing industries. He bridges technology innovation and business transformation, with hands-on expertise in supply chain, logistics and manufacturing, helping executive teams navigate complex change, globalization and digital disruption.

Moderator

Da Pont, Irene
Senior Coordinator (EU projects)
SEMI Europe

Abstract
Not applicable

Biography
Irene is Senior Coordinator for EU Projects at SEMI Europe in Brussels, where she leads initiatives focused on workforce development and talent growth in the semiconductor industry. Her work centers on building stronger links between industry and education through European-funded projects that promote skills development, upskilling, and reskilling across the sector. She coordinates the European Chips Skills Academy project and plays an active role in shaping new talent-focused initiatives and strategic project proposals. Irene holds a degree in European Law and a Master's in EU Policies, Projects and Funding.

Pantel Discussion Moderator

Ramundo Orlando, Stefano
Advocacy Manager
SEMI Europe

Abstract
Chips Act 2.0 and International Collaboration with Trusted Partners

Biography
As Europe moves towards the implementation of the Chips Act 2.0, strengthening international partnerships will be essential to building a more resilient, secure and competitive semiconductor ecosystem. Europe’s position across the semiconductor value chain depends not only on strengthening domestic capabilities, but also on deeper cooperation with trusted partners, including the US, Japan, Taiwan and South Korea.This session will examine how the Chips Act 2.0 can reinforce Europe’s strategic positioning and translate international partnerships into practical cooperation on supply chain resilience, technology, investment and innovation. It will also explore the role of initiatives such as ICOS in connecting European capabilities with trusted international ecosystems.

Welcome Remarks

Altimime, Laith
President
SEMI Europe

Abstract
Coming Soon

Biography
Laith Altimime, as President of SEMI Europe, leads SEMI’s activities in Europe and the Middle East and Africa (EMEA). Altimime has P&L responsibility as well as ownership of all Europe region programs and events, including SEMICON Europa. He is responsible for establishing industry standards, advocacy, community development, expositions, and programs. He provides support and services to SEMI members worldwide that have supply chain interests in Europe. He manages and nurtures relationships with SEMI members in the region and globally as well as with local associations and constituents in industry, government, and academia. Altimime has more than 30 years of international experience in the semiconductor industry. Prior to joining SEMI in 2015, He held senior leadership positions at NEC, KLA-Tencor, Infineon, Qimonda, and imec. Altimime holds an MSc from Heriot-Watt University, Scotland.

Opening Remarks & The Future Semiconductor Workforce: Skills, Inclusion and Retention

Srivastava, Kartikey
Manager, EU Projects
SEMI Europe

Abstract
Europe’s semiconductor ambitions depend not only on technology and investment, but on having the people and skills needed to support a growing and rapidly changing industry.Drawing on the work of three European initiatives: the European Chips Skills Academy, the European Chips Diversity Alliance and RESCHIP4EU - this opening presentation will explore some of the key workforce challenges facing the semiconductor sector, from developing the right skills and attracting new talent to creating workplaces where people can progress and stay.The presentation will also share findings from ECDA’s latest research on employee retention, highlighting the factors that influence people’s experiences and decisions to remain within the sector. Together, these perspectives will set the scene for the wider discussion on how AI is changing skills, recruitment and the workplace and what this means for the future semiconductor workforce.

Biography
Kartikey Srivastava is EU Projects Manager at SEMI Europe, where he coordinates the European Chips Diversity Alliance, an Erasmus+ project supporting skills and inclusion across Europe's semiconductor ecosystem. He has worked on a range of Erasmus+ and Horizon Europe initiatives in the semiconductor sector, focusing on project coordination, stakeholder engagement, and strategic communications. Kartikey works with partners from industry, academia, research organisations, and public authorities across Europe to deliver collaborative projects with long-term impact. He holds an MBA from ESMT Berlin and a Master's degree in International Political Economy from King's College London.

Opening remarks by session chair

Frieling, Christopher
Director Advocacy and Public Policy
SEMI Europe

Abstract
Opening remarks by session chair

Biography
Christopher Frieling is Director for Advocacy and Public Policy and Head of office at the SEMI Europe Brussels Office. He has a background in EU affairs, innovation, and tech policy. Mr. Frieling has 15+ years of experience in Brussels and leads SEMI's team for advocay and oversees all of SEMI's engagement in European projects. Prior to SEMI he worked at the Brussels office of Fraunhofer in several roles including most recently as Senior Advisor. Mr. Frieling holds an MSc in Economics of Science and Innovation and a Bachelor of Business Administration.

Standards for AI-enabled Factories

da Silva, Mark
Sr. Director, Manufacturing Collaborations
Semi US

Abstract
Coming soon

Biography
Coming soon

Buried crystallographic defect detection in Si/SiGe structures with Photomulinescence imaging

Sipőcz, Tamás
R&D Team Leader
Semilab Semiconductor Physics Laboratory Co. Ltd.

Abstract
Next generation logic and memory structures are build on Si/SiGe superlattice layers for creating FinFET/CFET or 3D-DRAM devices. The lattice constant difference of Si and SiGe is leading to strained EPI layers, which can relax depending on the Ge content, growth parameters and layer thickness. Relaxation of the EPI layers could generate misfit dislocations (MD) and threading dislocations (TD) in the structure. These defects can reach the surface, causing cross-hatch patterns, but most of the defects are remain below surface, buried under the EPI layers. Photoluminescence (PL) imaging technique is a non-contact and non-destructive method for detect these defects below surface and characterize the semiconductor sample goodness for later device production. Semilab's room temperature PL tool, En-Vision, is capable of measuring samples with high resolution, thus creating an opportunity for process optimization and defect characterisation.

Biography
Tamás Sipőcz is the team leader of semi PL imaging team at optics division in Semilab and joined the company 6 years ago, in 2020. He holds a Diploma in Pharmaceutical and Synthetic Chemistry from Eötvös Loránd University and has contributed to multiple publications and conferences.With his knowledge in optical metrologies, he supervises various metrology developments and research in the fields of room temperature photoluminescence imgaing.

Coming Soon

Wipprecht, Thomas
CEO
Siegert Wafer GmbH

Abstract
Coming Soon

Biography
Coming Soon

Impact of the AI Factory on EU Enviromental Regulations

Munsey, Michael
Global VIce President Semiconductor Industry
Siemens

Abstract
Data center growth, especially as it pertains to the AI factory, is straining our energy grids and forcing countries to evaluate how to generate enough electricity to power future growth. With racks witihin data centers approaching 1MW per rack, hyper scalers are investigating how to supply enough power from the grid to the chip. EU environemtnal regulations must be considered for the future of powering data centers. The entire ecosystem is connected, from the chip to the package to the board to the blade to the rack to the data center to the grid. The entire ecosystem must be optimized and standards across the ecosystem can help optimize and allieviate the future strain on the grid.

Biography
With over 30 years of experience in the semiconductor industry, Michael Munsey leverages his extensive background in global business development, strategy, sales, and marketing to drive semiconductor technology advancements at Siemens. Before joining Siemens, he held leadership positions at several prominent companies, including Perforce where he was Senior Vice President of Marketing and Strategy and oversaw the acquisition and integration of Methodics, Dassault Systèmes where he was Vice President of the High Tech Industry and built their Semiconductor Industry, and Cadence Design Systems where he oversaw their functional verification program and introduced the Incisive verification platform. Munsey began his career in semiconductor design at IBM after obtaining degrees from Tufts University. He is actively involved in several industry groups focused on setting standards and shaping the direction of the semiconductor sector. Additionally, he is an active member and volunteer of Tau Beta Pi.

Beyond Adaptive Manufacturing: Unlocking the Full Potential of the Integrated Autonomous Manufacturing Site

Wall, Leona
Head of Vertical Sales Electronics & Semiconductors Germany
Siemens AG

Abstract
As the semiconductor industry faces unprecedented cost pressures, labor shortages, and increasing process complexity, isolated fab automation is no longer sufficient. While conventional tools optimize individual processes, fabs continue to struggle with siloing between engineering, IT, OT, and facility operations. This presentation outlines the strategic paradigm shift toward the integrated autonomous manufacturing site. Moving beyond adaptive manufacturing to stable, scaled operations requires a unified digital and physical ecosystem. We examine how breaking silos across domains and connecting facility management with production data enables true self-optimization, predictive infrastructure resilience, and maximum energy efficiency. Attendees will gain actionable insights into how software-enabled integration - leveraging a robust data foundation and advanced automation architectures - accelerates ramp-up times, drives ROI, and transforms the fab into an agile, autonomous ecosystem for future-proof manufacturing.

Biography
Dr. Leona Wall is Head of Vertical Sales Electronics & Semiconductors Germany at Siemens AG. She leads Siemens' strategic engagement with semiconductor and electronics customers in Germany and has a proven track record of supporting industry leaders in scaling manufacturing capacity and navigating complex transformation initiatives across the semiconductor value chain. With a background in strategy consulting at Siemens Advanta and academic research at EPFL Lausanne, her expertise spans large-scale transformation, integrated industrial solutions, and innovation at the intersection of technology and business.

Keynote - With CHERI, can we afford to ignore hardware security?

Bormann, Joerg

Siemens EDA

Abstract
In response to the evolving geopolitical landscape, governments are increasingly driving cybersecurity through regulatory frameworks, such as the Cyber Security Act, and by incentivizing research through targeted funding. Siemens EDA occupies a pivotal role at the intersection of academic research and semiconductor manufacturing. We fulfill this role by actively contributing to the cybersecurity community—partnering with the CHERI Alliance and shaping standards like the Common Weaknesses Enumeration (CWE) and about security collaterals for third-party IP at IEEE. Furthermore, our verification portfolio leverages formal methods to identify deeply embedded malicious modifications in hardware, addressing a critical risk vector in CHERI-based system design.

Biography
Jörg Bormann is Product Manager for Advanced Verification at Siemens EDA. He is responsible for Siemens EDA’s formal Trust and Security verification technology and the GapFree solution, that formally verifies all circuit functionality. Previous employments include Infineon, Intel and OneSpin Solutions.Jörg Bormann received in 2009 his Dr.-Ing. from the University of Kaiserslautern after an extra-occupational graduation on the GapFree verification approach. His professional interest includes new approaches for the verification of the interaction of firmware and hardware of embedded systems.

Digital Twin and Architecture Exploration for Chiplet Ecosystem Optimization

Behmann, Nicolai
Technical Solution Architect
Siemens EDA

Abstract
The transition from monolithic SoCs toward chiplet-based architectures introduces new opportunities for scalability, reuse, and heterogeneous integration, but also creates new challenges in system architecture, interoperability, performance optimization, and ecosystem integration. In particular, combining chiplets from multiple vendors requires system developers to evaluate architectural choices and integration effects long before all physical components are available.This presentation introduces a Digital Twin-driven methodology for exploring and optimizing heterogeneous chiplet-based systems, combining virtual prototypes with physical components in hybrid environments. The approach enables chiplets, interconnects, memories, software workloads, and system-level behavior to be represented and evaluated at different levels of abstraction. Virtual models can therefore complement available silicon, enabling architecture exploration to start early and progressively evolve toward hybrid and physical system configurations.A particular focus is placed on multi-vendor chiplet interoperability. By integrating virtual representations of chiplets and subsystem components from different suppliers into a common system environment, architectural alternatives can be evaluated without requiring a complete physical implementation. This enables earlier investigation of system partitioning, chiplet selection, communication topology, memory architecture, compute allocation, and hardware/software interactions.The presentation will show how virtual and hybrid experimentation can turn the Digital Twin into an active architecture exploration environment rather than a static representation of the final system. Design alternatives can be evaluated against representative software workloads, allowing architects to investigate system-level trade-offs and identify integration issues before committing to silicon and packaging decisions.Ultimately, this approach provides a path toward a more open and collaborative chiplet ecosystem, where interoperability, architecture decisions, and system optimization can be evaluated digitally across vendor boundaries, reducing dependency on physical prototypes and enabling earlier convergence on system architectures.

Biography
Nicolai Behmann is a Technical Solution Architect at Siemens EDA, focusing on Digital Twin implementation and innovation at automotive customers through the PAVE360 program. His main interests include Machine Learning accelerators and Co-Design as well as mixed-fidelity modelling techniques. Before that, Nicolai was responsible for next-generation Compute Hardware for L4 robotaxis at Volkswagen. The topic of his PhD thesis and prior research at the Leibniz University Hannover includes application-specific hardware for automotive image signal processing

Heterogeneous Integration for Chiplets for Broad Industrial Applications

Han, BJ
CEO
Silicon Box

Abstract
This presentation explores a broad range of applications utilizing chiplet integration. The diversity of these applications poses significant manufacturing challenges, particularly when investment for production variety must be minimized. To address these hurdles, various manufacturing schemes are evaluated, and the current industry consensus is examined. Ultimately, the direction of this technological convergence will provide valuable insights for future investment strategies.

Biography
Dr. BJ Han is the CEO and co-founder of Silicon Box, a forefront semiconductor integration and advanced packaging company. An industry pioneer and inventor with over 300 patents, Dr. Han brings extensive expertise to Silicon Box to address the global shortage in chiplet integration infrastructure. His innovations, including Quad Flat No-Lead (QFN) and Fine-Pitch BGA (FBGA) packages, ship over 100 billion units annually.Prior to founding Silicon Box, Dr. Han spent 20 years at STATS ChipPAC, serving as Chief Executive Officer and Chairman of the Board. His distinguished 40-year career also includes leadership and research roles at AT&T Bell Labs, IBM Research, and Amkor, as well as consulting with Bain & Company. Recognized globally for his contributions, he was awarded the Leonardo International Prize in 2025 for strategic investments in Italy's technological landscape and named to Tatler’s Asia’s Most Influential list in 2024 and again in 2025. Dr. Han holds a PhD from Columbia University and is an alumnus of the Advanced Management Program (AMP) at Harvard University.

'Prompt or Perish? How AI is Revolutionising Skills, Hiring & Workplace Ethics'

Deo, Navneeta
Startup Advisor
Silicon Catalyst

Abstract
Coming soon

Biography
Navneeta Deo is a semiconductor industry leader with 15 years of experience spanning hardware design, product definition, and product management across low-power, connectivity, computing, and security applications, including senior product leadership roles at ams OSRAM and Infineon Technologies.Navneeta currently serves as an Advisor at Silicon Catalyst, mentoring early-stage deeptech semiconductor startups on translating technical ideas into scalable, market-ready products and product strategy.In parallel, she is pursuing independent PhD research on AI-based security for resource-constrained and embedded devices, exploring the intersection of machine learning, side-channel security, and energy-constrained system design.She also shares her perspective on semiconductor topics through her own publication, reaching audience interested in semiconductors, hardware, and AI.

Enabling the Transition to Mercury-Free Silicon Wafer Metrology

Hager, Thomas

Siltronic

Abstract
The Minamata Convention on Mercury is accelerating the reduction of mercury use and creating challenges for established electrical characterization methods in the semiconductor industry. Hg-CV measurements are widely established for the characterization of bulk and epitaxial silicon, providing reliable and high precision information on carrier concentration and related electrical properties. Existing standards, e.g. SEMI MF1392 or SEMI MF723, provide an important foundation for comparable silicon wafer characterization. However, increasing restrictions on mercury drive the semiconductor industry toward reliable and sustainable Hg-free metrology solutions. New and revised SEMI standards can facilitate this transition by defining common measurement procedures, performance criteria, and correlation methods between established Hg-CV and alternative Hg-free techniques.Siltronic, one of the top five global silicon wafer manufacturers and the only Western-based manufacturer among these leading suppliers, considers advanced metrology essential for maintaining its position as a technology leader. This is particularly important for Siltronic’s strategic focus on leading-edge and power products, where reliable and accurate material characterization is crucial.Standardized qualification and correlation procedures can enable the introduction of Hg-free technologies while maintaining measurement accuracy, reproducibility, traceability, and comparability across the semiconductor supply chain. Close cooperation between wafer manufacturers, equipment suppliers, semiconductor customers, and standardization bodies will therefore be essential. International standardization of Hg-free electrical characterization can become a key enabler for sustainable, future-proof silicon wafer metrology without compromising the stringent requirements of next-generation semiconductor technologies.

Biography
Dr. Thomas Hager is Director Metrology International at Siltronic AG and holds a Ph.D. in Physics. He has extensive experience in semiconductor technology and metrology, with expertise in semiconductor laser testing and silicon wafer characterization. His professional background combines research and development of advanced testing and metrology solutions with management responsibilities. Prior to joining Siltronic, he worked at OSRAM Opto Semiconductors, where he gained experience in semiconductor laser technology and testing.

Innovative Primary Substitution and Secondary Valorisation Routes for Europe's Silicon and Silicon Carbide Semiconductor Raw Material Value Chains

Somi Ganesan, Nagarajan
Research Scientist
SINTEF AS

Abstract
Silicon (Si) and silicon carbide (SiC) are foundational to modern electronics. Si powers logic, memory, and photovoltaic technologies, while SiC is critical for high-efficiency power electronics in electric vehicles, renewable energy systems, defense and aerospace applications. They drive digital and green transitions, holding complementary and non-substitutable roles in the global semiconductor value chain. Both materials start from the same source: quartz. Quartz is transformed through thermal and chemical processes into EG-Si (Electronic grade), achieving purity levels of 9-12N, and then drawn into Czochralski (CZ) or Float-zone (FZ) ingots for wafer production. SiC is produced by carbothermic synthesis, mixing quartz with carbon at temperatures up to 2500°C to form boules and wafers for high-power applications.High-quality quartz comes in two distinct grades. High-purity quartz (HPQ, >5N SiO₂) is indispensable for manufacturing quartz crucibles used in the CZ pulling of Si-ingots. Metallurgical-garde quartz (MGQ, 2N-3N) with precise granulometry and morphology is a critical bottleneck for Europe’s metallurgical grade (MG-Si) and SiC production, directly impacting the security of supply for semiconductor-grade SiC and poly-Si, amongst other strategic industrial outputs.ReSiLient, an EU-funded project, aims to strengthen Europe’s strategic capabilities in Si and SiC production by developing and upscaling integrated, sustainable process routes. The project will demonstrate the production of high-purity silica utilizing domestic minerals such as olivine and aplite, as well as industrial by-products such as Si slurry, quartz, and graphite residues. The high-purity silica produced will be utilized for the production of Si ingots and SiC boules, supporting a more resilient and circular European semiconductor raw material value chain.

Biography
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The role of Atomic-Level Purification (ALP) on reliability and yield in advanced packaging

Jahanshah Rad, Elmira Zahra
CTO
SisuSemi Ltd

Abstract
The semiconductor device structure is moving towards 3-D, high aspect ratio, and vertical, while the size of device is shrinking. Consequently, the role of surface area is becoming more important than ever. By nature, the surface part of a material is the worst part of it as it is in contact with contamination-rich environment and as it is the most impacted part of a material when it comes to uncontrolled reactions (e.g. with oxygen).The role of surface is even more critical in advanced packaging techniques as the surface quality defines the packaging yield and reliability. In hybrid bonding, the formation of void and the bond strength are highly dependent on having pristine surface. The impact of surface is crucial in wafer-wafer, wafer-die, and die-die bonding [1-3].Atomic-level purification is an emerging technology that provides atomic-level smoothness on the surface, reduces contaminants significantly, and provides a stoichiometrically uniform surface. All these surface properties are vital in packaging process as cleaning, surface activation, and unwanted oxides and contaminants on the surface result in unsuccessful packaging and reduces the production yield and reliability.ALP is a technology enabling the best control over surface reactions, stoichiometry, cleaning, and smoothness. This technology uses controlled reactions in ultrahigh vacuum environment which makes cleaning and smoothing processes more uniform and accurate on atomic level.Tadatomo Suga 2025 Jpn. J. Appl. Phys. 64 050801C. Shi, Y. Gao, J. Ding, W. Liu, Y. Chang, Y. Liu, Z. Xue, X. Wei, Applied Surface Science, Volume 737, 2026,166955Y.-S. Kim, T.H. Nguyen, and S.-H. Choa, 2022. Micromachines 13 (4): 537

Biography
BiographyZahra (Elmira) Jahanshah Rad holds a PhD in physics from the University of Turku with over 10 years of experience in high and ultrahigh vacuum systems, semiconductor device structures, and surface science. She has authored more than 26 peer-reviewed publications and is the inventor of six patents in semiconductor technology. Elmira is the Chief Technology Officer and co-founder of SisuSemi Ltd., a Finnish startup developing energy-efficient semiconductor solutions. Her work focuses on improving the powerefficiency and operational lifespan of silicon-based devices through advanced surface and vacuum engineering. She is committed to translating scientific research into sustainable technologies with real-world impact.

From Fragmented Data to Resilient Fabs: AI-Augmented Engineering for Europe’s Semiconductor Future

Varin, Arnaud
High-Tech Manufacturing Product Manager
Spotfire

Abstract
Europe’s semiconductor industry is entering an era defined by geopolitical uncertainty, supply chain pressures, rising manufacturing complexity, and an urgent need to improve competitiveness. In this environment, fab performance is not only a matter of equipment, process technology, or capacity. It increasingly depends on how fast engineering teams can turn complex, fragmented manufacturing data into trusted decisions.Today, yield, quality, process, equipment, test, wafer, and operational data often live across separate systems, tools, and teams. Engineers spend too much time moving between applications, reconciling data, rebuilding context, and repeating analysis before they can act. As fabs become more automated and data-rich, this fragmentation becomes a strategic risk: if something goes wrong, the same automation that increases productivity can also increase the volume of defective material produced before the issue is detected, understood, and contained.This presentation will explore a future in which industrial AI & analytics becomes a connected decision environment for semiconductor manufacturers. Rather than replacing engineers with AI, companies need to focus on augmenting engineering expertise with contextual analytics, domain-specific intelligence, statistical guidance, wafer-centric representations, and AI-assisted investigation. This approach helps engineers ask better questions, move faster across data domains, identify patterns earlier, and make decisions with confidence.Using Spotfire as an example of this vision, the session will discuss how visual analytics, advanced analytics, wafer-level analysis, scalable data access, and AI-assisted workflows can come together to support the next generation of fab management. The focus will not be on a product roadmap, but on broader perspectives: How software can help European fabs become more resilient, more adaptive, and more competitive while keeping human expertise at the center of manufacturing decisions.

Biography
Arnaud is the High-Tech Manufacturing Product Manager for Spotfire, with a focus on industrial investigations, data visualization, and semiconductor manufacturing use cases.Since joining Spotfire in 2013, Arnaud has worked closely with customers, frontline engineers, and scientists to understand complex analytical workflows and translate them into product capabilities that help engineering and operations teams make better-informed decisions. He currently leads Spotfire’s semiconductor manufacturing product investments, including wafer-centric analytics and yield and quality-improvement workflows. His work focuses on helping fabs connect fragmented data domains and tools, accelerate engineering investigations, and bring advanced analytics, visual exploration, and AI-assisted workflows into large-scale manufacturing environments.

From Fragmented Data to Resilient Fabs: AI-Augmented Engineering for Europe’s Semiconductor Future

Chimera, Alessandro
Industry Solution Lead
Spotfire

Abstract
Europe’s semiconductor industry is entering an era defined by geopolitical uncertainty, supply chain pressures, rising manufacturing complexity, and an urgent need to improve competitiveness. In this environment, fab performance is not only a matter of equipment, process technology, or capacity. It increasingly depends on how fast engineering teams can turn complex, fragmented manufacturing data into trusted decisions.Today, yield, quality, process, equipment, test, wafer, and operational data often live across separate systems, tools, and teams. Engineers spend too much time moving between applications, reconciling data, rebuilding context, and repeating analysis before they can act. As fabs become more automated and data-rich, this fragmentation becomes a strategic risk: if something goes wrong, the same automation that increases productivity can also increase the volume of defective material produced before the issue is detected, understood, and contained.This presentation will explore a future in which industrial AI & analytics becomes a connected decision environment for semiconductor manufacturers. Rather than replacing engineers with AI, companies need to focus on augmenting engineering expertise with contextual analytics, domain-specific intelligence, statistical guidance, wafer-centric representations, and AI-assisted investigation. This approach helps engineers ask better questions, move faster across data domains, identify patterns earlier, and make decisions with confidence.Using Spotfire as an example of this vision, the session will discuss how visual analytics, advanced analytics, wafer-level analysis, scalable data access, and AI-assisted workflows can come together to support the next generation of fab management. The focus will not be on a product roadmap, but on broader perspectives: How software can help European fabs become more resilient, more adaptive, and more competitive while keeping human expertise at the center of manufacturing decisions.

Biography
Arnaud is the High-Tech Manufacturing Product Manager for Spotfire, with a focus on industrial investigations, data visualization, and semiconductor manufacturing use cases.Since joining Spotfire in 2013, Arnaud has worked closely with customers, frontline engineers, and scientists to understand complex analytical workflows and translate them into product capabilities that help engineering and operations teams make better-informed decisions. He currently leads Spotfire’s semiconductor manufacturing product investments, including wafer-centric analytics and yield and quality-improvement workflows. His work focuses on helping fabs connect fragmented data domains and tools, accelerate engineering investigations, and bring advanced analytics, visual exploration, and AI-assisted workflows into large-scale manufacturing environments.

Pantel Discussion Moderator

Le Greves, Frederique
President
ST Microelectronics

Abstract
Chips Act 2.0 and International Collaboration with Trusted Partners

Biography
As Europe moves towards the implementation of the Chips Act 2.0, strengthening international partnerships will be essential to building a more resilient, secure and competitive semiconductor ecosystem. Europe’s position across the semiconductor value chain depends not only on strengthening domestic capabilities, but also on deeper cooperation with trusted partners, including the US, Japan, Taiwan and South Korea.This session will examine how the Chips Act 2.0 can reinforce Europe’s strategic positioning and translate international partnerships into practical cooperation on supply chain resilience, technology, investment and innovation. It will also explore the role of initiatives such as ICOS in connecting European capabilities with trusted international ecosystems.

Session Chair

Lopez, Jerome
Sr Manager & Sr Expert : Semiconductor Packaging
STMicroelectronics

Abstract
Coming Soon

Biography
Coming Soon

When the physical world meets AI: ST intelligent sensing at the core

Trollo, Lisa
Marketing and Communication manager, MEMS Sensors Subgroup
STMicroelectronics

Abstract
The next wave of AI is not confined to the cloud or the screen — it is becoming physical, embedded in the objects, machines and environments that surround us. This is where ST’s intelligent sensing sits at the core, transforming raw signals from the real world into actionable insights in real time.Sensors enable a new class of physical AI applications: from predictive maintenance and smart mobility to robotics, industrial automation, and consumer devices that understand context and intention. Combining high‑performance, low‑power sensing with on‑device AI and secure connectivity allows customers to move from data collection to local decision-making at the edge.

Biography
After joining ST in 2012, Lisa contributed to several success stories in consumer, automotive and industrial markets, such as the massive Inertial Measurement Unit (IMU) product deployment in the smartphone industry. Always working to help developers find the best solution for their applications, Lisa is currently in charge of our MEMS Ecosystem as well as Marketing Communication where she plays a key role in defining ST’s Artificial Intelligence strategy for MEMS and sensors. Lisa graduated with a Master’s degree in Telecommunication Engineering in 2006 from The University of Trento, Italy.

Panelist

Le Grevès, Frédérique
President France & EVP Europe and France Public Affairs
STMicroelectronics

Abstract
Coming Soon

Biography
Frédérique Le Grevès is STMicroelectronics’ Executive Vice President, Europe and France Public Affairs. She has also held the position of President of STMicroelectronics France since March 2021.In 1990, Le Grevès started her career in marketing and communication for various international companies in Europe and in the US. From 1995 to 2003, she worked at Aptiv (ex-Delphi Automotive) as EMEA Communication Director. In 2003, Le Grevès joined Nissan Motors as VP Communication for Europe and in 2004, she moved to Los Angeles as VP Communications for Nissan Americas. Le Grevès returned to France in 2008 and joined the Renault Group as Global VP for Corporate Communication. Two years later, she expanded her role to Global VP of Communications and Deputy to the Chief Marketing and Communication officer. In 2011, Le Grevès was appointed Chief of Staff for the Renault Nissan Mitsubishi Alliance Chairman and CEO. More recently, she worked as senior advisor for several companies helping on corporate effectiveness, operations efficiency, and brand reputation.Le Grevès has been an independent board member of the Supervisory Board of TRIGO Holding from May 2021 to December 2024 and sat on the Strategic Board of Clinatec since October 2021. She is also an independent Director of the Supervisory Board of North Atlantic (formerly Esso SAS) and became a member of their audit committee in June 2024. In 2022, Le Grevès was appointed President of the Strategic Committee for the Electronics Industry sector in France, and in June 2025 became President of the newly created French Electronics Federation (FdEF). She has also been Vice President of the European Semiconductor Industry Association (ESIA) since 2023. Le Grevès was promoted Knight of the Legion of Honor by the French Ministry of Economy and Finance in January 2023.Born in Suresnes, France, in 1967, Frédérique Le Grevès graduated with a master’s degree in business management from the Paris School of Business (1991) and graduated from the Senior Executive Program at the London Business School (2019).

Building the Workforce for the Future Fab: Anticipating capability needs and developing people at scale

Matteoda, Alice
VP - Business Human Resources Front-End Manufacturing
STMicroelectronics

Abstract
Coming Soon

Biography
Alice Matteoda is Front-End Manufacturing Business Human Resources at STMicroelectronics. She leads the people strategy for ST’s global front-end manufacturing organization, supporting workforce transformation, talent development, and organizational effectiveness across the company’s front-end manufacturing network. With nearly 20 years of international HR leadership experience in semiconductors, aerospace, automotive, and industrial manufacturing, she has extensive expertise in leading large-scale business transformations, organizational development, and capability-building initiatives. Alice is also co-founder of STEM by Women, an association promoting women’s careers in STEM fields

PFAS-free lubricants and greases for semiconductor manufacturing

de la Presilla, Roman
CEO
Sverion AB

Abstract
Emerging PFAS regulations are threatening the availability of perfluorinated lubricant oils and greases used throughout semiconductor manufacturing equipment. If Europe intends to lead the world in transitioning away from PFAS chemistry, we must take action towards deploying alternative lubricant chemistries now, particularly considering qualification timelines and industry specific validation requirements for new lubricants.This work showcases the development and production of ionic liquid lubricants and greases that offer a PFAS-free lubrication solution for demanding vacuum and ultra-clean environment applications. The new lubricants developed are not just "PFAS-free": they are silicon-free, halide-free, lihium-free, and fluorine-free. Third-party laboratory studies show that, when compared to state-of-art vacuum lubricants, they offer 10,000 times lower evaporation, up to 30 times the lifetime, up to 50% friction reduction in ball bearings, ball screws, and linear guides operated in a vacuum atmosphere and a remarkable level of surface protection. This scalable and Europe-manufactured lubricant platform has been validated in vacuum-operated machine components, providing the European semiconductor industry with a practical pathway to replace PFAS-based lubricants while establishing leadership in next-generation high-performance lubrication for vacuum applications.

Biography
Dr. Román de la Presilla is the CEO and co-founder of Sverion AB, a Swedish deep-tech company developing next-generation ionic liquid lubricants for high-performance industrial applications, including the semiconductor, aerospace, and defense industries. He co-founded Sverion in 2024 to translate his research into commercial technologies, developing PFAS-free, high-efficiency lubrication solutions.Román holds a PhD in Machine Design from KTH Royal Institute of Technology, where he maintains a research affiliation with the Department of Engineering Design. His work focuses on tribology, lubrication, and ionic materials for extreme operating conditions. He has authored numerous scientific publications and actively collaborates with academia and industry to accelerate the development and deployment of sustainable, high-performance lubrication technologies.

Engineering for cyber resilience: Through-life modelling and analysis

Shaikh, Siraj

Swansea University

Abstract
Coming Soon

Biography
Siraj Shaikh is a Professor in Systems Security at Swansea University (UK), where his research interests sit at the interface of automotive cybersecurity, systems engineering and cyber-physical systems security. Siraj is well published in automotive cybersecurity, and he currently is a Member of the College of Experts part of the UK’s Department for Transport (DfT) Scientific Advisory Council (SAC).Previously, he has been an Industrial Fellow to HORIBA MIRA, funded by the Royal Academy of Engineering (RAEng). More recently he served as an Independent Scientific Adviser to The Alan Turing Institute under the BridgeAI initiative. He serves as Chair for the Security Workstream of the Global Automotive Advisory Council at SEMI.

Engineering Bonding Materials for Power Devices Using Stress-Relaxing Sintering Materials and Transient Liquid Phase Diffusion Bonding Sheet

Abe, Shintaroh
Senior R&D Manager
TANAKA Precious Metals

Abstract
The continuous evolution of power semiconductor devices, particularly SiC and GaN, is driving increasing demands on bonding technologies in advanced packaging. Bonding layers must provide electrical conduction, thermal management, and mechanical compliance against coefficient of thermal expansion (CTE) mismatch under high-temperature conditions.In this study, we present an integrated approach to engineering bonding materials for next-generation power device packaging. This approach combines stress-relaxing sintering materials, transient liquid phase diffusion bonding (TLP bonding) sheets, and emerging Cu-containing systems, enabling optimized material selection for die attach, clip attach, and substrate attach.First, a stress-relaxing sintering paste is introduced for die attach and clip attach. This material can be applied by dispensing or printing, offering flexibility for various package structures. Its engineered microstructure, with resin domains dispersed within the sintered network, reduces elastic modulus while maintaining high thermal conductivity. This enables effective stress dispersion and achieves stable reliability beyond 2000 thermal cycles with suppressed interfacial degradation. Compatibility with bare Cu surfaces further supports cost reduction and simplified processing.Second, a TLP bonding sheet is presented for applications requiring high-temperature stability, including die attach and substrate attach. This material enables bonding at relatively low temperatures (~250 ℃) while forming high-melting-point intermetallic compounds after bonding. The bonding layer maintains high mechanical strength at 300 ℃ and demonstrates reliability beyond 2500 thermal cycles. This approach is particularly advantageous for large-area joints, making it suitable for substrate-level interconnections and large die applications.A bonding material selection framework is proposed, where stress-relaxing sintering materials are used for applications requiring compliance and process flexibility, while TLP bonding sheets are suited for high-temperature and large-area bonding.Finally, Cu-containing bonding materials are briefly introduced as a future direction to improve cost efficiency and compatibility with Cu-based substrates.In conclusion, a multi-material bonding strategy enables reliable bonding solutions for next-generation power devices.

Biography
Shintaroh Abe is a Global R&D Senior Manager at Tanaka Europe, specializing in bonding materials for power semiconductor packaging. His work focuses on the development and global deployment of Ag adhesives and stress-relaxing sintering materials for die attach applications.He has experience in copper nanoparticle and printed electronics materials, and has expanded technologies originally developed in Japan into overseas markets, supporting their adaptation and advancement in both Asia and Europe. He has been engaged in global R&D activities, contributing to the development of next-generation composite materials for power devices.

From Electrification to Physical AI: Securing Europe's Leadership in Power Semiconductors

Malaquin, Cedric
Practice Lead, Power Markets
TechInsights

Abstract
For decades, Europe has been at the forefront of power electronics and power semiconductor innovation, enabling advances in industrial automation, energy infrastructure, and automotive electrification. European companies have built a unique ecosystem spanning OEMs, Tier 1 suppliers, semiconductor manufacturers, wafer fab equipment companies, materials suppliers, and world-class research organizations.Today, the semiconductor industry is entering a new chapter. As artificial intelligence expands beyond the datacenter into the physical world, demand for efficient, reliable, and sustainable power management is set to grow dramatically. From AI datacenters and robotics to smart factories and intelligent energy systems, power semiconductors will be critical enablers of the next wave of productivity and economic growth.Europe is well-positioned to capture this opportunity. Its long-standing strengths in automotive, industrial, and energy applications provide a strong foundation for emerging markets such as AI infrastructure and physical AI. Yet competitive pressures are intensifying as China expands manufacturing capacity, strengthens domestic supply chains, and accelerates development across both silicon and wide-bandgap power semiconductor technologies.This presentation will examine the evolving global power semiconductor landscape, Europe's competitive advantages, and the strategic actions needed to sustain technology leadership. It will explore how investment, innovation, ecosystem collaboration, and international partnerships can strengthen resilience, enhance competitiveness, and support long-term growth as the industry moves from the age of electrification to the era of physical AI.

Biography
Cédric Malaquin is Practice Lead for Power Markets at TechInsights, with over 20 years of experience in the semiconductor industry. He specializes in power semiconductors and RF front-end technologies, covering both compound semiconductor and silicon technologies across automotive, industrial, consumer, and datacenter applications. Prior to TechInsights, Cédric led the Radio Frequency Devices Market Analysis team at Yole Group and held a variety of technical roles at Soitec in process development, integration, and electrical characterization. He combines deep technical expertise with market insight to help clients navigate the rapidly evolving semiconductor landscape.

Compartmentalizing a CANopen stack with CHERIoT

Melder, Hugo

Technical University of Munich

Abstract
Based on the CHERIoT architecture, we propose two architectures to restrict the blast radius of a potential exploit in an embedded system with a CANopen protocol stack. In both architectures, software components are compartmentalized and CAN frames filtered. The first architecture provides a lightweight firewall designed for reusing legacy C/C++ CAN stacks. The second architecture also features a firewall, but additionally offers strict flow isolation via sockets.We implement these architectures on a CHERIoT evaluation board. The resilience of the system is demonstrated through fault injection, showing safe recovery of crashed components without compromising the entire system. Its real-time viability is assessed by measuring latency and compartmentalization overhead.

Biography
Hugo Melder is a computer scientist interested in compilers, programming language runtimes, embedded systems, hardware acceleration, and security research.Over the past four years, he has worked across both hardware and software, including porting the Objective-C runtime to new architectures, designing FPGA accelerators, and contributing to open-source projects such as LLVM, GNUstep, and Apple’s Grand Central Dispatch. His work also includes reverse engineering and security research.Hugo recently completed a Bachelor of Science in Informatics at the Technical University of Munich with a minor in Electrical Engineering. He is also a co-founder of FAFO e.V., a nonprofit focused on semiconductor research and applied science.

Session Chair

Enzelberger-Heim, Michael
Fab Manager
Texas Instruments

Abstract
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Biography
Coming soon

Panelist

Floriot, Didier
Director Strategy Technology, Devices and Materials
Thales Las France SAS

Abstract
Coming Soon

Biography
Didier FLORIOT -. was graduated from Supelec in 1992 as electrical engineering in Semiconductor Physics. He received his M.S. and Phd from the university of Paris VI in 1993 and 1995 in the domain of III-V semiconductors. He joined the Thales research & Technology Center and worked on the development of the power InGaP/GaAs HBT technology up to his qualification. From 2000 to 2007, he was team leader at Alcatel Thales III-V Lab, a joint research group on III-V opto-microwave devices and power semiconductors. He joint UMS (United Monolithic Semiconductors) in 2007 in charge of technological and product cooperation with a focus on wide bandgap Sc. He occupied different positions up to the Director of technology innovation. In 2021, he joint Thales SA as Director corporate covering the domain of specific technologies including advanced technology of integration. Since 2026, he is now Director of Technologies, Devices and Material at the Global Business Unit Land and Air Systems at Thales. He is driving the technical & industrial parts of the project of transfer in Europe of advanced packaging technology (Foxconn / Thales / Radiall Joint Venture).

Winning in the EU: Margin & Complexity Over Volume

Tal, Oded
CEO
The MAX Group

Abstract
European fabs cannot outspend the industry’s volume leaders on capital. Leading-edge manufacturers reinvest a large share of their revenue into capacity, a level of spending few companies can sustain, and fewer still can sustain year after year. For most of the industry, including most European fabs, trying to compete this way is not realistic.This talk presents a different strategy. Fabs in the EU do not need to win on volume. They can win on margin instead, running high-mix, high-complexity work where customers pay for reliability and precision rather than the lowest cost per chip. European specialty manufacturers already follow this model, and it comes with a fraction of the capital intensity.Choosing this strategy is the easy part. Running it well is not. High-mix, high-WIP environments are unforgiving of weak operational discipline, and the fabs that get it wrong lose the very margin advantage they set out to capture.This talk draws on field results from directly supporting over 200 fabs globally to unpack what separates fabs that capture the margin advantage from those that lose it to their own complexity, and leaves attendees with a pointed question: is your fab built to compete this way, or just positioned to?

Biography
Oded Tal founded the MAX Group in 1999 and serves as CEO. Under his leadership, MAX has grown into the leading provider of management, operations, and engineering services to the semiconductor industry. He has also held executive roles for MAX clients navigating M&A, including CEO of TSI Semiconductors, where he led its transformation and sale.Before founding MAX, Tal held various positions in the semiconductor and automotive industries in the United States and Israel. After serving in the Israeli Air Force, where he taught piston engine maintenance, he began his career at Computest Automotive Test Equipment in development and operations management. He has served on the CS Mantech technical committee and board of directors, along with other commercial and NGO entities, and currently sits on the board of directors of Enablence Technologies.Tal holds a PhD in industrial engineering from Louisiana State University, where his research focused on hidden losses in automated semiconductor manufacturing. He also holds an MEM in engineering management from Ohio State University and a BS in industrial engineering, with a focus on manufacturing, from the University of New Haven.

Coming Soon

Doyle, Catherine
Technical Program Manager
Tokyo Electron Europe Ltd.

Abstract
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Biography
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Navigating the Perfect Storm: Why the Future of AI Depends on Manufacturing Innovation

Schmidt, Berthold
CTO
TRUMPF

Abstract
Artificial intelligence is fueling an unprecedented global semiconductor ramp. Around the world, new fabs, pilot lines, research centers and innovation ecosystems are being launched at remarkable speed.At the same time, the industry is entering one of its most significant technological transitions in decades. For years, progress was driven primarily by transistor scaling and shrinking feature sizes. Today, a fundamental question is emerging: What will ultimately enable the next generation of AI?[From Scaling to Systems]The industry's attention is widening from compute alone toward broader system architectures.Advanced Packaging, including hybrid bonding, co-packaged optics, new materials and increasingly complex manufacturing processes, is becoming a decisive differentiator. The future will not be determined solely by how small we can make transistors, but by how effectively we connect chips, move data, manage heat and integrate entirely new system architectures. This transition represents one of the most profound shifts the semiconductor industry has experienced in decades.[Europe's Opportunity in the Age of AI]For Europe, this transformation creates a unique opportunity. Europe holds world-class positions in many of the technologies that make next-generation semiconductors possible: optics, photonics, laser and plasma technologies, metrology, materials engineering, power electronics and semiconductor manufacturing equipment. Across industrial clusters such as Leuven, Dresden and Eindhoven, Europe has built capabilities that are deeply embedded in the global semiconductor ecosystem. The opportunity is not only to contribute technologies, but to help shape how future semiconductor systems are designed and manufactured.[With Speed and Collaboration to Industrial Impact]The challenge is not a lack of innovation. The challenge is transforming innovation into industrial impact at the speed required by a rapidly changing market.At the same time, global competition is intensifying. New semiconductor research centers, pilot lines and innovation ecosystems are emerging around the world. Europe's success will increasingly depend on how effectively we connect research and industry, accelerate technology transfer, shorten innovation cycles and build industrial momentum.EUV has demonstrated that breakthrough innovation emerges when complementary capabilities are connected through trust, long-term commitment and shared ambition. Replicating this success in the next wave of semiconductor innovation will require strong public-private partnerships that create trusted environments for collaboration, accelerate technology transfer and bridge the gap between research excellence and industrial deployment.Success will also require Europe to rediscover some of the entrepreneurial strengths that once defined its industrial leadership: the willingness to act decisively, move quickly and embrace calculated risk. In an increasingly competitive global environment, research institutions and industry must work together with greater urgency and shared purpose, as has become common practice in several Asian innovation ecosystems.[Creating the Conditions for Indispensability]Europe's greatest opportunity in the age of AI is not to achieve technological independence, but to remain technologically indispensable. Governments must take a more entrepreneurial approach to enabling industrial progress. Beyond funding, Europe will need faster decision-making, more agile regulatory frameworks and a reduction in administrative barriers. In a race defined by speed of execution, the ability to create competitive framework conditions quickly may become as important as technological excellence itself.

Biography
Dr. rer. nat. Berthold SchmidtChief Technology Officer (CTO)Member of the Managing Board of TRUMPF SE + Co. KGHead of Corporate Technology & New Business, Electronics Division, EUV Division, and New Sectors.Born in 1968 in Würzburg. Studied physics at the University of Würzburg and earned his doctorate at the Technical University of Munich.In 2013, joined TRUMPF Laser Marking Systems in Grüsch, Switzerland, in the Research and Development department.2015: Director of the Central Department of Corporate Research at TRUMPF GmbH + Co. KG, Ditzingen.2016: CEO of TRUMPF Photonics Inc. in Cranbury, NJ (USA).2017: Also CTO of TRUMPF Laser Technologie GmbH, Ditzingen.From 2020 to 2023, CEO of TRUMPF Photonic Components GmbH, Ulm.Member of the Executive Board since July 2023.

Pantel Discussion Moderator

Fagas, Georgios
Director
Tyndall National Institute

Abstract
Chips Act 2.0 and International Collaboration with Trusted Partners

Biography
As Europe moves towards the implementation of the Chips Act 2.0, strengthening international partnerships will be essential to building a more resilient, secure and competitive semiconductor ecosystem. Europe’s position across the semiconductor value chain depends not only on strengthening domestic capabilities, but also on deeper cooperation with trusted partners, including the US, Japan, Taiwan and South Korea.This session will examine how the Chips Act 2.0 can reinforce Europe’s strategic positioning and translate international partnerships into practical cooperation on supply chain resilience, technology, investment and innovation. It will also explore the role of initiatives such as ICOS in connecting European capabilities with trusted international ecosystems.

PIXEurope Pilot Line Training: Advanced Skills in PIC manufacturing for Industry

Wintersteller, Elisabeth
Training Programme Manager
Tyndall National Institute

Abstract
Skills shortages remain a major barrier to innovation in photonics, particularly in the evolving field of Photonic Integrated Circuits (PICs). Addressing this challenge requires coordinated, structured approaches beyond isolated training efforts. This work presents the development of a comprehensive training programme, outlining its objectives, design principles, and early outcomes. The training programme is designed and delivered within PIXEurope, the first fully integrated, open-access PIC pilot line, which bridges the gap between laboratory prototyping and full-scale manufacturing. Targeting SMEs, start-ups, and industrial users, it delivers industry-aligned training in advanced PIC manufacturing, leveraging Pilot Line infrastructure and expertise. By focusing on training unique to pilot line technologies, it will complement existing initiatives in the field. Its objective is to equip users to become literate in the pilot line research, technologies, and processes and to enable them to translate and apply the skills and expertise in their own environments. The programme will be fully operational by summer 2028 and expected to engage 1000 users annually.It is designed as a modular and expandable structure, with low access barriers being critical for its success. The programme offers training in PIC design, fabrication, packaging, testing, reliability, and equipment operation. These courses are delivered as stand-alone modules at introductory, advanced and specialised levels, allowing users to select courses aligned with their skills, needs, and interests.One example of an advanced stand-alone module is hands-on training in micro-transfer printing, a key enabling technology for heterogeneous integration in next-generation PICs. Developed and delivered by Tyndall National Institute’s in-house experts, this course offers the world’s first hands-on training programme in this cutting-edge technology for heterogeneous integration. It provides training on the state-of-the-art equipment, processes and semiconductor materials that underpin micro-transfer printing. To date, 64 professionals have been trained, with consistent oversubscription reflecting strong demand within the PIC ecosystem. The course achieves a recommendation rate exceeding 90%, demonstrating the high quality of the training provided.

Biography
Elisabeth (Liz) Wintersteller is Training Manager in the Advanced Packaging Team at Tyndall National Institute, University College Cork. She has over a decade of experience designing and delivering large-scale STEM training programmes across universities and international research centres. Her expertise includes coordinating complex education initiatives at national, European, and global levels, with a strong focus on interdisciplinary, research-driven environments. Previously, she held project management roles in the Human Brain Project education programme and delivered training at EMBL. She also managed major photonics training programmes at IPIC. In her current role, she leads the training programme for PIXEurope, developing impactful activities aligned with advanced research and innovation needs.

ICOS²: Driving International Cooperation on Semiconductors

Fagas, Giorgos
Director of Strategic Development
Tyndall National Institute

Abstract
As Europe shapes a potential Chips Act 2.0, trusted international partnerships will be essential for strengthening resilience, competitiveness, and technological leadership. ICOS² (International Cooperation on Semiconductor Innovation and Supply Resilience) is a Horizon Europe initiative designed to support this ambition by providing evidence-based insights and strategic recommendations to inform European semiconductor policy and cooperation with key global partners.This presentation will highlight how ICOS² identifies opportunities for collaboration with leading semiconductor ecosystems, helping Europe build more resilient supply chains, accelerate innovation, and reinforce its position in the global value chain. The presentation will also discuss how ICOS² can contribute to the implementation of a future Chips Act 2.0 by providing practical pathways for international engagement, joint research and innovation activities, talent exchange, and strategic industrial cooperation.

Biography
Pr Giorgos Fagas (PhD, MBA) is Director of Strategic Development at Tyndall National Institute and a member of its Executive Leadership Team, where he shapes the institute’s international strategy and leads major cross-cutting initiatives. An expert in advanced semiconductors, nanoelectronics and quantum technologies, he has played a central role in European research and innovation, contributing to Ireland’s Silicon Island strategy and the EU Chips Act through the implementation of pilot lines such as FAMES, horizon scanning and coordinating numerous EU-funded projects. Advancing international collaboration, expanding pilot line activities, and driving technology foresight efforts that strengthen Europe’s semiconductor ecosystem and global partnerships, Giorgos is the Director of SiNANO and coordinator of the ICOS² EU Coordination and Support Action on ‘International Cooperation on Semiconductor Innovation and Supply Resilience’.

Core to edge IoT security with CHERI

Cox, Peter

UM Labs

Abstract
UM Labs, a member of the CHERI Alliance, is a UK based cybersecurity R&D company specialising in securing real-time communication on IP networks. Our software spans cloud-based core services and edge devices running as embedded systems. This session reviews UM Labs’ experience in porting Unicus® IoT, our security platform to CHERI. Unicus protects IoT services running Zigbee, MQTT and other protocols using a Core/Edge architecture. Unicus Edge connects local IoT sensors and actuators and provides an authenticated and encrypted uplink to Unicus Core which provides provisioning and management functions. UM Labs have ported both the Core and Edge components of our IoT security platform to CHERI. This process used both hardware and virtualised targets enabling verification of the code at both compile time and run time. Problems identified in either phase of development and testing can be addressed, improving the quality and security of the delivered software. This process reduces the risk that latent flaws in memory management and code separation cause security violations in production. Using CHERI to build a complete commercially deployable end-to-end network security service demonstrates the maturity of the technology and shows the value of CHERI in any development project.

Biography
Peter Cox is the CEO and founder of UM Labs, a UK based R&D Company specialising in developing cyber security technology for real-time communications. Peter has over 30 years of cyber security experience and was the co-founder of one of the first commercial firewall companies.At UM Labs Peter designed the Unicus® security platform for real-time communication security covering voice and video telephony, streaming video, cloud extended reality and IoT. Unicus is widely installed in defence, government and commercial networks where it secures communications for a European National Defence Force.

CHERI-Zephyr and Compartmentalisation of Userspace Threads

Jackson, Jennifer

University of Birmingham

Abstract
This talk demonstrates how isolated CHERI compartments can be built on top of Zephyr's existing userspace thread model, showing that PMP-based isolation can be replaced by hardware-enforced capabilities while granting software components only the authority they require.Zephyr's userspace threads are a natural fit for building high-level software compartments because they already provide many of the isolation properties that compartments require. Today, this isolation is enforced through kernel-managed permissions and architecture-specific memory protection mechanisms such as RISC-V's PMP (Physical Memory Protection). CHERI enables the same security guarantees to be enforced directly through hardware capabilities, providing fine-grained, bounded access to memory without the region limits and domain-switching overheads associated with PMP. For example, each userspace thread is allocated its own stack, with isolation currently enforced through PMP. Under CHERI, this boundary can instead be enforced through a bounded stack capability installed by the kernel on entry, ensuring that out-of-bounds accesses are detected as hardware capability violations. Likewise, existing userspace system call interfaces map naturally onto CHERI compartment entry points, enabling controlled transfers of execution and authority between isolated software components. This enables developers to fully compartmentalise the library code their applications rely on to mitigate exploits or supply chain attacks. During the talk we will introduce CHERI-Zephyr and its development, explore how Zephyr’s userspace model aligns with CHERI compartments, and then present an AES encryption library case study implemented as an isolated proof-of-concept compartment.

Biography
Jennifer JacksonJennifer Jackson is a Research Fellow at the University of Birmingham, where she leads the development of CHERI-Zephyr and the CHERI-Zephyr Working Group. She has worked extensively with CHERI technologies since 2021, including Arm Morello and CHERI-RISC-V platforms, with a focus on applying capability-based security to embedded and real-time systems. With a background in Electronic Engineering, she brings over 25 years of engineering and research experience spanning industry and academia. Her interests include memory safety, software compartmentalisation, computer architecture, and the co-development of hardware, firmware, and software, alongside FPGA-based system design and collaborative Git-based open-source development.Jesse SpielmanJesse Spielman is a postdoctoral researcher at the University of Durham. He works on the CHERI-Zepyhr project implementing compartmentalisation features using CHERI technology. He recently completed his PhD at the University of Birmingham on the topic of using side channels to attack neural network activation functions. He is now developing expertise in the CHERI ecosystem and cybersecurity more broadly, having previously worked for 10 years on the technical side of film and TV visual effects production. He enjoys figuring out why things aren't working.

Efficient Linkage-Based Compartmentalization on CHERI

Gao, Dapeng

University of Cambridge

Abstract
We present an efficient linkage-based model for in-process compartmentalization built on CHERI memory safety.Our techniques enable the fine-grained compartmentalization of the entire UNIX user-space, which can scale to 10K+ compartments on desktop systems.The model's ""push-button"" compartmentalization along existing library boundaries regularly hosts 500+ compartments per process for large applications such as Chromium, far exceeding the number of concurrently available protection domains supported by other mechanisms (e.g., up to 16 for Intel MPK).Furthermore, custom policies can divide libraries into even more granular compartments.Of the thousands of C/C++ programs we have tested, only the V8 JavaScript engine required source-level adaptation (<300 lines of changed code concerning garbage collection and JIT compilation) to operate with compartmentalization.We implement the model for CHERI-extended versions of Armv8-A and RISC-V through support in the compiler toolchain and operating system, demonstrating the benefits of a single-address-space model, such as the smooth delegation of memory between compartments, as well as compartment-aware debugging and visualization.We evaluate using multiple processors, including Arm's superscalar Morello and, notably, the first commercial CHERI-enabled RISC-V application core—Codasip's in-order dual-issue X730.

Biography
Dapeng Gao is working towards a PhD on CHERI compartmentalization at the University of Cambridge under the supervision Prof. Robert N. M. Watson. Previously, he worked on the formal verification of a CHERI-enabled RISC-V processor for his master's thesis.

Using existing CHERI semantics for CHERI-native temporal safety

Wang, Yuecheng

University of Cambridge

Abstract
Unlike CHERI's native support for spatial memory safety, CHERI lacks inherent architectural support for temporal memory safety: capabilities can be freely copied and may remain reachable after the lifetime of the allocation they reference has ended. Existing approaches typically require additional metadata, memory scanning, or substantial software support, introducing performance and memory overheads. This talk explores how architectural support for temporal safety can instead be integrated with CHERI while avoiding external metadata and shadow tables.We will present the key design choices developed across three recent works: using capability bounds to protect temporal metadata within allocations, encoding temporal state directly into capabilities, and exploiting CHERI's hierarchical capability semantics to manage temporal state efficiently. We will then show how these ideas can be extended to support repeated reuse of the same memory. Together, these design choices demonstrate how existing CHERI semantics can be leveraged to provide efficient temporal safety with broad security guarantees. These ideas have resulted in three work of mine so far: two have been accepted at top-tier security conferences, while the other one is currently under review.

Biography
I'm a second year PhD student, supervised by Prof Simon Moore. My PhD is about explore architectural extension to CHERI that supports efficient temporal memory safety. During the second-year of my PhD, I have successfully produced three paper on CHERI temporal safety, two have been accepted by top-tier security conferences, one is current under review by another top-tier conference.

Intra-allocation bounds enforcement in CheriBSD

Mazzinghi, Alfredo

University of Cambridge

Abstract
CheriBSD is the first UNIX operating system kernel with mature CHERI spatial memory safety support.CheriBSD kernel allocators introduce bounds enforcement guarantees as part of the API contract; however, there are additional opportunities to narrow capability bounds to minimise software privileges. Richardson (UCAM-CL-TR-949) introduces compiler-assisted sub-object bounds to automatically narrow capability bounds with the C address-of operator, so that pointers to structure members are automatically bound to prevent access to adjacent members. Importantly, this also applies to array members, which are more likely to be indexed with a dynamically calculated value. This technique is valuable to mitigate memory corruption attacks that only partially overwrite the contents of a structure, without overflowing the allocation boundaries. In practice, we have found this to be relevant for a number of past FreeBSD kernel vulnerabilities and has real impact on the mitigation rate achieved by CHERI memory safety. As part of our work, the CheriBSD kernel has become the largest body of software shipping with compiler-assisted sub-object bounds enabled by default.While sub-object bounds are valuable, they are currently considered to be a best-effort feature. This means that bounds may not precisely constrain access to nearby structure members under certain alignment conditions. Furthermore, sub-object bounds only apply to those cases in which the compiler can understand that the code derives a pointer to a sub-object. This talk introduces the problem of intra-allocation bounds enforcement in CHERI, grounding the discussion with quantitative and qualitative evaluation data from the CheriBSD implementation. While this discussion uses CheriBSD as a reference implementation, it applies equally to other operating system kernels, such as Linux, and user-space software.As part of our work on CheriBSD, we identify a wider class of intra-allocation bounds use cases and evaluate implications for further bounds enforcement opportunities.We identify three classes of intra-allocation bounds enforcement: compiler-assisted sub-object bounds, sub-allocation code patterns in kernel C code, and domain-specific bounds enforcement. In all these cases, a region of address space is further split into different logical components, possibly with different data types, which are accessed separately via pointer indirection. While the compiler toolchain can automatically handle most sub-object bounds enforcement, the other cases are not straightforward to detect and resolve. We contribute different approaches, developed within CheriBSD, to properly narrow bounds for these additional intra-allocation categories.At the same time, we introduce the problem of bounds representability for intra-allocation bounds. CHERI capability compression schemes introduce additional alignment requirements for large objects. The same restrictions apply to pointers to different regions within a larger address space allocation. In order to ensure precise intra-allocation separation, each separate region must be constructed taking into account these alignment rules. This has a significant impact on the security guarantees offered by intra-allocation bounds enforcement. We show how this affects the different classes of intra-allocation bounds; in particular, we measure the existence of unrepresentable sub-object bounds in the CheriBSD kernel and discuss how the issue has been addressed. This is especially relevant for large arrays embedded in kernel structures and variable-length arrays. Ultimately, we evaluate practical strategies to resolve these challenges, showcasing source code refactoring techniques, toolchain enhancements, and fail-close semantics that maximize the security guarantees of intra-allocation bounds.

Biography
Alfredo is a Senior Research Engineer at University of Cambridge and Research Engineer at Capabilities Limited.Their main research interest is on memory safety in operating systems, but also in temporal safety, tracing and program analysis. They have developed the initial CHERI pure-capability port of the CheriBSD operating system, which is currently one of the most mature CHERI-enabled code-bases. Other notable interests are the CHERI RISC-V standardisation effort, as well as the CHERI extensions to QEMU. They have also contributed to ports of various other software to CHERI, such as nginx, gRPC, CPython and Redis.

CVA6-CHERI - Ratified Specification Implemented and Vector Support Planned

Woodruff, Jonathan

University of Cambridge

Abstract
CVA6-CHERI has been under development as an ASIC-ready open-source demonstrator for the ratified RVY CHERI specification for the last two years. The Capabilities Limited team has recently pulled CVA6-CHERI forward to the ratified version of the RVY specification, along with QEMU, LLVM, OpenSBI and CheriBSD, achieving boot on the new specification on FPGA. New features include richer PTE enforcement, including SSTATUS bits for controlling generational revocation in the kernel, and removal of exceptions on capability branches. Timing has improved due to the architecture upgrade, and CVA6-CHERI now normally passes timing at 50MHz on the Genesys2 FPGA. CVA6-CHERI has also completed changes in response to formal verification, and is fielding issues from ASIC consumers as maturity approaches.We have also begun plans for the next phase of CVA6-CHERI development. The AIVHAI project plans to extend CVA6-CHERI with standard vector and matrix extensions using a hybrid of the PULP Ara interface and the Google Coral vector unit. We will describe our plans in this direction, which include AI-automated formal verification of the components and integrated system.

Biography
Dr Jonathan Woodruff is an Assistant Research Professor with expertise in processor architecture and microarchitecture as well as low-level software optimisation. Specialising in capability processor design, he has pushed into full-system optimisations including cache hierarchy, core timing, and multi-core designs as well as explorations into major security approaches including control flow integrity and private execution.

High performance CHERI tag controller

Joannou, Alexandre

University of Cambridge

Abstract
CHERI’s memory safety relies on its capabilities being unforgeable. A CHERI system provides this unforgeability guarantee by using a tagged memory: for each memory location that can hold a capability (128-bits), there exists an out-of-band tag to indicate raw data or valid CHERI capability. When a tag is set, it is safe to use the corresponding 128-bit data as a capability. Every memory write must carry a tag (1 if a valid capability is written, 0 for any other write) to ensure no capability can be crafted without obeying strict capability derivation rules. Current memory systems do not typically support tagged memory, and therefore need extending to support CHERI.The AXI tag controller aims to enable integration of CHERI capability tags with a standard memory system. It receives a tagged request which uses the AXI user field to carry the tag associated with a capability carried in the data field, and splits it into two requests, one for tag, and one for data. Neither of these new requests requires tagged memory, and they can therefore be serviced by conventional memory. The data request can be forwarded unchanged (except for the user field no longer being present), and the tag request can be aimed at a dedicated region of the standard memory, only accessed by the tag controller as a tag store.The tag controller provides some configuration flexibility to map the covered region and the tag store region, prevents access to the later, and uses it to back a hierarchical tag table consisting of root and leaf tag bits. Together with caching, using a hierarchical approach minimises required bandwidth for tag traffic, and ensures very low overheads for accesses to large regions of memory without tags. It uses a separate cache for the root table and the leaf table, allowing for low lookup latency on hit.The system verilog IP implementing the AXI tag controller leverages the HPDCache as its tag caches, and offers parameterizable tag table grouping factor and cache sizes as well as capability sizes should alternative CHERI format be explored. It can be used to enable CHERI systems to integrate with otherwise tag-oblivious memories, and is in use in our CVA6-CHERI work.

Biography
Alexandre Joannou is a senior researcher a the University of Cambridge. He joined the CHERI research team in 2013 for his PhD and has been contributing to the project since then at a architectural and micro-architectural level.

Coming Soon

Osswald, Marc
Business Unit Head Global Services
VAT Group

Abstract
Coming Soon

Biography
Coming Soon

Panelist

Frey, Christophe
Chairman of the Board
Vertical Compute

Abstract
Coming Soon

Biography
Christophe Frey is Chairman of the Board of Vertical Compute. he worked at Arm in various VP roles for 20 years. He has been the General Manager of Arm France from 2014 to 2026. Under his leadership, Arm’s French entity has experienced significant workforce growth, up to 500 employees. He also served as Vice-President of European Engagements, focusing on strengthening Arm’s presence within the European semiconductor ecosystem, engaging with public authorities, startups and partners. In 2025 he co-managed Arm Germany. Since 2026 he is acting as a mentor and ecosystem leader supporting startups in several European initiatives like the Silicon Catalyst ChipStart EU and the European Chip Design Platform accelerator. In 2024 he became an operating Partner at C4 Ventures investment fund, where he brings his 30 years of experience in the semiconductor industry, operations, and management in an international context. He also acts as an advisor for the French startup Arago and Chairman of the board of ChipMango, as well as advisory board member of SaasOffice. He holds a MS degree from PHELMA Grenoble and has held various roles in design, management, and program management at STMicroelectronics in Crolles, France, for 12 years.

Breaking the Volume Barrier in Mid-IR Photonics: From Specialized Sensors to Scalable Semiconductor Integration

Piotrowski, Adam
CEO
VIGO Photonics S.A.

Abstract
The Mid-Infrared (Mid-IR, 2–20 µm) spectral range holds immense promise for high-precision gas sensing, semiconductor metrology, environmental monitoring, and industrial IoT due to the distinct molecular "fingerprint" absorption bands located in this region. Despite its transformative potential, widespread commercial adoption of Mid-IR photonic devices has historically been constrained by fundamental industry barriers: high manufacturing costs, complex III-V and II-VI compound material engineering, the need for bulky cryogenic cooling, and a lack of standardized Photonic Integrated Circuit (PIC) platforms and micro-optical packaging.This presentation outlines the key technological and manufacturing breakthroughs required to scale Mid-IR photonics from niche, high-cost applications to high-volume semiconductor manufacturing. We explore advances in High Operating Temperature (HOT) detector architectures, plasmonic-enhanced absorbers, and wafer-level epitaxy (MBE/MOCVD) transition to 4-inch and 6-inch fabrication lines. Furthermore, we address strategies for heterogeneous integration with CMOS platforms and scalable packaging methods aimed at reducing Size, Weight, and Power (SWaP). By bridging the gap between complex compound optoelectronics and mainstream semiconductor manufacturing workflows.

Biography
A graduate of Warsaw University of Technology in 2002 with a master’s degree in electronics engineering. Holder of a Ph.D. degree in technical sciences obtained at the Military University of Technology in 2008.Since 2002, Adam Piotrowski has been working at VIGO Photonics S.A., introducing novel semiconductor production technologies to the company and managing its production. Since 2015, he has been acting as the President of the Board of VIGO Photonics S.A. and the President of the Polish Technological Platform on Photonics, being an Employer Association. Since 2017, he has been a member of the Board of Stakeholders of the Photonics21 Partnership, taking an active participation in the European technological development of photonics and microelectronics.He is the author of many publications on the methods of manufacture and application of the infrared detectors. He is responsible for the application development of novel sensor systems, especially laser-based, affordable gas detectors and analyzers. He took part in multiple national, European and pure industrial projects.

Coming Soon

Aal, Andreas

Volkswagen Commercial Vehicles

Abstract
Coming Soon

Biography
Andreas (SM/CRP) drove the semiconductor strategy activities at VW for many years, focusing on technology capability enhancements for the most advanced node-based chip products, including improved integration schemes, as well as optimisation of power electronics module qualification (both in funding projects and direct collaboration with industry players). In 2023, he joined VW Commercial Vehicles as system architect and project manager for Mobility-as-a-Service computing system solutions. He has 26 years of experience in the semiconductor industry, has authored over 50 publications on reliability, has given tutorials at IEEE IRPS and IIRW, as well as invited/keynote speeches at various conferences/conventions. Andreas is chair of the German VDE ITG MN 5.6 WG on (f)WLR, reliability simulations and qualification, chair of the European chapter of the SEMI Automotive Advisory Council and serves the Federal Ministry of Education and Research (BMBF) industry advisory board on cybersecurity. He is also a founding member of the Fraunhofer Chiplet Centre of Excellence (CCoE) and active within JEDEC and DKE.

Organic Image Sensors for Smart Rings and Medical Devices

Joimel, Jerome
CEO
VSTech Sensors

Abstract
Wearable health monitoring and SWIR-based imaging share a common bottleneck: today's photoplethysmography (PPG) and image sensors are built on rigid silicon or III-V substrates that constrain form factor, cost, and spectral coverage. This talk presents organic photodiode (OPD) technology as a route past that bottleneck and shows how a single thin-film sensor platform is being developed across two applications — a flexible PPG sensor for smart rings, and a low-cost SWIR camera originally developed for drone vision that also opens a path toward SWIR fluorescence imaging in medical devices.TechnologyOrganic photodiodes rely on a solution-processed, coatable active layer — a blended donor/acceptor bulk heterojunction sandwiched between hole- and electron-transport layers, an anode and a cathode, and a barrier encapsulation. This active layer can be deposited directly onto thin-film-transistor (TFT) backplanes on glass or polyimide, or onto CMOS read-out circuits, using standard coating equipment already used in the display and semiconductor industries. Because the photoactive stack is only a few hundred nanometers thick, the resulting sensor is sub-millimeter and mechanically flexible down to single-digit-millimeter bend radii. By tuning the absorber chemistry across three organic formulations, the same architecture covers the visible (380–700 nm), near-infrared (700–900 nm) and short-wave infrared (900–2500 nm, SWIR) bands without changing the backplane or camera design. VSTech holds an IP portfolio of 75 patents across 33 families covering the photoactive materials, device architecture and integration processes.Application 1 — Smart ringsContinuous PPG monitoring inside a ring is limited by available surface area and by the rigidity of conventional silicon-photodiode-plus-LED packages, which push most rings on the market today toward an 8 mm width. VSTech's OPD sensor strip integrates three photodiode channels (4.75 mm² each) tuned to green, red and near-infrared wavelengths (530/660/940 nm) alongside an embedded LED, on a single flexible substrate only 3.3 mm wide and conformable down to a 6 mm bend radius. The multi-channel, multi-wavelength architecture is designed to improve measurement robustness, while the flexible thin-film substrate follows the ring's curvature without the mechanical stack-up of rigid dies. This sensor has been introduced as a demonstration of how organic photodiodes can reduce ring width while keeping three independent PPG channels.Application 2 — SWIR camera: from drone vision to fluorescence imagingThe same coatable active layer, tuned into the SWIR band (1100–1500 nm), is being developed for a low-cost, cooling-free camera for drones, where SWIR vision improves usability in fog, rain and low-visibility conditions but has so far been limited by the cost of InGaAs sensors (commonly above $10k per unit). By replacing the InGaAs detector with an OPD active layer coated onto a CMOS read-out circuit, the same pixel architecture can be produced at a fraction of the cost per unit area, at the expense of some performance relative to cooled InGaAs — a trade-off acceptable for single-mission or high-volume deployment.This drone-vision camera architecture is directly relevant to a second, medical use case: SWIR fluorescence imaging. Fluorescence agents such as indocyanine green (ICG) emit into the SWIR/NIR-II window (roughly 1000–1300 nm), where reduced tissue scattering and autofluorescence give sharper contrast and deeper penetration than the NIR-I (700–900 nm) window used by most current fluorescence-guided surgery cameras. A low-cost, uncooled SWIR sensor built on the same OPD-on-CMOS architecture developed for drone vision could lower the barrier to adopting SWIR fluorescence imaging in surgical and diagnostic instruments, an application VSTech is now exploring as an extension of its drone camera work.Manufacturing and scale-upBoth applications rely on the same manufacturing logic: OPD active layers are applied by standard coating processes compatible with existing TFT and CMOS supply chains, allowing the same core sensor architecture to move from pilot-line production toward higher-volume manufacturing without requalifying the underlying device stack for each substrate or application.What attendees will take awayThis talk will cover the device physics and layer stack that give OPDs their spectral tunability, the design choices behind the smart ring and drone-vision SWIR camera described above, and the technical rationale for extending the same SWIR sensor toward fluorescence imaging applications.

Biography
Jerome Joimel is CEO and co-founder of VSTech Sensors, a French deep-tech company developing organic photodiode (OPD) sensors for smart rings, medical imaging, and low-cost SWIR cameras. He has spent more than 20 years in high-tech industries, taking technology from lab to pilot line to mass production and building international technical and operational teams.Before co-founding VSTech in 2024, Jerome spent a decade at Isorg, the pioneer of OPD-based image sensors, where he held four successive roles: R&D Process Manager, Chief Technology Officer, VP Strategic Partnerships, and Chief Operating Officer. He built Isorg's OPD process and IP strategy from the ground up, co-authored seven patents on OPD processes and applications, led its Series C fundraising with two major Japanese investors, set up its China business development office in Shenzhen, and directed production and quality through the launch of the first OPD-based wearable sensor.Earlier in his career, Jerome led development of the first fully flexible OTFT/OPD photodetector at Plastic Logic (Cambridge, UK) and worked on the technology transfer from its pilot line to mass production in Dresden, Germany. He began his career at Hewlett Packard's Printed Electronics Group in Ireland, working on thin-film testing and characterization on plastic substrates.Jerome holds an Engineering degree (Master's level) in Electronics and Industrial Computing, from IFITEP / Université Pierre et Marie Curie – Paris 6. He has spoken at CES, SID Display Week, SEMI FLEX, LOPE-C, IDTechEx and other leading industry events.

High-throughput modelling for materials in microelectronics

Turunen, Erja
Executive vice president
VTT Technical research centre of Finland

Abstract
Material innovations are emerging as a key driver of semiconductor progress as conventional scaling and device architectures approach their practical limits. Future performance and functionality gains will increasingly depend on new materials, advanced integration technologies, and novel semiconductor platforms rather than geometric scaling alone.The ability to systematically design and run virtual “what-ifs” scenarios in an integrated manner is widely recognised as a way to accelerate the respective R&D&I processes by an order of magnitude compared to trial-and-error approaches. The integrated computational materials engineering approach fuelled by AI-driven machine learning also enables the development of higher-performing materials and the identification of more cost-effective and sustainable solutions.VTT ProperTune has been developed over the course of the last 20 years and can be applied to a range of material problems and subject domain areas. Most recently, the VTT ProperTune applied to microelectronics material domains has been initiated. In parallel with the development of new building blocks for this novel modelling tool on classical computing platforms, VTT is studying algorithmic concepts inspired by quantum computing to enhance future capabilities.The objective is to investigate key material properties, including permittivity, piezoelectric coefficients, elastic constants, and density, as well as the differences between single-crystal and oligo-/polycrystalline materials. These properties largely determine the performance of microelectronics, sensors, and power electronics.A key aspect is the implementation of high-throughput workflows in which computational and experimental tasks are highly automated, in line with the vision of VTT’s Material Accelerator Platform (MAP) initiatives. Equally important is the strong integration with VTT’s design microfabrication and piloting activities.

Biography
Dr. Erja Turunen is the executive vice president of one of VTT’s two business units: Digital systems. As the leader of the unit, Erja’s work involves strategic planning, engaging stakeholders and representing VTT in different organisations. Erja is also a member of VTT’s executive committee. Erja’s current responsibility area is Digital systems covering microelectronics, quantum, flexible electronics, sensing solutions, physical AI, connectivity and cyber security.Prior to her current role, she used to work as vice president in two different excellence area at VTT. Turunen is also a respected researcher herself. She began her career at the Tampere University of Technology following by Aalto and has done her PhD from material science.Erja has been at VTT 25 years and having various management positions more than 20 years. Erja has been member for multiple European initiatives and networks. Currently she is active in BoD’s for Kvanttinova Oy, Tamlink Oy and Enter Espoo Oy

Hidden Costs, Visible Gains: How Sub-Fab Thermal Intelligence Drives Uptime, Energy Savings, and Sustainable Operations

Joyner, Mark
Sales Executive Expert, Semiconductor
Watlow Electric Manufacturing Company

Abstract
Driving Fab Uptime, Sustainability, and Operational Resilience Through AI-Enabled Thermal Analytics for Sub-Fab SystemsEvent/Format: Fab Management Forum at Semicon Europa 2026Company: Watlow Electric Manufacturing Co.Presenter: Mark JoynerE-mail: mark.joyner@watlow.comPresentation: Oral PresentationAs semiconductor fabs continue to scale advanced manufacturing operations while facing increasing pressure to improve uptime, energy efficiency, sustainability, and operational resilience, greater visibility into sub-fab thermal systems has become critical. This presentation demonstrates how fab-level thermal analytics and connected monitoring technologies can help semiconductor manufacturers identify inefficiencies, predict failures earlier, optimize maintenance strategies, and improve overall fab performance.Presentation Format: Fab Management Forum Technical SessionMotivationModern European semiconductor fabs rely heavily on Advanced Process Control (APC), Fault Detection and Classification (FDC), and fab-level analytics to improve yield and productivity. However, many thermal systems in the sub-fab and utility layers such as exhaust heating, abatement, forelines, gas delivery, and nitrogen heating are typically monitored only through local controller alarms and periodic maintenance. Despite operating outside the main process chambers, these systems have a direct impact on equipment uptime, process stability, energy consumption, safety, and environmental compliance, yet they often fall outside the scope of traditional fab-level monitoring.As a result, issues such as temperature and power drift, clogging or deposition in exhaust systems, sensor degradation, leaks, and wiring faults are frequently detected only after they lead to process excursions, unplanned downtime, or environmental risk. At the same time, European fabs face increasing pressure to reduce energy use and CO2 emissions while maintaining high-volume production in alignment with EU semiconductor and sustainability objectives. This work was motivated by the combined challenges of uptime risk, latent thermal-driven variability, and limited visibility into the energy and health performance of sub-fab thermal assets.This case study examines how systematic, sub-fab level thermal monitoring can complement existing APC and manufacturing analytics to support both competitiveness and sustainability in European semiconductor manufacturing.Scope and ObjectivesThe work combines expertise in thermal systems engineering, semiconductor manufacturing, and data analytics to investigate how high-resolution thermal data from sub-fab systems can be transformed into actionable operational insights. Data was collected from industrial heaters, SCRs, and control panels using connected controllers and supplemental monitoring points. The dataset included temperatures, setpoints, power consumption, electrical resistance, and controller health indicators, streamed into a standardized analytics pipeline.The analytics framework targets five key classes of failure and inefficiency modes that are relevant to production sub‑fab environments and can be characterized using fab‑level thermal monitoring:Thermal drift identified through long-term deviations in power-to-temperature response.Clogging and deposition effects in abatement and exhaust systems, detected via changes in temperature uniformity and power behavior; in one system, this enabled extending maintenance intervals from two weeks to twelve weeks.Heating faults and post-maintenance anomalies, such as mis-wired or degraded zones, identified through correlated power and temperature trends.Sensor and controller degradation, detected through abnormal thermal or power behavior prior to protective shutdowns.Energy inefficiencies, quantified through power trends linked to insulation loss, configuration errors, or drifted setpoints.The case study presents production examples and use cases illustrating several classes of failure and inefficiency and demonstrates how the same physics-informed methods can generalize across additional modes. The objective is to convert raw thermal signals into actionable information for engineering teams without duplicating existing Manufacturing Execution System (MES) or Advanced Process Control (APC) dashboards, while providing Application Programming Interface (API) access that exposes system-level data through a unified interface.Core InnovationThe core contribution of this work is a thermal analytics framework tailored specifically to semiconductor sub-fab systems. Rather than treating thermal data as generic IoT signals, the approach incorporates physics-informed features, including zone-to-zone balance, thermal response behavior, and electrical-to-thermal relationships.Key characteristics include early detection of heater and Silicon Controlled Rectifier (SCR) degradation, engineering-oriented outputs such as health indicators and fault precursors, and a low-disruption deployment model leveraging existing controller infrastructure. Results are exposed through standard interfaces to enable integration with fab analytics platforms. The data pipeline is designed to be secure, scalable, and compatible with evolving cybersecurity requirements.Collaboration & Ecosystem FitThe proposed framework is designed to complement existing fab analytics, APC, and FDC infrastructures, enabling collaboration between fabs, equipment suppliers, and control system providers. Standardized data access and APIs support joint development with R&D partners and facilitate reuse across multiple European fabs operating similar sub-fab architectures. By improving visibility into energy and health performance of utility systems, the approach aligns with European semiconductor and sustainability initiatives aimed at reducing energy consumption, emissions, and operational risk across the manufacturing ecosystem.Benefits and OutlookThe case study demonstrates measurable benefits, including reduced unplanned downtime, improved energy efficiency, and increased confidence in process stability. The framework is designed to scale across repeatable sub-fab system architectures using standardized industrial communication protocols, enabling deployment without hardware redesign while maintaining disciplined data models and integration practices.Over the next 3 - 5 years, the approach can evolve toward tighter integration with control systems through edge-based analytics and selective closed-loop actions, such as guided setpoint adjustments or power balancing within validated safety limits.Demonstrated using Watlow and Eurotherm industrial control platforms, the methodology is transferable to other controller ecosystems that support common industrial protocols, supporting the long-term goal of competitive, resilient, and environmentally sustainable semiconductor manufacturing in Europe.

Biography
Mark Joyner is a seasoned semiconductor industry professional with over three decades of experience spanning engineering and commercial roles. Originally from London, England, he began his career in the industry in 1989 and has since built deep expertise at the intersection of advanced thermal technologies and wafer fabrication.In his current role at Watlow, Mark leads Sales and Account Management across Europe, working with wafer fabs to deploy high-performance thermal solutions that enhance process stability, operational reliability, energy efficiency, and equipment uptime across fab and sub-fab environments.Mark holds an MSc in Molecular Electronics from Cranfield Institute of Technology. He lives in Edinburgh, Scotland, with his wife and son.

The Global Semiconductor Market: Crossing the $1 Trillion Milestone in Q3 2026 and the Outlook Ahead

Pröttel, Tobias
CEO
WSTS

Abstract
The global semiconductor industry is experiencing an unprecedented period of growth, reaching a historic milestone by surpassing US$1 trillion in annual sales already in August 2026. Driven primarily by accelerating investments in artificial intelligence, data center infrastructure, and advanced computing, the market is expanding at a pace never seen before.Drawing on the latest statistics from World Semiconductor Trade Statistics (WSTS), this presentation examines the key developments shaping the global semiconductor market in 2026. It highlights the extraordinary growth of the Memory and Logic segments, regional market dynamics, and the contrasting developments across major end-use applications. Particular attention is given to the European semiconductor market and the differences between traditional Automotive and Industrial applications and the rapidly expanding AI-driven data center segment.Looking ahead, the presentation provides an updated market outlook based on WSTS forecasts, with global semiconductor sales projected to exceed US$1.6 trillion in 2026 and reach approximately US$2.1 trillion in 2027. The analysis offers insights into the underlying growth drivers, evolving market structure, and future opportunities for the global semiconductor industry.

Biography
Tobias PröttelCEO, World Semiconductor Trade Statistics (WSTS)Tobias Pröttel is the CEO of World Semiconductor Trade Statistics (WSTS), a global non-profit organization providing semiconductor market statistics and forecasts. In his role, he leads the organization's worldwide activities, working closely with leading semiconductor companies and regional industry associations to ensure reliable and transparent market intelligence.With extensive experience in the semiconductor industry, Tobias focuses on global market developments, industry trends, and forecasting. He regularly engages with industry leaders and international organizations to provide insights into the evolving semiconductor landscape and the key drivers shaping its future.

Europe’s Independent Wide-Bandgap Foundry Service - From Customer Needs to Industrial Scale

Fischer, Axel
Director Sales EMEA
X-Fab

Abstract
The growing demand for advanced power electronics is reshaping industries ranging from AI infrastructure and data centers to renewable energy, industrial automation, and aerospace. As innovation accelerates, the ability to industrialize new technologies quickly and reliably becomes a key competitive advantage.This presentation explores how independent foundries, strategic partnerships, and manufacturing excellence are helping bridge the gap between innovation and high-volume production. It highlights the role of collaboration, quality-driven processes, and scalable manufacturing ecosystems in supporting the next generation of power semiconductor technologies and strengthening Europe's position in the global semiconductor landscape.

Biography
Axel Fischer is Head of Sales EMEA at X-FAB, based at the company's manufacturing site in Erfurt, Germany.He is responsible for driving sales across X-FAB’s complete technology and manufacturing portfolio, including CMOS, Power, MEMS, and Photonics solutions.With more than 30 years of experience in the microelectronics industry, Axel has held leadership positions spanning Marketing, Sales, Product Management, Technical Support, and Operations. He has developed deep expertise in building and scaling high-tech businesses across international markets.Axel began his career with Cypress Semiconductor in Munich and subsequently joined Texas Instruments in Nice, where he worked within the ASIC and Chipset organization.He later spent 21 years with Samsung Semiconductor, holding several executive leadership roles, including Head of Business Units, and played a key role in establishing and growing Samsung’s Foundry business across the EMEA region.Before joining X-FAB, Axel served as Chief Commercial Officer at ITEN, the Lyon-based pioneer in solid-state microbattery technology.In addition to his executive responsibilities, Axel actively supports emerging technology companies as an advisor and supports the Board of Directors of ElectraMet (USA).Axel holds a Master's degree in Automation Engineering and Electronics from the Technical University of Chemnitz, Germany.

Opening Remarks by Session Chair

Woittennek, Michael
Vice President Business Unit Wide-Bandgap
X-Fab

Abstract
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Biography
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Mobile Manipulation Robot-Based Fully Auto Fab Solutions

Jian, Guan
Vice President
YOUIBOT Robotics

Abstract
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Biography
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Closing Remarks by Session Chair

Rüster, Christian
Program Manager Funding Projects
ZEISS Semiconductor Manufacturing Technology

Abstract
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Biography
Comign Soon