Driving Heterogeneous Integration for AI and Beyond

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Abstract
The semiconductor industry is undergoing a transformative shift, with advanced packaging emerging as a critical enabler of performance, scalability, and cost-efficiency in the post-Moore era. Heterogeneous integration (HI), which combines diverse chiplets with varying process nodes and functionalities into a single package, addresses technical challenges such as shrinking transistor sizes, increasing interconnect density, and optimizing power efficiency. The surge in demand for artificial intelligence (AI) applications, particularly high-performance computing (HPC) and data center AI chips, has further accelerated the need for innovative packaging solutions like 2.5D/3D ICs, fan-out wafer-level packaging (FOWLP), and panel-level packaging (PLP). These technologies enable higher bandwidth, lower latency, and compact form factors essential for AI-driven workloads. Recent product developments, including chiplet-based architectures and high-bandwidth memory (HBM) integration, underscore the industry’s focus on powering next-generation AI systems.This presentation explores the technical imperatives and market dynamics driving advanced packaging, with a deep dive into panel-level packaging (PLP). PLP offers significant cost advantages by processing multiple packages simultaneously on larger panels, enhancing economies of scale compared to traditional wafer-level packaging. However, both the substrate and PLP markets face challenges, notably the lack of standardized panel sizes, which complicates equipment design and increases costs. PLP’s economic viability is further constrained by its suitability primarily for high-volume devices, limiting its total market size. Despite these hurdles, the convergence of technology and equipment requirements between substrate and PLP markets is fostering a more robust equipment supplier ecosystem, potentially unlocking greater scalability and innovation.The presentation will also highlight Lam Research’s cutting-edge solutions for advanced packaging, focusing on its advancements in chiplet-to-chiplet and chiplet-to-substrate heterogeneous integration. By addressing warpage, electroplating uniformity, and other manufacturing challenges, Lam Research is enabling scalable, high-performance packaging solutions tailored for AI, 5G, automotive, and consumer electronics applications. This convergence of market needs and technological innovation positions advanced packaging as a cornerstone of the semiconductor industry’s future.

Biography
Herbert Oetzlinger graduated from HTL Braunau in 1987 with a specialization in high-power electronics and electrotechnics. With over 30 years of experience in the semiconductor industry, he has built deep expertise in wet processing, particularly in advanced packaging technologies involving electroplating, wet etching, and wafer/substrate cleaning.Herbert held the role of Vice President of Business Development at Semitool Inc., where he was recognized for his deep process and hardware knowledge. During his tenure, he collaborated with leading global companies on innovations such as Fan-Out, Embedded Wafer-Level Ball Grid Array (E-WLB), and other cutting-edge developments in wafer-level advanced packaging.In 2012, he founded Semsysco GmbH and served as its CEO. Under his leadership, Semsysco became a global leader in high-speed electrochemical deposition, known for its comprehensive capabilities in wet processing for both wafer and panel-level applications.Following Lam Research’s acquisition of Semsysco in 2022, Herbert joined Lam as Vice President and Head of the Panel Product Line, where he continues to drive innovation in advanced packaging solutions.

Laser-based Annealing of Nickel Contacts for SiC Devices: Towards Thermally Robust Power Interfaces in 3D Integration

Clair, Maurice
Head of Process Development
3D-Micromac AG

Abstract
Thermal management and electrical integrity are critical bottlenecks in 2.5D/3D packaging, particularly for wide-bandgap semiconductors such as silicon carbide (SiC), which enable next-generation power-dense systems in the automotive and high-performance computing sectors. In this context, Ohmic contact formation (OCF) for SiC must evolve beyond conventional rapid thermal processing (RTP) to meet the demands of thin substrates, reduced thermal budgets, and higher integration density.This contribution explores a laser-based approach for localized OCF on SiC using diode-pumped solid-state lasers (DPSSL) with UV wavelengths. The study investigates the effect of varying laser fluence, pulse duration, and beam overlap on the formation of nickel silicide (Ni_xSi_y) contacts on 350 µm-thick 4H-SiC wafers with 70 nm NiAl metallization. Qualitative process trends are derived based on structural, electrical, and chemical performance indicators, with an emphasis on suppressing carbon-rich interfacial layers – a key factor in interface reliability under high thermal and electrical loads.Key findings show that:(1) Laser-based OCF enables electrically stable contact formation even under high laser fluences, indicating robustness and process tolerance;(2) laser energy density controls Ni_xSi_y thickness and uniformity in a predictable manner;(3) Optimized pulse overlap below 30% mitigates the formation of carbon accumulation at the metal/SiC interface.This laser-driven method represents a promising alternative to RTP, particularly where localized processing and reduced thermal budgets are required. By minimizing global substrate heating and enhancing interface stability, the approach facilitates improved thermal integration compatibility for SiC-based power devices in 2.5D/3D packaging environments.

Biography
Maurice Clair studied Mechanical Engineering at the University of Technology Chemnitz (Germany). He joined 3D-Micromac in 2005 as a development engineer and is now team leader of the technology and innovation management department. In his current role, he serves as the technical lead for ohmic contact formation on SiC (silicon carbide) materials, a critical area in advancing semiconductor technologies.Through his expertise in laser technologies, he has been instrumental in the development of innovative laser micromachining processes, including: laser trimming techniques for fine-tuning electronic components with both digital and analogue approaches and beam shaping for ultra-short pulsed lasers.

Development and manufacturing of Co-Packaged optics demonstrator on IC Substrate technology for the beyond state-of-the-art smart NICs and Switches

Park, Gyuhyeon

Advanced Technologies and Solutions

Abstract
As artificial intelligence, machine learning, and big data workloads have explosive growth, the demand for high-performance infrastructure as hyperscale data centre is pushing the limits. HiConnects is aiming to support industrial challenges by developing heterogenous integration core technology solution for energy-efficient and high-performance cloud and edge computing.In a subtask 3.3.2, we focused on the development of a co-packaged optics demonstrator based on the specifications of NVIDIA and the photonic components development in the pilot line. Specifically, the defined design will be delivered from NVIDIA after specifications of the envisioned product requirements for co-packaged optics NIC and switch. According to the design, AT&S will provide the proper solution on Integrated Circuit Substrate (ICS) or PCB with considering system levels needs. In addition, the simulation of heat spreading and mechanical stability (warpage) will be executed by considering different material parameters such as CTE, thermal and electrical conductivity, dielectric constant, and dissipation factor, respectively. PHIX will provide optimized interconnect solution and assemble the Silicon Photonics Transceiver interposer developed by IMEC, network chip, and driver ICs on the ICS. Thermosonic flip-chip bonding technique will be used where Gold micro bumping will be applied either on the ICS or chips. The micro-optical lenses from Teramount will be bonded on the SiPh transceiver chip and Fiber Connector will be attached accordingly. Finally, a functional testing of fully co-packaged optics demonstrator will be done by NVIDIA.In this work, we investigated the test vehicle in order to achieve the working demonstrator at the end of HiConnects project. The progress for the test vehicle preparation and output from the project will be presented in this talk. In addition, we will outline a perspective supply chain for co-packaged optics in smart NICs and switches.

Biography
Gyuhyeon Park obtained his Doctor of Engineer (Dr.-Ing) in Mechanical Science and Engineer from the Technical University of Dresden, Germany in 2021. He continued his research at Leibnitz Institute for Solid State and Materials Research (IFW-Dresden) as post-doctor in Dresden, Germany in 2023. His research focused on the fabrication of micro-sized device with thin film of magneto-thermo-electric quantum material.After he join Advanced Technologies and Solutions (AT&S), Austria, now he is focusing on the Optical Communication in the R&D department as Project Manager and delivering successful projects across various industries.

The Acceleration of Test Requirements Driven by Advanced Packaging

Pizza, Fabio
Business Segment Manager
Advantest Europe

Abstract
The growing complexity of systems, enabled by advanced packaging, is driving an unprecedented increase in test requirements.Key challenges - such as faster signal speeds, higher integration, power demands, thermal dissipation, limited access to critical test nodes, and early detection of failures - are driving new semiconductor test strategies. Trends and directions for the future of test are described.In particular, the advent of generative AI has significantly accelerated complexity challenges in test automation.To meet the ever-growing demand for computing power in HPC, graphics, gaming, AI, and ADAS applications, the semiconductor industry is rapidly adopting advanced packaging solutions at scale. This trend enables new approaches, such as multi-vendor and multi-chip integration for large SoCs.Testing across all stages of the manufacturing process is now a critical enabler of both quality and cost efficiency.At the wafer level, Automated Test Equipment (ATE) must provide system-level test coverage to prevent the costly packaging of defective silicon.At the package level, ATE faces increasing challenges, including managing large volumes of test data through limited access ports while also controlling power and thermal conditions.Innovative test strategies and technologies are required to address these demands, particularly those that manage thermal issues throughout the entire test flow. Effective thermal control solutions, from wafer to singulated die and from package to system-level test, are becoming essential for efficiently testing advanced 2.5D and 3D package assemblies.As a result, the role of the ATE-based test cell is evolving—from pure defect detection to complex system-level validation and optimized yield ramps for each new technology node and integration approach.

Biography
Fabio Pizza is a Business Segment Manager at Advantest Europe, within the V93000 Product Unit Marketing organization. Based in the Advantest Italy office, he is responsible for developing and executing strategies to protect and grow the V93000 market share in the Performance Digital segment — including HPC/AI, Mobile/Automotive Application Processors, and ADAS.In his role, Fabio drives the definition of competitive solutions and product roadmaps aligned with customer requirements for performance, cost of test, and innovation.He holds a Master’s degree in Electronics Engineering from Politecnico di Milano (Italy) and brings over 20 years of experience in the semiconductor industry.

Arago: Practical Optical Computing

Muller, Nicolas
CEO
Arago

Abstract
Arago has built an energy-efficient AI chip powered by light, codenamed JEF, designed to run AI workloads with 10x to 30x lower energy and cost overhead. Its mission is to drive the course of history forward. Based in France, North America, and Israel, Arago has assembled a world-class team of engineers, scientists, and operators from leading companies and research labs, and is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent deeptech venture firms and exited founders.

Biography
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Topic Coming Soon

Frey, Christophe
Vice-President of EU Engagements & General Manager
Arm France

Abstract
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Biography
Based in Sophia Antipolis France, he has been the General Manager of Arm France since 2014. He also serves as VP of EU Engagements where he focuses on strengthening Arm’s presence within the European semiconductor ecosystem.Prior to Arm he has held various roles in design and management at STMicroelectronics in Crolles, France, for 12 years. He contributed to establish the Crolles2 alliance with Philips and Motorola, an experience that led to his first international immersion in Austin Texas.He then joined the startup SOISIC, where he served as VP of Engineering before the company was acquired by Arm in 2006. At Arm, he has spent four years in Silicon Valley California as VP of Operations.In 2024 he became an operating Partner at C4 Ventures investment fund, where he brings his 30 years of experience in the semiconductor industry.He holds a MS degree from PHELMA Grenoble.

Ubiquitous AI Computing - AI Everywhere

Bond, Andy
Director - Silicon Verification
Axelera AI

Abstract
Artificial Intelligence, Machine Learning, ChatBots, MCPs, and a plethora of other terms associated with the evolution of computing are becoming as ubiquitous as the technology itself. Whether it's asking Alexa for cinema recommendations from the comfort of your sofa, prompting Siri to curate a playlist for your Monday morning commute, or utilizing GitHub Copilot to fix your Python syntax, AI has become an integral part of our daily lives.Despite this widespread integration, the underlying technology remains largely centralized and cloud-based, leaving edge customers underserved by existing solutions. From security and retail to industrial applications, robotics, automotive, and energy sectors, the demand for AI solutions continues to rise, yet the availability of suitable options lags behind.The edge space presents a unique challenge due to the contrasting requirements of performance, cost, and power consumption, making it a technically demanding yet ripe area for innovation. When combined with the fragmented nature of these sectors and the diverse range of applications, the prospect becomes even more fascinating and challenging.This presentation aims to introduce this rapidly evolving landscape and highlight the future challenges ahead. By referencing Axelera’s innovative hardware and software approach, we hope to initiate a discussion on how we can progress together.

Biography
Andy has accumulated over 25 years of experience in the semiconductor industry, working across various fields from processors to networking, as well as audio and finance.His experience covers most aspects of consumer electronics, primarily in the roles of design verification engineer and manager.Beginning his career at ST Micro, Andy has led teams at Icera Semiconductor, NVIDIA, and Cirrus Logic. Currently, as the Director of Silicon Verification at Axelera AI,he is applying his expertise to the dynamic field of artificial intelligence.

Topic Coming Soon

Schulze, Joerg
Spokesperson for the Bavarian Chips Alliance, Director of the Fraunhofer IISB
Bayern Innovativ GmbH

Abstract
Coming Soon

Biography
Experienced Semiconductor Physicist and Engineer with a demonstrated history of working in the research industry and academia. Skilled in Research and Development (R&D) for semiconductor-based Micro, Nano, Opto, Power, Quantum Electronics. Experienced Lecturer and Teacher in Experimental Physics, Semiconductor Physics-Engineering-Technolog

From Atoms to Algorithms: European Suppliers’ Technological Race to Stay Ahead in the Semiconductor Market

Haferl, Stephan
CEO
Comet

Abstract
Coming Soon

Biography
Stephan Haferl holds a Master’s degree in Mechanical and Process Engineering from the prestigious Swiss Federal Institute of Technology (ETH) in Zurich, as well as a Ph.D. His academic background laid the foundation for a career deeply rooted in technological expertise.He joined Comet in 2007 and has since held several leadership roles, helping drive the company’s growth through his strengths in business development, innovation and strategic leadership.Before joining Comet, Stephan served as General Manager at Bartec-Meta Physics SA and Chief Operating Officer at Bartec Bacab SA, where he played a key role in operational and strategic development.As CEO, Stephan Haferl leads Comet with a strong commitment to innovation and long-term value creation.

High-End Dose Management: X-ray Inspection protecting Next-Generation Advanced Packaging

Stickler, Daniel
Director X-Ray Technology & Components
Comet AG

Abstract
As semiconductor devices grow smaller, denser, and more complex, advanced packaging demands inspection solutions that deliver both clarity and care. Traditional X-ray approaches often struggle to balance image quality with sample integrity — a challenge magnified in fragile next-generation packages. Comet Yxlon is changing the game by pioneering real-world dose management studies and introducing next-generation inspection technologies that minimize radiation exposure without compromising resolution. This presentation will explore how advanced dose optimization not only safeguards sensitive components but also unlocks new levels of reliability, speed, and insight for semiconductor manufacturers. By adding intelligent dose control to X-ray inspection, Comet Yxlon is helping the industry move faster, with greater confidence, into the era of heterogeneous integration and 3D architectures.

Biography
Dr. Daniel Stickler is Director X-ray Technology & Components at Comet AG, X-Ray System Division. Based in Hamburg, Germany, he holds a PhD in Physics from the University of Hamburg and has extensive experience in X-ray imaging, semiconductor X-ray applications and product innovations.

Optimizing water usage footprint: Direct water recycling from abatements

Osten, Pascal

DAS Environmental Expert GmbH

Abstract
As semiconductor manufacturing advances, exhaust gas treatment systems—particularly point-of-use (POU) abatement units—play a vital role in maintaining safe and stable operation. These systems often rely on water to manage byproducts generated during gas treatment. By rethinking how this water is managed and treated, new opportunities arise to reduce overall water consumption without compromising process integrity. This presentation explores how aligning gas and water treatment at the POU level enables significant water recycling, with fresh water savings of over 90% achievable through targeted strategies.Our work focuses on enhancing water reuse by introducing a tailormade particle removal system installed directly after the abatement POU. This system is designed to address process-specific particle loads, which can otherwise limit recirculation potential. By removing these particles efficiently, the treated water becomes suitable for reuse within the same abatement units—creating a closed-loop solution tailored to the demands of the gas treatment process.This approach builds on field observations across multiple fabs and process types, where we observed that particle characteristics in abatement wastewater are closely linked to the upstream semiconductor processes. Recognizing this dependency, we have developed a flexible particle separation solution that can be adapted to different tool sets and chemistries. Early application of this system has shown that water quality can be stabilized sufficiently to support continuous reuse, while maintaining abatement performance and reliability.In addition, we address the issue of salt accumulation, a common challenge in high-recycle environments, through conductivity-based monitoring and control strategies. This ensures long-term operational stability even as recycling rates increase.This presentation highlights the potential of integrating gas and water treatment strategies in a purposeful way. Rather than viewing abatement systems as isolated water consumers, they can be transformed into platforms for water efficiency through the application of process-informed treatment technologies. A key takeaway is the importance of considering wastewater characteristics early in fab planning and collaborating with treatment technology providers to enable point-of-use or semi-centralized recycling concepts.

Biography
Pascal Osten is a German engineer currently serving as Technical Director for Global Water Treatment at DAS Environmental Experts GmbH.Born in Berlin, he studied physics and water management in Dresden, earning a degree in engineering.He began his professional career at wks Technik GmbH, working as a project engineer in environmental engineering for water and wastewater treatment facilities. During his time there, he contributed to several research and development efforts, some of which resulted in patent applications.Over the years, he took on increasing responsibilities, including leading a team in process engineering. In this role, he supported the successful implementation of a variety of customer projects, focusing on practical, reliable solutions.Today, at DAS Environmental Experts GmbH, Pascal draws on his hands-on experience in water treatment to support the development and execution of sustainable solutions for the semiconductor industry and beyond. He remains committed to advancing technologies that balance performance with environmental responsibility.

Leveraging Virtual Twins and AI/ML in semiconductor industry using 3DEXPERIENCE platform

Joshi, Smriti
Senior Manager Technical Solution - Semiconductor Industry
Dassault Systèmes

Abstract
Semiconductor companies optimize every stage of their operations—from research and chip design to production and supply chain—by leveraging a combination of multi-scale virtual twins and artificial intelligence. It helps reducing, downtime, enhance scalability, and improve resource efficiency, contributing to sustainable design and production practices.In this talk, we will present different virtual twins and AI/ML experiences for semiconductor industry. We will present how it can visualize, model and simulate the entire environment of sophisticated experience on a single platform known as 3DEXPERIENCE. This platform facilitates sustainable business innovation across the full product lifecycle from materials to process to equipment to fab virtual twins.Virtual twins replicate physical objects just like digital twins do, but they take it further, simulating the processes and interactions within an entire system or ecosystem. This could be a game-changer for the semiconductor industry and beyond, offering a more holistic approach to understanding and solving complex challenges. By incorporating real-world data in real-time, virtual twins can support various stages of semiconductor development, from product introduction to end-of-life, by optimizing and streamlining design, manufacturing, and testing processes. It can also accurately model and predict electrical and thermal behavior, and mechanical performance characteristics of the semiconductor device using simulation virtual twins. These simulations can be used to fine-tune designs for optimal performance. Simulation plays a significant role in the virtual twin, allowing companies to test product designs virtually, avoiding the need for costly prototypes. This accelerates development and ensures higher product performance. Additionally, simulation virtual twins can be used to predict real-world performance and understand failure modes, leading to design improvements over time.Along with creating virtual twins, it is very important to have AI-driven chip design and analysis. AI in chip design involves using artificial intelligence techniques, particularly machine learning, to improve the design, verification, and testing of semiconductor devices.

Biography
Smriti is currently working as a Technical Solution Senior Manager for Semiconductor Industry (High-tech) with Dassault Systèmes. She is responsible for understanding, consolidating and driving semiconductor technical solutions. She develops new solutions and provide enablement worldwide for semiconductor customers. She has over 14 years of R&D experience working with different foundries ST Microelectronics, Altis Semiconductor, X-FAB and research lab like CEA –LETI and Lip6 (U.P.M.C.).She received her Doctoral (Ph.D) degree in Nanoelectronics and Nanotechnolgy from INP Grenoble (France) in 2013.

Adhesives for highly efficient optical coupling of Photonic Integrated Circuits

Hartwig, Alexander
Senior Strategic Business Development Engineer
Delo Industrial Adhesives

Abstract
The emergence of 5G technology and artificial intelligence (AI) has significantly accelerated the demand for high-speed data communication, leading to the development of advanced packaging solutions such as 2.5D/3D packaging for AI applications. Silicon photonics packaging has emerged as a promising alternative to traditional copper-based electronics, offering faster data transmission with lower power consumption.Yet, the packaging of photonic integrated circuits (PICs) still faces challenges in achieving high performance and reliability. Key hurdles include the need for precise optical coupling with minimal loss, as well as maintaining reliability through reflow processes and environmental stress.Adhesives are crucial in overcoming these challenges at various stages of the packaging process. Understanding the necessary properties of adhesives - such as bond strength, optical transmission, and resistance to environmental stresses - is critical for successful packaging applications.This presentation explores active alignment strategies for optical coupling involving the use of adhesives. It discusses methods such as direct butt-coupling of fiber array units (FAUs) to PICs, surface coupling, and employing microlens arrays (MLAs) that allow for more relaxed alignment tolerances. Emphasis is placed on the adhesive requirements needed to ensure efficient coupling.Experimental data on coupling efficiency, tested under conditions like reflow and 85°C/85% relative humidity, are presented to demonstrate these approaches' robustness. These findings underscore the crucial role of adhesives in enhancing the performance and reliability of advanced photonic systems.Moreover, a novel approach will be presented, that preserves optical properties following wafer-level processing steps, such as sawing and grinding, by selecting materials with distinctive optical characteristics.

Biography
Dr. Alexander Hartwig, who holds a PhD in Physics, is a seasoned professional in the fields of solid state physics and adhesive technology. He is currently a Teamleader for Business Development Engineering at DELO Industrial Adhesives, where he focuses on developing innovative adhesive solutions for various applications.With many years of industry experience, Dr. Hartwig combines his deep scientific knowledge with practical engineering skills to support business growth and technological advancements. His expertise makes him a valuable voice at industry conferences and events, where he shares insights on the latest trends and developments in adhesive technology.

Topic Coming Soon

Heger, Tim
President Semiconductor Chamber Solutions Division
Edwards Vacuum

Abstract
Coming Soon

Biography
Tim Heger joined Atlas Copco Group in 2020 in the product company Leybold in Cologne as a Process Development Manager and has since then built a successful career within the Group. In 2023 he was appointed General Manager of Ceres Technologies based in the USA and prior to this he held a variety of positions within operations, supply chain and product management. Tim, a German citizen, will be based in Burgess Hill, UK and will relocate over the next few months. He holds a Master of Science in Mechanical Engineering from the University of Applied Science in South Westphalia, Germany.

A Novel Approach for the Volume Production of Wide-Bandgap Semiconductor

Barbar, Ghassan
Sales Director
ELEMENT 3-5 GmbH

Abstract
In this work we describe another epitaxial process. Here we present data of aluminum nitride (AlN), graphene interlayers and of SiC on AlN thin films on sapphire and of epitaxial growth of SiC on SiC grown by Next Level Epitaxy (NLE). The new process is using a surface temperature around 250°C by combining PVD (physical vapor deposition) and CVD (chemical vapor deposition). The growth procedure in NLE is similar to the MOCVD growth process with substrate cleaning, start layer and main layer. Compared to the reactive sputter processes and pulsed sputter epitaxy the NLE uses different plasma sources in various combinations.The NLE system is a homemade novel deposition system. In the current configuration, it has a capacity of up to 70 x 200 mm wafer at one time. As Al-source pure Al was used. As nitrogen source nitrogen gas, as Si-source silane and as carbon source for graphene and SiC methane which were introduced by a homemade ion gun. Additionally, argon, oxygen and hydrogen were used. During the process the surface temperature of the wafer was kept around 250°C. The used plasma sources are all designed as stripe sources. The wafer is placed on the carrier which is moving front and back in the growth chamber under the stripe sources. First the substrates were cleaned with a mixture of argon and oxygen and after with argon and hydrogen using the plasma. After the in-situ cleaning first a monolayer of aluminum was deposited followed by low plasma power and low growth rate AlN and after higher plasma power and higher growth rate AlN. The graphene layers were used as interlayer sandwiched between AlN and were compared with AlN grown in one step with the same total growth time. The experiments for SiC growth started recently. As seed for the SiC growth NLE-AlN on sapphire was used. Since AlN is counted as 2H-AlN it can act as seed for 2H-SiC and 4H-SiC.

Biography
Ghassan Barbar (Sales Director) received the chemical engineering degree from the university of Applied Science, Berlin, Germany in 2001. In 2022 he took over the position of sales director at ELEMENT 3-5 GmbH with a special focus on the product management for the ACCELERATOR 3500K. Prior to this, he worked as an independent consultant in the semiconductor industry. Before that, he joined Ebner Group in 2011 and held several roles within the sapphire department (FAMETEC) In 2018, he built up within the group SiC crystal growth division, which is a spin-off company (EEMCO) since 2020. Before that, he worked at AIXTRON in R&D for development of high-k and metal gate for CMOS applications by CVD/PECVD. Ghassan holds over 15 patents in crystal growth of Sapphire and SiC.

Optimizing Fab Performance: Proven Strategies from Materials to Manufacturing

Amade, Antoine
President Europe and the Middle East (EMEA) Region
Entegris

Abstract
In a world of rising complexity, speed, and billion-euro investments, fab startups face unprecedented pressure. Our presentation outlines key strategies for effective contamination and material management, and shares concrete, experience-based insights to support fab ramp-up and operational efficiency. With a focus on risk mitigation, digitalization and data sharing, environmental responsibility and workforce training, we provide proven and innovative solutions from specification definition to startup and beyond.

Biography
As president of the Europe and the Middle East (EMEA) region at Entegris, Antoine Amade is responsible for driving regional strategies and leading efforts to expand into markets that can benefit from Entegris’ unparalleled expertise in advanced purity and materials solutions. These include sectors such as semiconductor, desalination, clean hydrogen energy, and other high-tech and data-intensive industries.With 30 years of experience at Entegris, Mr. Amade has held leadership roles in gas and liquid microcontamination market management, strategic account management, and regional sales management. He has also held business management positions overseeing the market in North America.He holds a degree in Chemical Engineering from ENS Chimie Lille and is an active member of the SEMI Electronic Materials Group and the Global Automotive Advisory Council for Europe.

Topic Coming Soon

Koitzsch, Christian
President and Managing Director
European Semiconductor Manufacturing Company (ESMC)

Abstract
Coming Soon

Biography
Dr. Christian Koitzsch has been the president and managing director of the European Semiconductor Manufacturing Company (ESMC) since beginning of 2024. He was raised in Thueringia, is married and is father of two children. He studied Electrical Engineering at Technische Universität Ilmenau and North Carolina State University in Raleigh (US) and received a PhD in solid state physics from the University of Neuchâtel, Switzerland.

High-Resolution Inspection of Hybrid Bonds, Microbumps, and TSVs - Are X-ray Methods Ready for the challenges of Advanced Packaging?

Hansson, Björn

Excillum AB

Abstract
The push for higher performance, lower power consumption and smaller form factors combined with lower cost per function is driving the shift from 2D scaling to heterogeneous integration and advanced packaging methodologies. As advanced packaging grows in complexity, ensuring the yield and reliability of the intricate interconnects becomes increasingly challenging, necessitating the requirement for improved high-precision inspection methods from off-line failure analysis to at- and in-line inspection. X-ray nano-computed tomography (nano-CT) and X-ray laminography addresses this challenge by offering 3D X-ray imaging with sub-micron resolution, enabling precise visualization of critical internal features.While traditional X-ray imaging has been limited by resolution and throughput constraints, recent breakthroughs in nano-focus X-ray sources now enable true sub-micron 3D inspection at improved measurement times. X-ray imaging techniques must however always balance resolution, speed and if any sample preparation can be performed. To illustrate these enhancements this communication present case studies from two different cutting edge devices.First a comprehensive 3D X-ray imaging evaluation of an HBM memory stack connected by ~20 µm microbumps was performed. Using nano-CT, we demonstrate that a 30-second scan provides sufficient resolution for initial structural assessment—from redistribution layers (RDLs) and vias in the substrate and interposer to the intricate micro-bumps within the stack. By increasing scan time, more detailed features—such as voids and internal defects—can be revealed. For non-destructive inspection of full-sized packages, X-ray laminography offers significant advantages. Here we demonstrate laminography scans of the HBM microbumps acquired in just a few minutes and discuss the benefits and trade-offs of longer exposure times on image quality and resolution.Second, in addition to HBM microbumps, we present measurements from an AMD Ryzen 7 5800X3D processor, featuring hybrid copper bonding with 1.5 µm vias at 9 µm pitch. Here, individual bond pads are clearly resolved, enabling analysis of planarity information that typically has seemed to difficult for 3D X-ray imaging.Together, these results highlight that X-ray nano-CT and laminography are now practical, high-value tools for R&D, failure analysis, and yield ramp-up in advanced packaging.

Biography
Björn Hansson has been working with advanced X-ray sources at Excillum AB since 2011, serving as Director of Sales and Marketing, CEO and now CTO. Prior to Excillum AB, Björn was involved in early development of laser plasma sources for EUV lithography at the Royal Institute of Technology in Stockholm, as a Co-Founder of Innolite AB and finally as a Senior Scientist at Cymer, Inc. (now ASML). He holds a Ph.D. in applied physics from KTH Royal Institute of Technology, Stockholm.

Topic Coming Soon

Blaschitz, Herbert
Executive VP of Advanced Technology Facilities
Exyte

Abstract
Coming Soon

Biography
Herbert Blaschitz, Executive VP of Advanced Technology Facilities at Exyte, is a recognized leader in the semiconductor industry. He has played a pivotal role in the profitable expansion of Exyte’s semiconductor business, growing it from 1 billion euros in 2014 to over 6 billion euros in 2023.Before joining Exyte, he held various positions at Jenoptik, Asyst, and Siemens Semiconductor (now Infineon). Originally from Austria, Herbert has lived and worked in Germany, France, the USA, and currently resides in Singapore.Herbert Blaschitz earned a degree in electrical engineering from HTBL of Klagenfurt, Austria, and a degree in business administration from GSBA in Zurich, Switzerland.

Sovereignty Comes from the Strongest Link in the Chain: Why Europe's technological strategy should be all in on areas of comparative advantage

Bithell, Ed
Head of Strategy and Sovereign Partnerships
Fractile

Abstract
Technological sovereignty is often discussed in maximalist or minimalist terms, either demanding an entire onshore manufacturing chain or simply stockpiles of end products that rapidly become obsolete. Neither is a credible strategy for Europe: what we need is to focus on areas of competitive advantage which give strategic leverage in the long term, combined with wise partnerships overseas.The strategic focus should thus be on parts of the supply chain that are ideally placed to maximise value and technological advantage in Europe, without leaning on inputs that are more expensive here. Fabless manufacturing is such a case, with AI making advanced semiconductors more strategically vital than ever before. If Europe succeeds in cutting edge innovation in these areas, the resulting technological advantages will enable global collaborations where Europe is a vital player, boosting European prosperity and resilience.

Biography
Ed Bithell is Head of Strategy and Sovereign Partnerships at Fractile. Prior to this, he was a UK civil servant and diplomat, as well as a policy analyst for emerging technologies such as semiconductors. Fractile is building the hardware needed to unlock colossal scaling of frontier AI inference compute. The company’s custom silicon and software ecosystem is built around delivering hundreds of times faster access to memory, in turn allowing for extremely low inference latency while maximising throughput and minimising cost.

The APECS pilot line is powering the evolution of chiplet technologies

Aschenbrenner, Rolf
Director Deputy
Fraunhofer IZM

Abstract
The pilot line for »Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems« (or APECS in brief) is a key part of the EU Chips Act, as it will propel innovation in chiplet technology and enrich the semiconductor research and production capacities in Europe. The institutes cooperating in the Research Fab Microelectronics Germany (FMD) are working closely with other European partners to complete the APECS line and contribute substantially to making Europe more technologically resilient and competitive in the global semiconductor industry. The pilot line will give large industry players and SMEs or smaller start-ups easier access to cutting-edge technology and feed into more reliable and resilient semiconductor value chains.The presentation will discuss the role of Fraunhofer IZM in the APECS pilot line with its expertise for the hardware integration of chiplet systems. With its access to individual chiplet components, the institute can cover the entire process flow needed to create fully functioning systems. Its researchers are working on modern 300mm interposer technologies, high-density substrates, advanced assembly technologies, and the necessary processes for the advanced heterointegration of highly integrated systems. Fraunhofer IZM is establishing itself as a key partner for system-level heterointegration in Europe with several focus innovations.

Biography
Rolf Aschenbrenner received the B.S. degree in mechanical engineering from the University for Applied Science, Gießen, Germany in 1986 and the M.S. degree in physics from The University of Gießen, Germany, in 1991. Since March 1994 he has been employed at the Fraunhofer Institute for Reliability and Microintegration (IZM), where he is presently the deputy director and head of the Business Development Team.

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Horstmann, Manfred
General Manager and Senior Vice President
GlobalFoundries

Abstract
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Biography
Manfred Horstmann serves as General Manager and Senior Vice President at GlobalFoundries (GF), overseeing European fabs, including GF’s 300mm manufacturing facility in Dresden. He also leads the GlobalFoundries Engineering Services (GFES) teams in Singapore, Penang, Bangalore, and Malaysia, supporting GF’s global manufacturing operations.Since 2020, he has transformed the Dresden Fab cluster into Europe’s largest 300mm wafer facility, achieving a two and a half output increase in less than three years, boosting productivity and strategically optimizing operations. He and his team led the development and production of a highly differentiated technology portfolio (55nm-22nm) for applications in fast growing markets such as automotive, MCUs, display drivers, audio amplifiers, security chip cards, radio frequency (RF) and 5G technology.With over 27 years of experience in multiple leadership positions in spanning research, technology development, product engineering, and large-scale operations, Mr. Horstmann has held leadership roles at Advanced Micro Devices (AMD), Motorola, and IBM in Germany and the United States.Mr. Horstmann holds over 100 patents, has authored more than 200 scientific papers and serves on advisory boards for Forschungszentrum Jülich and Nanoelectronic Materials Laboratory. Mr. Horstmann earned his Diploma and PhD in Physics from Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen.

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Clarius, Tom
Director EHS&S
Globalfoundries

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Biography
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Kamineni, Himani
Director, Advanced Packaging
GLOBALFOUNDRIES

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Biography
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„Materials, Innovations for Generations”

Joerger, Michael
Head of Business Line Power Electronic Materials
Heraeus Electronics GMBH

Abstract
In the face of increasing environmental regulations and growing demand for sustainable electronics, the semiconductor and electronic packaging industries are under pressure to reduce their carbon footprint without compromising performance. This presentation introduces a series of material innovations that demonstrate how sustainability and high performance can go hand in hand.We showcase three key developments: (1) recycled gold bonding wire, which maintains electrical and mechanical reliability while significantly reducing the environmental impact (2) Die Top System Silver as a viable alternative to Die Top System Gold, offering comparable electrical performance with a lower environmental and economic cost; and (3) recycled tin in solder pastes, which supports circular economy principles and reduces the carbon intensity of assembly processes.

Biography
Dr. Michael Jörger has 20 years experience in managing product development and launching of innovative materials for electronics and renewable energies with a focus of Power Modules and Semiconductor Packaging materials.Michael holds a Ph.D in Material Science from ETH Zurich, Switzerland, and a diploma in chemistry from the University of Karlsruhe in Germany.Currently he is leading the Business Line Power Electronic Materials at Heraeus Electronics.

It’s Time to Futureproof our Prosperity by Superfueling Innovation, Enabling Next-Gen AI

Van den hove, Luc
President & CEO
imec

Abstract
The AI field is evolving at an incredibly fast pace, with major models and updates being released almost every month. As these models evolve beyond Large Language Models towards next-gen AI with advanced reasoning capabilities, compute systems struggle to handle the heterogeneous workloads in a performant and sustainable way. However, developing new, AI-optimized compute architectures and the enabling semiconductor technologies takes much more time than writing algorithms. To prevent bottlenecks slowing down AI-based advancements, we must reinvent compute architectures and semiconductor technology platforms. The presentation will shed light on the need for flexible, versatile compute architectures implemented in flexible, versatile technology platforms while addressing the increasing challenges of density, power and memory. To speed up both advanced semiconductor technology R&D and full stack innovation for future AI applications, imec is expanding its pilot line infrastructure under the EU Chips Act. Next to new infrastructure, imec aims to boost innovation through intensified collaborations with complementary knowledge partners and through further internationalization, attracting global talent and building strong, local ecosystems for diverse application domains, like health and automotive. Transformative innovations for humankind hinge on the innovation pace of the semiconductor industry. It’s time to supercharge our innovation engine, it’s time to futureproof our prosperity.

Biography
Luc Van den hove is President and CEO of imec since July 1, 2009. Before he was executive vice president and chief operating officer. He joined imec in 1984, starting his research career in the field of silicide and interconnect technologies.In 1988, he became manager of imec’s micro-patterning group (lithography, dry etching); in 1996, department director of unit process step R&D; and in 1998, vice president of the silicon process and device technology division. In January 2007, he was appointed as imec's EVP & COO. Luc Van den hove received his PhD in electrical engineering from the KU Leuven, Belgium.In 2023, he was honored with the Robert N. Noyce medal for his leadership in creating a worldwide research ecosystem in nanoelectronics technology with applications ranging from high-performance computing to health.In 2025, he was awarded the honorary distinction from the Flemish Community in recognition of his impressive role in strengthening Flanders as a leading innovative region.He has authored or co-authored more than 200 publications and conference contributions.

The EU Chips Design Platform: a catalyst for fabless startups in Europe

Hoofman, Romano
Strategic Development Director
imec

Abstract
The EU Chips Design Platform will enable fabless companies to access the resources they need quickly and efficiently via a cloud-based virtual environment, offering chip design resources, training, and capital. Coordinated by imec, twelve key European research players in the semiconductor ecosystem have joined forces in a consortium to create this design platform.The platform aims to onboard the first startups and small and medium enterprises by early 2026, providing them with low-barrier access to European design capabilities, including route-to-chip fabrication, packaging, and testing. It will offer customized support to access commercial electronic design automation (EDA) tools, intellectual property (IP) libraries, EU Chips Act pilot line technologies, and access to design IP repositories, including open-source options. Additionally, the platform will feature a startup support program with incubation, acceleration, and mentoring activities next to financial assistance to help early-stage companies turn their innovative ideas into reality.

Biography
Romano Hoofman is Strategic Development Director at imec since 2016. He is currently responsible for the innovation programs at IC-Link and for the coordination of both the EU Chips Design Platform and the EUROPRACTICE Service.He started his career in industry, where he worked as a Principal Scientist at Philips Research and later on NXP Semiconductors. He covered many different R&D topics, ranging from CMOS integration, advanced packaging, thin film batteries, photovoltaics and (bio)sensors.Romano received his PhD from the Technical University of Delft in 2000, where he investigated charge transport in semi-conducting polymers. He has authored more than 30 publications and holds more than 10 patents in various research areas.

Accelerating nanoelectronic device innovation through atomistic simulation–driven material screening

Pourtois, Geoffrey
Fellow
Imec

Abstract
The introduction of new materials in nanoelectronics has been a key driver of innovation and scaling since Moore's law began. Examples include the introduction of high-k insulating dielectrics, metal gates, silicon-germanium alloys, and alternatives to copper for interconnect layers. However, while the periodic table offers inspiration, it also presents challenges. The main issue is not only identifying materials with the right phase and properties but also ensuring they maintain these properties at the nanometer scale, can be conformally deposited, remain stable through various process steps, and have a low environmental impact. Thus, enabling new materials is a complex, multi-dimensional, time- and resource-intensive problem that requires a proper methodology and rigorous testing with devices at relevant dimensions. Traditionally, material candidates are identified through literature research and numerous trial-and-error experimental steps. Recent advancements in atomistic simulations are helping to optimize this procedure, enabling virtual screening of materials without prior experimental measurements. We will illustrate this process through the identification of candidates to build a selector function for memory arrays.As process nodes continue to shrink, the spacing between parallel memory cells in the stack decreases, increasing the load on metal interconnects. Leakage current becomes an unavoidable issue, causing crosstalk between neighboring memory cells, affecting read and write operations, interfering with stored data, reducing storage lifespan, and increasing power consumption. To effectively suppress it, it is essential to control all possible leakage paths. The most efficient solution is to directly connect each memory cell to an independent device called a "selector," forming the memory array. The latter should ideally be built-in the memory device. Such a selector operates by switching between a high-resistance state (off) and a low-resistance state (on) when a certain threshold voltage is applied. Through this presentation, we will show how virtual material screening based on atomistic simulations of amorphous materials were used to design materials with tailored properties. When combined with machine learning, this approach is narrowing down potential candidates for device exploration and provide insights into precursor selection for the atomic layer deposition (ALD) of nanometer-thick films, while accounting for sustainability dimensions.

Biography
Geoffrey Pourtois studied Chemistry (1997) and obtained a PhD in Chemistry (2002) at the university of Mons Hainaut, Belgium. In 2003, he joined imec in Belgium, where he has been working in the field of atomistic modeling, with a special attention for establishing relations between material, interface defects and electrical device performances.From 2003 to 2025, he has been building and heading the group of material simulation and physics in imec, where he has been focusing on the modeling, using atomistic simulations, of nanoelectronic related materials. His group is being involved in building fundamental insights into the relations between material, interface and device electrical performances for CMOS, memory, and exploratory devices concepts. During their exploration endeavour, his team studied complex material gate stacks involved in CMOS and memory applications and contributed to the identification and the study of new materials for interconnect, emerging and magnetic memories. He was nominated imec fellow in 2020 and (co-) authored ~ 420 oral and peer-reviewed publications.

Sub-THz HR SOI interposer with integrated hybrid thermal TSV and liquid micro-cooling

Novoselov, Evgenii
Process Integration Engineer
imec VZW

Abstract
The increasing demand for miniature, high-frequency devices in millimetre-wave applications such as 6G communications, next-generation radar, and sensing has uncovered inherent limitations in current packaging technologies. RF signal integrity, thermal challenges, and integration of dissimilar materials are among the issues that need to be addressed for enabling scalable and reliable high-performance modules. To solve these challenges, we designed a silicon (Si) interposer platform to enable the heterogeneous integration of an Indium Phosphide (InP) chip with a 94 GHz RF antenna, monolithic microwave integrated circuit (MMIC) structures, and integrated microfluidic cooling.Our interposer features a multifunctional embedded Cu layer that serves as a ground plane for MMICs, an antenna radiation efficiency reflector, and thermal spreader for enhanced thermal dissipation. In addition, the interposer features dense arrays of 20 × 100 μm Cu TSVs with vertical RF signal routing and low resistance, as well as efficient thermal conduction from active areas to the backside heat sink. Wafer level oxide-oxide fusion bonding was used to integrate top RF part with bottom microfluidic cooling part.InP chip is bonded with Cu/Ni/Sn micro-bumps, offering high-density low-resistive electrical interconnects and structurally reliable bonding. A mechanical test vehicle has been implemented to test bump quality, alignment precision, and structural strength, with inspection results to be presented.To further improve high-frequency signal routing, the interposer also features coplanar waveguide (CPW) traces optimized for low insertion loss at 94 GHz. Further, monolithically integrated microfluidic channels in the Si substrate enable active, localized cooling right below high-power components, further enhancing system thermal performance under load.We present RF measurements like S-parameters of CPW structures and antenna structures with effective transmission and impedance matching at 94 GHz. Thermal testing confirms the efficiency of combined microfluidic and Cu-based thermal management.

Biography
Evgenii Novoselov was born in Saint Petersburg, Russia, in 1988. He received his B.Sc. in Photonics and M.Sc. in Optoinformatics (summa cum laude) from ITMO University in 2009 and 2011, respectively. In 2017, he earned his Ph.D. from Chalmers University of Technology, Gothenburg, Sweden, with a dissertation on MgB2 hot-electron bolometer mixers for sub-mm wave astronomy.After completing his Ph.D., Evgenii joined the Microwave Electronics Laboratory at Chalmers as a postdoctoral researcher, where he worked on W-band graphene FET-based resistive mixers. Since 2019, he has been with imec in Leuven, Belgium, where he currently holds the position of Senior Process Integration Engineer. His work focuses on heterogeneous component integration, including BEOL, MEMS, RF systems, and hyperspectral imaging technologies.

From Insight to Action: Elevating Employee Efficiency with Smart Detection and Targeted Data Delivery (joint presentation with ST Microelectronics)

Smith, Holland
Director of Data Science
INFICON

Abstract
In an era where it is increasingly easy to be overwhelmed by data, timely and efficient decision-making is critical to maintaining optimal factory operations. This talk will highlight the results of a joint collaboration between INFICON and ST Microelectronics. Together, we are developing an innovative application aimed at transforming how factories operate and respond to challenges. In addition to providing real-time tracking of key performance indicators (KPIs), the application detects various types of operational anomalies. These anomalies are automatically assessed to determine their potential impact, and the application allows workflow management by assigning tasks to the appropriate factory workers, ensuring rapid response and resolution. Our collaboration is focused on enhancing employee efficiency by delivering data that is specifically tailored to each worker's role, minimizing information overload, and providing actionable insights exactly when and where they are needed. By combining comprehensive operations tracking with smart detection and targeted data delivery, this solution enables semiconductor factories to operate with greater precision and reduced downtime.

Biography
Dr. Holland Smith is Director of Data Science at INFICON IMS, where he leads AI initiatives spanning classical machine learning to LLM-based agentic AI systems across INFICON's software and smart sensor portfolio. His team's high level focus is the transformation of semiconductor and industrial manufacturing operations through optimization, intelligent automation and predictive analytics.Holland joined INFICON FPS in 2016, where he architected and deployed Smart Manufacturing systems in 200mm and 300mm fabs worldwide. As a semiconductor data systems expert and contributing developer of the INFICON FPS Digital Twin, he enables advanced fab scheduling, optimized WIP movement, and predictive manufacturing capabilities. Dr. Smith has published research and spoken widely on automated throughput and cycle time forecasting that enables high-fidelity fab modeling across multiple time horizons.Prior to INFICON, Holland worked as a Technology Development Engineer at Intel D1D/X in Hillsboro, OR, focusing on thin film process development and subfab optimization for challenging deposition processes. Dr. Smith earned a PhD and M.S. in Materials Science and Engineering with a minor in Solid State Physics and a B.S. with Honors in Engineering Physics from UC Berkeley, plus a B.A. with Honors in Slavic Languages from Stanford University.Joint Presentation with: Thomas Gimmig has twenty-five years of experience in semiconductor manufacturing. After holding various positions in maintenance, engineering, and production management at ST Microelectronics, finishing as Production Director of the Rousset plant in 2019, he moved to manufacturing central functions in 2022. Initially, he was in charge of Front-End Operational Excellence programs, developing the LEAN leaders community, and leading smart manufacturing transformation programs. He recently became the head of Industry 4.0 programs for ST Microelectronics manufacturing. Thomas Gimmig holds a master's degree in electronics.

From Semiconductors to Quantum: Infineon's Multi-Technology Approach

Luber, Sebastian
Senior Director Technology & Innovation
Infineon Technologies AG

Abstract
Quantum computing holds significant potential to revolutionize the future of technology, and Infineon Technologies is contributing to this evolution through its developments in quantum hardware. This presentation will showcase Infineon's activities in superconducting circuits, semiconducting SiGe-based qubits, and ion trap technologies. Drawing on its expertise in semiconductor manufacturing and design, Infineon is addressing key challenges in scalability, integration, and reliability for quantum computing systems. The session will explore how Infineon's components and modules contribute to the development of robust quantum computing systems across these three leading technology platforms. Emphasis will be placed on the holistic approach, which combines deep materials science knowledge, advanced process technologies, and collaboration within the quantum ecosystem. Join us to gain insight into how Infineon is shaping the future of computing.

Biography
Sebastian M. Luber holds a PhD in technical physics from the Walter Schottky Institute at the Technical University of Munich and is Senior Director for Technology & Innovation at Infineon Technologies AG. He coordinates Infineon's activities in the field of quantum technologies and acts as an advisor to the Management Board. Luber is involved in a variety of external committees and activities dealing with quantum technologies. Among others, he is member of the Program Committee for Quantum Technologies of the Federal Ministry of Education and Research, and active in QUTAC, the German Quantum Technology & Application Consortium. Previously, he held various positions in the company, including Sensor Technology Line Manager and Automotive Program Manager.

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Gan, Terence
Executive Director
Institute of Microelectronics

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Biography
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Singh, Navab
Director, MEMS Program at the Institute of Microelectronics, Singapore
Institute of Microelectronics

Abstract
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Biography
Dr. Navab SINGH [M.TECH/IIT Delhi, Ph.D./NUS Singapore] is a Senior Scientist and Director at Institute of Microelectronics (IME), A*STAR, Singapore, leading MEMS program. As a Senior Scientist/ Member of Technical staff and Principal Investigator of Nanoelectronics program, in 7 years [2005-2011], he developed highly scaled lateral and vertical nanowire gate-all-around FETS, NVM devices and high efficiency silicon solar cells. Prior to that Dr Singh worked on lithography technology development for 9 years [1996–2004] focusing on resolution enhancement techniques. Dr. Singh has authored or co-authored more than 190 technical papers (citations > 1900 & h-index: 22) in referred archival journals and conferences and has filed more than 20 technology disclosures. His nanowire gate-all-around FET papers have been selected for pre-conference publicity by IEDM and SSDM conferences. He is a recipient of George E. Smith Award 2007 for best paper in IEEE Electron Device Letters, Singapore National Technology Award 2008 for his outstanding contributions to the research and development of nanowire-technology platform, enabling the realization of ultimately scaled CMOS integrated circuits and new class of electronic bio-sensors, IME Excellence Award 2009 for industry project developing Surround Gate Transistor (SGT) technology, and A*STAR TALENT award 2010 for Leading, Educating and Nurturing Talents.

Digitalization in Semiconductor Manufacturing Supply Chain – Need of Global Collaboration

Gossner, Harald
Senior Principal Engineer
Intel

Abstract
Semiconductor-X introduces a secure and interoperable dataspace for the international semiconductor supply chain.Demonstrating key use cases for planning, optimizing, regulatory reporting and enablement of new business models using digital twin technology.Semiconductor-X is working with US and Asian partners to align the international standardization of digital twins and data space connectors for semiconductor supply chain usage.

Biography
Harald Gossner holds the position of a Senior Principal Engineer at Intel. He received his diploma degree in physics from Ludwig-Maximilians-University, Munich in 1990 and his PhD in electrical engineering from Universität der Bundeswehr, Munich in 1995. For 15 years he has worked on the development of electrostatic discharge (ESD) protection concepts with Siemens and Infineon Technologies. In 2011 he joined Intel leading the system ESD robustness development for Intel products.He is the co-founder and co-chair of the Industry Council on ESD Target Levels representing more than 60 companies including all leading semiconductor manufacturers. He is President Emeritus of the EOS/ESD Association, Rome, NY, IEEE Fellow and editor of IEEE Electron Device Letters.In his role as technology advisor, he is member of the industry advisory boards of the Bavarian Government and of several Fraunhofer institutes. He is part of the expert commission on AI of the German Economic Council. Since 2024 he is leading the project Semiconductor-X, coordinating the development of a dataspace for a resilient supply chain of semiconductors for Europe. He is also driving the build-up of a design ecosystem of innovative designs in digital leading edge technologies in Europe.

Superconducting Quantum Chips as the Foundation for Quantum Computing

Hassel, Juha
VP of Quantum Technilogies
IQM Quantum Computers

Abstract
Quantum computing based on superconducting chips is currently one of the most promising approaches for industrially relevant quantum computing. In this presentation, we will review IQM's comprehensive approach to quantum computing, spanning from chip design to full-scale systems, and showcase exemplary computing applications that are enabled by today's quantum computers. We will highlight the key aspects related to superconducting quantum chips, including the specific requirements and solutions for maintaining quantum coherence. Additionally, we will provide an overview of IQM's chip fabrication capabilities and how they align with the company's vision for scaled-up, future systems that will be necessary for fault-tolerant quantum computing. We will also present key performance metrics for our chips, including T1 coherence times of up to nearly one millisecond and 2-qubit gate fidelities of up to 99.93%, which have been achieved using IQM's tunable coupler approach. Furthermore, we will deliver a status update on the development of our full Quantum Processing Units (QPUs), featuring our current-generation chips with up to 54 and 150 qubits. Finally, we will outline IQM's scaling roadmap towards fault-tolerant quantum computing.

Biography
Dr. Juha Hassel received his PhD title in 2004 from Helsinki University of Technology (now Aalto University). As of March 2024, he holds the position of Vice President of Quantum Technologies at IQM Quantum Computers, where he has worked in different leadership positions since 2019. Before joining IQM, he served as Principal Scientist at VTT Technical Research Centre of Finland, where he also led the Applied Quantum Electronics team within the national Centre of Excellence – Quantum Technology Finland.

Strengthening Semiconductor Supply Chains in an Era of Disruption

O'Dowd, Barry
Head of Global Business Development Semicon
Kuehne+Nagel

Abstract
In this session, Barry O’Dowd, Head of Global Business Development Semicon, at Kuehne+Nagel, will explore the key risks facing semiconductor logistics and how companies can proactively mitigate them. He will introduce practical strategies for assessing and strengthening transportation resilience by drawing from real-world examples and lessons learned from industries with highly complex supply chains.Attendees will gain insights into:■ How the semiconductor industry is adapting to global disruptions and reshoring trends■ The role of data-driven risk mitigation tools in evaluating transportation lanes■ Best practices for securing critical shipments, from wafer fabrication materials to capital equipment■ The importance of continuous risk assessment in an evolving supply chain landscapeWith decades of experience optimising Semicon logistics, Barry will share how industry leaders can turn supply chain resilience into a competitive advantage, ensuring stability, security, and seamless operations in a rapidly changing world.

Biography
Based in Dublin, Ireland, Barry brings more than 30 years of international logistics expertise, In his current role, Barry leads strategic growth and innovation within the company’s semiconductor logistics segment—one of the key focus areas under Kuehne+Nagel’s global Roadmap 2026 strategy. Recognizing the industry’s unique supply chain demands, he has been instrumental in developing SemiconChain—a dedicated, quality-certified network now spanning more than 35 locations across major semiconductor hubs.

Advances in AlScN Thin Films Deposited by Lam Research Pulsed Laser Deposition Platform

Dekkers, Matthijn
Director Engineering Pulsed Laser Deposition technique (PLD)
Lam Research

Abstract
Pulsed laser deposition (PLD) is a very versatile thin film deposition technology that has the ability to deposit a wide range of advanced thin film materials. With today’s market demand for enhanced and new material systems, PLD enables layers that cannot practically be deposited by conventional technologies like physical vapor deposition (PVD) reactive sputtering.This deposition solution enables more advanced device design and is driving the next generation of radio frequency (RF) filters for 5G, WiFi 6 and 6E, high-end micro-electromechanical systems (MEMS), ferroelectric memory and photonics applications.For piezoelectric aluminum scandium nitride, PLD has extended the limits of scandium doping in the AlScN compound, resulting in very high piezoelectric properties. Additionally, this PLD platform enables precise control over thickness uniformity and thin film stress, which are crucial for high-yield (RF) MEMS applications.For the first time in semiconductor production, Lam is using lasers to deposit thin films and bringing PLD to wafer-level mass production. Lam Research PLD is expected to be key in developing cutting-edge specialty technologies devices, such as RF filters for 5G and Wi-Fi 6 and high-end MEMS microphones.

Biography
Matthijn Dekkers earned his PhD in Applied Physics from the University of Twente in 2007, the same year he co-founded SolMateS. As Chief Technology Officer, he led the R&D division in scaling the Pulsed Laser Deposition (PLD) technique for industrial applications. Following SolMateS’ acquisition by Lam Research in 2022, Matthijn assumed the role of Director of Engineering for PLD, where he continues to drive innovation in advanced materials processing.

Driving Heterogeneous Integration for AI and Beyond

Oetzlinger, Herbert
Vice President and Head of the Panel Product line
Lam Research

Abstract
The semiconductor industry is undergoing a transformative shift, with advanced packaging emerging as a critical enabler of performance, scalability, and cost-efficiency in the post-Moore era. Heterogeneous integration (HI), which combines diverse chiplets with varying process nodes and functionalities into a single package, addresses technical challenges such as shrinking transistor sizes, increasing interconnect density, and optimizing power efficiency. The surge in demand for artificial intelligence (AI) applications, particularly high-performance computing (HPC) and data center AI chips, has further accelerated the need for innovative packaging solutions like 2.5D/3D ICs, fan-out wafer-level packaging (FOWLP), and panel-level packaging (PLP). These technologies enable higher bandwidth, lower latency, and compact form factors essential for AI-driven workloads. Recent product developments, including chiplet-based architectures and high-bandwidth memory (HBM) integration, underscore the industry’s focus on powering next-generation AI systems.This presentation explores the technical imperatives and market dynamics driving advanced packaging, with a deep dive into panel-level packaging (PLP). PLP offers significant cost advantages by processing multiple packages simultaneously on larger panels, enhancing economies of scale compared to traditional wafer-level packaging. However, both the substrate and PLP markets face challenges, notably the lack of standardized panel sizes, which complicates equipment design and increases costs. PLP’s economic viability is further constrained by its suitability primarily for high-volume devices, limiting its total market size. Despite these hurdles, the convergence of technology and equipment requirements between substrate and PLP markets is fostering a more robust equipment supplier ecosystem, potentially unlocking greater scalability and innovation.The presentation will also highlight Lam Research’s cutting-edge solutions for advanced packaging, focusing on its advancements in chiplet-to-chiplet and chiplet-to-substrate heterogeneous integration. By addressing warpage, electroplating uniformity, and other manufacturing challenges, Lam Research is enabling scalable, high-performance packaging solutions tailored for AI, 5G, automotive, and consumer electronics applications. This convergence of market needs and technological innovation positions advanced packaging as a cornerstone of the semiconductor industry’s future.

Biography
Herbert Oetzlinger graduated from HTL Braunau in 1987 with a specialization in high-power electronics and electrotechnics. With over 30 years of experience in the semiconductor industry, he has built deep expertise in wet processing, particularly in advanced packaging technologies involving electroplating, wet etching, and wafer/substrate cleaning.Herbert held the role of Vice President of Business Development at Semitool Inc., where he was recognized for his deep process and hardware knowledge. During his tenure, he collaborated with leading global companies on innovations such as Fan-Out, Embedded Wafer-Level Ball Grid Array (E-WLB), and other cutting-edge developments in wafer-level advanced packaging.In 2012, he founded Semsysco GmbH and served as its CEO. Under his leadership, Semsysco became a global leader in high-speed electrochemical deposition, known for its comprehensive capabilities in wet processing for both wafer and panel-level applications.Following Lam Research’s acquisition of Semsysco in 2022, Herbert joined Lam as Vice President and Head of the Panel Product Line, where he continues to drive innovation in advanced packaging solutions.

A Sustainable Dicing Innovation for Cutting-Edge Semiconductor Challenges

Keil, Christian
Director Business Development & Sales
Lidrotec Gmbh

Abstract
The production of semiconductor components (chips) is realized on thin wafers and is an energy and resource-intensive process that can take up to 12 weeks. Before the chips can be further processed, they must be separated on the wafer by the so-called dicing - a critical process step that introduces considerable damage to the chip frontside, backside and sidewalls.The market development of recent years combined with the AI boom leads to a high demand for computing power and data storage, e.g., for training of AI models. In consequence this growing demand leads to a steady increase in energy consumption.To counteract rising energy consumption, innovative, more efficient product designs, e.g., HBM, are required. These are mostly achieved by a broader use of modern packaging methods, e.g., Advanced Packaging and Hybrid Bonding.Unfortunately, these modern packaging and bonding methods lead to an increasing demand on chip quality and cleanliness, which cannot be achieved with most of the currently used dicing methods.As a result, semiconductor manufacturers have to utilize complex multi-step separation processes, including plasma dicing, which are not only expensive but also consume a large amount of chemical process gases.Our innovative LidroCUT process, based on ultrashort pulse laser in liquid overcomes these challenges. The liquid cools down and binds the emerging nano particles into the liquid, leading to a debris free surface and contamination free sidewalls, enabling hybrid bonding without additional cleaning steps, proven by optical inspection.Meanwhile, the cooling capacity of the liquid allows for a precise laser power use, leading to high quality, burr free, edges and high break strength.LidroCUT is literally cutting edge.

Biography
Christian Keil graduated with a Master of Science in Mechanical Engineering from the Ruhr University Bochum in 2017. He gained his first professional experience as a process engineer commissioning machines and training customer employees all over the world. After half a decade as a process engineer he reoriented himself and moved into the sales departments. He joined Lidrotec as Sales Manager in 2023​ and is today Director of Business Development & Sales at Lidrotec.

BTO-enhanced Silicon Photonics for Next-Generation Optical Transceivers

Mohn, Fabian
Reliability and Packaging Lead
Lumiphase AG

Abstract
As global data traffic continues to surge, the demand for faster, more energy-efficient, and scalable optical communication systems is driving the need for innovation in photonic integration. Traditional silicon photonics, while mature, faces limitations in speed, power consumption, and footprint.Lumiphase addresses these challenges by developing and manufacturing photonic integrated circuits based on a proprietary barium titanate (BTO) technology. This technology uses the Pockels effect and enables true electro-optic modulation, offering significant advantages over conventional silicon-based solutions.In this presentation, we will introduce our BTO-based photonic integration technology, highlight its advantages for optical data communication, and discuss key challenges and ongoing developments in bringing this technology to scale.

Biography
Fabian Mohn is a Staff Engineer and team lead of the Reliability & Packaging team at Lumiphase. The team is responsible for wafer-to-chip singulation processes, the design and assembly of test vehicles for chip-level performance and reliability evaluation, and the development and execution of accelerated reliability and robustness qualification protocols for Lumiphase’s BTO-based silicon photonics devices.Fabian holds a PhD in Physics, which he earned in 2012 while working at IBM Research – Zurich. Before joining Lumiphase in 2022, he worked on the development of silicon and silicon carbide power semiconductor modules, gaining extensive experience in packaging and reliability engineering.

Innovative AMC Filtration solutions for future semiconductor production challenges

Zoermer, Manfred

Mann+Hummel Molecular GmbH

Abstract
Filtration is crucial for maintaining high quality and process stability in semiconductor manufacturing. As processes advance and device geometries become more complex, high precision optics and process equipment demand optimal protection from particulate and molecular contamination.As process nodes advance, molecular contamination has become just as important as particulate contamination. The necessity for innovative filtration solutions is emphasized by stricter requirements and new process chemicals.

Biography
Manfred Zoermer (born 1965), after studying chemistry (with focus on inorganic and high energy chemistry), started his professional career as sales engineer for analytical technology within the sales area Baden-Wuerttemberg. Several global positions in his career at suppliers of critical process materials to microelectronics, MEMS and compound semiconductor manufacturers connected him directly with clean room technology and led to high special process environment affinity. Further positions in and outside a wide range of industries in sales and marketing, led him to join MANN+HUMMEL Air Filtration at the beginning of 2020. In his current position, he is responsible for the development of a broadband product portfolio, particularly introducing chemical process technology to the air filter community. Manfred is involved as an expert in the standards and guidelines of VDMA, DIN and ISO workgroups.

Closing Europe’s Greentech Talent Gaps

Barberis, Riccardo
Regional President, Northern Europe
ManpowerGroup

Abstract
Despite recent geopolitical changes, nearly half (47%) of employers worldwide plan to increase green business transformation investment and most (91%) do not have the talent they need to achieve their sustainability goals. The role of the semiconductor industry in Europe will become increasingly important to sustaining green innovation and energy security as geopolitical uncertainty continues to disrupt global supply chains. The challenge will grow as most employers (74%) report difficulty finding skilled talent today and aging populations continue to decrease the size of the total workforce. This presentation will leverage data from nearly 40,000 employers and 14,000 workers to explore the challenges and opportunities this poses for the semiconductor industry.Current tech talent shortagesTech worker sentimentTech skills gapsEmployer best practicesRegional partnership opportunities ManpowerGroup Employment Outlook SurveyThe ManpowerGroup Employment Outlook Survey is the most comprehensive, forward-looking employment survey of its kind, used globally as a key labor market indicator. The Net Employment Outlook (NEO) is derived by taking the percentage of employers anticipating an increase in hiring activity and subtracting from this the percentage of employers expecting a decrease in hiring activity. ManpowerGroup Global Talent BarometerThe ManpowerGroup Global Talent Barometer measures worker well-being, job satisfaction, and confidence. around the world. The Talent Barometer leverages independent survey best-practices and statistically significant samples to create a powerful tool to better understand what workers want globally. The research aims to improve the future of work through deeper understanding of key drivers of workforce sentiment today.

Biography
Riccardo Barberis was appointed Regional President, Northern Europe in May 2021, and in January 2025 expanded his responsibilities to include France, ManpowerGroup's largest market in the region. In this role, Barberis oversees all of ManpowerGroup's brands and offerings across the region – Manpower, Experis, and Talent Solutions. Barberis will lay the path to further accelerate ManpowerGroup's diversification, digitization, and innovation plans, creating even more value for clients and candidates and strengthening our performance in the region.​Riccardo joined ManpowerGroup in 1998 and has held numerous leadership positions in Europe and Latin America, most recently as country manager for ManpowerGroup Italy. With more than 25 years of experience including many international roles his deep industry knowledge and passion for a client-first, candidate-centric approach consistently delivers superior results.An accomplished executive, Riccardo holds an Executive MBA from Bocconi University (Milan), has completed management programs at INSEAD and speaks five languages. Currently serving as Board Member of Junior Achievement Europe, he has previously held positions as Vice President of the Italian Industry Association (Assolavaro) and President of ManpowerGroup's Human Age Institute. Riccardo lives with his family in Paris.

Chipstainability - A Megatrend to Strengthen Europe's Leading Role for Global Collaborations

Wunderer, Stefan
Government Funding Manager
Nokia Solution and Networks GmbH & Co. KG

Abstract
In times of geopolitical unrest, climate change as a global problem has to be tackled by closely collaboration with other nations. Europe should use its leading position in microelectronics sustainability to meet the needs of the present without compromising the ability of future generations. The example of ICT shows how strategic cooperation can be used to reduce energy consumption and embodied emissions in microelectronics. The future-oriented results of a recent IPCEI ME/CT Chipstainability Workshop are presented and discussed.

Biography
Stefan Wunderer is driving future topics in mobile communications since more than 40 years, mostly filling leading positions in network optimisation, customer support and training. Within Nokia, he is head of Nokia's IPCEI ME/CT chip design project in Ulm and Nürnberg and facilitating the RAN Energy Efficiency task force. Additionally, Stefan is lecturing sustainability at the University of Würzburg, leading an international SNS-JU research team for Social Needs and Value Creation as well as working within the Scientists for Future in Cologne. He is actively supporting the working group Women in Telecommunications and Research (WiTaR).

Some Material-Related Reliability Challenges that go with Package Roadmap Needs

Mavinkurve, Amar
Principal Materials & Process Devt Engineer
NXP Semiconductors

Abstract
As the usage of electronics keeps increasing and taking over or enabling or facilitating many tasks in our daily lives, society is becoming increasingly dependent on the useful life validation and related to that reliability and safety. To accurately predict this, it is of the utmost importance to understand the most relevant failure mechanisms in packaging. This presentation will elaborate on some failure mechanisms in packaging materials and interconnects that become steadily more relevant with the ongoing trend towards miniaturization, heterogenous integration and advanced requirements. On one hand, some examples of extrinsic failure mechanisms will be given, impacting yield, and potentially increasing the risk of high impact customer returns. On the other hand, some wear-out failure mechanisms related to interconnect and material degradation will also be presented, towards approaches to increase robustness and predictability of these degradation mechanisms using metrics that can efficiently be monitored using AI techniques.

Biography
Dr. Amar Mavinkurve leads the Global Materials Team within Package Innovation (Core Technologies) at NXP. He completed his PhD in Polymer Science from the University of Groningen in the Netherlands in 1996. This was followed with a stint at Philips Research working on various topics like polymer-metal interfaces, polymer processing and textiles. He joined NXP Semiconductors in 2004 (at that time still Philips) and has worked mainly on packaging materials and reliability with specific interest in interconnect systems and aging behaviour of packaging materials.

Glass Core Substrates: Driving Scalability for HVM Through A Versatile Process Control Solution

Pau, Monita
Strategic Marketing Director for Advanced Packaging
Onto Innovation

Abstract
Heterogeneous integration packaging technologies have seen increased adoption driven by the rapidly growing demand for advanced end applications like artificial intelligence (AI) and high-performance computing (HPC). Research and development of glass core substrates are gaining momentum due to their superior mechanical stability and ability to enable the fabrication of high-density metal interconnects and the integration of optical interconnects. However, due to the brittle and rigid nature of glass, their adoption also poses significant manufacturing challenges. Stringent process control is required starting from the bare glass panel and throughout the entire glass core fabrication and buildup process to ensure high manufacturing yield and product reliability.In this presentation, we will present the integration of a high throughput and multifunctional process control solution starting from the fabrication of through glass vias (TGV) in the glass core. Real-time process control of the laser modification and wet etching process is made possible through the ability to inspect and perform CD measurements across 100% of the panel surface. Besides CD monitoring, we will also demonstrate the ability to detect missing and abnormal TGV as these defects can directly impact the electrical performance of the product. Glass is brittle and prone to cracking or chipping during handling and processing. Microcrack detection before and after metallization is crucial to help detect the mechanical damage early to avoid for downstream yield loss.With its unique integrated metrology and inspection capability, the same in-line process control solution can also be applied throughout the buildup process. From monitoring the defectivity and CD of the traces post-patterning and metallization, to the 3D measurement of RDL/bump height and panel warpage. This enables for real-time response to variations in material, equipment and process conditions and ensure high productivity and manufacturing yield.To realize the full benefits of glass as a core material for advanced IC substrate to enable high density interconnects, an advanced inspection and metrology solution is vital. Its multi-functionality and flexibility to handle a wide range of panel sizes up to 650mm x 650mm provides the industry a scalable path to bring glass core substrate from research and development to high volume manufacturing by the end of this decade.

Biography
Monita Pau currently serves as the Strategic Marketing Director for Advanced Packaging at Onto Innovation. With over 15 years of experience, she has held various positions in applications engineering, marketing and strategic business development in both semiconductor capital equipment and electronic materials companies. Her expertise spans across frontend and backend of line process control solutions as well as materials for advanced packaging and assembly. Monita holds a Ph.D. degree in Chemistry from Stanford University.

Integration and Assembly of Co-Packaged Optics (CPO) for smart Networks and Switches

Sundararajan, Anneirudh
Project Leader - Photonics Packaging
PHIX Photonics Assembly

Abstract
The rapid scaling of data center bandwidth requirements is pushing the limits of traditional pluggable optical modules, leading to the emergence of Co-Packaged Optics (CPO) as a promising solution for next-generation network interface cards (NICs) and switch architectures. This presentation outlines a collaborative workflow and integration scheme for CPO systems, highlighting the step-by-step assembly of photonic integrated circuits (PICs), drivers (EICs), and high-bandwidth fiber optics connectors for smart networking devices. We describe the joint contributions from key industrial and research partners—including Teramount (TM), AT&S, IMEC, PHIX, and NVIDIA—covering substrate design, optical/electronic die integration, and high-precision flip-chip bonding. Emphasis is placed on the alignment precision and thermal stability required for the successful coupling of fiber arrays, drivers (EICs) to PICs. The final packaging steps are optimized for signal integrity and thermal management to enable deployment in high-performance data center environments.

Biography
Anneirudh Sundararajan is a Project Leader at PHIX Photonics Assembly, where he leads several EU-funded initiatives as well as customer-driven projects. He specializes in flip-chip bonding technology and the advanced packaging of photonic integrated circuits (PICs). Prior to joining PHIX, Anneirudh worked in Germany as a Process Development Engineer at a photonic packaging company, gaining hands-on experience in scalable photonic assembly processes. Anneirudh pursued his PhD at the University of Twente, where his research focused on the integration of optical components with MEMS-based microfluidic systems. His work involved the development of Coriolis mass flow sensors and spectroscopic techniques for multiparameter fluid characterization. With a strong interdisciplinary background in optics, microfluidics, and photonic packaging, he is actively contributing to the development of next-generation photonic sensing platforms.

Photonic Integrated Circuits for LiDAR: Enabling 4D Machine Vision with PICs

Nicolaescu, Remus
Managing Director
Pointcloud

Abstract
Detailed and accurate three dimensional (3D) mapping of dynamic environments is essential for machines to interact with their surroundings, and for human machine interaction. While considerable effort has been spent in order to create the equivalent of the CMOS image sensor for the 3D world, scalable, high performance, reliable solutions have proven elusive. Focal plane array (FPA) sensors using frequency modulation (FM) light detection and ranging (LiDAR) have shown potential to meet all the requirements and also provide direct measurement of radial velocity as a fourth dimension (4D). In this talk we present the latest results in the development of large scale, high performance coherent LiDAR FPAs enabled by comprehensive chipscale optoelectronic integration. An overview of performance of a 352x176 pixels two dimensional FM LiDAR FPA comprising over 0.6 million photonic components with all photonics and associated electronics components integrated on chip will be presented, as well as future development directions.

Biography
Remus Nicolaescu is the Co-founder and Managing Director of Pointcloud GmbH/Inc., a Zurich based technology company developing coherent 4D imaging solutions using silicon photonics. Prior to Pointcloud, he held executive roles with technology companies in the US, Europe and Asia. He started his career at Intel, where he performed pioneering work in silicon photonics topics, such as optical Raman amplifiers and lasers in silicon waveguides, and high-speed silicon photonics modulators. He obtained his Masters and Ph.D. in Physics from University of Bucharest and Texas A&M University respectively, and MBA from INSEAD.

From Complexity to Advantage: Strategic Levers for Future Ready Fabs

Notarnicola, Giovanni
Partner
Porsche Consulting

Abstract
In a climate of geopolitical instability and market contraction, especially in automotive and energy-linked segments, European semiconductor players must rethink how to stay competitive. Can AI truly revolutionize one of the most time-consuming and costly steps in the fab journey, such as product qualification? Possibly, but only if companies learn to unlock the value of the data they already have.This session explores how collaboration across traditionally siloed domains, technology, operations, and digital, can generate real-world efficiency and speed. We’ll share concrete examples and pragmatic insights from the field, showing how to build the right ecosystem of specialized capabilities to enable faster, more resilient fab scale-up.

Biography
TBD

Robust SiC MOSFET Devices for Drive Train Applications

Schwaiger, Stephan
Automotive Electronics
Robert Bosch GmbH

Abstract
SiC technology replaces its silicon competitor in many automotive applications, especially in drive train inverters for high voltage batteries of electric vehicles. Using the higher efficiency in partial load operation, SiC traction inverters outperform Si inverters and allow to extend the range of an electric car. As a result, SiC technology gained market shares and many semiconductor players took significant development efforts to improve the SiC MOSFET performance, i.e. reducing the on-state resistance with the goal to enable smaller and cheaper traction inverters. However, also other improvements, e.g. improvements in switching behavior or the integration of new features like sensing elements improve the applicability on system level.This talk provides an overview of SiC MOSFET technology for drive train applications. It sums up the key performance indicators for a technology enabling a performant design of a drive train inverter. Furthermore, the talk discusses the advantages of integrating sensing elements on chip level and gives an insight on measures to increase robustness necessary to maintain high quality products with low failure rates. The talk provides an insight into recent advances of Bosch’s SiC technology designed for reliable, high performance automotive applications.

Biography
Stephan Schwaiger studied physics at the university of Hamburg and finished with a doctorate degree in 2012. He started in semiconductor industry in Bosch’s central research department working power semiconductors. Since 2015 he works on the development of SiC semiconductors for the section Automotive Electronics at Bosch focusing on technology and device development.

Topic Coming Soon

Avice Huet, Gwenaelle
Executive Vice President of Europe Operations
Schneider Electric

Abstract
Coming Soon

Biography
Gwenaelle Avice Huet has been Schneider Electric’s Executive Vice President of Europe Operations since September 4, 2023 and serves on its Executive Committee. She is responsible for Schneider Electric’s full business portfolio across Europe Operations, representing the company’s contribution to the development of the EU’s agenda to accelerate Europe’s green and digital transformation.Gwenaelle joined Schneider Electric in 2021 as Senior-Vice President of Corporate Strategy, before entering the Executive Committee as Chief Strategy and Sustainability Officer. Before joining Schneider Electric, Gwenaelle worked at ENGIE (formerly GDF SUEZ) in various roles, from Senior Vice-President of European and Regulatory affairs, to leading the Renewables energy business. In her last role, she was on the Executive Committee of ENGIE, serving as the Chief Executive Officer of ENGIE North America and in charge of the Global Business Line on Renewable Energies.Gwenaelle started her career at the French National Centre for Scientific Research and the French Atomic Energy Commission on nuclear energy before joining the World Bank in Washington D.C. as a consultant. She also worked for the service of the French Prime Minister within the General Secretary of European affairs with responsibility for energy and competitiveness matters, and as the advisor on energy and climate change for various ministers.Gwenaelle also serves on the Board of Air France – KLM. She holds a degree in Physics and Chemistry from the Ecole Normale Supérieure Paris-Saclay, a post-graduate diploma in Molecular Chemistry from France’s Ecole Polytechnique and an engineering degree from the Corps des Ponts et Chaussées. She has also been nominated as a Young Global Leader by the World Economic Forum. She is based in Europe.

Opening Remarks

Manocha, Ajit
President and CEO
SEMI

Abstract
Opening Remarks

Biography
Throughout his career, Ajit Manocha has been a champion of industry collaboration as a critical means of advancing technology for societal and economic prosperity. He has been adept at forming strong partnerships with customers, suppliers, governments, academia, and communities for these efforts.In his current role as President and CEO of SEMI, the global industry association serving the electronics manufacturing supply chain, Manocha has positioned the organization to tackle major challenges facing the industry by building up workforce development programs to address its growing talent shortage and lack of gender parity.Previously, he held senior worldwide operations leadership roles at Philips Semiconductors (NXP) and Spansion before serving as President and CEO at GLOBALFOUNDRIES. He has served on the boards of SEMI, SIA, and GSA.Manocha began his career as a research scientist at AT&T Bell Laboratories, where he was granted over a dozen patents related to semiconductor manufacturing processes that served as the foundation for modern microelectronics manufacturing.Manocha was an advisor to President Obama on the Advanced Manufacturing Partnership Steering committee and on the President’s Council of Advisors on Science and Technology (PCAST). In 2012, during his tenure at GLOBALFOUNDRIES, he was awarded the prestigious “EHS Achievement Award — Inspired by Akira Inoue” for his commitment and action on Environmental Health and Safety standards. Additionally, he has excelled in people development by teaching courses such as “Leadership by Example” and “Classroom to Cleanroom to Boardroom.”In December 2019, Manocha was named an “All Star of the Semiconductor Industry” by VLSI Research for his visionary leadership in restructuring SEMI from its traditional position to represent the expanded electronics supply chain. In February 2020, he was inducted into the Silicon Valley Engineering Hall of Fame.

Welcome Remarks

Altimime, Laith
President
SEMI Europe

Abstract
Welcome Remarks

Biography
Laith Altimime, as President of SEMI Europe, leads SEMI’s activities in Europe and the Middle East and Africa (EMEA). Altimime has P&L responsibility as well as ownership of all Europe region programs and events, including SEMICON Europa. He is responsible for establishing industry standards, advocacy, community development, expositions, and programs. He provides support and services to SEMI members worldwide that have supply chain interests in Europe. He manages and nurtures relationships with SEMI members in the region and globally as well as with local associations and constituents in industry, government, and academia. Altimime has more than 30 years of international experience in the semiconductor industry. Prior to joining SEMI in 2015, He held senior leadership positions at NEC, KLA-Tencor, Infineon, Qimonda, and imec. Altimime holds an MSc from Heriot-Watt University, Scotland.

Silicon Carbide in AC Motor Drives

Puukko, Joonas
Senior Field Application Engineer
Semikron Danfoss

Abstract
With recent technological advancements, silicon carbide is becoming the first choice for enabling energy savings and increasing power density. However, motor drives and silicon carbide MOSFETS are two topics that seemed impossible to combine: high costs, fast switching transitions, lack of short circuit capability, and reliability concerns were all persistent roadblocks, preventing a tangible return on investment. But it is time to rethink. By merging state of the art packaging technology with the latest generation of SiC MOSFETs, we provide a totally new degree of design freedom to motor drive design engineers.

Biography
biography

Production-Proven Chemical-Free Green Alternative to Solvent and Piranha Wafer Processing using Ozone

Sundin, Phillip
Business Development Manager
Shellback Semiconductor Equipment

Abstract
Efforts to implement green technologies in semiconductor manufacturing have historically been slow with acceptance, blocked by perceived concerns over performance risk, operational disruption, and cost. Nowhere is this more apparent than in photoresist stripping, where aggressive chemistries like sulfuric-peroxide mixtures and hazardous solvents like NMP and DMSO remain standard, despite their well-documented environmental burdens. This paper presents a comprehensive assessment of a novel process that offers a rare and timely exception: chemical-free resist removal using ozone gas diffused through heated deionized water.Unlike ozone-dissolved water systems this method operates in a high-temperature, ozone-rich gas environment. The result is rapid, surface-driven chemical deconstruction of the resist polymer, eliminating the need for persistent oxidizers or solvents, while producing minimal downstream contamination. Comparative lifecycle analysis across chemical input, energy use, waste generation, worker exposure, and effluent treatability reveals a substantial reduction in environmental burden—without compromising technical requirements. Measured CO₂e emissions per wafer are reduced by over 70% relative to sulfuric-peroxide and solvent-based strip methods. Tool-level performance data confirms comparability with common process chemistries, complete resist removal, and throughput on par with legacy methods.The maturity of this process approach marks a departure from previous “green tech” proposals that failed to meet manufacturability thresholds. At a time when fabs face mounting pressure from hyperscaler customers, EU carbon regulation, and Scope 3 accounting mandates, this process uniquely aligns technical performance with immediate sustainability impact. Its adoption represents a meaningful step forward in closing the longstanding gap between sustainability goals and operational realities.The paper will first substantiate its environmental advantages through modeled CO₂e comparisons per wafer, based on documented chemical usage rates for conventional and ozone-based strip processes. It will then confirm the technical soundness of the method—grounding its effectiveness in known reaction pathways and supporting it with fab-level data on resist removal, compatibility, and defectivity. Together, these findings show that the process can be deployed now—without tradeoffs—to meet rising green manufacturing demands.

Biography
Phillip SundinBusiness Development Manager at SHELLBACK Semiconductor TechnologyPhillip Sundin is a seasoned professional in the semiconductor equipment industry with over 3-decades of experience with wet-processing equipment. He is currently serving as the Business Development Manager at SHELLBACK Semiconductor Technology. In this role, he plays a pivotal part in driving the company's expansion and customer engagement efforts.At SHELLBACK, Phillip has been instrumental in the company's global growth initiatives. A notable focus is the increased awareness and adoption of the Torrent Eco-Clean system, which incorporates SHELLBACK's award-winning HydrOzone chemical-replacement technology. This environmentally safe surface preparation system can reduce or eliminate the need for traditional chemicals, aiding clients in achieving their greenhouse gas reduction goals. The Torrent system is particularly significant in supporting the semiconductor industry's projected expansion to a $1 trillion valuation by 2030.Phillip's expertise lies in identifying and capitalizing on emerging market opportunities within the semiconductor sector, particularly involving wet-processing equipment. His strategic insights, leadership and passion have been critical in positioning SHELLBACK as a key player in the semiconductor equipment industry.

Plan Virtual, Build Sustainable: Combining the Real and the Digital World

Westrich, Katharina
Global VP of Electronics, Semiconductors & Simulation
Siemens AG

Abstract
As global semiconductor demand accelerates, the industry faces a dual challenge: scaling rapidly while scaling sustainably. Greenfield fabs offer a unique opportunity to embed net-zero principles from the outset—but the transformation must also extend to brownfield sites through modernization and retrofitting.What if every decision in fab planning and operations could be validated virtually—before a single foundation is laid, a system installed, or a solution deployed?At Siemens, we are making this vision a reality. By applying digital twins across the entire fab lifecycle—from conceptual design through construction and operations—we enable sustainability to be engineered in from day one. Our approach integrates: Deep domain expertise, AI-powered analytics, IT/OT convergence and real-time simulation.The result? Smarter, faster decisions that optimize energy use, reduce emissions, and minimize downtime. With Siemens, the fab of the future isn’t just more cost-effective—it’s inherently more sustainable.

Biography
Katharina heads Siemens’ global activities for Electronics & Semiconductor and Simulation, leading a team dedicated to unlocking the potential of resilient, smart, and sustainable semiconductor manufacturing across the entire value chain. As an elected member of the Semiconductor Climate Consortium (SCC) Governing Council, Katharina reinforces her commitment to drive positive change within the semiconductor ecosystem. Her dynamic leadership places her at the forefront of digitalization and sustainability solutions – transforming the everyday through innovative technologies.Previously, Katharina held various strategic positions within Siemens, including heading the Research & Pre-Development department. She championed sustainable practices and contributed to the development of next-generation Siemens products.She holds a Master of Science degree from the Catholic University Eichstaett-Ingolstadt.

Digital Twin-Enabled Heterogeneous Package Assembly: AI-Driven Yield Optimization Through Early Design and Equipment Modeling

Dudek, Heiko

Siemens EDA

Abstract
As heterogeneous integration and advanced packaging technologies become crucial enablers for next-generation electronics, manufacturing yield optimization presents unprecedented challenges. This paper introduces an innovative approach that bridges the gap between package design and manufacturing through advanced digital twin modeling of assembly equipment, enabling predictive yield optimization at the design stage which ultimately will decrease time to market by reducing the number of prototypes required. Our methodology implements a comprehensive Assembly Design Kit (ADK) framework that incorporates both physical equipment constraints and process variations.

Biography
Heiko Dudek joined Siemens Digital Industries in 2021, and holds a M.Sc. in Electrical Engineering from University of Applied Science, Munich. He is in EDA for 27 years, holding various positions, including application engineering, R&D, services and technical sales. These days his is looking after solutions around 3D-IC & Heterogeneous Advanced IC Packaging within Europe.

Topic Coming Soon

Gualandris, Fabio
President Quality, Manufacturing & Technology
STMicroelectronics

Abstract
Coming Soon

Biography
Fabio Gualandris is STMicroelectronics’ President, Quality, Manufacturing, andTechnology and has held this position since July 2023. He was responsible for the company’s Back-End Manufacturing & Technology organization since 2016 and also led the Company’s Testing Council, alongside its manufacturing strategy in Asia and efforts in System-in-Package technology. Gualandris is a member of ST’s Executive Committee.Gualandris joined SGS Microelettronica (now ST) R&D in 1984. He became R&DDirector of Operations in 1989 and became Automotive BU Director in 1996. Aftertwo years as President and CEO of Semitool, he rejoined ST in 2000 as Group VP responsible for memory products including the RAM/PSRAM and Automotive Flash.In 2005, Gualandris was appointed CEO of ST Incard, an ST smart-card subsidiary. In 2008-2010, he served as VP and Supply Chain General Manager at ST’s memory JV with Intel. In 2011, Gualandris was appointed ST’s Executive Vice President, Product Quality Excellence. Gualandris has authored several technical and managerial papers and holds multiple international patents. He serves as Chairman of STS, ST's manufacturing JV in China.Fabio Gualandris was born in Bergamo, Italy, in 1959. He holds a Master’s degree in Physics from the University of Milan.

Droplet assisted D2W bonding – introducing fluidics for improved bond front control for low-defect sequential D2W hybrid bonding

Schmidt, Thomas
Product Manager
SUSS MicroTec SE

Abstract
Increased control of bond front propagation using DIW droplets dispensed prior to actual die placement could be a powerful approach to reduce the risk of bond voids caused by entrapped air and make thin and also large die handling less complex regarding the bond head design. The technique has the potential to support future D2W bonding with die thicknesses <30µm at improved yield.

Biography
Thomas Schmidt is Product Manager within the Bonder product line of SUSS in Sternenfels. After graduating with a degree in microsystems engineering from the University of Applied Sciences Kaiserslautern, Zweibruecken site, he held various positions within the MEMS/semiconductor industry and also taught at the Baden-Wuerttemberg Cooperative State University (DHBW) in Loerrach and at the Albert-Ludwigs-University in Freiburg on the topics of advanced lithography, microsystems technology and CMOS microelectronics.Since December 2017, Mr. Schmidt has been a member of the bonder team at SUSS, where he is responsible for the permanent wafer bonding product line with a focus on fully automated production systems that enable both established bonding techniques (for MEMS, packaging, etc.) and newer bonding developments such as D2W and W2W hybrid bonding for advanced packaging.

JePPIX: The joint European platform for photonic integrated components and circuits

Williams, Kevin
Professor
Technical University Eindhoven

Abstract
Integrated photonics offers us the way to a faster, more precise and more energy efficient future. The sustained growth of the internet is already critically dependent on photonic integrated circuits. Photonic integrated circuits (PICs) are now emerging in industry labs for imaging and metrology with precision, size, and they are showing efficiencies which can be orders of magnitude beyond non-integrated technologies. Supply chains are now aligning to support product developments across many market sectors.JePPIX - the Joint European Platform for Photonic Integrated Components and Circuits - is a vibrant community of foundries, software vendors, testing experts, packaging companies, technology innovators, equipment suppliers and PIC-enabled module developers. Together they play a key role in defining the road to commercialization in new and emerging sectors. JePPIX is a pioneer of the open-access foundry model for integrated photonics - specifically indium phosphide but also heterogeneous approaches - enabling the end-user to drive product development. Companies and researchers have already been prototyping using commercial JePPIX services for more than a decade. Product developers are focussing on metrics critical to quality, reproducibility, reliability and the seamless interconnection of accelerated design-fab-test cycles which are required to prepare a design for production. Going forwards, strategies are being developed to accelerate design through the delivery of manufacturing excellence within sustainable commercial value chains. The telecommunications sector has already shown how premium PIC technology can be delivered. The next wave of product innovation is more diverse in terms of platforms, components, and circuits. Foundry manufacturing offers a compelling route to accelerated deployment of products across multiple sectors. We will elaborate the future challenges and perspectives for research and innovation for PIC technologies.

Biography
Kevin Williams is full professor and chair of the Photonic Integration research group at Eindhoven University of Technology (TU/e). He has extensive experience in the design, fabrication and measurement of InP based photonic devices and integrated circuits, including semiconductor lasers, amplifiers, high speed modulators and photonic switches. Kevin was coordinator for the EC JePPIX Pilot Line which matured the full supply chain from software, design, production and test for foundry based PIC manufacturing. The team has played a key role in establishing the Photonic Integration Technology Centre and plays an active role in the Chips JU PIXEurope project.

The Role of Time Critical Logistics in Complex Global Supply Chains

Schoenzetter, Remy
Global Head of Business Unit High Tech & Semicon
time:matters GmbH

Abstract
As semiconductor supply chains stretch across continents and rely on tightly sequenced production flows, even minor delays can lead to significant disruptions. In a world impacted by geopolitical shifts, supply shortages, and accelerating innovation cycles, the ability to respond quickly is no longer optional - it’s a strategic necessity.In this session, Remy Schoenzetter, Head of the Business Unit High Tech & Semicon at time:matters, explores the critical role of agile, time-sensitive logistics in securing continuity and responsiveness across the semiconductor value chain. Drawing on global experience in supporting semiconductor manufacturers and equipment suppliers, he will outline how time-critical networks, courier terminals, and 24/7 operational control are becoming increasingly important.This talk offers a strategic perspective on how companies can rethink urgency, resilience, and agility - transforming logistics from a cost driver into a competitive edge.

Biography
Remy Schoenzetter is the Global Head of the High Tech & Semicon Business Unit at time:matters, a logistics service provider specializing in time-critical logistics.With over a decade of experience in supply chain management, air freight, and freight forwarding, Remy brings a pragmatic, hands-on perspective to complex logistical challenges.His career spans various roles across different logistical networks, including leadership positions in operations, customer service, and strategic partner management. Prior to his current role, Remy served as Head of Operations Western Europe, where he oversaw a team of logistics experts and led transformative initiatives across the region.He is known for connecting cross-functional teams and translating customer urgency into solutions that drive performance and resilience.Remy holds a Master’s degree in Finance, complemented by certifications in Lean, Agile, and professional coaching. He combines analytical thinking with a people-centered leadership style, and currently contributes to the SEMI Supply Chain Initiative as a strategic partner.

From Lab to Leadership - Europe’s bet on Semiconductor Startups

Machold, Michael
Operational Director - Venture Lab Quantum/Semicon
TUM Venture Labs

Abstract
The semiconductor industry is evolving rapidly. While traditional technologies advance, new computing paradigms are emerging: quantum computing leverages quantum mechanical principles, neuromorphic computing mimics the brain's neural structure, and photonic computing uses light instead of electrons for processing. This session explores these technological trends and examines how European semiconductor startups are positioned to drive innovation. We'll discuss the strategic importance of semiconductor development for Europe's technological sovereignty and economic future. We'll also highlight how collaborative ecosystems are helping startups overcome challenges in this capital-intensive sector by bridging research and commercialization. Join us to discover how industry, investors, policymakers, and entrepreneurs can work together to strengthen Europe's position in the global semiconductor landscape.

Biography
Michael Machold is Operational Director at TUM Venture Labs Quantum/Semicon, where he is building the leading incubation program for founders in semiconductors, photonics, nanotech, and quantum technologies, actively driving Europe's deep-tech startup ecosystem.With over a decade of experience at Infineon Technologies, including serving as Director – Head of Product Management Automotive Microcontroller, Michael brings deep insights into the semiconductor industry. He holds an M.Sc. in Electrical Engineering from TUM and an Executive MBA from ESADE Business and Law School.

Strategic advances in III-V RF Technologies for energy-efficient 5G infrastructure

U'Ren, Gregory
Senior Technical Expert
United Monolithic Semiconductors (UMS)

Abstract
III-V semiconductor technologies, including GaAs and GaN/SiC, are at the core an effort lead by UMS to strengthen European sovereignty in advanced rf components for terrestrial and non-terrestrial 5G due to their unrivaled performance in high-frequency, high-power, and high-linearity applications. This talk will highlight the strategic role of III-V technologies in enabling energy-efficient RF front-ends and system-in-package (SiP) solutions, addressing the growing demands of 5G and SATCOM networks. By combining advancements in MIMC device technology, innovative device architectures, and heterogeneous integration, the ambition is to realize a 40% reduction in power consumption across the full radio link. Efficiency gains in the network reduce operating costs from the combination of reduced energy consumption and reduced thermal management.

Biography
Dr. Gregory U’Ren is presently with United Monolithic Semiconductors (UMS) leading strategic innovation initiatives. He has held both leadership and individual roles contributing to the advancement of a broad range of specialty technologies including SiGe BiCMOS, RF-SOI, MEMS, and GaN. He is a senior member of IEEE, presently also serving on the advisory board at the Fraunhofer Institute for Applied Solid State Physics, a member of American Physics Society, and holds over 30 patents. He completed his Ph.D. and MS at the University of California Los Angeles.

Shifting boundaries: Advancing Memory and Compute, Together.

Dubois, Sylvain
CEO
VERTICAL COMPUTE

Abstract
Compute chip performance has surged over the last decades, but memory performance, using technologies like SRAM, DRAM, and 3D-NAND, has lagged, leading to complex memory hierarchies. The recent rise of Generative AI has pushed memory demands beyond current capabilities, resulting in expensive High-Memory-Bandwidth (HBM) chips and AI systems in the cloud, just as scaling roadmaps for the memory technologies are stalling.This presents an opportunity for Vertical Compute's integrated memory, which vertically integrates magnetic bit strings directly above transistors. This offers greater density than DRAM (> Gb/mm2) and SRAM-like access latency (~10ns). Direct CMOS integration eliminates data bus bottlenecks, reducing power and enabling high-performance, in-memory compute for LLM inference on a single chip.This presentation will cover the state of Generative AI hardware, the 100X potential of vertical integrated memories, and the path to industrial production.

Biography
Sylvain Dubois is the CEO and co-founder of Vertical Compute, a hardware semiconductor startup developing a proprietary vertical integrated memory technology, designed to unleash the data flow for data intensive workloads. He previously worked at Google, in Advanced Technology Sourcing & Partnerships for the Google Cloud Infrastructure group in Sunnyvale, CA. His responsibilities included identifying, analyzing, and developing emerging technology trends, with a focus on Artificial Intelligence hardware acceleration compute chips, memory, and chiplet integration. Prior to his role at Google, he served as Vice-President of Business at Crossbar, a California-based deep tech startup specializing in novel memory development.