Empowering Next-Gen Semiconductor Innovation with the 3DEXPERIENCE Platform

,

Abstract
The semiconductor industry plays a pivotal role in enabling the adoption of new technologies and addressing bottlenecks in their implementation. This industry is currently experiencing rapid growth and technological innovation, driven by increasing demand in sectors such as AI, automotive (especially electric and software-defined vehicles), 5G, and consumer electronics. The complexity of advanced technologies needs the collaboration across the entire ecosystem, from materials and equipment suppliers to design and manufacturing partners. This collective effort drives innovation and ensures that the increasing demands of the digital world are met. This type of collaboration goes beyond the semiconductor fab, bringing together designers, OEMs, and foundries—all of whom gain from a platform that offers distinct value.In this talk, we introduce a model-based systems engineering approach-based platform i.e; 3DEXPERIENCE platform. It addresses key challenges in semiconductor development by enabling the design and manufacturing of complex, multi-domain chips through cloud collaboration, virtual twin simulations, and streamlined workflows. This comprehensive platform helps overcome growing design complexity, silos, and supply chain inefficiencies—ultimately supporting faster innovation, improved performance, and reduced time-to-market for next-generation semiconductor solutions.

Biography
Manuel REI - Semiconductor Industry Solution Experience DirectorManuel joined Dassault Systèmes in 1986 and has over 35+ years of experience supporting high-tech and automotive global companies, including relocations in South Korea and USA for the deployment of Dassault Systèmes solutions within Samsung Electronics, LG Electronics and IBM hardware divisions.He leads High Performance Semiconductor Industry Solution Experience, leveraging virtual twins to turn semiconductor complexity into business profitability , and deployed at customers such as NXP, Broadcom, Samsung Electronics, Qualcomm and STMicroelectronics.

Laser-based Annealing of Nickel Contacts for SiC Devices: Towards Thermally Robust Power Interfaces in 3D Integration

Clair, Maurice
Head of Process Development
3D-Micromac AG

Abstract
Thermal management and electrical integrity are critical bottlenecks in 2.5D/3D packaging, particularly for wide-bandgap semiconductors such as silicon carbide (SiC), which enable next-generation power-dense systems in the automotive and high-performance computing sectors. In this context, Ohmic contact formation (OCF) for SiC must evolve beyond conventional rapid thermal processing (RTP) to meet the demands of thin substrates, reduced thermal budgets, and higher integration density.This contribution explores a laser-based approach for localized OCF on SiC using diode-pumped solid-state lasers (DPSSL) with UV wavelengths. The study investigates the effect of varying laser fluence, pulse duration, and beam overlap on the formation of nickel silicide (Ni_xSi_y) contacts on 350 µm-thick 4H-SiC wafers with 70 nm NiAl metallization. Qualitative process trends are derived based on structural, electrical, and chemical performance indicators, with an emphasis on suppressing carbon-rich interfacial layers – a key factor in interface reliability under high thermal and electrical loads.Key findings show that:(1) Laser-based OCF enables electrically stable contact formation even under high laser fluences, indicating robustness and process tolerance;(2) laser energy density controls Ni_xSi_y thickness and uniformity in a predictable manner;(3) Optimized pulse overlap below 30% mitigates the formation of carbon accumulation at the metal/SiC interface.This laser-driven method represents a promising alternative to RTP, particularly where localized processing and reduced thermal budgets are required. By minimizing global substrate heating and enhancing interface stability, the approach facilitates improved thermal integration compatibility for SiC-based power devices in 2.5D/3D packaging environments.

Biography
Maurice Clair studied Mechanical Engineering at the University of Technology Chemnitz (Germany). He joined 3D-Micromac in 2005 as a development engineer and is now team leader of the technology and innovation management department. In his current role, he serves as the technical lead for ohmic contact formation on SiC (silicon carbide) materials, a critical area in advancing semiconductor technologies.Through his expertise in laser technologies, he has been instrumental in the development of innovative laser micromachining processes, including: laser trimming techniques for fine-tuning electronic components with both digital and analogue approaches and beam shaping for ultra-short pulsed lasers.

Driving Backend Efficiency – Automation in Wafer Probing and Dicing for the European Semiconductor Industry

Eikelkamp, Dominik
Head of Key Account Management Semiconductor
ACCRETECH (Europe) GmbH

Abstract
As Europe’s semiconductor industry advances toward smart manufacturing and supply chain resilience, backend automation is emerging as a key enabler of yield, flexibility, and competitiveness. This presentation shows how ACCRETECH supports this shift with wafer probing and dicing automation aligned with the EU Chips Act 2.0 and AI-ready fabs.We showcase real-world use cases of the fully automated AP3000 prober and AD3000T-Plus dicer, which eliminate manual handling, increase throughput, and enhance process stability, repeatability, and product quality—while also reducing errors, cycle times, and resource useProber AP3000 automation features:- Automates Probe Card handling via Overhead Transport (OHT) or AGV for hands-free probe card exchange- Automated FOUP Handling for smooth wafer transfer- In-Process Probe Card Inspection to maintain test quality and reduce unnecessary manual maintenance cycles- BigDATA Integration for advanced fab-wide analyticsDicer AD3000T-Plus automation features:- Automated Blade Exchange System (ABES) for barcode-controlled, tool-free blade replacement- Automated Plate Conditioning System (APCS) for inline chuck surface cleaning- Stable Performance Monitoring across wafer types and lotsBoth systems address backend challenges tied to chiplet integration, hybrid bonding, and advanced packaging. Europe’s growing network of OSATs, foundries, and R&D hubs supports wider adoption of such solutions.Automation also plays a strategic role in meeting EU Chips Act 2.0 targets, including 20% global semiconductor market share by 2030. ACCRETECH technologies enable lights-out operation, high-mix/low-volume production, and readiness for AI-driven fab control—essential for European competitiveness and sovereignty.Key Takeaways for Fab Managers and Decision-Makers:- Clear examples of cost, yield, and quality benefits from backend automation- Parallel automation features of AP3000 and AD3000T-Plus- Backend’s role in building a sustainable, resilient EU semiconductor ecosystemThis presentation invites fabs to rethink backend not as a bottleneck, but as a driver of performance and innovation.

Biography
Dominik Eikelkamp is a technology-driven sales leader with over 10 years of experience in the semiconductor industry, specializing in high-precision equipment and fully automated manufacturing solutions. His work is centered on enabling “lights-out” factory environments—integrating advanced machinery, MES platforms, and data-driven control systems to drive efficiency, traceability, and resilience in production.Throughout his career, Dominik has partnered with leading semiconductor and electronics manufacturers across Europe to design and implement intelligent factory concepts. He brings deep practical experience in automation planning, including the integration of both front-end and back-end semiconductor tools such as CMP, probing, dicing, and grinding systems, as well as the configuration of SMT production lines and factory-wide software ecosystems.He is known for bridging technical understanding with business strategy—leading multinational projects, managing key accounts, and advising executive stakeholders on the deployment of scalable, autonomous production systems. His ability to align complex automation technologies with long-term operational goals has made him a trusted advisor in both greenfield and retrofit factory transformations.Dominik holds a Bachelor of Engineering in Environmental Technology and brings a systems-thinking approach to the evolving challenges of semiconductor manufacturing.

Development and manufacturing of Co-Packaged optics demonstrator on IC Substrate technology for the beyond state-of-the-art smart NICs and Switches

Park, Gyuhyeon

Advanced Technologies and Solutions

Abstract
As artificial intelligence, machine learning, and big data workloads have explosive growth, the demand for high-performance infrastructure as hyperscale data centre is pushing the limits. HiConnects is aiming to support industrial challenges by developing heterogenous integration core technology solution for energy-efficient and high-performance cloud and edge computing.In a subtask 3.3.2, we focused on the development of a co-packaged optics demonstrator based on the specifications of NVIDIA and the photonic components development in the pilot line. Specifically, the defined design will be delivered from NVIDIA after specifications of the envisioned product requirements for co-packaged optics NIC and switch. According to the design, AT&S will provide the proper solution on Integrated Circuit Substrate (ICS) or PCB with considering system levels needs. In addition, the simulation of heat spreading and mechanical stability (warpage) will be executed by considering different material parameters such as CTE, thermal and electrical conductivity, dielectric constant, and dissipation factor, respectively. PHIX will provide optimized interconnect solution and assemble the Silicon Photonics Transceiver interposer developed by IMEC, network chip, and driver ICs on the ICS. Thermosonic flip-chip bonding technique will be used where Gold micro bumping will be applied either on the ICS or chips. The micro-optical lenses from Teramount will be bonded on the SiPh transceiver chip and Fiber Connector will be attached accordingly. Finally, a functional testing of fully co-packaged optics demonstrator will be done by NVIDIA.In this work, we investigated the test vehicle in order to achieve the working demonstrator at the end of HiConnects project. The progress for the test vehicle preparation and output from the project will be presented in this talk. In addition, we will outline a perspective supply chain for co-packaged optics in smart NICs and switches.

Biography
Gyuhyeon Park obtained his Doctor of Engineer (Dr.-Ing) in Mechanical Science and Engineer from the Technical University of Dresden, Germany in 2021. He continued his research at Leibnitz Institute for Solid State and Materials Research (IFW-Dresden) as post-doctor in Dresden, Germany in 2023. His research focused on the fabrication of micro-sized device with thin film of magneto-thermo-electric quantum material.After he join Advanced Technologies and Solutions (AT&S), Austria, now he is focusing on the Optical Communication in the R&D department as Project Manager and delivering successful projects across various industries.

The Acceleration of Test Requirements Driven by Advanced Packaging

Pizza, Fabio
Business Segment Manager
Advantest Europe

Abstract
The growing complexity of systems, enabled by advanced packaging, is driving an unprecedented increase in test requirements.Key challenges - such as faster signal speeds, higher integration, power demands, thermal dissipation, limited access to critical test nodes, and early detection of failures - are driving new semiconductor test strategies. Trends and directions for the future of test are described.In particular, the advent of generative AI has significantly accelerated complexity challenges in test automation.To meet the ever-growing demand for computing power in HPC, graphics, gaming, AI, and ADAS applications, the semiconductor industry is rapidly adopting advanced packaging solutions at scale. This trend enables new approaches, such as multi-vendor and multi-chip integration for large SoCs.Testing across all stages of the manufacturing process is now a critical enabler of both quality and cost efficiency.At the wafer level, Automated Test Equipment (ATE) must provide system-level test coverage to prevent the costly packaging of defective silicon.At the package level, ATE faces increasing challenges, including managing large volumes of test data through limited access ports while also controlling power and thermal conditions.Innovative test strategies and technologies are required to address these demands, particularly those that manage thermal issues throughout the entire test flow. Effective thermal control solutions, from wafer to singulated die and from package to system-level test, are becoming essential for efficiently testing advanced 2.5D and 3D package assemblies.As a result, the role of the ATE-based test cell is evolving—from pure defect detection to complex system-level validation and optimized yield ramps for each new technology node and integration approach.

Biography
Fabio Pizza is a Business Segment Manager at Advantest Europe, within the V93000 Product Unit Marketing organization. Based in the Advantest Italy office, he is responsible for developing and executing strategies to protect and grow the V93000 market share in the Performance Digital segment — including HPC/AI, Mobile/Automotive Application Processors, and ADAS.In his role, Fabio drives the definition of competitive solutions and product roadmaps aligned with customer requirements for performance, cost of test, and innovation.He holds a Master’s degree in Electronics Engineering from Politecnico di Milano (Italy) and brings over 20 years of experience in the semiconductor industry.

Review of the Gases & Materials incoming Supply Chain to Manufacture Chips in Europe

Castrogiovanni, Lorenzo
Vice President Electronics Europe
Air Liquide

Abstract
Review of the gases & materials incoming supply-chain to manufacture chips in Europe

Biography
VICE PRESIDENT EUROPE - SEMICONDUCTORS - INTERNATIONAL EXPERIENCE - MBA - INDUSTRIAL ENGINEERI’m a capable and inspired manager with more than 25 years of experience in industrial environments, internationally.I have an extensive knowledge of semiconductors' industry and the process industries such as chemicals, refining, steel, hydrogen, power & utilities.I perform in business strategy, team leadership, multi-country P&L management and industrial operations.I’m recognized as trustful, innovative and customer oriented. I have clearly appreciated interpersonal and communication capabilities, systematically relying on emphatic listening and capturing attention with storytelling.

Optimisation of supply chain of high-end optronics/photonics components in small quantities: is it possible in Europe?

Saint-Pé, Olivier
Senior Expert
Airbus DS

Abstract
While most European institutions (EU, ESA, national governments...) fully recognize the strategic nature of Space business, it remains difficult in this area to meet the conflicting needs of developing high-performance custom components in very limited quantities at an affordable price. These demands are particularly contradictory for key optronics and photonics components such as image sensors, high data rates transceivers, and Photonics Integrated Circuits (PICs), whose production technologies are optimized for large volumes and require expensive non-recurring investments upstream of any production.After an introduction recalling why Space is an increasingly strategic field for Europe, the authors will explain why Space needs are specific and broad based on the example of photon detectors and why COTS devices are not able to efficiently answer most of the needs. In the last part of the talk, examples of low-volume supply chains of detectors meeting space technical needs will be presented, as well as axes proposed to make such productions more efficient in Europe.

Biography
Technical expert in the field of optical detection, he has been highly involved in Phase 0/A-B1 studies for many TSEIO optical instruments since more than 35 years, successfully codesigning focal planes and corresponding custom detectors for missions such as Huygens, GAIA, GOCI, Sentinel 2, METimage, Trishna and LSTM.As R&T and R&D study manager, he has contributed to passive and active optical instrument innovations in particular by pioneering several new detection technologies for space applications such as CMOS Image Sensors, microbolometers, T2SL, MCT APD and SPAD/SiPM, including the understanding of radiation effects on their performances and the developments of innovative methods and means for their characterizationsHe has technically mentored many internships and young engineers within TSEIO in the field of optical detection and has been co-supervisor for 15 PhD thesis. He is the author or co-author of more than 100 papers in the field of space optical detection and instrumentation.In the frame of internal and institutional R&D/R&T studies, he has set several collaborations with European industrial and academic stakeholders in the field of optical detection.His deep knowledge about the physics and manufacturing processes of optical detectors regularly serves to find out anomalies root causes during projects Phase B2/CD and Phase E.

Arago: Practical Optical Computing

Muller, Nicolas
CEO
Arago

Abstract
Arago has built an energy-efficient AI chip powered by light, codenamed JEF, designed to run AI workloads with 10x to 30x lower energy and cost overhead. Its mission is to drive the course of history forward. Based in France, North America, and Israel, Arago has assembled a world-class team of engineers, scientists, and operators from leading companies and research labs, and is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent deeptech venture firms and exited founders.

Biography
Coming Soon

Capturing Value in the Age of Compute-Enabled Intelligence

Frey, Christophe
Vice-President of EU Engagements
Arm France

Abstract
Every industrial revolution has been powered by an engine. Today, compute drives the age of intelligence, reshaping how humans interact with technology. Early machines were human-intensive: cars needed a crank handle; PCs demanded keyboard and mouse. By the late 20th century, products became connected and reactive with touchscreens and apps. With AI, systems are shifting from reactive to proactive: autonomous companions that act for us, powered by far more compute. The next leap brings “guardian” systems that augment us demanding orders-of-magnitude more capability. Capturing value in this transition requires pairing technical breakthroughs with new business models and ecosystem structures that translate innovation into durable economic impact.

Biography
Based in Sophia Antipolis France, he has been the General Manager of Arm France since 2014. He also serves as VP of EU Engagements where he focuses on strengthening Arm’s presence within the European semiconductor ecosystem.Prior to Arm he has held various roles in design and management at STMicroelectronics in Crolles, France, for 12 years. He contributed to establish the Crolles2 alliance with Philips and Motorola, an experience that led to his first international immersion in Austin Texas.He then joined the startup SOISIC, where he served as VP of Engineering before the company was acquired by Arm in 2006. At Arm, he has spent four years in Silicon Valley California as VP of Operations.In 2024 he became an operating Partner at C4 Ventures investment fund, where he brings his 30 years of experience in the semiconductor industry.He holds a MS degree from PHELMA Grenoble.

Topic Coming Soon

Hidma, Anne
Senior Vice President EUR & US
ASML

Abstract
Coming Soon

Biography
Anne is responsible for ASML’s customer and research partnerships, as well as business operations across these regions.As such, Anne’s team addresses customers’ future technology roadmaps, application challenges, and operational requirements.Next to the financial and operational management of our customer business, she drives improvements in ASML’s products and services together with the broader ASML organization to better meet customer needs.Anne is a member of the Executive Team of ASML.Prior to ASML, Anne was a Partner at McKinsey & Company. She led the Advanced Industries practice in the Benelux and was a core part of the Strategy & Corporate Finance practice in Europe.Anne obtained her MSc degree in Nanoscience at the faculty Applied Physics of Delft University of Technology. She holds an MBA degree from Columbia University in New York.

Ubiquitous AI Computing - AI Everywhere

Bond, Andy
Director - Silicon Verification
Axelera AI

Abstract
Artificial Intelligence, Machine Learning, ChatBots, MCPs, and a plethora of other terms associated with the evolution of computing are becoming as ubiquitous as the technology itself. Whether it's asking Alexa for cinema recommendations from the comfort of your sofa, prompting Siri to curate a playlist for your Monday morning commute, or utilizing GitHub Copilot to fix your Python syntax, AI has become an integral part of our daily lives.Despite this widespread integration, the underlying technology remains largely centralized and cloud-based, leaving edge customers underserved by existing solutions. From security and retail to industrial applications, robotics, automotive, and energy sectors, the demand for AI solutions continues to rise, yet the availability of suitable options lags behind.The edge space presents a unique challenge due to the contrasting requirements of performance, cost, and power consumption, making it a technically demanding yet ripe area for innovation. When combined with the fragmented nature of these sectors and the diverse range of applications, the prospect becomes even more fascinating and challenging.This presentation aims to introduce this rapidly evolving landscape and highlight the future challenges ahead. By referencing Axelera’s innovative hardware and software approach, we hope to initiate a discussion on how we can progress together.

Biography
Andy has accumulated over 25 years of experience in the semiconductor industry, working across various fields from processors to networking, as well as audio and finance.His experience covers most aspects of consumer electronics, primarily in the roles of design verification engineer and manager.Beginning his career at ST Micro, Andy has led teams at Icera Semiconductor, NVIDIA, and Cirrus Logic. Currently, as the Director of Silicon Verification at Axelera AI,he is applying his expertise to the dynamic field of artificial intelligence.

Scaling Intelligent Compute Through Topology-Agnostic Fabric IP for Chiplet Integration

Aldis, James

Baya Systems

Abstract
As the semiconductor industry embraces advanced packaging to unlock higher integration and performance, it faces growing complexity in designing systems with chiplets and heterogeneous components. The demand for bandwidth, compute density, and energy efficiency, is outpacing what traditional SoC integration can support, particularly for AI and high-performance computing workloads. At the same time, next-generation platforms must deliver consistent performance while reducing time-to-market, thermal impacts of data movement, and the resultant total system cost.This paper addresses the integration and data movement challenges at the heart of advanced packaging by introducing a new class of chiplet-ready fabric IP optimized for modular architectures. Developed to simplify multi-die system designs, the proposed solution supports both coherent and non-coherent communication under a unified architecture, enabling seamless on-die and die-to-die data movement.Unlike traditional and resource-intensive custom hardware design techniques, this fabric IP is software-defined, topology-agnostic, correct-by-construction, and highly scalable—accommodating diverse compute needs, memory, and accelerator elements within a single package. It delivers low-latency, high-throughput communication across scalable chiplet topologies, maintaining robust data movement even in complex multi-die configurations using 2.5D and 3D integration. By abstracting interconnect complexity and providing data-driven design capabilities, this approach helps teams ensure performance guarantees early in the design cycle, meeting both functional and thermal goals while accelerating system integration.The presentation will cover integration strategies, benchmarks demonstrating throughput and latency performance, and implications for heterogeneous packaging and chiplet-based deployment. It will also explore how this approach accelerates advanced packaging adoption through simulation-driven design, software-defined system fabrics, and intelligent chiplet partitioning enabled by data movement optimization.

Biography
Dr. James Aldis has been working in on-die and inter-die networking since the early 2000s, for Texas Instruments, Imagination Technologies, Intel Corporation and others. He has built chips using all the important independent NoC technologies of the last 20 years as well as many proprietary interconnect technologies. Additionally, he has made many contributions to industry ecosystem development in the areas of SystemC-TLM, OCP-IP, AMBA and HSA. James has a PhD in electronic engineering from the University of York and a BSc in pure mathematics from the University of Liverpool.

AI in Action: Changing How We Work, Decide & Create

Lange, Maik
AI Transformation Lead & Rapid Innovation Enthusiast
Bayer AG

Abstract
Why AI is a Game Changer for Bayer- How AI accelerates learning, sharing, and decision-making across BayerAI Transformation Journey at Bayer – Best Practices & Learnings- Building the Bayer Generative AI Community and fostering cross-functional collaboration- Success stories & lessons learned from implementing AI in real-world healthcare use casesInspiration & Outlook – The Business World in Transition- How AI redefines roles, skills, and leadership- The shift from human-only decision-making to AI-assisted intelligence

Biography
Maik LangeAI Transformation Lead | Lecturer | Founder | Innovation StrategistAs AI Transformation Lead with 22+ years of experience in IT and digital marketing — and 3+ years specializing in Generative AI and the Metaverse — I drive AI initiatives from emerging trends to real-world pilot projects, with a strong focus on better patient experiences and healthcare innovation.Since January 2023, I have been shaping the AI strategy at Bayer AG: co-founding the Generative AI Community, initiating use-case campaigns, and implementing pilot projects with state-of-the-art generative AI tools. I also build strategic partnerships with leading AI technology providers to accelerate innovation.From 2020 to 2022, I served as Digital Trend Master at Bayer, exploring AI and emerging technologies to strengthen digital health offerings. During this time, I redefined marketing formats through podcasts, VR experiences, and interactive live sessions.Teaching & knowledge transfer are at the heart of my work:- Lecturer at Media University Berlin and NOVA IMS Information Management School in Lisbon- Speaker at business summits and innovation forums- Trainer for executives through workshops, leadership hackathons, and project weeks- Organizer of Future Forums with institutions like Cambridge Business SchoolAs the Founder of AI Kids Academy TinkRebels.com (launching August 1), I prepare the next generation for an AI-driven world by empowering kids with hands-on AI skills through explorer and entrepreneur programs.Beyond corporate innovation, I am an AI Creator: publishing books, podcasts, and music, while developing Generative AI Innovation Labs — creative playgrounds where new solutions are tested, scaled, and brought to market readiness.

Topic Coming Soon

Schulze, Joerg
Spokesperson for the Bavarian Chips Alliance, Director of the Fraunhofer IISB
Bayern Innovativ GmbH

Abstract
Coming Soon

Biography
Experienced Semiconductor Physicist and Engineer with a demonstrated history of working in the research industry and academia. Skilled in Research and Development (R&D) for semiconductor-based Micro, Nano, Opto, Power, Quantum Electronics. Experienced Lecturer and Teacher in Experimental Physics, Semiconductor Physics-Engineering-Technolog

Panelist

Hamelin, Régis
CTO
Bluemorpho

Abstract
Panelist

Biography
Régis Hamelin earned an engineering degree in materials science and a PhD in Electronics from the University of Lille, where he researched semiconductor lasers with the IEMN optronics team in 1993. He spent seven years at CEA-LETI as a process engineer and program manager in optronics, developing expertise in compound semiconductor photonic components and packaging. In 2003, he co-founded Intexys Photonics, serving as CTO and board member in launching active optical cables for high-end supercomputers. In 2010, he joined the “COWIN” support action under FP7, leading to the foundation of BLUMORPHO, which he joined as CTO in January 2015. He is currently coordinator of the aCCCess CSA working closely with the network of Chips Competence Centers.

High Throughput Thin Film Coatings combining Maximal Uniformity and Minimal Defects for the Future of Acoustic Wave applications

Pereira, Daniel

Bühler Alzenau GmbH

Abstract
The evolution of RF filters for 5G has driven significant advancements in acoustic wave filter design and manufacturing, with several structures now widely tested and adopted in mass-market applications. The more recent trend is towards building Surface Acoustic Wave (SAW) filters on Piezo-on-Insulator (POI) wafers, a technology that extends performance into higher frequency bands essential for 5G. Challenges arise on the production of defect-free, high density oxides that couple to the piezoelectric materials (like LiTaO3 or LiNbO3) or on the supersmooth surfaces required for the production of the devices, particularly as pitch sizes decrease to accommodate higher frequencies. In this presentation, we explore the challenges associated with the manufacturing of SAW filters on POI substrates. We focus on how Bühler Leybold Optics' Semiconductor portfolio leverages decades of expertise in optics thin-film processing to address the complexity of next-generation RF devices. With emphasis on advanced thin-film deposition and planarization methods - including Magnetron Sputtering, Ion-Beam Assisted Deposition, and Ion Beam Trimming - these ensure mass-production solutions for the creation of consistent, high-quality films with minimal defects and maximal uniformity. These techniques not only enhance the performance and reliability of acoustic wave filters but also enable efficient processes such as wafer-to-wafer bonding, a critical requirement for POI technology.

Biography
Daniel Sá Pereira joined Bühler Leybold Optics in 2021 working on the Semiconductor Market Segment as a technical Sales Manager. Daniel is a Microelectronics Engineer from the New University of Lisbon, Portugal (2015) and a PhD in Physics from the University of Durham, United Kingdom (2019). His research focused on the characterization of organic materials for application in organic light emitting diodes (OLEDs). Since leaving academia, Daniel has joined Business Unit Optics at Bühler Alzenau GmbH to focus on emerging applications that combine the worlds of Optics with Semiconductor like Augmented Reality, RF Communications, Photonic Integrated Circuits, Ambient Light Sensors, etc.

Driving ICT Decarbonisation: Unlocking the Power of Product Carbon Footprint Insights

Richardson, Izzy

Carbon Trust

Abstract
As 2030 approaches and ICT sector confronts mounting climate pressures, hyperscalers are increasingly requesting Product Carbon Footprints (PCFs) from their semiconductor and component suppliers. While this growing demand can pose a challenge for semiconductor companies—many of which have complex supply chains—it also represents an opportunity. This presentation will explore why product-level carbon insights are becoming essential, and how they can unlock new paths to decarbonisation, innovation, and competitive advantage.Focusing on both the semiconductor industry and the broader ICT sector, the Carbon Trust will explain how PCFs can be robustly calculated, clearly communicated, and effectively leveraged. We will explore how high-quality, transparent PCFs can drive emissions reductions, inform better design and procurement decisions, and align with evolving regulatory and customer expectations.This session is both a call to action and a practical guide. Attendees will gain insight into starting, or strengthening, their PCF journey, whether to ensure compliance, enhance corporate sustainability strategies, or contribute meaningfully to the sector’s collective decarbonisation goals.

Biography
Izzy is an Associate at the Carbon Trust, where she supports corporate clients in the ICT sector on their journey to Net Zero. Izzy specialises in device and component manufacturers, supporting their product emissions reporting to enable accurate, transparent, and clear emissions communication on a B2B and B2C basis.The Carbon Trust is a mission-driven, not-for-dividend climate consultancy. For over 20 years, we have been pioneers in climate action, partnering with leading businesses, governments, and financial institutions around the world.We are a global network of 400 experts, with offices in the UK, the Netherlands, South Africa, Singapore, and Mexico.From strategic planning and target setting to implementation and communication, we are your expert guide for turning climate ambition into real impact. To date, we have helped set over 200 science-based targets and supported more than 3,000 organisations across 70 countries on their journey to Net Zero.

European Pilot Lines: Aligning Strategy, Efficiency, and Implementation

Noguet, Dominique
FAMES Pilot Line Project Coordinator
CEA-Leti

Abstract
FAMES Pilot Line

Biography
Dominique Noguet holds an engineering degree of the National Institute of Applied Sciences (INSA) in electrical engineering in 1992, and a PhD from National Polytechnic Institute of Grenoble (INPG) in 1998 (awarded best INPG PhD of the year). He started his carrier as a digital IC designer for telecommunication applications and then project manager in the same field. He led many projects at a national level (coordination of ANR projects) and in several European frameworks (FP5, FP6, FP7) He has been a key member of several IEEE standard groups and was subsequently elevated to the grade of IEEE Senior Member for his contributions. In parallel he held managerial positions at CEA-Leti as lab manager and department manager. In January 2023, he was appointed project manager for the French ‘France 2030’ flagship project NextGen on FD-SOI advanced nodes and reports to CEA-Leti’s CEO since then. He is currently the project coordinator of the Chips JU FAMES Pilot Line. Dominique has authored or co-authored more than 100 scientific papers (several best paper awards), book chapters and holds 20 patents.

Panelist

Lèquepeys, Jean-René
Deputy Director & CTO
CEA-Leti

Abstract
Panelist

Biography
Jean-René Lèquepeys received his engineering degree in 1983 from Centrale Supelec and taught physics for 2 years in Ouarzazate, Morocco. He joined CEA in October 1985, in Saclay, within the Central Security Office, in the laboratory for the evaluation of means of detection and intrusion. In 1987, he became the head of the laboratory. In 1993, he was recruited by DSYS, at LETI in Grenoble, as an R&D engineer, in the field of image processing. He then lead projects in the field of "Telecom" at LETI before becoming the head of "Telecom, Communicating Objects and Smart Card" programs in 1999, within the team of Jean-Frédéric Clerc. In 2005, he took in charge the Circuits Design Department at LETI / DSYS, and then created, in partenership with the Ecole des Mines de Saint-Etienne, a laboratory dedicated to electronic components safety analysis located in Gardanne (Paca). In 2010, from the common initiative of both LETI and LIST Directors, he launched DACLE division, relying on original bi-site and bi-institute model, and focusing on Electronic Architectures, Integrated Circuit Design and Embedded Software. He participated in the creation of the Division DCOS (Division of Silicon Components) in 2011, and then lead the division until the end of 2017, when he got back to the head of DACLE division in 2018. In 2000, Jean-René Lèquepeys received the famous award from SEE "Grand Prix de l'électronique Général Ferrié" for his work in the telecommunications field. He is the author of about fifteen patents in this field.In 2019 he was appointed Deputy Director in charge of programs at LETI and Deputy Director of the Director of LETI.

Embedded AI for Ultra Low Power Always-on Smart Imagers

Sicard, Gilles
Researcher
CEA Leti

Abstract
Current megapixel smart imagers, which incorporate computer vision capabilities, exhibit both high acquisition performance and complex real-time image processing at the expense of power consumption incompatible with battery-powered systems because preventing always-on usage. Based on results of two silicon demonstrators, this talk presents our architecture solutions to address this power issue to obtain ultra-low power always-on smart Image sensors. We will focus on our architectural choices to manage the trade-off between power consumption and object recognition capability in term of complexity, versatility and quality. We will discuss also the imager characteristics that have to be upgraded to reach a good algorithmic robustness with respect low power constraints.

Biography
Gilles SICARD received the PhD degree from the Grenoble Institute of technology in 1999. From 1999 to 2014, he was an associate professor with the Joseph Fourier University and he was a researcher with TIMA Laboratory (Grenoble-France). His research work was mainly focused on smart CMOS image sensors. In 2014, he joined CEA-LETI (Grenoble, France) as senior expert in the Image sensor and Display laboratory (L3I Lab.). He leads researches on Smart CMOS imagers using emerging technologies. He is author or co-author of more than 100 papers in international conferences and journals.

Topic Coming Soon

Castelein, Pierre
Parternship manager for visible imaging
CEA/Leti

Abstract
Coming Soon

Biography
Pierre Castelein obtained his engineering degree in electronics from the Institut Supérieur d'Electronique du Numerique (ISEN, France) in 1992 and a PhD in electronics from the Institut d'Electronique et Micro-électronique du Nord (IEMN, France) in 1997. Then he joined CEA-Leti, French technology research institute, global leader in miniaturization technologies enabling smart, energy-efficient and secure solutions for industry, as a characterization and modeling engineer for quantum IR imagers. Starting from 2004, he managed several R&D projects with the French Defense Procurement Agency) involving the design of advanced IR imagers. In 2012, he became coordinator of the joint laboratory between Lynred (global industry leader for advanced infrared imagers covering the entire infrared spectrum). From 2015 onwards, he was in charge of CEA-Leti's strategic partnership in infrared imaging . Since 2021, he is partnership manager for Visible Imaging technologies at CEA-Leti in interaction with STmicrolectronics and several international partners.

Panelist

Kinaret, Jari
Executive Director
Chips JU

Abstract
Panelist

Biography
Jari Kinaret was born in Finland and holds M.Sc. degrees in Theoretical Physics and Electrical Engineering from the University of Oulu in 1986 and 1987, respectively, and a Ph.D. in Physics from the Massachusetts Institute of Technology (MIT) in 1992. Prof. Kinaret has worked in various roles at research institutes and universities in Copenhagen, Denmark, and Gothenburg, Sweden. From 2013 to 2023, he served as the Director of the Graphene Flagship, a one-billion-euro research project dedicated to exploring the potential of graphene. In October 2023, Prof. Jari Kinaret assumed the role of Executive Director at Chips Joint Undertaking (Chips JU), a European public-private partnership that supports research, development, innovation, and future manufacturing capacities in the European semiconductor ecosystem.

From Atoms to Algorithms: European Suppliers’ Technological Race to Stay Ahead in the Semiconductor Market

Grede, André
CTO
Comet

Abstract
The semiconductor industry is accelerating into a new era, where breakthroughs are measured not only in nanometers but in the intelligence of entire systems. From the atomic scale of advanced materials to the power of algorithms in manufacturing and AI, the pace of change is relentless.For European suppliers, the stakes have never been higher. Global rivals are scaling fast, customers are insourcing more than ever, and complexity itself has become the ultimate competitive edge.In this environment, suppliers can no longer rely on products alone. Relevance will come from anticipating what customers need before they ask, being the trusted partner when complexity turns into risk, and unlocking the power of data to create intelligence that shapes the next generation of solutions.Comet’s CTO André Grede will chart the landscape ahead and invite us to rethink how European suppliers can turn today’s pressure into tomorrow’s advantage turning customer trust, early collaboration, and data-driven insight into their strongest competitive advantages.

Biography
André Grede is a seasoned technology leader with a deep background in electrical engineering and a passion for driving innovation in the semiconductor industry. He graduated in Electrical Engineering (Diplom-Ingenieur), specializing in high-frequency technology, from the Berlin Institute of Technology, where he began his career as a research associate in electrodynamics.In 2011, André joined TRUMPF Hüttinger in Freiburg as a Team Leader in R&D, later advancing to Head of the RF Product Development Group. His expertise in radiofrequency (RF) technologies brought him to Comet in 2015, where he served as Vice President of Global R&D and Technology for Plasma Control Technologies. In this role, he shaped the division’s technology and product roadmap for RF subsystems, a cornerstone of modern semiconductor manufacturing.Since 2023, André has been serving as Chief Technology Officer of Comet Group. With his pioneering spirit and forward-looking vision, he is driving the company’s transformation from a manufacturing-centered organization to one that fully integrates software and digital intelligence, positioning Comet as a key partner in the fast-evolving semiconductor landscape.

High-End Dose Management: X-ray Inspection protecting Next-Generation Advanced Packaging

Stickler, Daniel
Director X-Ray Technology & Components
Comet AG

Abstract
As semiconductor devices grow smaller, denser, and more complex, advanced packaging demands inspection solutions that deliver both clarity and care. Traditional X-ray approaches often struggle to balance image quality with sample integrity — a challenge magnified in fragile next-generation packages. Comet Yxlon is changing the game by pioneering real-world dose management studies and introducing next-generation inspection technologies that minimize radiation exposure without compromising resolution. This presentation will explore how advanced dose optimization not only safeguards sensitive components but also unlocks new levels of reliability, speed, and insight for semiconductor manufacturers. By adding intelligent dose control to X-ray inspection, Comet Yxlon is helping the industry move faster, with greater confidence, into the era of heterogeneous integration and 3D architectures.

Biography
Dr. Daniel Stickler is Director X-ray Technology & Components at Comet AG, X-Ray System Division. Based in Hamburg, Germany, he holds a PhD in Physics from the University of Hamburg and has extensive experience in X-ray imaging, semiconductor X-ray applications and product innovations.

Driving Semiconductor Innovation in Europe: How AI-Powered X-ray Inspection accelerates time-to-market

Drolz, Isabella
Vice President Marketing & Product Strategy
Comet AG

Abstract
Behind the semiconductor industry’s rapid advancements lies a powerful yet often overlooked European supply chain. Hidden champions like Comet are redefining what’s possible in advanced packaging through AI-driven 2D and 3D X-ray inspection. By combining cutting-edge imaging with Dragonfly’s intelligent analytics, manufacturers can detect critical defects earlier, optimize yield, and compress development cycles. This talk will highlight how Europe’s specialized ecosystem fuels global competitiveness, why advanced inspection is becoming indispensable for next-generation packaging, and how AI-powered X-ray technology is transforming time-to-market from a challenge into a strategic advantage.

Biography
Isabella Drolz is the Vice President Marketing & Product Strategy at Comet AG, Industrial X-ray Systems Division. She is responsible for Market and Product Management, Global Application Solution Centers, Marketing, and the Academia Program. She oversees the product brands Comet Yxlon and Dragonfly.The division is focused on developing CT and X-ray inspection solutions based on AI, as well as standalone software products for image processing and analysis, serving industries such as semiconductor, electronics, automotive, and research.Isabella holds a degree in Industrial Engineering, a Bachelor of Science in International Business Administration, and an MBA from Southern Nazarene University in Oklahoma City, USA.She has held several management positions in the mechanical and plant engineering industry, where she has driven market-oriented product development. Her strategic leadership plays a key role in positioning Comet’s X-ray and CT solutions to address current and emerging industry demands, especially in semiconductor inspection and advanced packaging technologies.

Leveraging hardware enabled AI image analysis for rapid 3D X-ray

Malin, Joscha
Senior Director Software Product Marketing
Comet AG

Abstract
The global demand for high-end computing power driven by AI, smartphones, IoT applications, high-performance computing, and new mobility applications is constantly rising while facing miniaturization demands. The semiconductor industry is focused on solving this challenge – for example with innovation in advanced packaging. As a consequence, yield and process control as well as the speed of new product introduction continue to gain importance as prototyping and verification costs increase while node sizes decrease. Typical inspection methods like optical or FIB-SEM are, therefore, complemented by advanced non-destructive inspection techniques like 3D X-ray inspection. Ultimately, advanced packaging companies seek non-destructive automated inspection tools which are fast enough to provide value within their production processes, increase yield and reduce waste at an early stage. The speech will show how combining innovation in X-ray hardware with cutting edge AI software can achieve rapid 3D inspection of advanced packaging and highlight how this combination increases the range of application "sweet spots".

Biography
Joscha Malin is the Director of Product Marketing for Software Solutions at the Systems Division of Comet that specializes in supplying X-ray and CT inspection solutions with a particular focus on the Semiconductor R&D and production sectors. In his role, Joscha oversees the division's software product portfolio, with the goal to enhance customer productivity by automation and empower them by data-driven insights derived from X-ray and CT image data. Joscha started his career with an Engineering diploma in Microelectronics from the Technical University Hamburg-Harburg. Over the years, he has worked in multiple roles within R&D in Semiconductor frontend design and system architecture, and within product management, with a consistent focus on image processing solutions.Bernhard Schläppi has a background in experimental physics with a focus on space-born mass spectrometers. He completed his PhD at the University of Bern before conducting research stays in Canada and at ETH Zürich, where he combined table-top XUV lasers with mass spectrometry to study aerosol formation. After joining a startup involved in producing flexible solar cells, he gained exposure to XRF as an analytical tool for semiconductors. In 2017, Bernhard joined Comet X-ray and transitioned into various roles, including Director Testing and Director of Product Development for Comet’s X-ray Module Division. Currently, he serves as a Program Manager for Microfocus X-ray modules, driving new solutions for the semiconductor and electronics markets at the international headquarters in Switzerland.

Innovative Etching Gas Development using Digital Twin

Ichikawa, Natsumi

Daikin Industries, Ltd.

Abstract
Author: Natsumi Ichikawa¹, Hisataka Hayashi¹, Simon Pelz², Julian Rechman²（¹Daikin Industries, Ltd. and ²Daikin Chemical Europe GmbH）In the semiconductor industry, advancing device miniaturization and integration demands improved performance. The stringent requirements for dry etching, crucial to device function, pose technical challenges. As a chemicals manufacturer, we address these with gases, but exploring optimal process conditions (applied power, gas flow rate, pressure) is time-consuming. To approach these issues, we adopted inductively coupled plasma etcher and capacitively coupled plasma etcher mirroring those in the 300mm mass production process. These etchers allow replication of issues using latest pattern wafers from client, alongside the ability to rapidly evaluate multiple gases due to the tool's stand-alone nature and user-friendly gas cylinder replacement. Leveraging this equipment and digital twin technology, we've innovated a method to optimize new gas capabilities. Utilizing Design of Experiments (DOE) and Machine Learning (ML), we've created a precise model predicting etching characteristics (profile and depth). Digital twin technology facilitates virtual experiments to find optimal conditions. In developing a C₄F₈ (GWP: 10300) alternative for the Bosch process, DOE shortlisted 19 conditions from 54. The digital twin, simulating 1960 conditions, identified CH₂=CF₂ (GWP: 0.052) as a promising alternative in a region distinct from C₄F₈'s conditions, achieving optimal results for CH₂=CF₂.To construct a more accurate prediction model, we also focused on plasma physical quantities such as electron and ion density, which represent the plasma state during etching. Unlike traditional ML that uses only process conditions incorporating plasma physical quantities significantly improved model precision. In optimizing conditions where SiO₂ etching rate exceeded 400 nm/min and SiO₂/Si selectivity reached 4 via CF₄ with H₂ incorporation, ion density inclusion, measured via quadrupole mass spectrometry, cut prediction error from 7.4% to 1.9%. These findings, presented at conferences such as DPS2024, are widely acclaimed. Our ongoing mission is to swiftly and effectively contribute to the semiconductor sector by developing new gases and process conditions using digital twin technology.

Biography
Natsumi Ichikawa is currently a chemical researcher at Daikin Industries. She holds a Master's degree in Catalytic Chemistry. She has strengths in synthetic and complex chemistry. Currently involved in semiconductor dry etching process, speciallizing Bosch Process and digtal twins.

Optimizing water usage footprint: Direct water recycling from abatements

Osten, Pascal

DAS Environmental Expert GmbH

Abstract
As semiconductor manufacturing advances, exhaust gas treatment systems—particularly point-of-use (POU) abatement units—play a vital role in maintaining safe and stable operation. These systems often rely on water to manage byproducts generated during gas treatment. By rethinking how this water is managed and treated, new opportunities arise to reduce overall water consumption without compromising process integrity. This presentation explores how aligning gas and water treatment at the POU level enables significant water recycling, with fresh water savings of over 90% achievable through targeted strategies.Our work focuses on enhancing water reuse by introducing a tailormade particle removal system installed directly after the abatement POU. This system is designed to address process-specific particle loads, which can otherwise limit recirculation potential. By removing these particles efficiently, the treated water becomes suitable for reuse within the same abatement units—creating a closed-loop solution tailored to the demands of the gas treatment process.This approach builds on field observations across multiple fabs and process types, where we observed that particle characteristics in abatement wastewater are closely linked to the upstream semiconductor processes. Recognizing this dependency, we have developed a flexible particle separation solution that can be adapted to different tool sets and chemistries. Early application of this system has shown that water quality can be stabilized sufficiently to support continuous reuse, while maintaining abatement performance and reliability.In addition, we address the issue of salt accumulation, a common challenge in high-recycle environments, through conductivity-based monitoring and control strategies. This ensures long-term operational stability even as recycling rates increase.This presentation highlights the potential of integrating gas and water treatment strategies in a purposeful way. Rather than viewing abatement systems as isolated water consumers, they can be transformed into platforms for water efficiency through the application of process-informed treatment technologies. A key takeaway is the importance of considering wastewater characteristics early in fab planning and collaborating with treatment technology providers to enable point-of-use or semi-centralized recycling concepts.

Biography
Pascal Osten is a German engineer currently serving as Technical Director for Global Water Treatment at DAS Environmental Experts GmbH.Born in Berlin, he studied physics and water management in Dresden, earning a degree in engineering.He began his professional career at wks Technik GmbH, working as a project engineer in environmental engineering for water and wastewater treatment facilities. During his time there, he contributed to several research and development efforts, some of which resulted in patent applications.Over the years, he took on increasing responsibilities, including leading a team in process engineering. In this role, he supported the successful implementation of a variety of customer projects, focusing on practical, reliable solutions.Today, at DAS Environmental Experts GmbH, Pascal draws on his hands-on experience in water treatment to support the development and execution of sustainable solutions for the semiconductor industry and beyond. He remains committed to advancing technologies that balance performance with environmental responsibility.

Leveraging Virtual Twins and AI/ML in semiconductor industry using 3DEXPERIENCE platform

Joshi, Smriti
Senior Manager Technical Solution - Semiconductor Industry
Dassault Systèmes

Abstract
Semiconductor companies optimize every stage of their operations—from research and chip design to production and supply chain—by leveraging a combination of multi-scale virtual twins and artificial intelligence. It helps reducing, downtime, enhance scalability, and improve resource efficiency, contributing to sustainable design and production practices.In this talk, we will present different virtual twins and AI/ML experiences for semiconductor industry. We will present how it can visualize, model and simulate the entire environment of sophisticated experience on a single platform known as 3DEXPERIENCE. This platform facilitates sustainable business innovation across the full product lifecycle from materials to process to equipment to fab virtual twins.Virtual twins replicate physical objects just like digital twins do, but they take it further, simulating the processes and interactions within an entire system or ecosystem. This could be a game-changer for the semiconductor industry and beyond, offering a more holistic approach to understanding and solving complex challenges. By incorporating real-world data in real-time, virtual twins can support various stages of semiconductor development, from product introduction to end-of-life, by optimizing and streamlining design, manufacturing, and testing processes. It can also accurately model and predict electrical and thermal behavior, and mechanical performance characteristics of the semiconductor device using simulation virtual twins. These simulations can be used to fine-tune designs for optimal performance. Simulation plays a significant role in the virtual twin, allowing companies to test product designs virtually, avoiding the need for costly prototypes. This accelerates development and ensures higher product performance. Additionally, simulation virtual twins can be used to predict real-world performance and understand failure modes, leading to design improvements over time.Along with creating virtual twins, it is very important to have AI-driven chip design and analysis. AI in chip design involves using artificial intelligence techniques, particularly machine learning, to improve the design, verification, and testing of semiconductor devices.

Biography
Smriti is currently working as a Technical Solution Senior Manager for Semiconductor Industry (High-tech) with Dassault Systèmes. She is responsible for understanding, consolidating and driving semiconductor technical solutions. She develops new solutions and provide enablement worldwide for semiconductor customers. She has over 14 years of R&D experience working with different foundries ST Microelectronics, Altis Semiconductor, X-FAB and research lab like CEA –LETI and Lip6 (U.P.M.C.).She received her Doctoral (Ph.D) degree in Nanoelectronics and Nanotechnolgy from INP Grenoble (France) in 2013.

Empowering Next-Gen Semiconductor Innovation with the 3DEXPERIENCE Platform

Rei, Manuel

Dassault Systemes

Abstract
The semiconductor industry plays a pivotal role in enabling the adoption of new technologies and addressing bottlenecks in their implementation. This industry is currently experiencing rapid growth and technological innovation, driven by increasing demand in sectors such as AI, automotive (especially electric and software-defined vehicles), 5G, and consumer electronics. The complexity of advanced technologies needs the collaboration across the entire ecosystem, from materials and equipment suppliers to design and manufacturing partners. This collective effort drives innovation and ensures that the increasing demands of the digital world are met. This type of collaboration goes beyond the semiconductor fab, bringing together designers, OEMs, and foundries—all of whom gain from a platform that offers distinct value.In this talk, we introduce a model-based systems engineering approach-based platform i.e; 3DEXPERIENCE platform. It addresses key challenges in semiconductor development by enabling the design and manufacturing of complex, multi-domain chips through cloud collaboration, virtual twin simulations, and streamlined workflows. This comprehensive platform helps overcome growing design complexity, silos, and supply chain inefficiencies—ultimately supporting faster innovation, improved performance, and reduced time-to-market for next-generation semiconductor solutions.

Biography
Manuel REI - Semiconductor Industry Solution Experience DirectorManuel joined Dassault Systèmes in 1986 and has over 35+ years of experience supporting high-tech and automotive global companies, including relocations in South Korea and USA for the deployment of Dassault Systèmes solutions within Samsung Electronics, LG Electronics and IBM hardware divisions.He leads High Performance Semiconductor Industry Solution Experience, leveraging virtual twins to turn semiconductor complexity into business profitability , and deployed at customers such as NXP, Broadcom, Samsung Electronics, Qualcomm and STMicroelectronics.

Adhesives for highly efficient optical coupling of Photonic Integrated Circuits

Hartwig, Alexander
Senior Strategic Business Development Engineer
Delo Industrial Adhesives

Abstract
The emergence of 5G technology and artificial intelligence (AI) has significantly accelerated the demand for high-speed data communication, leading to the development of advanced packaging solutions such as 2.5D/3D packaging for AI applications. Silicon photonics packaging has emerged as a promising alternative to traditional copper-based electronics, offering faster data transmission with lower power consumption.Yet, the packaging of photonic integrated circuits (PICs) still faces challenges in achieving high performance and reliability. Key hurdles include the need for precise optical coupling with minimal loss, as well as maintaining reliability through reflow processes and environmental stress.Adhesives are crucial in overcoming these challenges at various stages of the packaging process. Understanding the necessary properties of adhesives - such as bond strength, optical transmission, and resistance to environmental stresses - is critical for successful packaging applications.This presentation explores active alignment strategies for optical coupling involving the use of adhesives. It discusses methods such as direct butt-coupling of fiber array units (FAUs) to PICs, surface coupling, and employing microlens arrays (MLAs) that allow for more relaxed alignment tolerances. Emphasis is placed on the adhesive requirements needed to ensure efficient coupling.Experimental data on coupling efficiency, tested under conditions like reflow and 85°C/85% relative humidity, are presented to demonstrate these approaches' robustness. These findings underscore the crucial role of adhesives in enhancing the performance and reliability of advanced photonic systems.Moreover, a novel approach will be presented, that preserves optical properties following wafer-level processing steps, such as sawing and grinding, by selecting materials with distinctive optical characteristics.

Biography
Dr. Alexander Hartwig, who holds a PhD in Physics, is a seasoned professional in the fields of solid state physics and adhesive technology. He is currently a Teamleader for Business Development Engineering at DELO Industrial Adhesives, where he focuses on developing innovative adhesive solutions for various applications.With many years of industry experience, Dr. Hartwig combines his deep scientific knowledge with practical engineering skills to support business growth and technological advancements. His expertise makes him a valuable voice at industry conferences and events, where he shares insights on the latest trends and developments in adhesive technology.

Single Point of Failure: High Purity Quartz at the Heart of Global Chipmaking

Haus, Reiner
Managing Director
Dorfner Anzaplan GmbH

Abstract
High purity quartz (HPQ) is the basic raw material to produce quartz glass, used in a wide variety of semiconductor manufacturing, such as diffusion and etching processes, photolithography and silicon monocrystal growth. The current industry structure is dominated by a very limited number of quartz suppliers and the global supply is dependent on very few deposits concentrated near the village of Spruce Pine, North Carolina. This high dependence of the semiconductor industry on a single region has introduced significant risks related to geopolitical tensions, supply chain fragility, and increasing cost pressures.Geopolitical Risks: Trade tariffs, export bans, and supply rationing are becoming significant concerns for non-U.S. consumers.Single-Source Fragility: Past disruptions, including COVID-19 logistics challenges (2020–2022), and Hurricane Helene (2024), highlight the need for diversification.Market Control: Limited number of competitors follow a pricing strategy that limits competition and innovation.Sustainability and ESG Pressures: Increased regulatory requirements and sustainability expectations necessitate above-inflation price increases to maintain compliance.At Anzaplan unique experience in HPQ processing and plant design gained over the last 30 years and in over 100 HPQ projects considering independent impurity profiling, resource estimation, flowsheet optimization, ESG/LCA support, pilot processing, plant engineering, feasibility studies and vendor qualification can turn risk into a managed program.Thus, the presentation will highlight the operational and commercial risks along with the Hurricane Helene event and offers a practical de-risking playbook by dual-sourcing, strategic inventory, resilience clauses, accelerated qualifications, circularity, and supplier building, to help European fabs turn a hidden bottleneck into a managed advantage.

Biography
For decades Dr. Haus’ focus is on specialty minerals and rare metals with a strong academic background in Engineering Geology and Mineral Processing. After his PhD he held senior research manager positions at Karlsruhe Institute of Technology (KIT), Germany and Massachusetts Institute of Technology (MIT) in Boston, Mass.In 2000 he was appointed managing director and in 2010 became shareholder of Dorfner Anzaplan GmbH, a leading independent analytical, consulting and engineering firm in critical minerals and metals based in Germany with projects globally. Dr. Haus completed his EMBA in 2005 and recently became chairman of Anzaplan UK, a 100% subsidiary of Anzaplan in Germany.

Topic Coming Soon

Heger, Tim
President Semiconductor Chamber Solutions Division
Edwards Vacuum

Abstract
Coming Soon

Biography
Tim Heger joined Atlas Copco Group in 2020 in the product company Leybold in Cologne as a Process Development Manager and has since then built a successful career within the Group. In 2023 he was appointed General Manager of Ceres Technologies based in the USA and prior to this he held a variety of positions within operations, supply chain and product management. Tim, a German citizen, will be based in Burgess Hill, UK and will relocate over the next few months. He holds a Master of Science in Mechanical Engineering from the University of Applied Science in South Westphalia, Germany.

A Novel Approach for the Volume Production of Wide-Bandgap Semiconductor

Barbar, Ghassan
Sales Director
ELEMENT 3-5 GmbH

Abstract
In this work we describe another epitaxial process. Here we present data of aluminum nitride (AlN), graphene interlayers and of SiC on AlN thin films on sapphire and of epitaxial growth of SiC on SiC grown by Next Level Epitaxy (NLE). The new process is using a surface temperature around 250°C by combining PVD (physical vapor deposition) and CVD (chemical vapor deposition). The growth procedure in NLE is similar to the MOCVD growth process with substrate cleaning, start layer and main layer. Compared to the reactive sputter processes and pulsed sputter epitaxy the NLE uses different plasma sources in various combinations.The NLE system is a homemade novel deposition system. In the current configuration, it has a capacity of up to 70 x 200 mm wafer at one time. As Al-source pure Al was used. As nitrogen source nitrogen gas, as Si-source silane and as carbon source for graphene and SiC methane which were introduced by a homemade ion gun. Additionally, argon, oxygen and hydrogen were used. During the process the surface temperature of the wafer was kept around 250°C. The used plasma sources are all designed as stripe sources. The wafer is placed on the carrier which is moving front and back in the growth chamber under the stripe sources. First the substrates were cleaned with a mixture of argon and oxygen and after with argon and hydrogen using the plasma. After the in-situ cleaning first a monolayer of aluminum was deposited followed by low plasma power and low growth rate AlN and after higher plasma power and higher growth rate AlN. The graphene layers were used as interlayer sandwiched between AlN and were compared with AlN grown in one step with the same total growth time. The experiments for SiC growth started recently. As seed for the SiC growth NLE-AlN on sapphire was used. Since AlN is counted as 2H-AlN it can act as seed for 2H-SiC and 4H-SiC.

Biography
Ghassan Barbar (Sales Director) received the chemical engineering degree from the university of Applied Science, Berlin, Germany in 2001. In 2022 he took over the position of sales director at ELEMENT 3-5 GmbH with a special focus on the product management for the ACCELERATOR 3500K. Prior to this, he worked as an independent consultant in the semiconductor industry. Before that, he joined Ebner Group in 2011 and held several roles within the sapphire department (FAMETEC) In 2018, he built up within the group SiC crystal growth division, which is a spin-off company (EEMCO) since 2020. Before that, he worked at AIXTRON in R&D for development of high-k and metal gate for CMOS applications by CVD/PECVD. Ghassan holds over 15 patents in crystal growth of Sapphire and SiC.

Microelectronic solutions for ultra low current – low noise - high bandwidth nanopore sensing

Thei, Federico
CEO & Founder
Elements srl

Abstract
Solid-state nanopores, nanoscale apertures fabricated in silicon-based membranes, represent a promising breakthrough in next-generation biosensing technology. As analytes pass through nanopores, they generate weak electrical signals—unique current fingerprints that can be used for precise molecular identification. Capturing these signals without sacrificing sensitivity or bandwidth presents a significant microelectronic challenge.ELEMENTS SRL, an Italian company specializing in ASIC design for ultra-low current sensing, addresses this challenge by developing high-precision electronic systems capable of measuring currents in the sub-nanoampere and picoampere range. Their portfolio includes both turnkey instruments and OEM solutions tailored to demanding sensing applications.As a technology partner for imec’s solid-state nanopore system development, ELEMENTS provides the electronic infrastructure enabling high-throughput, high-bandwidth current sensing and real-time data processing for single-molecule protein sequencing.This presentation will explore the key design strategies and challenges in CMOS microelectronics for nanopore applications, focusing on low-noise analog front-ends, wide-bandwidth performance in the MHz range, and scalable data acquisition systems. We will highlight how optimized electronic design can unlock the full potential of nanopore technology for early disease detection and proteomic applications, paving the way for faster, more accurate molecular diagnostics.

Biography
Dr. Federico Thei is CEO and Founder at Elements srl (Italy) since 2014, responsible for strategic business development, new products concept design and industrial partnerships building, focusing on enabling nanopore technology to industrial applications.Graduated in Telecommunication Engineering in 2007, he received the Ph.D. in Information and Communication Technologies in 2011 at the University of Bologna, Italy, with a research activity focused on low noise microelectronics systems for nanopore and biosensors readout.He was visitor Ph.D. student at the University of Southampton (UK), University of Twente (NL) and several EU Companies in the electrophysiology field. For four years he was assistant professor for the electronic engineering course “Electronic digital systems” at the University of Bologna.He attended in 2015 the Technology Venture Launch Program Express in Menlo Park, Silicon Valley, winning the final pitch competition. In 2018 he attended The Business side of Biomedical Start-ups course at the University of Bocconi, Milan. In 2025 he received the American Innovation prize from the Italian – USA foundation.Coauthor of patents and papers in the microelectronic and nanopore field, he builds strong partnerships with Companies and research centers across the world, like EPFL, IMEC, Stanford NF, Bosch, offering the most advanced microelectronic solution for low noise and high bandwidth nanopore readout.

Optimizing Fab Performance: Proven Strategies from Materials to Manufacturing

Amade, Antoine
President Europe and the Middle East (EMEA) Region
Entegris

Abstract
In a world of rising complexity, speed, and billion-euro investments, fab startups face unprecedented pressure. Our presentation outlines key strategies for effective contamination and material management, and shares concrete, experience-based insights to support fab ramp-up and operational efficiency. With a focus on risk mitigation, digitalization and data sharing, environmental responsibility and workforce training, we provide proven and innovative solutions from specification definition to startup and beyond.

Biography
As president of the Europe and the Middle East (EMEA) region at Entegris, Antoine Amade is responsible for driving regional strategies and leading efforts to expand into markets that can benefit from Entegris’ unparalleled expertise in advanced purity and materials solutions. These include sectors such as semiconductor, desalination, clean hydrogen energy, and other high-tech and data-intensive industries.With 30 years of experience at Entegris, Mr. Amade has held leadership roles in gas and liquid microcontamination market management, strategic account management, and regional sales management. He has also held business management positions overseeing the market in North America.He holds a degree in Chemical Engineering from ENS Chimie Lille and is an active member of the SEMI Electronic Materials Group and the Global Automotive Advisory Council for Europe.

Smart Eyewear and Augmented Reality: State of the Art and Future Challenges

Ongarello, Tommaso
Smart Eyewear R&D Manager
EssilorLuxottica

Abstract
Smart eyewear has emerged as a pivotal technology in the evolution of augmented reality (AR), merging advanced optics, sensor integration, AI capabilities, and wearable ergonomics into a single, user-centric platform. This talk will provide an overview of the current state of the art in smart eyewear, including leading-edge developments in display technologies (waveguides, microLEDs, holographic optics), optical combiners and integration into the smart eyewear, as well as the future challenges that must be addressed to fully realize the potential of AR eyewear.

Biography
Tommaso Ongarello is an Italian physicist and researcher specializing in smart eyewear technologies and photonics. He currently serves as the Smart Eyewear R&D Manager at EssilorLuxottica, where he leads research and development initiatives focused on integrating digital technologies, bioengineering, and artificial intelligence into next-generation eyewear. Ongarello holds a Ph.D. in Physics and has a strong academic background, with research contributions in areas such as computer-generated holography and light–matter interactions. He has co-authored several scientific publications, including studies on wearable EEG devices and augmented reality applications. In collaboration with Politecnico di Milano, Ongarello helped establishing the EssilorLuxottica Smart Eyewear Lab in Milan. This joint research center aims to bridge the gap between academia and industry by fostering innovation in smart eyewear through interdisciplinary research

Public funding opportunities for the semiconductors industry in the EU

Isabelle, Marc
CEO & Founder
European economics

Abstract
The semiconductors industry is among the highest beneficiaries of public funding in the EU. Grants target R&D activities, first industrial deployment of breakthrough innovations and first of a kind manufacturing facilities. Securing such State aid and EU funding is a highly competitive process which requires a thorough understanding of the numerous opportunities and associated regulations. Based on several use cases, Marc Isabelle’s presentation will provide a valuable first dive into public funding opportunities for the semiconductors industry in the EU.< !-- notionvc: 139424bf-38c6-4d92-998a-7b884f187abe -- >

Biography
Marc ISABELLE, engineer & PhD in Economics, is the founder and CEO of european economics.Marc is a recognised expert in the public funding of strategic projects. Since 2009, he has helped 195 companies secure €43 billion in public funding for 250 major projects. These initiatives tackle key societal challenges - including disruptive innovation, decarbonisation, resilience and infrastructure - across a wide range of industrial sectors including microelectronics, software, telecoms, automotive, energy and environment, batteries, pharmaceuticals and biotech.Through his extensive work with the European Commission and national authorities, Marc has actively contributed to shaping the methodologies and best practices used to assess public funding applications and their compatibility with EU regulations.< !-- notionvc: f61cd834-db23-4b2f-9109-57db7fb89455 -- >

Strengthening Europe’s Semiconductor Ecosystem: The Role of ESMC

Koitzsch, Christian
President and Managing Director
European Semiconductor Manufacturing Company (ESMC)

Abstract
As Europe intensifies its efforts to strengthen its technological sovereignty and resilience, the establishment of ESMC – a joint venture of TSMC, Bosch, Infineon and NXP – in Dresden marks an important milestone for the continent’s semiconductor industry. With this €10 billion venture, the company not only builds one of Europe’s largest and most advanced semiconductor fabs but also creates a vibrant hub for semiconductor talent and innovation. Global collaboration stands at the core of this initiative: Its success is the direct result of the joint efforts of numerous companies and sets new benchmarks for partnership and sustainability – from pioneering green energy and resource efficiency to engaging with industry, academia and local communities. In this way, ESMC helps pave the way for a resilient, future-ready European ecosystem where innovation and sustainability thrive.

Biography
Dr. Christian Koitzsch has been the president and managing director of the European Semiconductor Manufacturing Company (ESMC) since beginning of 2024. He was raised in Thueringia, is married and is father of two children. He studied Electrical Engineering at Technische Universität Ilmenau and North Carolina State University in Raleigh (US) and received a PhD in solid state physics from the University of Neuchâtel, Switzerland.

Photonic Integrated Circuits (PIC) – Unique PVD solutions helping turn cost effective high volume manufacturing into reality

Tschirky, Maurus
Senior Manager Strategic Marketing, VP
Evatec AG

Abstract
The growing need for Photonic Integrated Circuits requires breakthroughs in manufacturing in order to go into high volumes. While various deposition technologies are state-of-the-art in institutes and R&D, the industry needs scalable and robust solutions to fulfill the demands given by the massive increase of computation and communication.Evatec – The Thin Film Powerhouse – has a long history in both Semiconductor and Photonic Industries and is able to combine the best of these worlds.By analyzing the materials of interest and evaluating their desired properties, we are able to combine specific tool features and material behaviors and offer PVD-solutions for most of the common materials used for active and passive building blocks of PICs. Waveguides from Silicon Nitride and Aluminium Nitride as well as modulators from Lithium Niobate and Barium Titanate can now be deposited reliably in high volumes on industry-proven platforms for substrates up to 300mm.

Biography
Maurus Tschirky is Senior Strategic Marketing Manager and Vice President at Evatec. He is globally responsible for Strategic Marketing and Business Development across the entire portfolio of market segments. His genuine interest in deposition technology and its applications for more than Moore typologies emphasizes his dedication to the 3D Heterogeneous Integration market in particular. Over 20 years, Maurus had a number of positions in the PVD-equipment industry (Balzers, Unaxis, Oerlikon and now Evatec) ranging from Application Engineer, System Engineer, Project Manager to Product Manager over the years and also spent 3 years leading a research section at CSEM in Landquart, Switzerland. He has a first Degree in Control Electronics from the University of Applied Sciences in Buchs, followed by a Master in Business Engineering / International Marketing from the Hochschule für Wirtschaft und Technik in Zurich, Switzerland.

High-Resolution Inspection of Hybrid Bonds, Microbumps, and TSVs - Are X-ray Methods Ready for the challenges of Advanced Packaging?

Hansson, Björn

Excillum AB

Abstract
The push for higher performance, lower power consumption and smaller form factors combined with lower cost per function is driving the shift from 2D scaling to heterogeneous integration and advanced packaging methodologies. As advanced packaging grows in complexity, ensuring the yield and reliability of the intricate interconnects becomes increasingly challenging, necessitating the requirement for improved high-precision inspection methods from off-line failure analysis to at- and in-line inspection. X-ray nano-computed tomography (nano-CT) and X-ray laminography addresses this challenge by offering 3D X-ray imaging with sub-micron resolution, enabling precise visualization of critical internal features.While traditional X-ray imaging has been limited by resolution and throughput constraints, recent breakthroughs in nano-focus X-ray sources now enable true sub-micron 3D inspection at improved measurement times. X-ray imaging techniques must however always balance resolution, speed and if any sample preparation can be performed. To illustrate these enhancements this communication present case studies from two different cutting edge devices.First a comprehensive 3D X-ray imaging evaluation of an HBM memory stack connected by ~20 µm microbumps was performed. Using nano-CT, we demonstrate that a 30-second scan provides sufficient resolution for initial structural assessment—from redistribution layers (RDLs) and vias in the substrate and interposer to the intricate micro-bumps within the stack. By increasing scan time, more detailed features—such as voids and internal defects—can be revealed. For non-destructive inspection of full-sized packages, X-ray laminography offers significant advantages. Here we demonstrate laminography scans of the HBM microbumps acquired in just a few minutes and discuss the benefits and trade-offs of longer exposure times on image quality and resolution.Second, in addition to HBM microbumps, we present measurements from an AMD Ryzen 7 5800X3D processor, featuring hybrid copper bonding with 1.5 µm vias at 9 µm pitch. Here, individual bond pads are clearly resolved, enabling analysis of planarity information that typically has seemed to difficult for 3D X-ray imaging.Together, these results highlight that X-ray nano-CT and laminography are now practical, high-value tools for R&D, failure analysis, and yield ramp-up in advanced packaging.

Biography
Björn Hansson has been working with advanced X-ray sources at Excillum AB since 2011, serving as Director of Sales and Marketing, CEO and now CTO. Prior to Excillum AB, Björn was involved in early development of laser plasma sources for EUV lithography at the Royal Institute of Technology in Stockholm, as a Co-Founder of Innolite AB and finally as a Senior Scientist at Cymer, Inc. (now ASML). He holds a Ph.D. in applied physics from KTH Royal Institute of Technology, Stockholm.

Topic Coming Soon

Blaschitz, Herbert
Executive VP of Advanced Technology Facilities
Exyte

Abstract
Coming Soon

Biography
Herbert Blaschitz, Executive VP of Advanced Technology Facilities at Exyte, is a recognized leader in the semiconductor industry. He has played a pivotal role in the profitable expansion of Exyte’s semiconductor business, growing it from 1 billion euros in 2014 to over 6 billion euros in 2023.Before joining Exyte, he held various positions at Jenoptik, Asyst, and Siemens Semiconductor (now Infineon). Originally from Austria, Herbert has lived and worked in Germany, France, the USA, and currently resides in Singapore.Herbert Blaschitz earned a degree in electrical engineering from HTBL of Klagenfurt, Austria, and a degree in business administration from GSBA in Zurich, Switzerland.

EYE2DRIVE: Redefining Vision Sensors for Dynamic Environments with Native HDR Technology

Vatteroni, Monica
CEO
EYE-TECH srl

Abstract
Vision sensors are at the heart of automotive, industrial, and mobility applications — yet they often face a critical trade-off between dynamic range, image quality, and robustness under non-ideal lighting. Traditional High Dynamic Range (HDR) approaches, based on multi-exposure fusion or logarithmic pixels, suffer from inherent limitations such as motion artifacts, flickering, and degraded signal-to-noise performance.EYE2DRIVE introduces a paradigm shift in vision sensing through an innovative, patented pixel-level technology that enables native single-frame global shutter HDR. At the core of the sensor is a linear pixel architecture combined with a smart conditioning circuitry, capable of adjusting the charge discharge and pixel sensitivity dynamically in response to real-world light conditions. This behavior mimics the adaptability of the human eye — without requiring multiple exposures or multi-gain architectures, dedicated processing, or non-standard CMOS processes.The result is a sensor that delivers:- High-quality HDR images with no post-processing- No flickering or motion-induced artifacts- Full compatibility with existing global shutter architectures- Ease of integration using standard CMOS flowsThis talk will provide a technical insight into the sensing principle, alongside a broader perspective on applications, integration roadmap, and market relevance. From autonomous driving to in-cabin monitoring and beyond, EYE2DRIVE is designed to address the most critical challenges of vision under extreme and variable lighting — enabling new levels of safety, performance, and flexibility in embedded vision systems.

Biography
Monica Vatteroni is CEO and CTO of EYE-TECH, the company behind the EYE2DRIVE brand — an innovative vision sensing solution that delivers native high dynamic range (HDR) imaging with unmatched adaptability under challenging and fast-changing lighting conditions.She holds a Master’s degree in Electronic Engineering and a PhD in Physics, and brings over 20 years of experience in CMOS image sensor design, microelectronics, and innovation leadership. Monica is the primary inventor of the patented technology that powers EYE2DRIVE — a novel architecture enabling single-frame, real-time HDR at the pixel level, overcoming the limitations of traditional HDR approaches such as motion artifacts, flicker, and post-processing needs.Her career spans both academic research and industrial development, with positions across the medical, industrial, and semiconductor sectors. From 2015 to 2016, she was a Postdoctoral Fellow at Université Claude Bernard in Lyon, working on a Marie Skłodowska-Curie Starting Grant project. Prior to that, she spent several years at the Biorobotics Institute of Scuola Superiore Sant’Anna, contributing to image sensors, vision systems, and sensorized platforms for biomedical applications. During the same period, she also collaborated with Eurotech S.p.A. and STMicroelectronics on CMOS image sensing technologies.From 2002 to 2008, Monica worked at NeuriCam, an SME in Trento, where she was responsible for the analog design and later the full development of intelligent CMOS cameras.She is the author or co-author of over 30 scientific publications in peer-reviewed journals and international conferences, and holds nine international patents in the field of image sensing.At EYE-TECH, she leads a multidisciplinary team committed to developing bio-inspired, highly adaptive vision systems for automotive, industrial, and embedded applications — transforming research-driven innovation into scalable, real-world solutions.

Capture Images with Perfect Vision - Breaking Through the Color Filter Limits with Color Splitting

Hoet, Jeroen
CEO
Eyeo

Abstract
For over five decades, the core mechanism behind color photography has remained largely unchanged. At the heart of nearly every CMOS image sensor lies the Bayer color filter array—a grid of red, green, and blue filters that allows silicon-based sensors to interpret color. Using this mosaic of RGB filters to capture color, each pixel is covered by a red, green, or blue filter, meaning that only one-third of the incoming light contributes to any given pixel’s signal. As a result, roughly 70% of photons are discarded before ever reaching the photodetector. This inefficiency leads to lower signal-to-noise ratios (SNR), a perpetual Achilles’ heel for smartphone and compact camera users.Now, a new frontier in imaging is emerging. New nanophotonic color splitting technology guides, rather than filters, light into sub-diffraction-limited waveguides. This innovative solution eliminates the inefficiencies of Bayer-based systems and unlocks a new era of ultra-compact, high-resolution, and light-hungry cameras across smartphones, XR, industrial inspection, and medical diagnostics.This session will discuss this innovation that replaces the Bayer filter entirely with a nanophotonic waveguide layer that splits light based on its wavelength and directs it to the appropriate pixel. Rather than absorbing unwanted wavelengths, this system uses vertical waveguides designed to separate colors, guiding photons with minimal loss and maximal resolution.

Biography
Jeroen Hoet is co-founder and CEO of the disruptive image sensor startup, eyeo, which develops a breakthrough imaging approach to unlock maximum light sensitivity and unprecedented native color fidelity for image sensors used in mobile devices, industrial systems, XR and more. As former entrepreneur in residence at imec, he successfully led the transition of a research-stage photonics technology into a compelling vision and business opportunity, paving the way for the launch of eyeo in 2024. Jeroen has extensive technical and business experience in the imaging and semiconductor industries with roles in engineering, marketing and executive management at companies such as Caeleste, KLA, and ICsense. He earned a master’s degree in engineering with a focus on microelectronics at Ghent University and an executive MBA from Vlerick Business School.

Practical Path to Autonomy: How AI Planning & Scheduling Transforms Today’s Fabs

Potter, Jamie
CEO & Cofounder
Flexciton Ltd

Abstract
Abstract will be provided soon

Biography
In 2016, Jamie co-founded Flexciton with a vision of transforming industrial and complex manufacturing sectors with AI and advanced optimisation technology. As CEO, he guided the company's cutting-edge solution from initial concept through development, testing, and successful commercial deployment within the semiconductor industry. Under his leadership, Flexciton transitioned from its first client implementation to serving numerous customers across the US, Europe, and Asia.Jamie oversaw the expansion of Flexciton's product offerings from short-term scheduling to the comprehensive Autonomous Technology suite designed for complex manufacturing environments. Beyond his role at Flexciton, Jamie is a founding member of the SEMI End-to-End Smart Manufacturing initiative and has represented the UK deep tech sector in high-level engagements, including meetings with the UK government at Downing Street. He is a top-ranked Oxford University graduate in Mathematics and Statistics and was named to the Forbes 30 Under 30 list in 2018.

Sovereignty Comes from the Strongest Link in the Chain: Why Europe's technological strategy should be all in on areas of comparative advantage

Bithell, Ed
Head of Strategy and Sovereign Partnerships
Fractile

Abstract
Technological sovereignty is often discussed in maximalist or minimalist terms, either demanding an entire onshore manufacturing chain or simply stockpiles of end products that rapidly become obsolete. Neither is a credible strategy for Europe: what we need is to focus on areas of competitive advantage which give strategic leverage in the long term, combined with wise partnerships overseas.The strategic focus should thus be on parts of the supply chain that are ideally placed to maximise value and technological advantage in Europe, without leaning on inputs that are more expensive here. Fabless manufacturing is such a case, with AI making advanced semiconductors more strategically vital than ever before. If Europe succeeds in cutting edge innovation in these areas, the resulting technological advantages will enable global collaborations where Europe is a vital player, boosting European prosperity and resilience.

Biography
Ed Bithell is Head of Strategy and Sovereign Partnerships at Fractile. Prior to this, he was a UK civil servant and diplomat, as well as a policy analyst for emerging technologies such as semiconductors. Fractile is building the hardware needed to unlock colossal scaling of frontier AI inference compute. The company’s custom silicon and software ecosystem is built around delivering hundreds of times faster access to memory, in turn allowing for extremely low inference latency while maximising throughput and minimising cost.

Panelist

Kutter, Christophe
Director
Fraunhofer EMFT

Abstract
Panelist

Biography
Christoph Kutter is director of Fraunhofer EMFT, an institute of the Research Fab Microelectronics Germany (FMD), of which he is currently co-spokesperson. He also holds a professorship specializing in solid-state technologies at the University of the Federal Armed Forces in Munich. His focus at Fraunhofer EMFT is on silicon technologies, MEMS, flexible electronics, biosystem integration and heterogeneous integration of various solid-state technologies. Christoph Kutter is currently Vice President of the VDE (Association for Electrical, Electronic & Information Technologies), a member of acatech (National Academy of Science and Engineering) and the BBAW (Berlin-Brandenburg Academy of Sciences BBAW). From 1995 to 2012, Christoph Kutter held various management positions at Infineon Technologies AG and Siemens AG, including Head of Communications Product Development, Head of Chip Card Development and Head of Central Research. Christoph Kutter was responsible for several central improvement projects to increase efficiency in research and development as well as for the management of the company-wide innovation initiative. From 1990 to 1995, Christoph Kutter worked as a research assistant at the High Magnetic Field Laboratory (Max Planck Institute for Solid State Physics) in Grenoble, France. Christoph Kutter received his Dipl. Phys. from the Technical University of Munich and his Dr. rer. nat. from the University of Constance in 1995.

Sustainability@Fraunhofer – Semiconductor Innovation for a Better World

Weinreich, Wenke

Fraunhofer IPMS

Abstract
This presentation highlights Fraunhofer’s commitment to sustainability, with a particular focus on pioneering initiatives in the semiconductor sector. We begin with a brief introduction to the Green ICT project, showcasing Fraunhofer’s contributions to the development of environmentally responsible information and communication technologies. The core of the presentation centers on the ongoing GENESIS project, in which Fraunhofer plays a key role across multiple work packages and leads Work Package 4 – Minimization of Waste and Emissions. GENESIS aims to advance sustainable innovation in semiconductor manufacturing by integrating resource-efficient processes and circular economy principles. We will present the activities and key achievements within WP4, providing insights into collaborative strategies and technological advancements that are shaping a more sustainable future for the semiconductor industry.

Biography
Dr. Wenke Weinreich joined Fraunhofer Center Nanoelectronic Technologies for PhD on new high-ks for DRAM in 2006. Since 2011, she worked as a senior scientist at Fraunhofer IPMS in the division CNT and continued the development of new high-k materials as well as their integration in MIM capacitors for memories and passive devices. Since 2016 she headed the group Energy Devices dealing with CMOS integrated Si-capacitors, Li-Ion batteries as well as piezo-, pyro- and thermoelectric energy harvesting and sensor concepts. Since 2019, she was heading the business unit IOT Components & Systems within CNT combining activities like low power sensors, power management, nanopatterning and RF as well as AI processors. Since 2020, she is director of the division CNT which combines three business units Next Generation Computing, Emerging Memory Solutions and IOT Components & Systems as well as a 300 mm cleanroom infrastructure. Since 2021, she is also deputy director of Fraunhofer IPMS and since 2022, head of Center for Advanced CMOS and Heterointegration, Saxony.

The APECS pilot line is powering the evolution of chiplet technologies

Aschenbrenner, Rolf
Director Deputy
Fraunhofer IZM

Abstract
The pilot line for »Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems« (or APECS in brief) is a key part of the EU Chips Act, as it will propel innovation in chiplet technology and enrich the semiconductor research and production capacities in Europe. The institutes cooperating in the Research Fab Microelectronics Germany (FMD) are working closely with other European partners to complete the APECS line and contribute substantially to making Europe more technologically resilient and competitive in the global semiconductor industry. The pilot line will give large industry players and SMEs or smaller start-ups easier access to cutting-edge technology and feed into more reliable and resilient semiconductor value chains.The presentation will discuss the role of Fraunhofer IZM in the APECS pilot line with its expertise for the hardware integration of chiplet systems. With its access to individual chiplet components, the institute can cover the entire process flow needed to create fully functioning systems. Its researchers are working on modern 300mm interposer technologies, high-density substrates, advanced assembly technologies, and the necessary processes for the advanced heterointegration of highly integrated systems. Fraunhofer IZM is establishing itself as a key partner for system-level heterointegration in Europe with several focus innovations.

Biography
Rolf Aschenbrenner received the B.S. degree in mechanical engineering from the University for Applied Science, Gießen, Germany in 1986 and the M.S. degree in physics from The University of Gießen, Germany, in 1991. Since March 1994 he has been employed at the Fraunhofer Institute for Reliability and Microintegration (IZM), where he is presently the deputy director and head of the Business Development Team.

Topic Coming Soon

Horstmann, Manfred
General Manager and Senior Vice President
GlobalFoundries

Abstract
Coming Soon

Biography
Manfred Horstmann serves as General Manager and Senior Vice President at GlobalFoundries (GF), overseeing European fabs, including GF’s 300mm manufacturing facility in Dresden. He also leads the GlobalFoundries Engineering Services (GFES) teams in Singapore, Penang, Bangalore, and Malaysia, supporting GF’s global manufacturing operations.Since 2020, he has transformed the Dresden Fab cluster into Europe’s largest 300mm wafer facility, achieving a two and a half output increase in less than three years, boosting productivity and strategically optimizing operations. He and his team led the development and production of a highly differentiated technology portfolio (55nm-22nm) for applications in fast growing markets such as automotive, MCUs, display drivers, audio amplifiers, security chip cards, radio frequency (RF) and 5G technology.With over 27 years of experience in multiple leadership positions in spanning research, technology development, product engineering, and large-scale operations, Mr. Horstmann has held leadership roles at Advanced Micro Devices (AMD), Motorola, and IBM in Germany and the United States.Mr. Horstmann holds over 100 patents, has authored more than 200 scientific papers and serves on advisory boards for Forschungszentrum Jülich and Nanoelectronic Materials Laboratory. Mr. Horstmann earned his Diploma and PhD in Physics from Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen.

Topic Coming Soon

Clarius, Tom
Director EHS&S
Globalfoundries

Abstract
Coming Soon

Biography
Coming Soon

Topic Coming Soon

Kamineni, Himani
Director, Advanced Packaging
GLOBALFOUNDRIES

Abstract
Coming Soon

Biography
Coming Soon

Horizon Europe ICOS : International Cooperation on Semiconductors for European Economic Resilience

Balestra, Francis
Director of Research
Grenoble INP-CNRS-SiNANO Institute

Abstract
This presentation will deal with the ICOS CSA project dedicated to International Cooperation On Semiconductors. International cooperation is key for speeding up technological innovation, reducing cost by avoiding duplicated research, boosting the resilience of the semiconductor value and supply chains, and is one of the objectives of the EU Chips Act. The final ICOS results will be highlighted, including the analysis of the semiconductor economic and technological landscapes in Europe and leading semiconductor countries, the identification of the most promising emerging technologies, the proposal of areas for potential cooperation and the opportunities for bilateral or multilateral research collaborations in the fields of advanced functionalities and computing.

Biography
BALESTRA Francis, CNRS Research Director at CROMA, is Director Emeritus of the European SiNANO Institute and Chair of IEEE Electron Device Society France, and has been Director of several Research labs. He coordinated many European Projects (ICOS, NEREID, NANOFUNCTION, NANOSIL, etc.) that have represented unprecedented collaborations in Europe in the field of Nanoelectronics. He founded and organized many international Conferences, and has co-authored more than 500 publications. He is member of several European Scientific Councils, of the Advisory Committees of International Journals and of the IRDS (International Roadmap for Devices and Systems) International Roadmap Committee as representative of Europe.

Innovative Materials Addressing Thermal Management in Advanced Packaging

Trichur, Ram
Global Head of Semiconductor Packaging Market Segment
Henkel Corporation

Abstract
The rapid adoption of AI applications powered by large language models (LLMs) is driving unprecedented demand for computational performance. This demand is accelerating the adoption of heterogeneous integration — including advanced 2.5D/3D chiplet architectures, high-density fan-out packaging, and co-packaged optics — as a means to extend Moore’s Law beyond traditional transistor scaling. At the same time, the growing use of AI at the edge and within mobile devices is placing new performance demands on application processors, prompting the industry to explore novel package architectures and enhanced thermal management solutions to sustain performance within the constrained form factors of mobile platforms.However, as device performance scales, so does power consumption. Logic, memory, optical components, power-delivery controllers, and other chiplets collectively generate significant heat, resulting in a tight thermal budget for the entire package. Effective thermal management has therefore become critical to maintaining system performance, reliability, and energy efficiency. This creates a unique opportunity for materials innovation: every material in the package stack that interfaces with the die can play a role in reducing hotspots, spreading heat, and efficiently extracting it. In this presentation, we introduce a suite of next-generation materials designed to address these thermal challenges.* High-thermal-conductivity liquid-molded underfills and encapsulants (>2 W/m·K) with sub-micron fillers for fine-pitch, void-free gap filling and excellent warpage control — ideal for 3D-stacked memory (HBM), TSV bridge dies, and wafer-/panel-level interposer builds with embedded passives and power components.* Sinterable and high-performance adhesive TIMs for side-by-side mobile application processor packages, and low-impedance phase-change TIMs supporting AI/HPC cloud processor cooling needs.* High-thermal capillary underfills (1.5 – >2 W/m·K) that protect first-level interconnects and mitigate localized hotspots in AI/HPC devices featuring co-packaged optics.We will share key innovations and performance data demonstrating how these materials significantly lower thermal impedance, improve heat spreading, and enhance device reliability across a range of heterogeneous integration platforms.

Biography
Ram Trichur is the global head of semiconductor packaging market segment at Henkel. He is responsible for the key strategic and financial objectives for this segment. He has more than 20 years of experience in the microelectronics industry covering both the front-end manufacturing and backend assembly processes. He has 3 patents and has published more than 50 publications and articles in leading conferences and industry magazines. He received his master’s degree in Electrical Engineering from University of Cincinnati and completed his executive education in business management from Stanford University’s Graduate School of Business.

„Materials, Innovations for Generations”

Joerger, Michael
Head of Business Line Power Electronic Materials
Heraeus Electronics GMBH

Abstract
In the face of increasing environmental regulations and growing demand for sustainable electronics, the semiconductor and electronic packaging industries are under pressure to reduce their carbon footprint without compromising performance. This presentation introduces a series of material innovations that demonstrate how sustainability and high performance can go hand in hand.We showcase three key developments: (1) recycled gold bonding wire, which maintains electrical and mechanical reliability while significantly reducing the environmental impact (2) Die Top System Silver as a viable alternative to Die Top System Gold, offering comparable electrical performance with a lower environmental and economic cost; and (3) recycled tin in solder pastes, which supports circular economy principles and reduces the carbon intensity of assembly processes.

Biography
Dr. Michael Jörger has 20 years experience in managing product development and launching of innovative materials for electronics and renewable energies with a focus of Power Modules and Semiconductor Packaging materials.Michael holds a Ph.D in Material Science from ETH Zurich, Switzerland, and a diploma in chemistry from the University of Karlsruhe in Germany.Currently he is leading the Business Line Power Electronic Materials at Heraeus Electronics.

Opening Keynote

Van den hove, Luc
President & CEO
imec

Abstract
The AI field is evolving at an incredibly fast pace, with major models and updates being released almost every month. As these models evolve beyond Large Language Models towards next-gen AI with advanced reasoning capabilities, compute systems struggle to handle the heterogeneous workloads in a performant and sustainable way. However, developing new, AI-optimized compute architectures and the enabling semiconductor technologies takes much more time than writing algorithms. To prevent bottlenecks slowing down AI-based advancements, we must reinvent compute architectures and semiconductor technology platforms. The presentation will shed light on the need for flexible, versatile compute architectures implemented in flexible, versatile technology platforms while addressing the increasing challenges of density, power and memory. To speed up both advanced semiconductor technology R&D and full stack innovation for future AI applications, imec is expanding its pilot line infrastructure under the EU Chips Act. Next to new infrastructure, imec aims to boost innovation through intensified collaborations with complementary knowledge partners and through further internationalization, attracting global talent and building strong, local ecosystems for diverse application domains, like health and automotive. Transformative innovations for humankind hinge on the innovation pace of the semiconductor industry. It’s time to supercharge our innovation engine, it’s time to futureproof our prosperity.

Biography
Luc Van den hove is President and CEO of imec since July 1, 2009. Before he was executive vice president and chief operating officer. He joined imec in 1984, starting his research career in the field of silicide and interconnect technologies.In 1988, he became manager of imec’s micro-patterning group (lithography, dry etching); in 1996, department director of unit process step R&D; and in 1998, vice president of the silicon process and device technology division. In January 2007, he was appointed as imec's EVP & COO. Luc Van den hove received his PhD in electrical engineering from the KU Leuven, Belgium.In 2023, he was honored with the Robert N. Noyce medal for his leadership in creating a worldwide research ecosystem in nanoelectronics technology with applications ranging from high-performance computing to health.He has authored or co-authored more than 200 publications and conference contributions.

The EU Chips Design Platform: a catalyst for fabless startups in Europe

Hoofman, Romano
Strategic Development Director
imec

Abstract
The EU Chips Design Platform will enable fabless companies to access the resources they need quickly and efficiently via a cloud-based virtual environment, offering chip design resources, training, and capital. Coordinated by imec, twelve key European research players in the semiconductor ecosystem have joined forces in a consortium to create this design platform.The platform aims to onboard the first startups and small and medium enterprises by early 2026, providing them with low-barrier access to European design capabilities, including route-to-chip fabrication, packaging, and testing. It will offer customized support to access commercial electronic design automation (EDA) tools, intellectual property (IP) libraries, EU Chips Act pilot line technologies, and access to design IP repositories, including open-source options. Additionally, the platform will feature a startup support program with incubation, acceleration, and mentoring activities next to financial assistance to help early-stage companies turn their innovative ideas into reality.

Biography
Romano Hoofman is Strategic Development Director at imec since 2016. He is currently responsible for the innovation programs at IC-Link and for the coordination of both the EU Chips Design Platform and the EUROPRACTICE Service.He started his career in industry, where he worked as a Principal Scientist at Philips Research and later on NXP Semiconductors. He covered many different R&D topics, ranging from CMOS integration, advanced packaging, thin film batteries, photovoltaics and (bio)sensors.Romano received his PhD from the Technical University of Delft in 2000, where he investigated charge transport in semi-conducting polymers. He has authored more than 30 publications and holds more than 10 patents in various research areas.

Accelerating nanoelectronic device innovation through atomistic simulation–driven material screening

Pourtois, Geoffrey
Fellow
Imec

Abstract
The introduction of new materials in nanoelectronics has been a key driver of innovation and scaling since Moore's law began. Examples include the introduction of high-k insulating dielectrics, metal gates, silicon-germanium alloys, and alternatives to copper for interconnect layers. However, while the periodic table offers inspiration, it also presents challenges. The main issue is not only identifying materials with the right phase and properties but also ensuring they maintain these properties at the nanometer scale, can be conformally deposited, remain stable through various process steps, and have a low environmental impact. Thus, enabling new materials is a complex, multi-dimensional, time- and resource-intensive problem that requires a proper methodology and rigorous testing with devices at relevant dimensions. Traditionally, material candidates are identified through literature research and numerous trial-and-error experimental steps. Recent advancements in atomistic simulations are helping to optimize this procedure, enabling virtual screening of materials without prior experimental measurements. We will illustrate this process through the identification of candidates to build a selector function for memory arrays.As process nodes continue to shrink, the spacing between parallel memory cells in the stack decreases, increasing the load on metal interconnects. Leakage current becomes an unavoidable issue, causing crosstalk between neighboring memory cells, affecting read and write operations, interfering with stored data, reducing storage lifespan, and increasing power consumption. To effectively suppress it, it is essential to control all possible leakage paths. The most efficient solution is to directly connect each memory cell to an independent device called a "selector," forming the memory array. The latter should ideally be built-in the memory device. Such a selector operates by switching between a high-resistance state (off) and a low-resistance state (on) when a certain threshold voltage is applied. Through this presentation, we will show how virtual material screening based on atomistic simulations of amorphous materials were used to design materials with tailored properties. When combined with machine learning, this approach is narrowing down potential candidates for device exploration and provide insights into precursor selection for the atomic layer deposition (ALD) of nanometer-thick films, while accounting for sustainability dimensions.

Biography
Geoffrey Pourtois studied Chemistry (1997) and obtained a PhD in Chemistry (2002) at the university of Mons Hainaut, Belgium. In 2003, he joined imec in Belgium, where he has been working in the field of atomistic modeling, with a special attention for establishing relations between material, interface defects and electrical device performances.From 2003 to 2025, he has been building and heading the group of material simulation and physics in imec, where he has been focusing on the modeling, using atomistic simulations, of nanoelectronic related materials. His group is being involved in building fundamental insights into the relations between material, interface and device electrical performances for CMOS, memory, and exploratory devices concepts. During their exploration endeavour, his team studied complex material gate stacks involved in CMOS and memory applications and contributed to the identification and the study of new materials for interconnect, emerging and magnetic memories. He was nominated imec fellow in 2020 and (co-) authored ~ 420 oral and peer-reviewed publications.

Welcome

Marent, Katrien
EVP & Chief Marketing and Communications Officer
imec

Abstract
Coming Soon

Biography
Katrien Marent has an engineering degree in microelectronics. She joined imec in 1992 as analog design engineer and specialized in design of low-noise readout electronics for high-energy physics. In 1999, she became press responsible and scientific editor at imec's business development division and was responsible for authoring and editing the research organization's numerous company technical documents and publications. In 2001, she was appointed corporate communications director at imec. Her responsibilities expanded in August 2007, when she got the position of external communications director including corporate, marketing and outreach communications. In October 2016, she became VP corporate, marketing and outreach communication. Since April 2020 she is Executive Vice President & Chief Marketing and Communications Officer and member of the executive board of imec.

Nanopores in Health: Where Silicon Meets Biology

Lenci, Silvia
Principal Member of Technical Staf
imec

Abstract
The convergence of semiconductor innovation and biomedical science is unlocking a variety of opportunities in healthcare diagnostics and therapeutics. Solid-state nanopores—nanoscale apertures fabricated in silicon-based membranes—represent a compelling frontier where advanced logic, integration, and materials engineering intersect with molecular biology. These devices enable label-free, single-molecule detection with high throughput. Unlike biological nanopores, solid-state variants benefit from CMOS-compatible fabrication, tunable geometry, and integration with photonic and electronic readout systems. Recent advances in nanofabrication, surface functionalization, and machine learning-driven signal processing have significantly enhanced their sensitivity, selectivity, and robustness. Imec’s leadership in semiconductor process innovation and integrated photonics provides a strategic advantage in accelerating the deployment of solid-state nanopore technologies across healthcare ecosystems. By leveraging its existing infrastructure for advanced logic nodes and heterogeneous integration, imec is pioneering scalable, cost-effective biosensing platforms that address global challenges including early disease detection, antimicrobial resistance, and pandemic preparedness.This presentation will showcase how imec’s semiconductor R&D ecosystem—traditionally focused on computing and mobility—is now catalyzing innovation in health. By leveraging imec’s strengths in chip manufacturing and system integration, solid-state nanopores exemplify how deep-tech can be harnessed to address global healthcare challenges. The talk aims to inspire cross-sector collaboration and highlight pathways for industrial deployment of silicon-based biosensing technologies.

Biography
Silvia Lenci graduated in Electronic Engineering at the University of Pisa (Italy) with a Master Degree in 2006, and a PhD in 2010, focusing on MEMS and bioMEMS. After her PhD, she started her career in imec Leuven as device and process engineer in GaN power electronics and sensors. She continued as integration engineer and project manager in the field of microfluidics, photonics, optics and MEMS, fabricated in the CMOS-compatible imec fabs. She is today project manager in solid state nanopore technology, focusing on the chip fabrication in fab. Bringing technology to life is her passion. Multidisciplinary interaction with processing, design, tape out and characterization teams is the core of her daily work.

Driving European Semiconductor Leadership: A Chiplet-Based Approach for the Automotive Sector

Hoffend, Dieter
Business Director Automotive Sector
imec

Abstract
Coming Soon

Biography
Dieter Hoffend is Business Director for the Automotive Sector at imec, where he leads strategic initiatives in chiplet technology and edge AI for the automotive industry. Based in Munich, he joined imec in February 2025, bringing more than 30 years of international experience in semiconductors, automotive electronics, and business leadership.Before joining imec, Hoffend built a distinguished career at Intel Corporation. He played a pivotal role in shaping Intel’s entry into the automotive market, serving on a three-person team that launched the company’s automotive strategy in 2005. This work set the foundation for Intel’s efforts in in-vehicle infotainment, advanced driver assistance systems (ADAS), and autonomous driving, and became a model for the broader semiconductor industry’s engagement with the automotive sector.Hoffend went on to lead Intel’s automotive sales in Europe, covering IT, connectivity, and Industry 4.0 and manufacturing solutions. He managed global relationships with major automotive OEMs and Tier-1 suppliers, driving significant growth and fostering long-term strategic partnerships. His leadership also extended to high-level collaborations with IT OEMs such as Hewlett Packard, Fujitsu Siemens Computers, and MEDION AG, as well as establishing Intel’s Foundry Services Business Development organization.Recognized for his ability to navigate complex markets and cultivate executive-level relationships, Hoffend has consistently delivered growth and innovation in highly competitive technology-based environments.

Space and Security Applications (title to be confirmed)

den Wijngaert, Nik Van
VP Aerospace & Security
imec

Abstract
Coming Soon

Biography
Coming Soon

Enviromentally aware IC chip manufacturing

Gallagher, Emily
Program Director
imec

Abstract
Coming Soon

Biography
Emily Gallagher is a director of the SSTS (Sustainable Semiconductor Technologies and Systems) program at imec, focusing on sustainability in semiconductor manufacturing processes. Emily earned her PhD in physics from Dartmouth College where she studied free electron lasers. After graduation, she joined IBM and became immersed in semiconductor technology. She held many roles at IBM from functional IC chip characterization to wafer process integration, to leading the EUV photomask development effort. She joined imec in 2014 to continue EUV development work. Emily has authored over 120 technical papers, holds ~30 patents, is an SPIE Fellow, cochairs the Scientific Advisory Board of the Advanced Research Center for Nanolithography (ARCNL) and is active in international organizations like SEMI's Semiconductor Climate Consortium and the PFAS Consortium.

Enabling the European Supply Chain

Soussan, Philippe
Technology Portfolio Director
imec

Abstract
Coming Soon

Biography
For 20 years Philippe Soussan has held different position in R&D management in imec in the field of sensors, photonics, 3D packaging. Addressing these technologies from R&D up to manufacturing levels. His background deals with wafer scale technologies, authoring over 100 publications, and holding more than 20 patents in these fields.From 2007 till 2011, he has led the group “Packaging, Microsystems and Hybrid Technology”. The group dealt with complex process integration using 3D interconnects, advanced packaging and micro fabrication of scaling and non-scaling driven components. In 2011, he became program manager for the smart system division of IMEC, which mission is to enable novel product in the field of More than Moore, such as sensors, microsystems in the field of RF and opto-electronics. In 2019, he was program director in the field of integrated photonics for sensing applicationsSince 2024, Philippe is in charge of strategy definition for IC-link by imec. This imec business line provides an access to design and manufacturing services in the most advanced ASIC and specialty technologies.

Panelist

De Boeck, Jo
EVP & CSO
imec

Abstract
Panelist

Biography
Jo De Boeck received his engineering degree in 1986 and his PhD degree in 1991 from the University of Leuven. Since 1991 he is a staff member of imec (Leuven). He has been a NATO Science Fellow at Bellcore (USA, 1991-92) and AST-fellow in the Joint Research Center for Atom Technology (Japan, 1998).In his research career, he has been leading activities on integration of novel materials at device level and new functionalities at systems level. In 2003 he became Vice President at imec for the Microsystems division and in 2005 started Holst Centre (Eindhoven) as General Manager of imec the Netherlands.From 2010 he headed imec’s Smart Systems and Energy Technology Business Unit. He is part-time professor at the Engineering department of the KU Leuven and held a visiting professorship at the TU Delft, Kavli Institute for Nanoscience (2003–2016). In 2011 he became Chief Technology Officer and in 2018 he was appointed Chief Strategy Officer. He is member of imec’s Executive Board.

European Pilot Lines: Aligning Strategy, Efficiency, and Implementation

Asselberghs, Inge
Strategic Development Director
IMEC

Abstract
Coming Soon

Biography
Coming Soon

Unlocking the potential of GaN-Si: Advancing 5G+/6G communication and power electronics

Collaert, Nadine

Imec

Abstract
Gallium Nitride on Silicon (GaN-Si) has emerged as a transformative technology for next-generation communication and power applications, offering a compelling balance between performance, cost, and scalability. In the realm of 5G+/6G communication infrastructure and handset applications, GaN-Si demonstrates significant promise with its ability to achieve high power density, efficient amplification, and compatibility with existing silicon manufacturing processes. Its scalability to larger wafer sizes provides a cost-effective alternative to GaN-SiC, particularly for base station infrastructure requiring operation at 28V and 48V. However, challenges such as thermal management, substrate losses, and achieving enhancement-mode (E-mode) devices for handset applications necessitate continuous innovation in materials and device architectures.For power electronics, GaN-Si has transitioned to mass production, delivering breakthroughs in efficiency and performance across a broad voltage range. Yet, as the technology matures, the research community is addressing critical challenges to expand its voltage range, improve integration levels, and enhance reliability under real-world conditions. This presentation outlines our roadmap for addressing these challenges through novel device designs, advanced substrates, and integration of new components. By balancing short-term industrial needs with long-term innovation, we aim to unlock the full potential of GaN-Si technology, driving advancements in high-frequency communication systems and energy-efficient power solutions.

Biography
Dr. Nadine Collaert is an imec fellow and part-time professor at the Vrije Universiteit Brussel (VUB). She is currently responsible for the advanced RF program looking at heterogeneous integration of III-V/III-N devices with advanced CMOS to tackle the challenges of next generation mobile communication. Before that, she was program director of the LOGIC Beyond Si program focused on the research on novel CMOS devices and new material-enabled device and system approaches to increase functionality. She has been involved in the theory, design, and technology of FinFET devices, emerging memories, transducers for biomedical applications and the integration and characterization of biocompatible materials. She has a PhD in electrical engineering from KU Leuven and she holds more than 500 publications and more than 15 patents in the field of device design and process technology.

Backing the Builders: Start-ups, Supply Chains, and Semicon Sovereignty

Engelmann, Michael
Principal
Imec.xpand

Abstract
Behind every breakthrough sensor device or imaging chip is a start-up entrenched in real-world supply and value chain decisions—from finding the right fabs and tools to coping with export rules and market access. At imec.xpand, one of the largest semicon-centric venture capital funds, we back founders tackling these challenges head-on, helping them move from breakthrough prototypes to scalable production. Imec plays a unique role as both technology partner and ecosystem hub, opening doors to global networks that deeptech ventures can’t access alone. But innovation doesn’t happen in a vacuum: today’s geopolitics and regional tech sovereignty agendas are reshaping how and where these ventures blossom. I’ll share stories of leading start-ups, what indicators we are looking for and what trends we are following.

Biography
https://www.linkedin.com/in/mengelmann/

Sub-THz HR SOI interposer with integrated hybrid thermal TSV and liquid micro-cooling

Novoselov, Evgenii
Process Integration Engineer
imec VZW

Abstract
The increasing demand for miniature, high-frequency devices in millimetre-wave applications such as 6G communications, next-generation radar, and sensing has uncovered inherent limitations in current packaging technologies. RF signal integrity, thermal challenges, and integration of dissimilar materials are among the issues that need to be addressed for enabling scalable and reliable high-performance modules. To solve these challenges, we designed a silicon (Si) interposer platform to enable the heterogeneous integration of an Indium Phosphide (InP) chip with a 94 GHz RF antenna, monolithic microwave integrated circuit (MMIC) structures, and integrated microfluidic cooling.Our interposer features a multifunctional embedded Cu layer that serves as a ground plane for MMICs, an antenna radiation efficiency reflector, and thermal spreader for enhanced thermal dissipation. In addition, the interposer features dense arrays of 20 × 100 μm Cu TSVs with vertical RF signal routing and low resistance, as well as efficient thermal conduction from active areas to the backside heat sink. Wafer level oxide-oxide fusion bonding was used to integrate top RF part with bottom microfluidic cooling part.InP chip is bonded with Cu/Ni/Sn micro-bumps, offering high-density low-resistive electrical interconnects and structurally reliable bonding. A mechanical test vehicle has been implemented to test bump quality, alignment precision, and structural strength, with inspection results to be presented.To further improve high-frequency signal routing, the interposer also features coplanar waveguide (CPW) traces optimized for low insertion loss at 94 GHz. Further, monolithically integrated microfluidic channels in the Si substrate enable active, localized cooling right below high-power components, further enhancing system thermal performance under load.We present RF measurements like S-parameters of CPW structures and antenna structures with effective transmission and impedance matching at 94 GHz. Thermal testing confirms the efficiency of combined microfluidic and Cu-based thermal management.

Biography
Evgenii Novoselov was born in Saint Petersburg, Russia, in 1988. He received his B.Sc. in Photonics and M.Sc. in Optoinformatics (summa cum laude) from ITMO University in 2009 and 2011, respectively. In 2017, he earned his Ph.D. from Chalmers University of Technology, Gothenburg, Sweden, with a dissertation on MgB2 hot-electron bolometer mixers for sub-mm wave astronomy.After completing his Ph.D., Evgenii joined the Microwave Electronics Laboratory at Chalmers as a postdoctoral researcher, where he worked on W-band graphene FET-based resistive mixers. Since 2019, he has been with imec in Leuven, Belgium, where he currently holds the position of Senior Process Integration Engineer. His work focuses on heterogeneous component integration, including BEOL, MEMS, RF systems, and hyperspectral imaging technologies.

From Insight to Action: Elevating Employee Efficiency with Smart Detection and Targeted Data Delivery (joint presentation with ST Microelectronics)

Smith, Holland
Director of Data Science
INFICON

Abstract
In an era where it is increasingly easy to be overwhelmed by data, timely and efficient decision-making is critical to maintaining optimal factory operations. This talk will highlight the results of a joint collaboration between INFICON and ST Microelectronics. Together, we are developing an innovative application aimed at transforming how factories operate and respond to challenges. In addition to providing real-time tracking of key performance indicators (KPIs), the application detects various types of operational anomalies. These anomalies are automatically assessed to determine their potential impact, and the application allows workflow management by assigning tasks to the appropriate factory workers, ensuring rapid response and resolution. Our collaboration is focused on enhancing employee efficiency by delivering data that is specifically tailored to each worker's role, minimizing information overload, and providing actionable insights exactly when and where they are needed. By combining comprehensive operations tracking with smart detection and targeted data delivery, this solution enables semiconductor factories to operate with greater precision and reduced downtime.

Biography
Dr. Holland Smith is Director of Data Science at INFICON IMS, where he leads AI initiatives spanning classical machine learning to LLM-based agentic AI systems across INFICON's software and smart sensor portfolio. His team's high level focus is the transformation of semiconductor and industrial manufacturing operations through optimization, intelligent automation and predictive analytics.Holland joined INFICON FPS in 2016, where he architected and deployed Smart Manufacturing systems in 200mm and 300mm fabs worldwide. As a semiconductor data systems expert and contributing developer of the INFICON FPS Digital Twin, he enables advanced fab scheduling, optimized WIP movement, and predictive manufacturing capabilities. Dr. Smith has published research and spoken widely on automated throughput and cycle time forecasting that enables high-fidelity fab modeling across multiple time horizons.Prior to INFICON, Holland worked as a Technology Development Engineer at Intel D1D/X in Hillsboro, OR, focusing on thin film process development and subfab optimization for challenging deposition processes. Dr. Smith earned a PhD and M.S. in Materials Science and Engineering with a minor in Solid State Physics and a B.S. with Honors in Engineering Physics from UC Berkeley, plus a B.A. with Honors in Slavic Languages from Stanford University.Joint Presentation with: Thomas Gimmig has twenty-five years of experience in semiconductor manufacturing. After holding various positions in maintenance, engineering, and production management at ST Microelectronics, finishing as Production Director of the Rousset plant in 2019, he moved to manufacturing central functions in 2022. Initially, he was in charge of Front-End Operational Excellence programs, developing the LEAN leaders community, and leading smart manufacturing transformation programs. He recently became the head of Industry 4.0 programs for ST Microelectronics manufacturing. Thomas Gimmig holds a master's degree in electronics.

From Vision to Reality: How Agentic AI Enables the Autonomous Factory

Behnke, John
General Manager Smart Manufacturing
INFICON

Abstract
The semiconductor industry has achieved remarkable results through decades of disciplined optimization, yet sustaining these gains requires ever-greater effort from highly skilled engineers, operators, and managers. Traditional machine learning and data science have delivered powerful predictive models and anomaly detection, but they remain bounded by human vigilance and manual intervention.Agentic AI represents the next leap forward: intelligent, factory-aware systems that not only analyze but also act: automating workflows, coordinating across applications, and learning from context. By evolving from contextual help to in-application assistants, to agentic data analysis, and ultimately to user- and factory-aware AI agents, fabs can transition from incremental improvements to systemic transformation. The vision is not simply higher yields or better scheduling, but maintaining world-class KPIs with significantly reduced effort, lower variability, and faster responsiveness to change.This talk will outline the path forward for bringing agentic AI from today’s proofs-of-concept into real-world fab operations. The direction is clear: leveraging agentic AI to extend scheduling optimization, dynamic factory modeling, equipment monitoring, and workflow automation beyond human-driven intervention. By building towards autonomous decision-making across complex, interconnected systems, agentic AI provides the blueprint for the truly autonomous factory.For fab managers, this is more than a technology shift, it is a redefinition of operational excellence. Agentic AI will allow organizations to scale expertise, capture knowledge, and ensure resilience in an increasingly complex manufacturing environment. As the industry prepares for the next era of smart manufacturing, understanding and adopting agentic AI is essential to remaining competitive.

Biography
Mr. Behnke has over 40 years of semiconductor industry experience. As the GM of INFICON’s FPS Product Line and Head of its IMS Marketing team, John leads a global team that develops and deploys Smart Manufacturing software and hardware solutions which improve factories performance. INFICON’s comprehensive Digital Twin of a factory enables advanced Factory Scheduling, optimized WIP movement and other advanced capabilities.He is also a Co-Chair of the Semi North America Smart Manufacturing Chapter as well as a founding member of Semi’s Smart Global Executive Committee. Prior to his current role at FPS John served as: the President of Novati Technologies, SVP and GM of the Semiconductor Group at Intermoleculor, CVP for Front End Manufacturing and Tech Transfers at Spansion and Director of Operations at AMD's Austin Fab 25.

From Semiconductors to Quantum: Infineon's Multi-Technology Approach

Luber, Sebastian
Senior Director Technology & Innovation
Infineon Technologies AG

Abstract
Quantum computing holds significant potential to revolutionize the future of technology, and Infineon Technologies is contributing to this evolution through its developments in quantum hardware. This presentation will showcase Infineon's activities in superconducting circuits, semiconducting SiGe-based qubits, and ion trap technologies. Drawing on its expertise in semiconductor manufacturing and design, Infineon is addressing key challenges in scalability, integration, and reliability for quantum computing systems. The session will explore how Infineon's components and modules contribute to the development of robust quantum computing systems across these three leading technology platforms. Emphasis will be placed on the holistic approach, which combines deep materials science knowledge, advanced process technologies, and collaboration within the quantum ecosystem. Join us to gain insight into how Infineon is shaping the future of computing.

Biography
Sebastian M. Luber holds a PhD in technical physics from the Walter Schottky Institute at the Technical University of Munich and is Senior Director for Technology & Innovation at Infineon Technologies AG. He coordinates Infineon's activities in the field of quantum technologies and acts as an advisor to the Management Board. Luber is involved in a variety of external committees and activities dealing with quantum technologies. Among others, he is member of the Program Committee for Quantum Technologies of the Federal Ministry of Education and Research, and active in QUTAC, the German Quantum Technology & Application Consortium. Previously, he held various positions in the company, including Sensor Technology Line Manager and Automotive Program Manager.

High Performance Audio Enabling the Future of AI Assistants: Advances in Intelligent Multi-Speaker Processing

Heiss, Manuela
Head of System Application Engineering MEMS Sensors
Infineon Technologies AG

Abstract
The rapid evolution of artificial intelligence (AI) assistants has transformed the way we interact with technology. However their ability to accurately process and understand multi-speaker environments remains a significant challenge. High performance microphones provide a crucial foundation for enabling complex machine learning use cases such as speaker diarization, speech separation, and speaker localization. By leveraging highest audio performance, AI assistants will be able to transcribe, translate, compile and understand human interactions, revolutionizing the way we work, communicate and collaborate.

Biography
Manuela Heiss is heading the system application engineering group for MEMS sensors at Infineon Technologies. Manuela joined Infineon in 2018 as a software engineer, followed by positions as system architect for IoT solutions at Infineon, Singapore. In 2022 Manuela established the system application engineering group for MEMS sensors at Infineon. Manuela and her team are focusing on enabling high performance acoustic solutions for consumer, industrial and automotive applications and thereby bridging the gab between technical innovation and customer-centric solutions.

Topic Coming Soon

Gan, Terence
Executive Director
Institute of Microelectronics

Abstract
Coming Soon

Biography
Coming Soon

Topic Coming Soon

Singh, Navab
Director, MEMS Program at the Institute of Microelectronics, Singapore
Institute of Microelectronics

Abstract
Coming Soon

Biography
Dr. Navab SINGH [M.TECH/IIT Delhi, Ph.D./NUS Singapore] is a Senior Scientist and Director at Institute of Microelectronics (IME), A*STAR, Singapore, leading MEMS program. As a Senior Scientist/ Member of Technical staff and Principal Investigator of Nanoelectronics program, in 7 years [2005-2011], he developed highly scaled lateral and vertical nanowire gate-all-around FETS, NVM devices and high efficiency silicon solar cells. Prior to that Dr Singh worked on lithography technology development for 9 years [1996–2004] focusing on resolution enhancement techniques. Dr. Singh has authored or co-authored more than 190 technical papers (citations > 1900 & h-index: 22) in referred archival journals and conferences and has filed more than 20 technology disclosures. His nanowire gate-all-around FET papers have been selected for pre-conference publicity by IEDM and SSDM conferences. He is a recipient of George E. Smith Award 2007 for best paper in IEEE Electron Device Letters, Singapore National Technology Award 2008 for his outstanding contributions to the research and development of nanowire-technology platform, enabling the realization of ultimately scaled CMOS integrated circuits and new class of electronic bio-sensors, IME Excellence Award 2009 for industry project developing Surround Gate Transistor (SGT) technology, and A*STAR TALENT award 2010 for Leading, Educating and Nurturing Talents.

Digitalization in Semiconductor Manufacturing Supply Chain – Need of Global Collaboration

Gossner, Harald
Senior Principal Engineer
Intel

Abstract
Semiconductor-X introduces a secure and interoperable dataspace for the international semiconductor supply chain.Demonstrating key use cases for planning, optimizing, regulatory reporting and enablement of new business models using digital twin technology.Semiconductor-X is working with US and Asian partners to align the international standardization of digital twins and data space connectors for semiconductor supply chain usage.

Biography
Harald Gossner holds the position of a Senior Principal Engineer at Intel. He received his diploma degree in physics from Ludwig-Maximilians-University, Munich in 1990 and his PhD in electrical engineering from Universität der Bundeswehr, Munich in 1995. For 15 years he has worked on the development of electrostatic discharge (ESD) protection concepts with Siemens and Infineon Technologies. In 2011 he joined Intel leading the system ESD robustness development for Intel products.He is the co-founder and co-chair of the Industry Council on ESD Target Levels representing more than 60 companies including all leading semiconductor manufacturers. He is President Emeritus of the EOS/ESD Association, Rome, NY, IEEE Fellow and editor of IEEE Electron Device Letters.In his role as technology advisor, he is member of the industry advisory boards of the Bavarian Government and of several Fraunhofer institutes. He is part of the expert commission on AI of the German Economic Council. Since 2024 he is leading the project Semiconductor-X, coordinating the development of a dataspace for a resilient supply chain of semiconductors for Europe. He is also driving the build-up of a design ecosystem of innovative designs in digital leading edge technologies in Europe.

Superconducting Quantum Chips as the Foundation for Quantum Computing

Hassel, Juha
VP of Quantum Technologies
IQM Quantum Computers

Abstract
Quantum computing based on superconducting chips is currently one of the most promising approaches for industrially relevant quantum computing. In this presentation, we will review IQM's comprehensive approach to quantum computing, spanning from chip design to full-scale systems, and showcase exemplary computing applications that are enabled by today's quantum computers. We will highlight the key aspects related to superconducting quantum chips, including the specific requirements and solutions for maintaining quantum coherence. Additionally, we will provide an overview of IQM's chip fabrication capabilities and how they align with the company's vision for scaled-up, future systems that will be necessary for fault-tolerant quantum computing. We will also present key performance metrics for our chips, including T1 coherence times of up to nearly one millisecond and 2-qubit gate fidelities of up to 99.93%, which have been achieved using IQM's tunable coupler approach. Furthermore, we will deliver a status update on the development of our full Quantum Processing Units (QPUs), featuring our current-generation chips with up to 54 and 150 qubits. Finally, we will outline IQM's scaling roadmap towards fault-tolerant quantum computing.

Biography
Dr. Juha Hassel received his PhD title in 2004 from Helsinki University of Technology (now Aalto University). As of March 2024, he holds the position of Vice President of Quantum Technologies at IQM Quantum Computers, where he has worked in different leadership positions since 2019. Before joining IQM, he served as Principal Scientist at VTT Technical Research Centre of Finland, where he also led the Applied Quantum Electronics team within the national Centre of Excellence – Quantum Technology Finland.

Rethinking Chip Design with Open Source EDA

Alexandre, Christophe

keplertech.io

Abstract
The rise of open source hardware, driven notably by RISC-V adoption, is generating growing interest in more open and flexible Electronic Design Automation (EDA) tools. Despite this momentum, the EDA landscape remains largely proprietary — with critical stages of both digital and physical design flows controlled by a small group of vendors. This limits reproducibility, collaboration, accessibility, and innovation.Unlike cloud or AI software stacks — where open source has become foundational — semiconductors and EDA have remained predominantly closed. But that paradigm is beginning to shift. A growing community of contributors and increasingly capable open source EDA projects are forming a viable ecosystem with real-world applicability.This talk will explore how open source EDA can be effectively leveraged today — not as a full replacement for industrial tools (at least not yet), but as a complementary layer that provides value in specific, practical contexts: - CI/CD for open hardware projects, enabling community-driven regression testing with license-free flows. - Early-stage architecture exploration and prototyping for SMEs, academic teams, startups, and newcomers — without requiring access to commercial toolchains. - Cloud-native flow scaling, where open licensing enables elastic, parallel experimentation on standard compute infrastructure.We will also highlight the contribution of keplertech.io, and introduce Naja — a modular C++/Python framework for post-synthesis netlist analysis, optimization, and EDA tool development.I will also consider the strategic relevance of open source EDA in the European context — how it can reduce dependency, foster innovation, enable reproducible flows, and support skills development, all of which are critical to Europe’s pursuit of greater semiconductor sovereignty.

Biography
Christophe Alexandre, Keplertech.ioWith 20 years of experience in Electronic Design Automation (EDA), I began my journey with a PhD in microelectronics from Sorbonne University (2008). In 2009, I co-founded Flexras Technologies, a startup specializing in FPGA prototyping tools, which was acquired by Mentor Graphics (now Siemens EDA) in 2015. There, I served as Chief Software Architect, leading global R&D teams and helping evolve our technology into a widely adopted commercial product.In 2022, I co-founded a new venture: keplertech.io, an EDA startup built on the belief that Open Source can unlock innovation in one of the most closed and complex industries—semiconductors, integrated circuits, and the tools used to design them. In a space dominated by a handful of major players, we aim to create meaningful opportunities for smaller, agile actors to thrive.I’m passionate about building complex systems from scratch and bringing ideas to life in the real world.LinkedIn: https://www.linkedin.com/in/christophe-alexandre-634bb36Mastodon: https://mastodon.social/@xtofalexnaja GitHub: https://github.com/najaeda/naja

Strengthening Semiconductor Supply Chains in an Era of Disruption

O'Dowd, Barry
Head of Global Business Development Semicon
Kuehne+Nagel

Abstract
In this session, Barry O’Dowd, Head of Global Business Development Semicon, at Kuehne+Nagel, will explore the key risks facing semiconductor logistics and how companies can proactively mitigate them. He will introduce practical strategies for assessing and strengthening transportation resilience by drawing from real-world examples and lessons learned from industries with highly complex supply chains.Attendees will gain insights into:■ How the semiconductor industry is adapting to global disruptions and reshoring trends■ The role of data-driven risk mitigation tools in evaluating transportation lanes■ Best practices for securing critical shipments, from wafer fabrication materials to capital equipment■ The importance of continuous risk assessment in an evolving supply chain landscapeWith decades of experience optimising Semicon logistics, Barry will share how industry leaders can turn supply chain resilience into a competitive advantage, ensuring stability, security, and seamless operations in a rapidly changing world.

Biography
Based in Dublin, Ireland, Barry brings more than 30 years of international logistics expertise, In his current role, Barry leads strategic growth and innovation within the company’s semiconductor logistics segment—one of the key focus areas under Kuehne+Nagel’s global Roadmap 2026 strategy. Recognizing the industry’s unique supply chain demands, he has been instrumental in developing SemiconChain—a dedicated, quality-certified network now spanning more than 35 locations across major semiconductor hubs.

Advances in AlScN Thin Films Deposited by Lam Research Pulsed Laser Deposition Platform

Dekkers, Matthijn
Director Engineering Pulsed Laser Deposition technique (PLD)
Lam Research

Abstract
Pulsed laser deposition (PLD) is a very versatile thin film deposition technology that has the ability to deposit a wide range of advanced thin film materials. With today’s market demand for enhanced and new material systems, PLD enables layers that cannot practically be deposited by conventional technologies like physical vapor deposition (PVD) reactive sputtering.This deposition solution enables more advanced device design and is driving the next generation of radio frequency (RF) filters for 5G, WiFi 6 and 6E, high-end micro-electromechanical systems (MEMS), ferroelectric memory and photonics applications.For piezoelectric aluminum scandium nitride, PLD has extended the limits of scandium doping in the AlScN compound, resulting in very high piezoelectric properties. Additionally, this PLD platform enables precise control over thickness uniformity and thin film stress, which are crucial for high-yield (RF) MEMS applications.For the first time in semiconductor production, Lam is using lasers to deposit thin films and bringing PLD to wafer-level mass production. Lam Research PLD is expected to be key in developing cutting-edge specialty technologies devices, such as RF filters for 5G and Wi-Fi 6 and high-end MEMS microphones.

Biography
Matthijn Dekkers earned his PhD in Applied Physics from the University of Twente in 2007, the same year he co-founded SolMateS. As Chief Technology Officer, he led the R&D division in scaling the Pulsed Laser Deposition (PLD) technique for industrial applications. Following SolMateS’ acquisition by Lam Research in 2022, Matthijn assumed the role of Director of Engineering for PLD, where he continues to drive innovation in advanced materials processing.

Driving Heterogeneous Integration for AI and Beyond

Oetzlinger, Herbert
Vice President and Head of the Panel Product line
Lam Research

Abstract
The semiconductor industry is undergoing a transformative shift, with advanced packaging emerging as a critical enabler of performance, scalability, and cost-efficiency in the post-Moore era. Heterogeneous integration (HI), which combines diverse chiplets with varying process nodes and functionalities into a single package, addresses technical challenges such as shrinking transistor sizes, increasing interconnect density, and optimizing power efficiency. The surge in demand for artificial intelligence (AI) applications, particularly high-performance computing (HPC) and data center AI chips, has further accelerated the need for innovative packaging solutions like 2.5D/3D ICs, fan-out wafer-level packaging (FOWLP), and panel-level packaging (PLP). These technologies enable higher bandwidth, lower latency, and compact form factors essential for AI-driven workloads. Recent product developments, including chiplet-based architectures and high-bandwidth memory (HBM) integration, underscore the industry’s focus on powering next-generation AI systems.This presentation explores the technical imperatives and market dynamics driving advanced packaging, with a deep dive into panel-level packaging (PLP). PLP offers significant cost advantages by processing multiple packages simultaneously on larger panels, enhancing economies of scale compared to traditional wafer-level packaging. However, both the substrate and PLP markets face challenges, notably the lack of standardized panel sizes, which complicates equipment design and increases costs. PLP’s economic viability is further constrained by its suitability primarily for high-volume devices, limiting its total market size. Despite these hurdles, the convergence of technology and equipment requirements between substrate and PLP markets is fostering a more robust equipment supplier ecosystem, potentially unlocking greater scalability and innovation.The presentation will also highlight Lam Research’s cutting-edge solutions for advanced packaging, focusing on its advancements in chiplet-to-chiplet and chiplet-to-substrate heterogeneous integration. By addressing warpage, electroplating uniformity, and other manufacturing challenges, Lam Research is enabling scalable, high-performance packaging solutions tailored for AI, 5G, automotive, and consumer electronics applications. This convergence of market needs and technological innovation positions advanced packaging as a cornerstone of the semiconductor industry’s future.

Biography
Herbert Oetzlinger graduated from HTL Braunau in 1987 with a specialization in high-power electronics and electrotechnics. With over 30 years of experience in the semiconductor industry, he has built deep expertise in wet processing, particularly in advanced packaging technologies involving electroplating, wet etching, and wafer/substrate cleaning.Herbert held the role of Vice President of Business Development at Semitool Inc., where he was recognized for his deep process and hardware knowledge. During his tenure, he collaborated with leading global companies on innovations such as Fan-Out, Embedded Wafer-Level Ball Grid Array (E-WLB), and other cutting-edge developments in wafer-level advanced packaging.In 2012, he founded Semsysco GmbH and served as its CEO. Under his leadership, Semsysco became a global leader in high-speed electrochemical deposition, known for its comprehensive capabilities in wet processing for both wafer and panel-level applications.Following Lam Research’s acquisition of Semsysco in 2022, Herbert joined Lam as Vice President and Head of the Panel Product Line, where he continues to drive innovation in advanced packaging solutions.

A Sustainable Dicing Innovation for Cutting-Edge Semiconductor Challenges

Keil, Christian
Director Business Development & Sales
Lidrotec Gmbh

Abstract
The production of semiconductor components (chips) is realized on thin wafers and is an energy and resource-intensive process that can take up to 12 weeks. Before the chips can be further processed, they must be separated on the wafer by the so-called dicing - a critical process step that introduces considerable damage to the chip frontside, backside and sidewalls.The market development of recent years combined with the AI boom leads to a high demand for computing power and data storage, e.g., for training of AI models. In consequence this growing demand leads to a steady increase in energy consumption.To counteract rising energy consumption, innovative, more efficient product designs, e.g., HBM, are required. These are mostly achieved by a broader use of modern packaging methods, e.g., Advanced Packaging and Hybrid Bonding.Unfortunately, these modern packaging and bonding methods lead to an increasing demand on chip quality and cleanliness, which cannot be achieved with most of the currently used dicing methods.As a result, semiconductor manufacturers have to utilize complex multi-step separation processes, including plasma dicing, which are not only expensive but also consume a large amount of chemical process gases.Our innovative LidroCUT process, based on ultrashort pulse laser in liquid overcomes these challenges. The liquid cools down and binds the emerging nano particles into the liquid, leading to a debris free surface and contamination free sidewalls, enabling hybrid bonding without additional cleaning steps, proven by optical inspection.Meanwhile, the cooling capacity of the liquid allows for a precise laser power use, leading to high quality, burr free, edges and high break strength.LidroCUT is literally cutting edge.

Biography
Christian Keil graduated with a Master of Science in Mechanical Engineering from the Ruhr University Bochum in 2017. He gained his first professional experience as a process engineer commissioning machines and training customer employees all over the world. After half a decade as a process engineer he reoriented himself and moved into the sales departments. He joined Lidrotec as Sales Manager in 2023​ and is today Director of Business Development & Sales at Lidrotec.

BTO-enhanced Silicon Photonics for Next-Generation Optical Transceivers

Mohn, Fabian
Reliability and Packaging Lead
Lumiphase AG

Abstract
As global data traffic continues to surge, the demand for faster, more energy-efficient, and scalable optical communication systems is driving the need for innovation in photonic integration. Traditional silicon photonics, while mature, faces limitations in speed, power consumption, and footprint.Lumiphase addresses these challenges by developing and manufacturing photonic integrated circuits based on a proprietary barium titanate (BTO) technology. This technology uses the Pockels effect and enables true electro-optic modulation, offering significant advantages over conventional silicon-based solutions.In this presentation, we will introduce our BTO-based photonic integration technology, highlight its advantages for optical data communication, and discuss key challenges and ongoing developments in bringing this technology to scale.

Biography
Fabian Mohn is a Staff Engineer and team lead of the Reliability & Packaging team at Lumiphase. The team is responsible for wafer-to-chip singulation processes, the design and assembly of test vehicles for chip-level performance and reliability evaluation, and the development and execution of accelerated reliability and robustness qualification protocols for Lumiphase’s BTO-based silicon photonics devices.Fabian holds a PhD in Physics, which he earned in 2012 while working at IBM Research – Zurich. Before joining Lumiphase in 2022, he worked on the development of silicon and silicon carbide power semiconductor modules, gaining extensive experience in packaging and reliability engineering.

Fabrication of Recrystallized SiC Wafer Carriers via Additive Manufacturing and CVI

Jung, Youngsuk

MADDE Inc.

Abstract
To address the limitations of conventional silicon carbide (SiC) manufacturing—such as high-temperature sintering, significant shrinkage, and restricted geometry—we present a novel process that enables the production of high-performance recrystallized SiC (R-SiC) components for semiconductor equipment. This approach combines binder jetting additive manufacturing (BJAM) with chemical vapor infiltration (CVI) to rapidly produce complex wafer carriers (baffle boats) with excellent thermal stability and dimensional accuracy.The process begins with the fabrication of porous green bodies using a custom-developed BJAM system tailored for SiC powders. These printed parts feature complex internal geometries and are subsequently densified through vapor-phase SiC deposition via CVI. Unlike conventional R-SiC fabrication that relies on high-temperature processing and mold-based shaping, this method achieves densification under lower thermal conditions while enabling precise control over residual porosity. The result is improved mechanical strength, reliable shape retention, and minimized material waste.Using this approach, we successfully manufactured wafer carriers in a fast and cost-effective manner. The printed R-SiC components demonstrated strong thermal shock resistance and dimensional stability under repeated exposure to high-temperature process environments. By combining the geometric freedom of additive manufacturing with the functional reliability of R-SiC, this process offers a scalable and economically viable pathway for next-generation ceramic components in semiconductor manufacturing.

Biography
Youngsuk Jung is the CTO and co-founder of MADDE, a company developing advanced additive manufacturing technologies for both ceramics and metals. He holds a Ph.D. in Automotive Engineering with a specialization in structural design optimization. Prior to founding MADDE, he conducted research on design for additive manufacturing at Hyundai Motor Company. His current work focuses on the development of customized 3D printers and design methodologies optimized for the additive manufacturing of high-performance industrial components.

Innovative AMC Filtration solutions for future semiconductor production challenges

Zoermer, Manfred

Mann+Hummel Molecular GmbH

Abstract
Filtration is crucial for maintaining high quality and process stability in semiconductor manufacturing. As processes advance and device geometries become more complex, high precision optics and process equipment demand optimal protection from particulate and molecular contamination.As process nodes advance, molecular contamination has become just as important as particulate contamination. The necessity for innovative filtration solutions is emphasized by stricter requirements and new process chemicals.

Biography
Manfred Zoermer (born 1965), after studying chemistry (with focus on inorganic and high energy chemistry), started his professional career as sales engineer for analytical technology within the sales area Baden-Wuerttemberg. Several global positions in his career at suppliers of critical process materials to microelectronics, MEMS and compound semiconductor manufacturers connected him directly with clean room technology and led to high special process environment affinity. Further positions in and outside a wide range of industries in sales and marketing, led him to join MANN+HUMMEL Air Filtration at the beginning of 2020. In his current position, he is responsible for the development of a broadband product portfolio, particularly introducing chemical process technology to the air filter community. Manfred is involved as an expert in the standards and guidelines of VDMA, DIN and ISO workgroups.

Closing Europe’s Greentech Talent Gaps

Barberis, Riccardo
Regional President, Northern Europe
ManpowerGroup

Abstract
Despite recent geopolitical changes, nearly half (47%) of employers worldwide plan to increase green business transformation investment and most (91%) do not have the talent they need to achieve their sustainability goals. The role of the semiconductor industry in Europe will become increasingly important to sustaining green innovation and energy security as geopolitical uncertainty continues to disrupt global supply chains. The challenge will grow as most employers (74%) report difficulty finding skilled talent today and aging populations continue to decrease the size of the total workforce. This presentation will leverage data from nearly 40,000 employers and 14,000 workers to explore the challenges and opportunities this poses for the semiconductor industry.Current tech talent shortagesTech worker sentimentTech skills gapsEmployer best practicesRegional partnership opportunities ManpowerGroup Employment Outlook SurveyThe ManpowerGroup Employment Outlook Survey is the most comprehensive, forward-looking employment survey of its kind, used globally as a key labor market indicator. The Net Employment Outlook (NEO) is derived by taking the percentage of employers anticipating an increase in hiring activity and subtracting from this the percentage of employers expecting a decrease in hiring activity. ManpowerGroup Global Talent BarometerThe ManpowerGroup Global Talent Barometer measures worker well-being, job satisfaction, and confidence. around the world. The Talent Barometer leverages independent survey best-practices and statistically significant samples to create a powerful tool to better understand what workers want globally. The research aims to improve the future of work through deeper understanding of key drivers of workforce sentiment today.

Biography
Riccardo Barberis was appointed Regional President, Northern Europe in May 2021, and in January 2025 expanded his responsibilities to include France, ManpowerGroup's largest market in the region. In this role, Barberis oversees all of ManpowerGroup's brands and offerings across the region – Manpower, Experis, and Talent Solutions. Barberis will lay the path to further accelerate ManpowerGroup's diversification, digitization, and innovation plans, creating even more value for clients and candidates and strengthening our performance in the region.​Riccardo joined ManpowerGroup in 1998 and has held numerous leadership positions in Europe and Latin America, most recently as country manager for ManpowerGroup Italy. With more than 25 years of experience including many international roles his deep industry knowledge and passion for a client-first, candidate-centric approach consistently delivers superior results.An accomplished executive, Riccardo holds an Executive MBA from Bocconi University (Milan), has completed management programs at INSEAD and speaks five languages. Currently serving as Board Member of Junior Achievement Europe, he has previously held positions as Vice President of the Italian Industry Association (Assolavaro) and President of ManpowerGroup's Human Age Institute. Riccardo lives with his family in Paris.

AI as a Catalyst: Transforming the Semiconductor Landscape Amid Geopolitical Shifts

Ernst, Benedikt
SVP, Head of Strategy and Transformation Electronics
Merck Electronics KGaA

Abstract
In an age where globalization has given way to a fragmented and unpredictable landscape, global companies face a new reality: navigating constant volatility and complexity. As organizations grapple with the intricacies of cost management, coordination, and strategic decision-making, they encounter both formidable challenges and exciting opportunities. At the forefront of this transformation is artificial intelligence (AI), a powerful catalyst driving innovation and reshaping geopolitical dynamics. AI not only propels advancements in the semiconductor industry but also accelerates the pace of innovation, bringing strong growth prospects for the semiconductor market and the European companies within this ecosystem. In this keynote presentation, Benedikt Ernst, Head of Transformation and Strategy for the Electronics Business of Merck KGaA, Darmstadt, Germany, will provide insights into how the company is redefining its strategy through a dynamic "local to local" approach. This strategy encompasses diversifying markets, reinventing research and development, and restructuring supply chains. Benedikt will discuss how the company is capitalizing on AI opportunities through digital transformation, which accelerates advancements in semiconductor materials to keep pace with the rapid growth of AI. He will also highlight the importance of decades of ecosystem collaboration in building the semiconductor industry. Furthermore, Benedikt will explore how the European ecosystem is uniquely positioned to gain a competitive edge in the AI era, demonstrating that through collaboration, we can thrive even amidst prevailing geopolitical tensions.

Biography
Benedikt Ernst is the Senior Vice President and Head of Strategy and Transformation at the Electronics business of Merck KGaA, Darmstadt, Germany. As a member of the Electronics Executive Committee, he is responsible for the end-to-end strategic development and transformation of the business sector, encompassing market competitive intelligence, strategic roadmap, business transformation programs, and business and portfolio development. He joined Merck KGaA, Darmstadt, Germany in 2006, and has had various management positions. Since 2018, he has been heading Strategy and Business Development for Electronics and Semiconductor. Before he was Commercial Director for the Semiconductor business and Head of Packaging Business Field. Benedikt Ernst studied physics at the Technical University of Munich and at the Max Planck Institute of Plasma Physics.

How AI gets a body

Fabrowsky, Jens
COO
Neura Robotics GmbH

Abstract
tbd.

Biography
Jens Fabrowsky, an experienced, renowned top manager with an impressive track record at Bosch, joined the NEURA Robotics management team as Chief Operating Officer (COO) on December 1, 2023. His decision to join NEURA Robotics is based on the conviction that the company plays a crucial role in realizing the visions of Industry 4.0 and cognitive robotics. Fabrowsky brings extensive experience in product development and operational leadership, which he is now applying at NEURA Robotics to support the company in its scale-up phase.His extensive experience in scaling businesses and hands-on mentality make him a valuable addition to NEURA Robotics as the company solidifies its position as a leading cognitive robotics hub in Germany.

Sustainability at NY CREATES. Addressing the most critical sustainability areas for responsible and sustainable semiconductor industry innovations.

Tolic, Frank
Director of Business Development
New York CREATES

Abstract
With the recent resurgence of the semiconductor chip industry across the globe, and expansion of new fabrication facilities in North America, Europe, and Asia, the semiconductor industry is now poised to become the central global economic driver. Estimates have growth exceeding $1 trillion by 2030 and $2 trillion by 2040. As the global demand increases for new technologies like AI, 5G, Quantum, and IoT, the industry must now be cognizant of the impact of our industry on the environment. There must be an established purpose beyond profits, losses, capacity, and demand to address this now realistic problem. Creating a future semiconductor industry focused on responsible and sustainable innovations is now at the forefront of many semiconductor organizations. NY CREATES is driving the establishment of a Sustainability Test Bed Program that addresses capabilities in the most critical sustainability areas for semiconductor Industry. We will present the program and the successful partnerships like SEMI’s Semiconductor Climate Consortium, and many other sustainability organizations. Having the most advanced shared 300mm Semiconductor Research and Development facility in the world, NY CREATES is now positioned to address this critical global need alongside the important partners in our ecosystem in addition to all our other research efforts.

Biography
Frank Tolic leads the Business Development efforts at NY CREATES. He is a technology executive with 30+ years of semiconductor experience in engineering and business related programs focused on research & development, strategic planning, marketing, sales, and product management.He has managed portfolios of over $1 Billion in business across the globe in support of semiconductor research, equipment, consumable, and technology companies, and has worked in number of commercial semiconductor research organizations as well as consortia and academia such as; Motorola, SEMATECH, Albany Nanotech, AIM Photonics and currently NY CREATES.

Topic Coming Soon

Boeckx, KATLEEN
Business Director Electronics
Nippon Gases

Abstract
Coming Soon

Biography
Katleen Boeckx is the Business Director for Electronics at Nippon Gases. She is a commercial engineer, and after several years working in telecommunications in Germany and the US, she joined Nippon Gases in 2004 as a product manager for semiconductor specialty gases.From 2010 to 2013, Boeckx moved to operations and led the Oevel specialty gases plant in Belgium. She is now responsible for strategically growing Nippon Gases’ semiconductor business in Europe. She is also accountable for providing commercial support to local business teams in all European countries, for further developing key customers and strategic supplier partnerships, and for timely adjusting the product portfolio and associated operational capabilities to the fast-changing market’s needs.

Chipstainability - A Megatrend to Strengthen Europe's Leading Role for Global Collaborations

Wunderer, Stefan
Government Funding Manager
Nokia Solution and Networks GmbH & Co. KG

Abstract
In times of geopolitical unrest, climate change as a global problem has to be tackled by closely collaboration with other nations. Europe should use its leading position in microelectronics sustainability to meet the needs of the present without compromising the ability of future generations. The example of ICT shows how strategic cooperation can be used to reduce energy consumption and embodied emissions in microelectronics. The future-oriented results of a recent IPCEI ME/CT Chipstainability Workshop are presented and discussed.

Biography
Stefan Wunderer is driving future topics in mobile communications since more than 40 years, mostly filling leading positions in network optimisation, customer support and training. Within Nokia, he is head of Nokia's IPCEI ME/CT chip design project in Ulm and Nürnberg and facilitating the RAN Energy Efficiency task force. Additionally, Stefan is lecturing sustainability at the University of Würzburg, leading an international SNS-JU research team for Social Needs and Value Creation as well as working within the Scientists for Future in Cologne. He is actively supporting the working group Women in Telecommunications and Research (WiTaR).

Smart Sensing with Neuromorphic Solutions: A Game Changer for Edge Applications

Ait Mahiout, KAMEL
PRESIDENT & CEO
Novasensing

Abstract
The accelerating demand for IoT, autonomous systems, and secure infrastructures underscores the urgent need for energy-efficient and high-performance sensing platforms. Conventional CPU/GPU-based architectures, despite their computational power, face significant barriers: high power consumption, reliance on advanced silicon nodes, and escalating costs tied to cloud-based data center infrastructures.NOVASENSING presents a disruptive neuromorphic computing approach purpose-built for semiconductor innovation. By eliminating traditional GPUs/CPUs and embedding intelligence directly into an event-driven, massively parallel architecture, our solution achieves sub-100 ns fully parallel processing with power consumption reduced from 1 W to 0.002 W. This design leverages scalable semiconductor nodes (55 nm down to 28 nm) with stackable integration, ensuring both manufacturability and cost-efficiency.The result is a sustainable, ultra-low power platform for smart sensing applications, including predictive maintenance, image and pattern recognition, and security systems. NOVASENSING’s architecture demonstrates how semiconductor design, when inspired by the brain’s efficiency, can drive both next-generation AI performance and eco-friendly scalability, aligning with the semiconductor industry’s roadmap toward energy-efficient, high-ROI solutions.

Biography
Kamel AIT Mahiout, CEO of Novasensing, brings over three decades of leadership in the semiconductor industry, with executive experience at Amkor Technology, Unity SC, and Applied Materials. He is recognized for driving global growth, restructuring organizations, and fostering C-suite collaboration across the ecosystem.

Some Material-Related Reliability Challenges that go with Package Roadmap Needs

Mavinkurve, Amar
Director Materials and Labs Package Innovation, CTO
NXP Semiconductors

Abstract
As the usage of electronics keeps increasing and taking over or enabling or facilitating many tasks in our daily lives, society is becoming increasingly dependent on the useful life validation and related to that reliability and safety. To accurately predict this, it is of the utmost importance to understand the most relevant failure mechanisms in packaging. This presentation will elaborate on some failure mechanisms in packaging materials and interconnects that become steadily more relevant with the ongoing trend towards miniaturization, heterogenous integration and advanced requirements. On one hand, some examples of extrinsic failure mechanisms will be given, impacting yield, and potentially increasing the risk of high impact customer returns. On the other hand, some wear-out failure mechanisms related to interconnect and material degradation will also be presented, towards approaches to increase robustness and predictability of these degradation mechanisms using metrics that can efficiently be monitored using AI techniques.

Biography
Dr. Amar Mavinkurve leads the Global Materials Team within Package Innovation (Core Technologies) at NXP. He completed his PhD in Polymer Science from the University of Groningen in the Netherlands in 1996. This was followed with a stint at Philips Research working on various topics like polymer-metal interfaces, polymer processing and textiles. He joined NXP Semiconductors in 2004 (at that time still Philips) and has worked mainly on packaging materials and reliability with specific interest in interconnect systems and aging behaviour of packaging materials.

Glass Core Substrates: Driving Scalability for HVM Through A Versatile Process Control Solution

Pau, Monita
Strategic Marketing Director for Advanced Packaging
Onto Innovation

Abstract
Heterogeneous integration packaging technologies have seen increased adoption driven by the rapidly growing demand for advanced end applications like artificial intelligence (AI) and high-performance computing (HPC). Research and development of glass core substrates are gaining momentum due to their superior mechanical stability and ability to enable the fabrication of high-density metal interconnects and the integration of optical interconnects. However, due to the brittle and rigid nature of glass, their adoption also poses significant manufacturing challenges. Stringent process control is required starting from the bare glass panel and throughout the entire glass core fabrication and buildup process to ensure high manufacturing yield and product reliability.In this presentation, we will present the integration of a high throughput and multifunctional process control solution starting from the fabrication of through glass vias (TGV) in the glass core. Real-time process control of the laser modification and wet etching process is made possible through the ability to inspect and perform CD measurements across 100% of the panel surface. Besides CD monitoring, we will also demonstrate the ability to detect missing and abnormal TGV as these defects can directly impact the electrical performance of the product. Glass is brittle and prone to cracking or chipping during handling and processing. Microcrack detection before and after metallization is crucial to help detect the mechanical damage early to avoid for downstream yield loss.With its unique integrated metrology and inspection capability, the same in-line process control solution can also be applied throughout the buildup process. From monitoring the defectivity and CD of the traces post-patterning and metallization, to the 3D measurement of RDL/bump height and panel warpage. This enables for real-time response to variations in material, equipment and process conditions and ensure high productivity and manufacturing yield.To realize the full benefits of glass as a core material for advanced IC substrate to enable high density interconnects, an advanced inspection and metrology solution is vital. Its multi-functionality and flexibility to handle a wide range of panel sizes up to 650mm x 650mm provides the industry a scalable path to bring glass core substrate from research and development to high volume manufacturing by the end of this decade.

Biography
Monita Pau currently serves as the Strategic Marketing Director for Advanced Packaging at Onto Innovation. With over 15 years of experience, she has held various positions in applications engineering, marketing and strategic business development in both semiconductor capital equipment and electronic materials companies. Her expertise spans across frontend and backend of line process control solutions as well as materials for advanced packaging and assembly. Monita holds a Ph.D. degree in Chemistry from Stanford University.

High speed oxide reduction and large die capillary underfill wettability improvement by ICP downflow plasma treatment

Furukawa, Ryota

Panasonic Connect Co., Ltd.

Abstract
Plasma cleaning technology has been widely used in microelectronics assembly processes. In the case of lead frames and power modules for automotive devices, the oxidation of Cu can easily occur through multiple heat processes, and this Cu oxide is detrimental to molding adhesivity.This poor moldability often causes delamination issues and the ‘popcorn effect’ in packages.Until recently, H₂/Ar mixed gas plasma treatment has been used to remove such oxides in order to eliminate poor moldability issues, but in this case, undesirable cross-contamination of Ag from pad material can occur due to physical ion bombardment effects.In addition, the oxide removal rate of H₂/Ar plasma treatment with a Reactive Ion Etching (RIE) parallel-plate configuration is quite slow and not uniform on the entire substrate.In order to realize a high-speed oxide reduction rate and no cross-contamination etching, Panasonic has developed a water vapor plasma treatment with an Inductive Coupled Plasma (ICP) downflow configuration.More than 100 nm/min oxide reduction rate was achieved, with excellent etching uniformity using this ICP downflow plasma treatment.In this case, oxide removal is almost completely achieved by OH and H radicals’ chemical reaction, so there are no cross-contamination issues.Plasma cleaning has also been used to improve capillary underfill wettability in flip-chip packaging. Delamination, crack, and void issues were avoided by utilizing oxygen-based plasma treatments after flip-chip bonding.However, recently, die sizes for advanced 2.5D/3D packages have increased, which has caused conventional parallel-plate RIE oxygen-based plasma treatment to have insufficient surface modification effect on the chip and substrate surfaces, as the oxygen radicals cannot reach the center part of the large dies.In this case, also, ICP downflow plasma treatment offers a solution.ICP plasma has double-digit higher plasma density than conventional parallel-plate RIE plasma systems, enabling high-density oxygen radicals to penetrate into the narrow gap between the chip and the substrate, and offers excellent surface modification effects, even at the center of large 80 mm square dies, for example.As a result, Panasonic is able to achieve high-speed oxide reduction processes without cross-contamination by water vapor plasma treatment, and large die capillary underfill wettability improvement by oxygen-based plasma treatment, with ICP downflow configuration plasma systems.

Biography
Ryota Furukawa is a staff engineer at Panasonic Connect Co., Ltd, currently in charge of plasma cleaning process development and sample builds.In 1990, he joined Kyushu Matsushita Electric Co., Ltd as a process engineer. Since then, he has been in charge of R&D activities and product development, and the development of plasma cleaning processes and dry etching processes. He received a master’s degree of radio chemistry from Kyushu University, Japan.

Integration and Assembly of Co-Packaged Optics (CPO) for smart Networks and Switches

Sundararajan, Anneirudh
Project Leader - Photonics Packaging
PHIX Photonics Assembly

Abstract
The rapid scaling of data center bandwidth requirements is pushing the limits of traditional pluggable optical modules, leading to the emergence of Co-Packaged Optics (CPO) as a promising solution for next-generation network interface cards (NICs) and switch architectures. This presentation outlines a collaborative workflow and integration scheme for CPO systems, highlighting the step-by-step assembly of photonic integrated circuits (PICs), drivers (EICs), and high-bandwidth fiber optics connectors for smart networking devices. We describe the joint contributions from key industrial and research partners—including Teramount (TM), AT&S, IMEC, PHIX, and NVIDIA—covering substrate design, optical/electronic die integration, and high-precision flip-chip bonding. Emphasis is placed on the alignment precision and thermal stability required for the successful coupling of fiber arrays, drivers (EICs) to PICs. The final packaging steps are optimized for signal integrity and thermal management to enable deployment in high-performance data center environments.

Biography
Anneirudh Sundararajan is a Project Leader at PHIX Photonics Assembly, where he leads several EU-funded initiatives as well as customer-driven projects. He specializes in flip-chip bonding technology and the advanced packaging of photonic integrated circuits (PICs). Prior to joining PHIX, Anneirudh worked in Germany as a Process Development Engineer at a photonic packaging company, gaining hands-on experience in scalable photonic assembly processes. Anneirudh pursued his PhD at the University of Twente, where his research focused on the integration of optical components with MEMS-based microfluidic systems. His work involved the development of Coriolis mass flow sensors and spectroscopic techniques for multiparameter fluid characterization. With a strong interdisciplinary background in optics, microfluidics, and photonic packaging, he is actively contributing to the development of next-generation photonic sensing platforms.

European Pilot Lines: Aligning Strategy, Efficiency, and Implementation

Pruneri, Valerio
Director
PixEurope

Abstract
Soon

Biography
Soon

Optimized Real-Time Production Scheduling in 300mm Fabs

Knopp, Sebastian
CTO
Planimize

Abstract
Scheduling decisions are critical in semiconductor manufacturing, especially in fully automated fabs. The Planimize Schedule Optimizer provides 24/7 real-time scheduling to steer activities in work centers such as photolithography and diffusion/cleaning. At its core is a powerful algorithm, based on years of academic research, capable of generating optimized schedules for thousands of lot steps in under one minute. It handles the full range of operational constraints, including mask handling, lot transportation, batching, and time constraints. Schedules are evaluated with all dependencies between lot steps taken into consideration. KPIs such as equipment throughput, cycle time, transport efficiency, and production targets are improved by considering them as optimization objectives in a mathematical model. The software is designed for seamless integration into existing MES environments. The Planimize Schedule Optimizer has been running continuously and reliably since 2023 in fully automated 300mm front-end fabs in Europe. In this talk, we present an overview of the algorithm and the real-world implementation of the software in production fabs.

Biography
Sebastian Knopp co-founded the company Planimize in 2021 where he currently serves as CTO, focusing on the development of optimization software to enhance factory efficiency. He completed his PhD Thesis on scheduling in semiconductor manufacturing (Saint-Etienne, France, 2016) and has a degree in computer science (Karlsruhe, Germany, 2006). Before founding Planimize, he worked at different companies on optimization software in the domains of logistics and education.Stéphane Dauzère-Pérès is Professor at Mines Saint-Etienne in its site of Gardanne, France. He received the Ph.D. degree from Paul Sabatier University in Toulouse, France, in 1992 and the H.D.R. from Pierre and Marie Curie University, Paris, France, in 1998. He was a Postdoctoral Fellow at M.I.T., U.S.A., in 1992 and 1993, and Research Scientist at Erasmus University Rotterdam, The Netherlands, in 1994. He has been Associate Professor and Professor from 1994 to 2004 at the Ecole des Mines de Nantes, France. His research interests broadly include modeling and optimization of operations at various decision levels (from real-time to strategic) in manufacturing and logistics, with a special emphasis on production planning (lot sizing) and scheduling, and on semiconductor manufacturing. He has published more than 115 papers in international journals and has contributed to more than 250 communications in national and international conferences. Stéphane Dauzère-Pérès has coordinated numerous academic and industrial research projects, including 4 European projects and 31 industrial (CIFRE) PhD theses. He was runner-up in 2006 of the Franz Edelman Award Competition, and won the Best Applied Paper of the Winter Simulation Conference in 2013 and the EURO award for the best theory and methodology EJOR paper in 2021.

Photonic Integrated Circuits for LiDAR: Enabling 4D Machine Vision with PICs

Nicolaescu, Remus
Managing Director
Pointcloud

Abstract
Detailed and accurate three dimensional (3D) mapping of dynamic environments is essential for machines to interact with their surroundings, and for human machine interaction. While considerable effort has been spent in order to create the equivalent of the CMOS image sensor for the 3D world, scalable, high performance, reliable solutions have proven elusive. Focal plane array (FPA) sensors using frequency modulation (FM) light detection and ranging (LiDAR) have shown potential to meet all the requirements and also provide direct measurement of radial velocity as a fourth dimension (4D). In this talk we present the latest results in the development of large scale, high performance coherent LiDAR FPAs enabled by comprehensive chipscale optoelectronic integration. An overview of performance of a 352x176 pixels two dimensional FM LiDAR FPA comprising over 0.6 million photonic components with all photonics and associated electronics components integrated on chip will be presented, as well as future development directions.

Biography
Remus Nicolaescu is the Co-founder and Managing Director of Pointcloud GmbH/Inc., a Zurich based technology company developing coherent 4D imaging solutions using silicon photonics. Prior to Pointcloud, he held executive roles with technology companies in the US, Europe and Asia. He started his career at Intel, where he performed pioneering work in silicon photonics topics, such as optical Raman amplifiers and lasers in silicon waveguides, and high-speed silicon photonics modulators. He obtained his Masters and Ph.D. in Physics from University of Bucharest and Texas A&M University respectively, and MBA from INSEAD.

From Complexity to Advantage: Strategic Levers for Future Ready Fabs

Notarnicola, Giovanni
Partner
Porsche Consulting

Abstract
In a climate of geopolitical instability and market contraction, especially in automotive and energy-linked segments, European semiconductor players must rethink how to stay competitive. Can AI truly revolutionize one of the most time-consuming and costly steps in the fab journey, such as product qualification? Possibly, but only if companies learn to unlock the value of the data they already have.This session explores how collaboration across traditionally siloed domains, technology, operations, and digital, can generate real-world efficiency and speed. We’ll share concrete examples and pragmatic insights from the field, showing how to build the right ecosystem of specialized capabilities to enable faster, more resilient fab scale-up.

Biography
TBD

European Pilot Lines: Aligning Strategy, Efficiency, and Implementation

Guttowski, Stephan
Managing Director of the Research Fab Microelectronics Germany (FMD)
Research Fab Microelectronics Germany (FMD)

Abstract
Panel discussion

Biography
Stephan Guttowski studied electrical engineering at TU Berlin and subsequently earned a doctorate in the field of electromagnetic compatibility. This was followed by a postdoctoral position at Massachusetts Institute of Technology (MIT) in Cambridge, USA. After his return, he initially worked in the Electric Drives Research Laboratory of DaimlerChrysler AG before moving to the Fraunhofer Institute for Reliability and Microintegration IZM in 2001. At IZM, he was initially head of the Advanced System Development Group before taking over at the System Design & Integration department. From June 2017 to December 2020, he was Technology Park Manager for Heterointegration at the Research Fab Microelectronics Germany (FMD). Since January 2021, he has led the joint office of the Fraunhofer Group for Microelectronics and FMD.

Robust SiC MOSFET Devices for Drive Train Applications

Schwaiger, Stephan
Automotive Electronics
Robert Bosch GmbH

Abstract
SiC technology replaces its silicon competitor in many automotive applications, especially in drive train inverters for high voltage batteries of electric vehicles. Using the higher efficiency in partial load operation, SiC traction inverters outperform Si inverters and allow to extend the range of an electric car. As a result, SiC technology gained market shares and many semiconductor players took significant development efforts to improve the SiC MOSFET performance, i.e. reducing the on-state resistance with the goal to enable smaller and cheaper traction inverters. However, also other improvements, e.g. improvements in switching behavior or the integration of new features like sensing elements improve the applicability on system level.This talk provides an overview of SiC MOSFET technology for drive train applications. It sums up the key performance indicators for a technology enabling a performant design of a drive train inverter. Furthermore, the talk discusses the advantages of integrating sensing elements on chip level and gives an insight on measures to increase robustness necessary to maintain high quality products with low failure rates. The talk provides an insight into recent advances of Bosch’s SiC technology designed for reliable, high performance automotive applications.

Biography
Stephan Schwaiger studied physics at the university of Hamburg and finished with a doctorate degree in 2012. He started in semiconductor industry in Bosch’s central research department working power semiconductors. Since 2015 he works on the development of SiC semiconductors for the section Automotive Electronics at Bosch focusing on technology and device development.

Inertial and Beyond – High performance for location and navigation

Abel, Emma
VP Engineering
Robert Bosch GmbH

Abstract
Inertial and magnetic sensors are essential pillars of a wide range of location and navigation applications. MEMS has conquered most of the inertial sensors market with good spec values at continuingly competitive prices and form factors thanks to CE synergies – where are the limits and how does this approach compare to other solutions? Leveraging increased accuracy of innovative magnetic sensors based on TMR and quantum technologies has the potential to open new navigation use cases and more.

Biography
Emma is VP Engineering at Robert Bosch GmbH in Reutlingen Germany and heads R&D for MEMS Sensors there. She joined the Bosch Group in 2002, and has since held various positions in field of MEMS, semiconductors and sensor R&D within various business units within BoschShe is a MEMS enthusiast, with previous roles including inertial sensor development, functional safety and MEMS Sensor industrialization for consumer electronics. Her current focus is on diversification in MEMS Sensors and their use in intelligent systems.Emma received her Masters Degree in Electronic and Electrical Engineering from the University of Strathclyde, in UK

Topic Coming Soon

Avice Huet, Gwenaelle
Executive Vice President of Europe Operations
Schneider Electric

Abstract
Coming Soon

Biography
Gwenaelle Avice Huet has been Schneider Electric’s Executive Vice President of Europe Operations since September 4, 2023 and serves on its Executive Committee. She is responsible for Schneider Electric’s full business portfolio across Europe Operations, representing the company’s contribution to the development of the EU’s agenda to accelerate Europe’s green and digital transformation.Gwenaelle joined Schneider Electric in 2021 as Senior-Vice President of Corporate Strategy, before entering the Executive Committee as Chief Strategy and Sustainability Officer. Before joining Schneider Electric, Gwenaelle worked at ENGIE (formerly GDF SUEZ) in various roles, from Senior Vice-President of European and Regulatory affairs, to leading the Renewables energy business. In her last role, she was on the Executive Committee of ENGIE, serving as the Chief Executive Officer of ENGIE North America and in charge of the Global Business Line on Renewable Energies.Gwenaelle started her career at the French National Centre for Scientific Research and the French Atomic Energy Commission on nuclear energy before joining the World Bank in Washington D.C. as a consultant. She also worked for the service of the French Prime Minister within the General Secretary of European affairs with responsibility for energy and competitiveness matters, and as the advisor on energy and climate change for various ministers.Gwenaelle also serves on the Board of Air France – KLM. She holds a degree in Physics and Chemistry from the Ecole Normale Supérieure Paris-Saclay, a post-graduate diploma in Molecular Chemistry from France’s Ecole Polytechnique and an engineering degree from the Corps des Ponts et Chaussées. She has also been nominated as a Young Global Leader by the World Economic Forum. She is based in Europe.

Opening Remarks

Manocha, Ajit
President and CEO
SEMI

Abstract
Opening Remarks

Biography
Throughout his career, Ajit Manocha has been a champion of industry collaboration as a critical means of advancing technology for societal and economic prosperity. He has been adept at forming strong partnerships with customers, suppliers, governments, academia, and communities for these efforts.In his current role as President and CEO of SEMI, the global industry association serving the electronics manufacturing supply chain, Manocha has positioned the organization to tackle major challenges facing the industry by building up workforce development programs to address its growing talent shortage and lack of gender parity.Previously, he held senior worldwide operations leadership roles at Philips Semiconductors (NXP) and Spansion before serving as President and CEO at GLOBALFOUNDRIES. He has served on the boards of SEMI, SIA, and GSA.Manocha began his career as a research scientist at AT&T Bell Laboratories, where he was granted over a dozen patents related to semiconductor manufacturing processes that served as the foundation for modern microelectronics manufacturing.Manocha was an advisor to President Obama on the Advanced Manufacturing Partnership Steering committee and on the President’s Council of Advisors on Science and Technology (PCAST). In 2012, during his tenure at GLOBALFOUNDRIES, he was awarded the prestigious “EHS Achievement Award — Inspired by Akira Inoue” for his commitment and action on Environmental Health and Safety standards. Additionally, he has excelled in people development by teaching courses such as “Leadership by Example” and “Classroom to Cleanroom to Boardroom.”In December 2019, Manocha was named an “All Star of the Semiconductor Industry” by VLSI Research for his visionary leadership in restructuring SEMI from its traditional position to represent the expanded electronics supply chain. In February 2020, he was inducted into the Silicon Valley Engineering Hall of Fame.

Building the Future: Global Fab Investment, Capacity Dynamics & Materials Market Outlook

Tseng, Clark
Sr. Director
SEMI

Abstract
The global semiconductor sector stands at a critical turning point, fueled by surging demand for AI, high-performance computing, and emerging technologies. This momentum is sparking record-breaking capital investments and breakthroughs throughout the ecosystem, from cutting-edge semiconductor fabs to advanced materials development.However, this expansion occurs against a backdrop of increasing volatility, including fluctuating trade policies, tariff adjustments, and geopolitical challenges that complicate investment strategies, supply chains, and sustained industry leadership.In this session, we will provide an in-depth review of SEMI’s most recent World Fab Forecast, spotlighting worldwide patterns in capital equipment expenditures, fab development, and capacity growth projections through 2028. We will delve into the role of government subsidies and regulatory changes in redirecting new fab initiatives and transforming the international semiconductor ecosystem.Additionally, we will assess the shifting demands for wafer fab materials as the industry navigates swift technological advancements. Participants will leave with actionable perspectives on aligning materials innovation and supply chain robustness with broader investment patterns to propel the semiconductor industry's next phase of advancement.

Biography
Clark Tseng is the Senior Director of Market Intelligence at SEMI. He is responsible for developing and executing global strategies that provide high-quality market research products and services, which monitor and analyze the dynamics of the semiconductor manufacturing supply chain.Clark specializes in analyzing and forecasting various microelectronics industries, including IDM, Fabless, Foundry, Memory, and OSAT, with a focus on the Asia-Pacific and China markets. Additionally, he oversees SEMI's global research partnerships.Clark has held several strategic and analytical roles in leading microelectronics companies before joining SEMI. At MediaTek, he served as Deputy Director of the Computing, Connectivity, and Metaverse Business Group. In this role, Clark provided market intelligence and competitive analysis for Computing (HPC/ASIC), Connectivity (5G/Wi-Fi), and Multimedia (XR and Auto) domains. Prior to that, he served as the division manager for Strategy and Business Development at Qimonda, where he oversaw market and competitive intelligence functions in the Asia/Pacific region. Clark began his career as an analyst at IDC, covering semiconductor, flat-panel display, and telecommunications markets.Clark holds a Bachelor of Business Administration and a Bachelor of Arts in International Relations from National Chengchi University in Taiwan.

SEMI MEMS & Sensors Industry Group (MSIG) Update

Carey, Paul
Director, SEMI MEMS & Sensors Industry Group
Semi

Abstract
The MEMS & Sensors Industry Group (MSIG), a SEMI technology community, continues to drive innovation and collaboration across the global MEMS and sensors ecosystem. In this presentation, MSIG will provide an update on its latest initiatives, strategic priorities, and industry engagement efforts. Highlights will include progress on key working groups and its R&D funding program. Attendees will gain insights into MSIG’s role in shaping the future of sensing technologies, fostering cross-sector collaboration, and supporting emerging applications in automotive, healthcare, industrial, and consumer markets. This update will also outline upcoming opportunities for member involvement and preview MSIG’s roadmap for the coming year.

Biography
Dr. Paul Carey has been the Director of the SEMI MEMS & Sensors Industry Group, MSIG, since 2021. He is responsible for managing MSIG including its US Government funded 2022-2027 (5-year) $25M Positioning, Navigation, and Timing (PNT) R&D program, online webinars, member outreach, and promoting MSIG’s mantra, “we help member companies sensorize the world!”Before joining SEMI, he worked at X-Ray imaging backplane supplier, dpiX (now called InnovaFlex Foundry) in process and equipment engineering management roles, Applied Materials, and FlexICs, a start-up company he co-founded. In earlier positions he was a postdoc at Siemens corporate research labs in Munich as well as a staff scientist and program leader at Lawrence Livermore National Laboratory where his group initially developed the low temperature polysilicon-on-plastic TFT technology.Dr. Carey received a double major BS from UC Berkeley in Electrical Engineering and Computer Science (EECS) and Materials Science and Engineering (MSE). He received his MS in EECS from UC Berkeley and Ph.D. in MSE from Stanford University.

Welcome Remarks

Altimime, Laith
President
SEMI Europe

Abstract
Welcome Remarks

Biography
Laith Altimime, as President of SEMI Europe, leads SEMI’s activities in Europe and the Middle East and Africa (EMEA). Altimime has P&L responsibility as well as ownership of all Europe region programs and events, including SEMICON Europa. He is responsible for establishing industry standards, advocacy, community development, expositions, and programs. He provides support and services to SEMI members worldwide that have supply chain interests in Europe. He manages and nurtures relationships with SEMI members in the region and globally as well as with local associations and constituents in industry, government, and academia. Altimime has more than 30 years of international experience in the semiconductor industry. Prior to joining SEMI in 2015, He held senior leadership positions at NEC, KLA-Tencor, Infineon, Qimonda, and imec. Altimime holds an MSc from Heriot-Watt University, Scotland.

Embedding Inclusion in Europe’s Semiconductor Strategy: Insights from ECDA

Srivastava, Kartikey
Senior Specialist, Communications
SEMI Europe

Abstract
Europe’s ambition to lead in semiconductors depends not only on growing the talent pool, but on ensuring that talent reflects the full diversity of Europe’s population. The European Chips Diversity Alliance is tackling this challenge by working to build a more inclusive and equitable semiconductor ecosystem. Through collaboration between academia, industry, and underrepresented communities, ECDA is helping to dismantle barriers to entry, drive culture change, and ensure that opportunities in chips are open to all.This talk will share findings from ECDA’s first DEI Report, highlighting the current state of this topic in Europe’s semiconductor industry and areas for action. It will also explore how ECDA is embedding inclusion into the future of chips, and how these efforts complement broader skills and sovereignty goals across the European semiconductor landscape.

Biography
Kartikey Srivastava is a Senior Specialist - Communications at SEMI Europe, where he focuses on strategic dissemination and exploitation efforts for several high-impact Erasmus+ and Horizon Europe projects, including HiCONNECTS, the European Chips Skills Academy, the European Chips Diversity Alliance, and METIS4Skills. His work has a strong emphasis on increasing the visibility, outreach, and long-term impact of EU-funded initiatives in the semiconductor and microelectronics sectors. At SEMI Europe, Kartikey develops and implements comprehensive communication strategies, creates compelling narratives for stakeholder engagement, and ensures alignment with project objectives and European Commission guidelines. He holds an MBA from ESMT Berlin, and a Master’s degree in International Political Economy from King’s College London.

Opening remarks

Cummings, Victoria
Senior Manager, Workforce Development and EU Projects
SEMI Europe

Abstract
Europe’s semiconductor industry will face a talent gap of 75,000 professionals by 2030. Addressing skills shortages, attracting and retaining talent, and fostering diversity are essential to sustaining innovation and competitiveness. At the same time, global collaboration is key to building resilient supply chains and advancing technological leadership through the Pilot Lines. This session will explore practical approaches to education, workforce development, cross-border cooperation, and inclusive talent strategies to secure Europe’s position in the semiconductor ecosystem.

Biography
Since joining SEMI Europe in 2023, Victoria manages projects that support workforce development, including the development of educational materials, awareness raising, and programs to improve DEI in the semiconductor sector. Currently, she oversees the European Chips Skills Academy (ECSA) and European Chips Diversity Alliance projects and is involved in several European projects related to skills development and education in microelectronics. Through these projects, Victoria contributes to the creation of targeted programs to attract and upskill talent for the most critical job shortages, assess employment trends and identify barriers to entry for underrepresented groups. Prior to entering the semiconductor industry, Victoria worked as a policy adviser for regulation on financial services and energy markets. She received a master’s degree in political science from Boston University in 2018.

Silicon Carbide in AC Motor Drives

Puukko, Joonas
Senior Field Application Engineer
Semikron Danfoss

Abstract
With recent technological advancements, silicon carbide is becoming the first choice for enabling energy savings and increasing power density. However, motor drives and silicon carbide MOSFETS are two topics that seemed impossible to combine: high costs, fast switching transitions, lack of short circuit capability, and reliability concerns were all persistent roadblocks, preventing a tangible return on investment. But it is time to rethink. By merging state of the art packaging technology with the latest generation of SiC MOSFETs, we provide a totally new degree of design freedom to motor drive design engineers.

Biography
biography

Strain Monitoring for High-Performance Semiconductor Devices by in-line Raman spectroscopy

Szekrényes, Zsolt
Head of Optical Spectroscopy & Inspection Department
Semilab Zrt.

Abstract
The growing demand to precisely control the various parameters and material properties of the next-generation semiconductor devices paves the way for spreading the application of new materials and metrologies in the semiconductor industry. Fast, non-invasive, and non-destructive measurement techniques are essential to provide valuable information on material properties and enable innovation in device performance. At SEMICON Europe, Zsolt Szekrényes will present Semilab’s latest research on cutting-edge in-line metrology for next-generation Fully Depleted Silicon-On-Insulator (FD-SOI) devices. His talk will highlight the use of Raman spectroscopy to evaluate strain and crystalline quality of ultrathin Si and Ge layers on Si wafer.

Biography
Zsolt Szekrényes is the head of optical spectroscopy & inspection department in Semilab and joined the company 10 years ago, in 2015. He holds a Diploma in Physics and a PhD in Material Science and Technology. He also contributed to multiple publications and conferences. With his wide knowledge in optical metrologies, he supervises various metrology developments and research in the fields of spectral photoluminescence, Raman spectroscopy and other imaging inspection technologies delivered for microLED, compound and semiconductor industry.

SETT: Spain’s Commitment to Strengthening Europe’s Semiconductor Ecosystem

Ponce, Francisco Javier
CEO, SETT
Sett Sociedad Española para la Transformación Tecnológica

Abstract
SETT, as a Spanish public business entity, offers opportunities for public-private collaboration through co-investment in strategic projects that contribute to Europe's strategic technological autonomy.Introducing PERTE Chip - Strategic Project for Economic Recovery and Transformation for Microelectronics and Semiconductors is a public-private initiative in Spain that seeks to boost semiconductors sector through transformative projects.Spain promotes PERTE Chip and other co-investment instruments within a framework of stable and sustained growth, affordable energy, infrastructure, and talent—key drivers for enhancing European competitiveness and leadership in the semiconductor sector.

Biography
Francisco Javier Ponce MartínezCEO of SETTIndustrial engineer from the Polytechnic University of Madrid and holder of a Master's Degree in Business Administration (MBA) from the Instituto de Empresa (IE). He began his professional career at the Spanish National Research Council (CSIC), holding various positions of responsibility at the CDTI (Center for Technological Development and Innovation) for more than 30 years.He began working at the CDTI in 1992, taking on the role of International Director of the CDTI as Spanish delegate to the European Union's R&D Programs during Framework Programs III and IV until 1998. Other notable positions within the CDTI include Head of the Spanish Presidency Office of the Eureka International Program for Technological Cooperation and Head of the Studies and Promotion Department between 2001 and 2010. From 2012 to 2018, he was Economic and Financial Director, assuming the role of Director General of the CDTI from 2018 to January 2024.In March 2024, he joined the Spanish Microelectronics and Semiconductors Society (SEMyS) as Deputy Director General.He is currently CEO of SETT.

Production-Proven Chemical-Free Green Alternative to Solvent and Piranha Wafer Processing using Ozone

Sundin, Phillip
Business Development Manager
Shellback Semiconductor Equipment

Abstract
Efforts to implement green technologies in semiconductor manufacturing have historically been slow with acceptance, blocked by perceived concerns over performance risk, operational disruption, and cost. Nowhere is this more apparent than in photoresist stripping, where aggressive chemistries like sulfuric-peroxide mixtures and hazardous solvents like NMP and DMSO remain standard, despite their well-documented environmental burdens. This paper presents a comprehensive assessment of a novel process that offers a rare and timely exception: chemical-free resist removal using ozone gas diffused through heated deionized water.Unlike ozone-dissolved water systems this method operates in a high-temperature, ozone-rich gas environment. The result is rapid, surface-driven chemical deconstruction of the resist polymer, eliminating the need for persistent oxidizers or solvents, while producing minimal downstream contamination. Comparative lifecycle analysis across chemical input, energy use, waste generation, worker exposure, and effluent treatability reveals a substantial reduction in environmental burden—without compromising technical requirements. Measured CO₂e emissions per wafer are reduced by over 70% relative to sulfuric-peroxide and solvent-based strip methods. Tool-level performance data confirms comparability with common process chemistries, complete resist removal, and throughput on par with legacy methods.The maturity of this process approach marks a departure from previous “green tech” proposals that failed to meet manufacturability thresholds. At a time when fabs face mounting pressure from hyperscaler customers, EU carbon regulation, and Scope 3 accounting mandates, this process uniquely aligns technical performance with immediate sustainability impact. Its adoption represents a meaningful step forward in closing the longstanding gap between sustainability goals and operational realities.The paper will first substantiate its environmental advantages through modeled CO₂e comparisons per wafer, based on documented chemical usage rates for conventional and ozone-based strip processes. It will then confirm the technical soundness of the method—grounding its effectiveness in known reaction pathways and supporting it with fab-level data on resist removal, compatibility, and defectivity. Together, these findings show that the process can be deployed now—without tradeoffs—to meet rising green manufacturing demands.

Biography
Phillip SundinBusiness Development Manager at SHELLBACK Semiconductor TechnologyPhillip Sundin is a seasoned professional in the semiconductor equipment industry with over 3-decades of experience with wet-processing equipment. He is currently serving as the Business Development Manager at SHELLBACK Semiconductor Technology. In this role, he plays a pivotal part in driving the company's expansion and customer engagement efforts.At SHELLBACK, Phillip has been instrumental in the company's global growth initiatives. A notable focus is the increased awareness and adoption of the Torrent Eco-Clean system, which incorporates SHELLBACK's award-winning HydrOzone chemical-replacement technology. This environmentally safe surface preparation system can reduce or eliminate the need for traditional chemicals, aiding clients in achieving their greenhouse gas reduction goals. The Torrent system is particularly significant in supporting the semiconductor industry's projected expansion to a $1 trillion valuation by 2030.Phillip's expertise lies in identifying and capitalizing on emerging market opportunities within the semiconductor sector, particularly involving wet-processing equipment. His strategic insights, leadership and passion have been critical in positioning SHELLBACK as a key player in the semiconductor equipment industry.

European Pilot Lines: Aligning Strategy, Efficiency, and Implementation

La Via, Francesco

SiC Epitaxial Growth

Abstract
Soon

Biography
Soon

Beyond Simulation: Challenging the status quo

Westrich, Katharina
Global VP of Electronics & Semiconductors
Siemens AG

Abstract
Europe’s ambition to double fab capacity by 2030 is more than a growth target – it’s a call to rethink how fabs and assembly lines are planned, build built and run. At Siemens, we’re answering that call by combining the real and digital worlds to optimize the chip and fab lifecycle—unlocking new levels of efficiency, resilience, and transparency. What if every decision in fab planning and operations could be validated virtually—before a single foundation is laid, a system installed, or a solution deployed? With digital twins, AI-driven analytics, and our deep semiconductor expertise, this future is already taking shape. Building the fabs of tomorrow also demands robust, future-ready infrastructure —from intelligent facility and building systems, efficient electrification solutions to resilient power grids—all seamlessly integrated. But the transformation doesn’t stop with the fab: Our PLM data backbone and EDA portfolio connect the entire chip lifecycle: from ideation and IP management, through accelerated design & verification powered by predictive simulation codes and all the way to manufacturing planning and high-yield production driven by MES and data-driven modelling. At Siemens, we’re not just imagining the future of fabs— we are realizing it. Virtually and physically.

Biography
Katharina heads Siemens’ global activities for Electronics & Semiconductor, leading a team dedicated to unlocking the potential of resilient, smart, and sustainable semiconductor manufacturing across the entire value chain. As an elected member of the Semiconductor Climate Consortium (SCC) Governing Council, Katharina reinforces her commitment to drive positive change within the semiconductor ecosystem. Her dynamic leadership places her at the forefront of digitalization and sustainability solutions – transforming the everyday through innovative technologies.

Digital Twin-Enabled Heterogeneous Package Assembly: AI-Driven Yield Optimization Through Early Design and Equipment Modeling

Dudek, Heiko

Siemens EDA

Abstract
As heterogeneous integration and advanced packaging technologies become crucial enablers for next-generation electronics, manufacturing yield optimization presents unprecedented challenges. This paper introduces an innovative approach that bridges the gap between package design and manufacturing through advanced digital twin modeling of assembly equipment, enabling predictive yield optimization at the design stage which ultimately will decrease time to market by reducing the number of prototypes required. Our methodology implements a comprehensive Assembly Design Kit (ADK) framework that incorporates both physical equipment constraints and process variations.

Biography
Heiko Dudek joined Siemens Digital Industries in 2021, and holds a M.Sc. in Electrical Engineering from University of Applied Science, Munich. He is in EDA for 27 years, holding various positions, including application engineering, R&D, services and technical sales. These days his is looking after solutions around 3D-IC & Heterogeneous Advanced IC Packaging within Europe.

Advances in Wafer-Level MEMS Packaging: From Harsh Environment Sensors to Quantum Applications

Roshanghias, Ali
Head of Research Unit for Heterogeneous Integration Technologies
Silicon Austria Labs GmbH

Abstract
Advanced packaging are key to unlocking the full potential of MEMS sensors, particularly in applications requiring miniaturization, robustness, and extreme environmental tolerance. This talk will focus on recent innovations in wafer-level integration and packaging of MEMS sensors at Silicon Austria Labs, highlighting their critical role in enabling high-performance sensing systems.We will present two recent success stories that demonstrate the capabilities of advanced wafer-level packaging approaches. The first involves the integration and hermetic packaging of MEMS sensors designed for harsh environments exceeding 250 °C, addressing challenges such as material compatibility, thermal stress, etc. The second case explores the development of a chip-scale quantum sensor achieved through wafer stacking and heterogeneous integration, showcasing the potential of MEMS technologies in emerging quantum applications.

Biography
Dr. Ali Roshanghias is the head of the research unit for heterogeneous integration technologies (HIT) at Silicon Austria Labs (SAL). He received his Ph.D. in materials science and technology in 2012. He pursued his career as a post-doc researcher in Japan and Austria in the fields of electronic materials and advanced microelectronics packaging. In 2015 he joined Silicon Austria Labs (formerly known as CTR Carinthian Tech Research AG). His research interests include heterogeneous integration technologies, interconnect materials, hybrid flexible electronics, and 3D integration

Is ultrahigh-vacuum technology potential to develop surface passivation for imaging sensors?

Jahanshah Rad, Elmira Zahra

SisuSemi Ltd

Abstract
Even if high-vacuum (HV, 5‧10^-8 - 1‧10^-4 mbar) technology has been used in the current silicon technology, ultrahigh vacuum environment (UHV, 1‧10^-12 - 5‧10^-8 mbar) is still rare in the Si industry. So far UHV has been utilized, particularly, in industrial UHV-CVD (chemical vapor deposition) instruments to grow SiGe transistors and highly doped source/drain contact areas. However, UHV methods have been often considered complex for large scale Si industry. On the other hand, a problem with HV is that time for adsorbing impurity (or contamination) atoms from HV environment on a solid surface to cover it completely is very short: e.g. about 1 s when the background pressure is 1‧10^-6 mbar. In other words, it is very difficult in practice to avoid the incorporation of impurity atoms into Si-device surfaces and to prepare atomically clean Si surfaces with the current industrial methods. In contrast, UHV provides ultraclean environment to modify well-defined Si surfaces or interfaces before they become contaminated by environment impurities. For example, if the background pressure is 1‧10^-10 mbar in UHV instrument, then surfaces remain clean for 10 000 s during a fabrication process. When an atomic level control of Si device surfaces and interfaces is considered, UHV environment could provide a clear benefit to the Si technology. For instance, performance of the CMOS-based imaging sensors depends strongly on atomic level point defects at Si interfaces [1-4] because defect levels increase the dark (or leakage) current of sensors via increased thermal generation of carriers via defect levels. Thus, durable passivation of these defects is relevant to development of the devices. Here we present a feasible route to integrate benefits of UHV technology with industrial methods to develop the surface passivation. Our results show that applying UHV-based treatments reduces defect density, leakage current, and power consumption in Si based devices. [1] M. Bigas, et al. Review of CMOS image sensors, Microelectronics Journal 37 (2006) 433.[2] J. L. Regolini, et al. Passivation issues in active pixel CMOS image sensors, Microelectronics Reliability 47 (2007) 739.[3] J.-P. Carrère, et al. CMOS Image Sensor: Process impact on Dark current, IEEE International Reliability Physics Symposium (2014).[4] A. S. Alj, et al. Dark Current and Clock-Induced Charges in a Fully Depleted Charge Domain CDTI-Based CCD-on-CMOS Image Sensor, IEEE Sensors Journal 24 (2024) 25652.

Biography
Zahra (Elmira) Jahanshah Rad is a Ph.D. candidate at the University of Turku with over eight years of experience in high and ultrahigh vacuum systems, semiconductor device structures, and surface science. She has authored more than 26 peer-reviewed publications and is the inventor of six patents in semiconductor technology. Zahra is the Chief Technology Officer and co-founder of SisuSemi Ltd., a Finnish startup developing energy-efficient semiconductor solutions. Her work focuses on improving the power efficiency and operational lifespan of silicon-based devices through advanced surface and vacuum engineering. She is committed to translating scientific research into sustainable technologies with real-world impact.

InP Photonics Integrated Circuits empowering next generation Datacenter Generation

Stolze, Gunnar
Chief Commercial Officer
SMART Photonics

Abstract
SMART Photonics is a foundry for Indium Phosphide (InP) integrated photonic circuits (PICs), offering solutions for data and telecommunication, as well as for sensing, such as Lidar, and medical applications. InP PICs play an important role in empowering next generation data centers, powering 1.6T, 3.2T and beyond optical communication links within the data centers. New InP PIC designs and advances in speed and PIC power of building blocks are presented, enabling higher speed, reducing power consumption and boosting performance.

Biography
Gunnar Stolze joined SMART Photonics in April 2025 as Chief Commercial Officer, overseeing the company’s commercial strategy and execution. He brings over two decades of global experience in the photonics industry.Before SMART Photonics, Gunnar spent 10 years at Novanta Inc., where he served as Senior Vice President of Commercial Operations for the Photonics Division and General Manager of multiple business units, working across Munich, Boston, and Manchester.Earlier in his career, Gunnar led market expansion initiatives for GaAs and InP technologies into industrial, consumer, and datacom sectors at Oclaro in Zurich. He began his professional journey at HP/Agilent as an Application Expert for DWDM optical component testing.Gunnar holds a BSc in Electrical Engineering from TU Hamburg and an MSc in Physics from Dartmouth College, New Hampshire.

III-V Engineered Substrates, beyond classical SOI substrates

Roda Neve, Cesar
R&D Program Manager
SOITEC

Abstract
For the forthcoming generation of wireless communication systems, high-frequency electronics, and advanced radar architectures, there is a pressing need for substrate technologies that surpass the inherent limitations of conventional silicon (Si) and silicon-on-insulator (SOI) platforms. Engineered substrates that incorporate emerging compound semiconductors—most notably gallium nitride (GaN) and indium phosphide (InP)—offer a unique opportunity to harness superior electron transport properties, enhanced thermal conductivity, and scalable integration, while simultaneously enabling precise control over dielectric and thermal management. The successful integration of III–V semiconductors onto advanced engineered substrates relies on a combination of innovative approaches, including direct bonding, layer transfer, and heterogeneous integration strategies. These techniques not only pave the way for optimized RF device performance but also address critical challenges associated with material availability, manufacturability, and cost competitiveness, thereby accelerating the large-scale commercialization of III–V-based wireless technologies. Particular emphasis is placed on application-driven advances spanning millimeter-wave communications, 5G/6G front-end modules, satellite and aerospace electronics, and high-power amplifier technologies. In this work, we provide an overview of the most recent developments in the design and fabrication of III–V engineered substrates, and outline their prospective roadmap toward industrial adoption and widespread deployment in future RF applications.

Biography
Cesar Roda Neve received his Msc. Engineer degree from the ICAI Universidad Pontificia de Comillas, Madrid, Spain, in 2000. In 2004 he joined the University Carlos III of Madrid where he worked on optoelectronic devices for ROF links. In 2006 he joined the Microwave Laboratory of the UCLouvain, Belgium, where he specialized on the use of Si-based substrates for RF applications, in particular trap-rich HR-SOI. He received his Ph.D. degree by UCLouvain in engineering sciences in 2010. Since then, he has worked on R&D and new technologies development at several companies and for a wide variety of topics, from RF and large signal characterization, 2.5D/3D integration, to GNSS and UAV/satellite communications. In 2021 he joined Soitec as R&D Program Manager, working on strategic research applications and emerging technologies, focusing on quantum technologies and applications, as well as on RF, 6G, and advanced CMOS technologies.

Substrate engineering for the benefit of advanced devices and integration

Bonnin, Olivier
Technology Development Sr Director
Soitec

Abstract
The continuous evolution of microelectronics and optoelectronics relies heavily on the development of innovative substrates that enable both performance enhancement and heterogeneous integration. Substrate engineering has emerged as a key enabler for advanced devices, offering tailored material properties, optimized interfaces, and scalable integration platforms. By leveraging techniques such as layer transfer, strain engineering, defect control, and heterogeneous bonding, engineered substrates provide pathways to overcome fundamental limitations of conventional materials. This approach not only supports the scaling of transistor architectures but also fosters the integration of diverse functionalities, including photonics, RF, power electronics... In this context, substrate engineering represents a cornerstone for the next generation of semiconductor devices, ensuring improved efficiency, reliability, and cost-effectiveness while enabling disruptive system-level innovations.

Biography
Olivier Bonnin is Senior Director of Soitec's Technology Development, which is gathering experts in various fields (Fundamental of Physics and simulation, Material, Process, Metrology and Device) and development teams.He joined Soitec in 2006 as Product Engineering Manager and participated in the introduction of most of the existing Soitec's products.Olivier Bonnin has authored or co-authored more than 30 papers. He has a PhD in Material sciences from CNRS.

Topic Coming Soon

Gualandris, Fabio
President Quality, Manufacturing & Technology
STMicroelectronics

Abstract
Coming Soon

Biography
Fabio Gualandris is STMicroelectronics’ President, Quality, Manufacturing, andTechnology and has held this position since July 2023. He was responsible for the company’s Back-End Manufacturing & Technology organization since 2016 and also led the Company’s Testing Council, alongside its manufacturing strategy in Asia and efforts in System-in-Package technology. Gualandris is a member of ST’s Executive Committee.Gualandris joined SGS Microelettronica (now ST) R&D in 1984. He became R&DDirector of Operations in 1989 and became Automotive BU Director in 1996. Aftertwo years as President and CEO of Semitool, he rejoined ST in 2000 as Group VP responsible for memory products including the RAM/PSRAM and Automotive Flash.In 2005, Gualandris was appointed CEO of ST Incard, an ST smart-card subsidiary. In 2008-2010, he served as VP and Supply Chain General Manager at ST’s memory JV with Intel. In 2011, Gualandris was appointed ST’s Executive Vice President, Product Quality Excellence. Gualandris has authored several technical and managerial papers and holds multiple international patents. He serves as Chairman of STS, ST's manufacturing JV in China.Fabio Gualandris was born in Bergamo, Italy, in 1959. He holds a Master’s degree in Physics from the University of Milan.

Inkjet Printing of Etch Masks for Semiconductor Manufacturing: A Sustainable Alternative to Screen Printing and Lithography

Volk, David
Product Manager
SUSS MicroTec SE

Abstract
Etch masks in semiconductor manufacturing have traditionally been deposited by screen printing or photolithographic methods, both of which involve limitations in process flexibility, material efficiency, and sustainability. An alternative approach based on inkjet printing with tailored materials has been developed, enabling direct, maskless, and digital deposition. The process, its advantages, and experimental results on semiconductor substrates are presented

Biography
David studied Printing Technology in Stuttgart and graduated as Ph.D. in 2014 at the Institute of Microsystems Engineering of the University of Freiburg, Germany. He worked in different roles leading application development activities in the field of functional inkjet printing. Since 2022 he is working for SUSS as product manager. His focus is on establishing inkjet printing as manufacturing technology for the semiconductor industry.

Semiconductor Training & Skills for the future

Guy, Owen
Professor
Swansea University

Abstract
The semiconductor industry is facing a shortage of talent. This presentation will highlight a number of new initiatives, developing skills, training and education programmes to attract new talent into the semiconductor sector.The presentation will present AI powered tools for engagement and training, as well as highlighting the use of AI and Machine Learning in a wafer characterisation application. Highlights of AI-powered skills, engagment and training solutions will be presented along with a demonstration of an interactive AI-training tool.

Biography
Prof. Owen Guy FRSC is a research Professor at Swansea University. He was Head of Chemistry until August 2025 and is Director of the Centre for Nanohealth, as well as a co-director of the Centre of Integrative Materials (CISM). Owen has over 20 years’ experience in semiconductor device research (silicon, silicon carbide, graphene & MEMS technology) and is developing collaborative research and education programmes with the Compund Semiconductor Cluster in the UK.Owen is leading new outreach initiatives to develop the talent pipeline for the semiconductor industry in the UK and Europe and is developing innovative training aids.

Designing Chiplets & 3DIC for Silicon Lifecycle Management

Zorian, Yervant
Technical Fellow
Synopsys, Inc.

Abstract
Recent advances in Artificial Intelligence accelerators, automotive systems, and high-performance computing (HPC) in data centers have led to an acceleration in the adoption of advanced chiplets and 3DIC packaging technologies. This course will present today's trends in high-end electronic systems and their needs for advanced chiplets and 3DIC systems and concentrate on the resiliency challenges and solutions for such chiplets and 3DIC systems. It will introduce the key concepts and terminology concerning the above issues, summarizing the main solutions adopted to minimize the probability of faulty circuits to reach the operational phase, and to mitigate the effects of possible faults affecting the circuits in the field.

Biography
Dr. Yervant Zorian is a pioneering engineer and technology leader renowned for his contributions to the fields of electronic design automation and test technologies. With a distinguished career that spans academia and industry, Dr. Zorian has made significant contributions to the development and implementation of innovative testing techniques for complex integrated circuits. As a prolific author and inventor, he has contributed to numerous publications and patents in the field. Dr. Zorian has also served in various leadership roles within professional organizations, furthering the advancement of technology and knowledge in his areas of expertise. Zorian won the 2005 Hans Karlsson Award and is a Chief Architect and Fellow at Synopsys.

JePPIX: The joint European platform for photonic integrated components and circuits

Williams, Kevin
Professor
Technical University Eindhoven

Abstract
Integrated photonics offers us the way to a faster, more precise and more energy efficient future. The sustained growth of the internet is already critically dependent on photonic integrated circuits. Photonic integrated circuits (PICs) are now emerging in industry labs for imaging and metrology with precision, size, and they are showing efficiencies which can be orders of magnitude beyond non-integrated technologies. Supply chains are now aligning to support product developments across many market sectors.JePPIX - the Joint European Platform for Photonic Integrated Components and Circuits - is a vibrant community of foundries, software vendors, testing experts, packaging companies, technology innovators, equipment suppliers and PIC-enabled module developers. Together they play a key role in defining the road to commercialization in new and emerging sectors. JePPIX is a pioneer of the open-access foundry model for integrated photonics - specifically indium phosphide but also heterogeneous approaches - enabling the end-user to drive product development. Companies and researchers have already been prototyping using commercial JePPIX services for more than a decade. Product developers are focussing on metrics critical to quality, reproducibility, reliability and the seamless interconnection of accelerated design-fab-test cycles which are required to prepare a design for production. Going forwards, strategies are being developed to accelerate design through the delivery of manufacturing excellence within sustainable commercial value chains. The telecommunications sector has already shown how premium PIC technology can be delivered. The next wave of product innovation is more diverse in terms of platforms, components, and circuits. Foundry manufacturing offers a compelling route to accelerated deployment of products across multiple sectors. We will elaborate the future challenges and perspectives for research and innovation for PIC technologies.

Biography
Kevin Williams is full professor and chair of the Photonic Integration research group at Eindhoven University of Technology (TU/e). He has extensive experience in the design, fabrication and measurement of InP based photonic devices and integrated circuits, including semiconductor lasers, amplifiers, high speed modulators and photonic switches. Kevin was coordinator for the EC JePPIX Pilot Line which matured the full supply chain from software, design, production and test for foundry based PIC manufacturing. The team has played a key role in establishing the Photonic Integration Technology Centre and plays an active role in the Chips JU PIXEurope project.

RISC-V Meets Brain-Inspired Intelligence

Amrouch, Hussam
Prof. Dr.-Ing.
Technical University of Munich (TUM)

Abstract
Brain-inspired Hyperdimensional Computing (HDC) offers a compelling alternative to conventional neural networks by leveraging high-dimensional vector algebra for efficient and robust machine learning. We demonstrate that customizing RISC-V to the specific requirements of HDC algorithms enables highly energy-efficient edge training, achieving performance within merely a few microjoules.

Biography
Professor Amrouch is heading the Chair of AI Processor Design at the Technical University of Munich. He is, the head of Brain-inspired Computing at the Munich Institute of Robotics. He is the head of the Semiconductor Test and Reliability at the University of Stuttgart. He is also the Academic Director of TUM Venture. He is the Founding Director of Munich Center for AI Chips.

X-ray CT scanning inspection for advanced semiconductor packaging

Kumazawa, Takashi
General Manager
Techno Horizon Co., LTD

Abstract
In cutting-edge semiconductor packaging, X-ray CT scanning inspection is recognized as an effective method for ensuring the quality of bumps and substrates. However, with the trend toward larger chips and smaller bumps, there is a growing demand for even faster inspection speeds.Furthermore, there is a trend shifting from substrate materials made of silicon to those made of glass. To establish new processing technologies and ensure quality, high-speed X-ray CT scanning inspection is required.Techno Horizon is addressing these new demands in X-ray CT scanning inspection for cutting-edge semiconductor packaging by applying AI technology to reduce imaging time, enhance automated inspection programs, accommodate larger object sizes, and adopt vacuum suction mechanisms.Furthermore, we are developing a new CT scanning method to enable 100% inline inspection.We will provide details for the conference.

Biography
Takashi Kumazawa has over 25 years of experience in the industrial and medical imaging industries, as well as more than 20 years of experience in international business. He is currently General Manager of the Robotics Innovation Business Unit at Techno Horizon Co., Ltd., leading global initiatives in semiconductor X-ray inspection, PCB AOI, machine vision, optics, and soldering systems. With extensive experience in sales & marketing, R&D, and manufacturing, he combines strong leadership and technical expertise to drive innovation and business growth.

The Role of Time Critical Logistics in Complex Global Supply Chains

Schoenzetter, Remy
Global Head of Business Unit High Tech & Semicon
time:matters GmbH

Abstract
As semiconductor supply chains stretch across continents and rely on tightly sequenced production flows, even minor delays can lead to significant disruptions. In a world impacted by geopolitical shifts, supply shortages, and accelerating innovation cycles, the ability to respond quickly is no longer optional - it’s a strategic necessity.In this session, Remy Schoenzetter, Head of the Business Unit High Tech & Semicon at time:matters, explores the critical role of agile, time-sensitive logistics in securing continuity and responsiveness across the semiconductor value chain. Drawing on global experience in supporting semiconductor manufacturers and equipment suppliers, he will outline how time-critical networks, courier terminals, and 24/7 operational control are becoming increasingly important.This talk offers a strategic perspective on how companies can rethink urgency, resilience, and agility - transforming logistics from a cost driver into a competitive edge.

Biography
Remy Schoenzetter is the Global Head of the High Tech & Semicon Business Unit at time:matters, a logistics service provider specializing in time-critical logistics.With over a decade of experience in supply chain management, air freight, and freight forwarding, Remy brings a pragmatic, hands-on perspective to complex logistical challenges.His career spans various roles across different logistical networks, including leadership positions in operations, customer service, and strategic partner management. Prior to his current role, Remy served as Head of Operations Western Europe, where he oversaw a team of logistics experts and led transformative initiatives across the region.He is known for connecting cross-functional teams and translating customer urgency into solutions that drive performance and resilience.Remy holds a Master’s degree in Finance, complemented by certifications in Lean, Agile, and professional coaching. He combines analytical thinking with a people-centered leadership style, and currently contributes to the SEMI Supply Chain Initiative as a strategic partner.

Enabling Sustainability through Digitization and AI

Kumar, Kaushik
Technologist
Tokyo Electron Europe Ltd

Abstract
The semiconductor market is expected to reach $1 trillion by 2030, largely driven by AI technologies. This growth introduces complexities in device structures, leading to higher development costs and timelines. As equipment makers, we face the challenge of managing these complications while controlling expenses and time. We will explore how AI can help us tackle these challenges sustainably, enabling us collaborate to meet both operational efficiency and Net-Zero targets.

Biography
Kaushik started his career as an Etch Engineer in IBM Microelectronics in New York in 1999. He joined TEL in 2009 at its R&D center in Albany, New York. Since then he has had a wide range of responsibilities that includes managing the R&D Etch team in Albany, New York to managing the TEL teams in imec, Belgium. Currently, he serves in the role of a Technologist supporting TEL's customers and partners in Europe.

Topic Coming Soon

Rensink, Alexander
Senior Director Account Management & Business Development
TSMC

Abstract
Coming Soon

Biography
Dr. Alexander Rensink is responsible for account management & business development in the EMEA region at TSMC. Besides HPC, Smartphone and IoT markets, the Automotive semiconductor growth opportunity is one of his focus areas. Prior to joining TSMC, Alexander worked at European semiconductor companies ams and NXP Semiconductors in various strategic & business management roles. Alexander is a Dutch citizen and holds a Ph.D. in Electrical Engineering.

From Lab to Leadership - Europe’s bet on Semiconductor Startups

Machold, Michael
Operational Director - Venture Lab Quantum/Semicon
TUM Venture Labs

Abstract
The semiconductor industry is evolving rapidly. While traditional technologies advance, new computing paradigms are emerging: quantum computing leverages quantum mechanical principles, neuromorphic computing mimics the brain's neural structure, and photonic computing uses light instead of electrons for processing. This session explores these technological trends and examines how European semiconductor startups are positioned to drive innovation. We'll discuss the strategic importance of semiconductor development for Europe's technological sovereignty and economic future. We'll also highlight how collaborative ecosystems are helping startups overcome challenges in this capital-intensive sector by bridging research and commercialization. Join us to discover how industry, investors, policymakers, and entrepreneurs can work together to strengthen Europe's position in the global semiconductor landscape.

Biography
Michael Machold is Operational Director at TUM Venture Labs Quantum/Semicon, where he is building the leading incubation program for founders in semiconductors, photonics, nanotech, and quantum technologies, actively driving Europe's deep-tech startup ecosystem.With over a decade of experience at Infineon Technologies, including serving as Director – Head of Product Management Automotive Microcontroller, Michael brings deep insights into the semiconductor industry. He holds an M.Sc. in Electrical Engineering from TUM and an Executive MBA from ESADE Business and Law School.

Strategic advances in III-V RF Technologies for energy-efficient 5G infrastructure

U'Ren, Gregory
Senior Technical Expert
United Monolithic Semiconductors (UMS)

Abstract
III-V semiconductor technologies, including GaAs and GaN/SiC, are at the core an effort lead by UMS to strengthen European sovereignty in advanced rf components for terrestrial and non-terrestrial 5G due to their unrivaled performance in high-frequency, high-power, and high-linearity applications. This talk will highlight the strategic role of III-V technologies in enabling energy-efficient RF front-ends and system-in-package (SiP) solutions, addressing the growing demands of 5G and SATCOM networks. By combining advancements in MIMC device technology, innovative device architectures, and heterogeneous integration, the ambition is to realize a 40% reduction in power consumption across the full radio link. Efficiency gains in the network reduce operating costs from the combination of reduced energy consumption and reduced thermal management.

Biography
Dr. Gregory U’Ren is presently with United Monolithic Semiconductors (UMS) leading strategic innovation initiatives. He has held both leadership and individual roles contributing to the advancement of a broad range of specialty technologies including SiGe BiCMOS, RF-SOI, MEMS, and GaN. He is a senior member of IEEE, presently also serving on the advisory board at the Fraunhofer Institute for Applied Solid State Physics, a member of American Physics Society, and holds over 30 patents. He completed his Ph.D. and MS at the University of California Los Angeles.

Shifting boundaries: Advancing Memory and Compute, Together.

Dubois, Sylvain
CEO
VERTICAL COMPUTE

Abstract
Compute chip performance has surged over the last decades, but memory performance, using technologies like SRAM, DRAM, and 3D-NAND, has lagged, leading to complex memory hierarchies. The recent rise of Generative AI has pushed memory demands beyond current capabilities, resulting in expensive High-Memory-Bandwidth (HBM) chips and AI systems in the cloud, just as scaling roadmaps for the memory technologies are stalling.This presents an opportunity for Vertical Compute's integrated memory, which vertically integrates magnetic bit strings directly above transistors. This offers greater density than DRAM (> Gb/mm2) and SRAM-like access latency (~10ns). Direct CMOS integration eliminates data bus bottlenecks, reducing power and enabling high-performance, in-memory compute for LLM inference on a single chip.This presentation will cover the state of Generative AI hardware, the 100X potential of vertical integrated memories, and the path to industrial production.

Biography
Sylvain Dubois is the CEO and co-founder of Vertical Compute, a hardware semiconductor startup developing a proprietary vertical integrated memory technology, designed to unleash the data flow for data intensive workloads. He previously worked at Google, in Advanced Technology Sourcing & Partnerships for the Google Cloud Infrastructure group in Sunnyvale, CA. His responsibilities included identifying, analyzing, and developing emerging technology trends, with a focus on Artificial Intelligence hardware acceleration compute chips, memory, and chiplet integration. Prior to his role at Google, he served as Vice-President of Business at Crossbar, a California-based deep tech startup specializing in novel memory development.

Multi-modal low power spatial sensing for XR with Single Photon Active Event Sensors.

van der Tempel, Ward
CTO
VoxelSensors SRL

Abstract
Low power perception for XR platforms remains an elusive target using traditional sensing methods, failing to deliver the essential balance of high performance, low latency, and energy efficiency required for all-day wearable devices. VoxelSensors introduces multi-modal spatial sensing powered by our Single Photon Active Event Sensor (SPAES) technology. Leveraging recent advance in MEMS mirror beam steering technology to achieve low power optical beam steering, combined our low power SPAD- & event-based sensor achitecture, we finally unlock low power sensing and perception solutions for XR.

Biography
Ward van der Tempel is co-founder and CTO at VoxelSensors and inventor of the Single Photon Active Event Sensor (SPAES) technology. He has over 15 years of experience in CMOS analog and digital sensor design and sensor fabrication process. He was co-founder and Product Director of Spectricity, developing miniature spectrometer solutions. Before this, he co-founded Optrima (merged with SoftKinetic, then acquired by Sony) to bring to market 3D Time-of-Flight technology. After the acquisition by Sony, Ward was Head of Technology at Sony DepthSensing Solutions, driving its 3D time-of-flight (ToF) development. Ward holds an MSc. Eng. degree and a Ph.D. in Electrical Engineering, both from the Vrije Universiteit Brussel, Belgium.

How VSORA Positions Europe at the Forefront of AI

Maalej, Khaled
CEO
VSORA

Abstract
The future of Artificial Intelligence will be defined by those who not only push the limits of technology, but who also ensure that innovation serves resilience, sovereignty, and shared prosperity. Europe stands at a turning point: to secure its place as a global leader, it must embrace breakthroughs that combine world-class performance with sustainability and accessibility.VSORA embodies this vision. Its proprietary architecture achieves what was once thought impossible: four times the application performance of today’s leaders, while consuming only half the power. It matches the maximum memory capacity achievable by current technologies, standing shoulder-to-shoulder with Nvidia and AMD, yet it goes further—dramatically reducing the cost per token and the cost of ownership for AI data center inference.This is not simply a technological advance; it is a strategic leap. By lowering barriers to AI deployment, VSORA makes the tools of the future more affordable, more efficient, and more European. In doing so, it ensures that Europe is not a passenger in the AI revolution, but a driver—shaping the global narrative, setting new standards, and proving that innovation with purpose can power a resilient and competitive economy.

Biography
Khaled Maalej is CEO of VSORA, a provider of ultra-high-performance chip solutions for artificial intelligence in data center and edge applications based in France. Before founding VSORA in 2015 with other DSP engineers, Maalej was CTO - Digital Tuner Business of Parrot, the leading drone provider, and DiBcom, a fabless semiconductor company that designed chipsets for low-power mobile TV and radio reception acquired by Parrot. He graduated from Ecole Polytechnique & Ecole Nationale Superieure des Telecommunications in Paris.

Emerging technologies for the defence sector

Konstari, Piia
Director, Microfabrication services
VTT Technical Research Centre of Finland

Abstract
The defence industry has traditionally been dominated by large integrators providing high-performance and durable solutions with life spans typically ranging from 10 to 40 years. While these capabilities remain relevant for modern warfare, there is also demand for cost-effective, high enough performing solutions that can be mass-produced and easily redesigned. Dual-use technologies are increasingly significant in the defence sector, with a growing number of new dual-use technology companies entering the field. Access to digital and critical technologies is considered important for Europe.

Biography
Piia Konstari is Director of Microfabrication services at VTT. She is responsible for VTT’s pilot line services in microelectronics and quantum technologies and for successful commercialization of those. Previously, as a Lead in Microelectronics and quantum technology at VTT, she was responsible for business development and commercialization activities of those areas. Piia has a background in sales both from VTT as well as from the semicondcutor industry.

Strategic Raw Materials and Sustainability: The Importance of Hyperpure Silicon.

Bünnig, Michael

Wacker Chemie AG

Abstract
WACKER Chemie AG is the global market, technology and quality leader for hyperpure silicon. Hyperpure silicon is the enabling material for silicon wafers. In 2023 Wacker started to invest once more in our hyperpure silicon capacities and capabilities. Therefore, Wacker is part of the public funded IPCEI ME/CT (Important Project of Common European Interest for Microelectronics and Communication Technologies) program with our strategic investment project “Etching Line Next” in Germany, Burghausen. Within this project, WACKER develops and deploys an innovative etching process for hyerpure silicon combined with a novel pre-treatment via thermal crushing and an innovative automated morphology sorting. This will result in an innovative silicon that will specifically meet future technical requirements to allow production of future leading-edge devices. We want to talk about the innovations of the project and in general about sustainable and challenging production of hyperpure silicon.These includes:- How to improve product quality and enabling the production of hyperpure silicon at constant level,- why hyperpure silicon enables the production of 300 mm wafers and why it is essential for future microelectronic applications,- how to face cost challenges e.g. energy costs with a high degree of automation andenhances sustainability in several respects.With hyperpure silicon being a strategic key raw material for semiconductors we are going to showcase how our investment project will contribute to a resilient European semiconductor supply chain while further supporting sustainability strategies and green technologies in the industry and therefore how hyperpure silicon in general contributions to a sustainable future.As hyperpure silicon for semiconductor application is the indispensable base for the global electronic value chain and the continuously growing market pushed by digitalization and decarbonization and ever tighter technical requirements trigger the same trend on the silicon supply side – growing demand and increasing technical requirements while also focusing on sustainability. All these challenges will be addressed in our pre-recorded talk.

Biography
Professional CareerSince March 2023 back with WACKERSenior Marketing Manager for PolysiliconWacker Chemie AG, 2011 - 2021Sales Manager Silicones for Customers in Energy Sector in DACH-RegionWalter De Gruyter, 2021 - 2022Senior Manager Book Production and Team LeadEducationHumboldt-Universität zu Berlin, 2020 - 2023Master of Arts - MA, PhilosophieSteinbeis University, 2014–2016Master of Business Administration (M.B.A.), MarketingUniversity of Applied Sciences, 2005 - 2011Diploma Industrial Engineering

Stitching-Based Resolution Enhancement in Wavefront Phase Measurement of Silicon Wafer Surfaces

Jiménez-Gomis, Miguel
Application Engineer
Wooptix S.L.

Abstract
The increasing demand for higher resolution and faster machinery in silicon wafer inspection is driven by the rapid rise in electronic device production and the continuous miniaturization of microchips. As feature sizes shrink and wafer sizes grow, there is a critical need for precise and efficient surface characterization tools. To address these challenges, this paper presents the design, development, and implementation of a novel measurement device capable of accurately characterizing the surface of silicon wafers through the stitching technique. We propose an advanced optical system architecture specifically optimized for evaluating the surface profile of silicon wafers, with particular emphasis on measuring roughness and nanotopography. The developed device achieves a lateral resolution of 7.56 µm and an axial resolution of 1 nm, enabling high-precision metrology. It is capable of scanning and analyzing an entire 300-mm wafer in approximately 60 minutes, while acquiring and processing approximately 400 million data points. The core methodology utilizes a wavefront phase sensor, which reconstructs the wafer’s surface geometry by analyzing two images displaced at carefully determined distances from the conjugate plane within the image space of a 4f optical system. The study further details the comprehensive calibration procedure and introduces a robust algorithm for transforming local measurement coordinates into global wafer coordinates. Quantitative phase imaging is obtained through the application of a wavefront intensity image reconstruction algorithm. Experimental validation demonstrates the system’s ability to differentiate between thinned dies bonded onto carrier wafers, detect variations in coplanarity, and identify bonding defects. Additionally, the residual stress in thin films deposited over the dies is quantified using the Stoney model, underscoring the system’s potential for comprehensive wafer inspection and advanced process monitoring in semiconductor manufacturing.

Biography
Miguel is Wooptix's application engineer and Phd candidate in the University of La laguna. His research is centered around finding novel use cases for semiconductor metrology technology in close collaboration with industry partners. With a background in consulting and computer science, Miguel bridges the gap between technology development and business use cases.

Designing Secure and Agile Microsystems Supply Chains: X-FAB’s Approach to MEMS, SiP and SoC Localisation

Herbig, Volker
Vice-President, BU MEMS
X-fab

Abstract
X-FAB Microsystems is playing an active role in shaping the future of semiconductor integration. We are doing this by establishing robust, application-specific supply chains for MEMS sensors, SiPs and SoCs. As the global demand for advanced sensing and integration solutions increases, we are collaborating with our customers to localise critical elements of the supply chain, thereby supporting European innovation and security. At the same time, a dedicated supply chain is emerging in China to serve regional market needs and ensure strategic flexibility in areas where X-FAB can contribute. Attendees will gain insights into how X-FAB’s microsystems strategy navigates complexity and contributes to a more secure and agile semiconductor ecosystem.

Biography
Volker Herbig, VP BU MEMS at X-FAB, oversees all MEMS activities within the X-FAB Group. Before assuming his current role, Volker worked as Director Product Marketing at X-FAB. Previously he held also engineering, marketing and management positions at Siemens, Inkjet Technologies and Carl Zeiss where, among other activities, he developed MEMS inkjet print heads and was responsible for setting up a manufacturing facility for those. Volker Herbig holds a master’s degree in physics from Humboldt University, Berlin, Germany.

X-FAB’s Automation & AI Journey: Smart Manufacturing for a Competitive Edge

Sampermans, Ulrike
VP Digital Transformation
X-Fab Group

Abstract
AI and automation are transforming semiconductor fabs into intelligent, adaptive systems. In this presentation , we’ll explore how manufacturers can harness these technologies to boost efficiency and global competitiveness. We’ll dive into X-FAB’s digital journey—examining the evolving role of engineers and how smart systems are reshaping operations in line with 2035 roadmap planning.

Biography
Ulrike has more than 22 years of international experience in corporate strategy, digital and automation management and business development. She has driven sustainable transformation across multiple industries.As Vice President Digital Transformation at X-FAB, she leads the group’s digitalization and automation efforts, focusing on innovation to boost efficiency, scalability, and sustainable growth.Previously, she held senior transformation roles at BASF, Accenture, and AECOM. With global experience across five continents, she applies proven strategies to enhance digital transformation, agility, and operational excellence. Ulrike holds a diploma in International Business and IT, a Bachelor of Arts, and an MBA.

MEMS & Imaging Outlook: Consolidation and Regional Strategies

Eloy, Jean-Christophe
President & Chairman
YOLE GROUP

Abstract
In recent years, the semiconductor supply chain has shown its vulnerability to disruptions caused by COVID-19, geopolitical tensions, and the China–US trade war, largely due to monopolies and regional specialization. In response, governments and corporations have launched initiatives such as the “chip acts” launched since 2022.These measures have reshaped both MEMS and imaging markets, but in different ways. The MEMS market, valued at $15.4B in 2024 and expected to reach $19.2B by 2030, has returned to growth from 2024, driven by the end of inventories, ongoing company consolidation (e.g., STMicroelectronics’ acquisition of NXP’s MEMS assets), and the expansion of China’s MEMS domestic ecosystem. The imaging market, worth $23.2B in 2024 and projected at $30.1B by 2030, has been less affected, thanks to its reliance on mature nodes. Sony remains dominant, while Chinese firms gain ground. In the thermal imaging segment, export restrictions of devices and raw materials are fostering the emergence of distinct regional ecosystems.This presentation will outline the evolving MEMS and imaging industry landscapes within the current geopolitical context.

Biography
Jean-Christophe Eloy is President & Chairman of the Yole Group.Created in 1998, the market research & strategy consulting company has grown to become a group of companies providing marketing, technology and strategy consulting, media in addition to corporate finance services. His mission is to oversee the strategic direction of Yole Group.All year long, Jean-Christophe builds deep relationships with leading semiconductor companies, discussing and sharing information across his global network. His aim is to get a comprehensive understanding of their strengths and guide their success.Jean-Christophe is a graduate from EMLyon Business School (Lyon, France) and has a Ph.D. in Semiconductor Engineering from the National Polytechnic Institute of Grenoble (France).

Turning Disruption into Advantage: Europe’s Opportunity to Shine.

West, John
Chief Analyst,​ Semiconductor Equipment​
YOLE GROUP

Abstract
The rapid rise of fabless chipmakers, combined with government interventions such as subsidies, tariffs, and protectionist policies, is reshaping global competition across the semiconductor supply chain. In this volatile environment, companies with manufacturing assets must strike the right balance between technology leadership, operational agility, and cost efficiency to remain competitive.This presentation examines how European chipmakers can leverage the region’s highly skilled workforce and deep manufacturing expertise to capitalize on emerging disruptive technologies and external market forces to strengthen their position in the global market.

Biography
John West is Chief Analyst, Semiconductor Equipment at Yole Group.He has over 20 years of industry experience and a successful track record in various strategy and consulting projects.John has a Bachelor's degree in Medical Physics from King's College London and an MBA from Cranfield School of Management.