Heterogeneous Integration - The New Driver of Innovation and Growth

Beica, Rozalia
Chief Sales Officer, Semiconductor Division
AT&S

Abstract
The explosive growth in data generated and computing needs, global network traffic and digital transformation are further driving the adoption of electronics and semiconductor devices. The need for more performing and smarter devices, with increased functionalities, that can address high bandwidth needs, faster speeds, parallel processing, with more efficient power consumption is driving the industry to further develop new and innovative technologies. While innovation in mobile devices continues, new emerging applications, such as IoT, Artificial Intelligence and 5G are expected to drive the next phase of innovation across the supply chain. The new driving forces are also shifting the importance in the industry from technology node scaling to system level integration. This presentation will give an overview of the global market trends highlighting the majorindustry trends and applications, the increased need and growth of heterogeneous and system level integration and the solutions that AT&S is bringing to the market to address current and future market needs.

Biography
Rozalia Beica is currently the CSO of Semiconductor Division, focusing on semiconductor and module activities within AT&S. Prior to AT&S she had several executive and C-level roles with various organizations across the supply chain: electronic materials (Rohm and Haas Electronic Materials, Dow & DuPont), equipment (Semitool, Applied Materials and Lam Research), device manufacturing (Maxim IC) and market research & strategy consulting firm (Yole Developpement). Rozalia is actively involved in various industry activities. Some of the current engagements include: Member of the Board of Governors for IEEE Electronics Packaging Society and Vice General Chair of 71th ECTC, Chair of the Heterogeneous Integration Roadmap WLP Technical Working Group, Chair of the Semi Strategic Materials Conference, Technical Chair of System in Package China Symposium, Advisory Board Member 3DinCites and IMPACT Taiwan. Past activities: IMAPS VP of Technology, General Chair IMAPS DPC, Program Director EMC3D Consortia, General Chair Global Semi & Electronics Forum, Technical Advisory Board Member SRC, several other memberships in industry committees. Rozalia has over 150 presentations & publications, including 3 book chapters on 3D Integration. Rozalia has a M.Sc in Chemical Engineering (Romania), a M. Sc. In Management of Technology (USA) and a Global Executive MBA from IE Business School (Spain).

Holistic thermal material characterization approach for thermal performance optimization of electronic packages

von Essen, Tobias
Head Of Marketing
Berliner Nanotest und Design GmbH

Abstract
Thermal management is a key component of electronic package design in general and heterogeneously integrated System-in-Package design in specific. Functionality, life expectancy and reliability of packages strongly depend on their thermal performance. The application of the right materials is most important to achieve the targets. Furthermore, numerical analysis for lifetime prediction requires correct material data for credible propositions.As material properties strongly depend on use case and field scenario, but material datasheets, unfortunately, tend not to provide the details and accuracy required, it is crucial to acquire material data reliably using suitable methods.The presentation will describe a systematic approach to identify the contribution of different materials in electronic packages to the overall thermal performance and which ones are potential bottlenecks. For the different material classes, different characterization methods are presented and discussed.Thermal interface materials (TIMs) are centerpiece of the discussion, as they contribute with up to two thirds to the overall thermal junction to case resistance. The best approach to TIM characterization is following the ASTM D 5470 guideline, which does not only provide thermal conductivity as output but also the interface resistance, which is a crucial component of thermal interfaces with continuously shrinking gap width.Second important group of materials in the list are metals and semiconductors in the package, all with rather high thermal conductivity and not possible to characterize using the ASTM D 5470 approach. However, a quite similar approach, moving from through-plane to in-plane measurement, will be presented. It allows the precise characterization of such materials and yields thermal conductivity and diffusivity as result, which is gratefully acknowledged input to numerical analysis. The same methodological approach enables the characterization of metal-based die attach materials such as solder and sintered material samples.Eventually, a system-level evaluation method will be shown that can provide performance benchmarking of assembled prototypes and can greatly serve as validation beacon for numerical models.In conclusion, an example of a typical electronic package will be shown, summarizing all presented methods and system-level test. The used complete off-the-shelve product family offering all the presented methods ready to use will be introduced.

Biography
Tobias von Essen studied Micro Systems Engineering and Systems Engineering at the University of Applied Sciences in Berlin, receiving his master’s degree in 2013, where he implemented a test stand for transient thermal characterization. Since 2011, he is part of the Nanotest team, first as student worker and, subsequent to his master’s thesis, as permanent employee. Tobias is responsible for marketing and sales activity at Nanotest, but also leads multiple software projects of Nanotest-proprietary characterization systems and partakes in method and system development. His scientific focus is steady-state thermal material characterization.

New solutions for plasma dicing, and new solutions for processing of SiC wafers ranging from ingot splitting, grinding, polishing to high speed and chipping free dicing.

Klug, Gerald
General Sales Manager
DISCO Hi-Tec Europe GmbH

Abstract
Wafer thinning (Kezuru and Migaku) and dicing (Kiru) is essential for advanced packaging, for achieving narrow street widths and for making thin dies for 3D-packaging. New solutions on plasma dicing in combination with latest tapes and grinding technology enable the supply of perfect top side, back side and side wall quality on dies in thickness range from 20 – 150 µm.Plasma dicing has various advantages comparing to the conventional dicing. However, during the plasma dicing process the sensitive wafer front can be at risk due to the surface being exposed to plasma gas. It is common to protect the wafer front surface by photoresist in the wafer fab, which increases the cost and the processing steps.DISCO has developed a special surface protection film and a total new processing flow for plasma dicing to overcome these issues. SiC is getting more and more important for the energy efficient devices. Since SiC is a very expensive material DISCO focuses on technologies for gaining as many as possible wafers and dies of outstanding quality out of it.SiC ingot splitting by KABRA:KABRA is a new method for SiC-ingot slicing by using a laser instead of a wire saw. In this process, a special layer is made inside of the ingot by laser irradiation and then the wafer is split from the ingot. 40% more wafers are obtained out of one ingot compared to conventional method.SiC ingot and wafer grinding and polishing:After splitting the wafer from the ingot, the ingot side and the wafer side need to be ground and polished. DISCO has developed grinding wheels and polishing pads (E Pad) suitable for wafer manufactures and device makers.SiC wafer dicing by blade or laser:To obtain more numbers of dies from a wafer, cutting streets can be reduced down to 50 µm and less. With our special technologies cutting speed and quality have been greatly improved, too.

Biography
Gerald Klug has studied business-engineering at the University of Siegen and graduated as Diplom-Engineer in 1998.He started his carrier as a designer and project engineer of steel cutting lines at a globally leading German machine manufacturing company.At the end of 2000, he joined DISCO as Sales Engineer. Meanwhile he has been working for DISCO for 19 years and is nowadays operating as General Sales Manager for the territory of Europe.

Drivers of Digitalisation: What is Digitalisation and why can it change so much?

Hopf, Gregor
Professor for Digital Transformation
Duale Hochschule Baden-Württemberg (State Cooperative University Baden-Württemberg)

Abstract
Digital Transformation is often misunderstood as a mere collection of computer-based technologies which allow for more efficient processes and possibly new product or service features. The change brought about by digitalisation however is more fundamental. The keynote will present and discuss the underlying powers of change which drive the digital transformation and which need to be understood in order to grasp and utliize its full powers of “creative destruction”.

Biography
Prof. Dr. Gregor Hopf received his PhD at the London School of Economics and is Professor for Digital Transformation at Baden-Württemberg’s State Cooperative University. In his research he specialises on questions of digital transformation namely online business models and online communication. Until 2016 he was the Head of the Taskforce for Digital Transformation of the State of Baden-Württemberg, coordinating all aspects of the government’s digital transformation agenda directly reporting to the prime minister.

Conference Chair, Session Chair

Kroehnert, Steffen
President and Founder
ESPAT-Consulting - Steffen Kroehnert

Abstract
Conference Chair, Session Chair

Biography
Steffen Kroehnert is President & Founder of ESPAT-Consulting based in Dresden, Germany. He is providing a wide range of consulting services around Semiconductor Packaging, Assembly, and Test, mainly for customers in Europe. Until June 2019, he worked for more than 20 years in different R&D, engineering, and management positions at large IDMs and OSATs in Germany and Portugal, namely Siemens Semiconductors, Infineon Technologies, Qimonda, NANIUM and Amkor Technology, where he most recently served as Senior Director Technology Development. Since 2016 Steffen has chaired the European SEMI integrated Packaging, Assembly, and Test - Technology Community (ESiPAT-TC). Steffen has authored or co-authored 23 patent filings and many technical papers in the field of Packaging Technology. He also co-edited the book “Advances in Embedded and Fan-Out Wafer Level Packaging Technologies”. He is an active member of several technical and conference committees of IEEE EPS, IMAPS, SEMI Europe, and SMTA. Steffen holds an M.Sc. in Electrical Engineering and Microsystems Technologies from the Technical University of Chemnitz, Germany.

High throughput & high yield heterogeneous integration with implemented metrology for collective D2W Bonding

Brandl, Elisabeth
Business Development Manager
EVG

Abstract
Heterogeneous integration offers several advantages in performance gain, functionality increase as well as yield enhancement. Depending on the device architecture and level of integration, several integration methods at different manufacturing levels can be used to create heterogeneous integrated systems. Processing on die level is often practiced, leading in some cases to throughput and yield considerations. Collective die to wafer bonding can enable several integration processes on wafer level via using a reconstituted transfer carrier approach. Especially in hybrid and fusion bonding this method enables heterogeneous integration as processes such as plasma activation are better performed on wafer level for high throughput.As for all semiconductor processes, collective die to wafer bonding demands suited and optimized measurement solutions for process monitoring and yield optimization. Fitting metrology combined with a feedback loop for production equipment is essential to increase yield of the whole integration process and an important factor in successful heterogeneous integration. Regarding metrology implementation, two scenarios are generally possible. One is the implementation of metrology within the bond equipment, which allows a quick reaction and the process parameters can be directly adjusted. The consideration of such implementation demands throughput matching for high equipment efficiency. The other implementation method is an external metrology tool, where the feedback is delayed, but on the other hand one metrology tool can serve several production tools.In the presentation the process flow of collective die to wafer bonding will be discussed in more detail as well as the advantages and disadvantages of the two metrology implementation scenarios.

Biography
Elisabeth Brandl received her master in technical physics from the Johannes Kepler University Linz, Austria in Semiconductor and Solid State Physics. Since 2014, she has been responsible for Product Marketing Management for temporary bonding and metrology at EVG.

Development of a foil based flexible interposer for power conditioning IC in energy autarkic systems

Yacoub-George, Erwin
Scientist
Fraunhofer EMFT

Abstract
The EU ECSEL project EnSO aims the development of autonomous micro energy sources (AMES) for innovative electronic devices that target key applications such as smart health, smart mobility and smart society. An AMES provides energy for sensors, data processing and data transmission and consists of micro storage element, energy harvester, smart charger and power conditioning IC. Smart integration of these building blocks to fabricate an AMES with an appropriate form factor was a key objective in the EnSO project.Although in printed electronics, the PCB board is ususally fabricated with an innovative technology it is often still assembled with bulky and rigid SMD components. In such a case, some of the primary advantages such as conformability and flexibility that are commonly attributed to printed electronics are lost. In order to overcome this limitation, we developed a new package type called “flexible interposer”. It consists of a Cu wiring film fabricated in roll to roll, a thinned IC and a flexible polymeric mould cover. The interposer is designed with a QFN format and is characterized by a reduced thickness and some mechanical flexibility.The flexible interposer approach was developed and characterized for a daisychain chip and a commercial power conditioning IC of the latest generation from STMicroelectronics. The fabrication process was established with the daisychain chip to facilitate electrical characterization and reliability testing and was then adapted for the STBC15 IC. 30 interposer samples have been prepared and characterized. The obtained process yield indicates a robust fabrication process. Since all process steps are compatible with roll to roll production, we expect a high potential for up-scaling that offers the chance to close the gap between research and market.The research results were obtained in the scope of EnSO project that has received funding from 1) EU under Grant Agreement no. 692482 and 2) BMBF with National Grant no. 16ESE0088.

Biography
Erwin Yacoub-George received his Ph. D in Chemistry (1994) at Technical University of Munich where he developed a production process for polysiloxane beads. Since 1994 he worked for the Fraunhofer Society in Munich. He started his research works on the development of optical biosensor systems. In 2002 he joined the flexible electronics team and developed self-assembly processes for thinned ICs as well as heterogeneous integration techniques for printed and large area electronics. He is currently working as a project manager on European and National research projects with a focus on thin chip integration in flexible foil substrates.

Virtual Prototyping for System-in-Package with Heterogeneous Integration - Enabler for faster Time-to-Market

Gadhiya, Ghanshyam
Research Associate
Fraunhofer ENAS

Abstract
Heterogeneous Integration in System-in-Package (SiP) based on Fan-Out Wafer Level Technologies allows to meet various requirements such as improved performance, smaller form-factor, functional safety and low cost for upcoming new applications. Due to the thermo-mechanical stresses leading to device failure, the reliability risks must be assessed during the development of new products aiming for a design optimized for reliability. Virtual Prototyping (VP) based on Finite Element (FE) simulation allows the analysis of the thermo-mechanical situation during fabrication, tests and service within short time, allowing shorter development time. However, it requires parametric FE models, precise material and experimental data for validation. Because of this initial investment, it is advised to develop the VP schemes in a way that they are able to cover a wide variety of future products.The talk will present a modular system of parametric FE models that enables virtual reliability assessments of various SiP products based on Fan-Out Technologies such as WLSiP, eWLB-PoP, RCP, InFO, FOPLP, WFOP, SiWLP and SWIFT-PoP [1][2]. By combination of common packaging components like die, mold, redistribution layers, solder balls, vias, integrated passives, and boards from the library of pre-calibrated parametric FE models in ANSYS, digital twins of a large number of individual package configurations can readily be generated, e.g. 2D, 2.5D and 3D/PoP. The talk highlights the flexibility of the modular system of parametric FE models by four very different industrial packages: Radar sensor, Silicon photomultiplier, Automotive inertial sensor and Camera module. The VP scheme for a new pad design of a multi-chip SiP sensor is demonstrated in detail to show the great support that virtual optimization and qualification schemes can provide. They can reduce Time-to-Market of new SiP products by 50%-75%.References[1] https://doi.org/10.1109/ESTC.2018.8546352[2] https://doi.org/10.1115/1.4043341

Biography
Ghanshyam Gadhiya received his M.Sc. degree in Micro and Nano Systems, with a specialization in Finite element analysis of power module from Technical university of Chemnitz in 2013. Since 2014, he is working as a scientific researcher at the Micro materials center, Fraunhofer ENAS. His main research focus includes parametric finite element modelling, thermo-mechanical simulation and optimization of microelectronics packages using FE-program ANSYS. He has been also involved with several industrial projects for residual stress, humidity and vibrational analysis. His current research interests include fan-out wafer level packaging technology, system-in-package, virtual prototyping and micro-electronics failure analysis.

Innovative Packaging and Evaluation Approach for an Universal Sensor Platform

Brockmann, Carsten
Group Manager Sensor Nodes and Embedded Microsystems
Fraunhofer Institut für Zuverlässigkeit und Mikrointegration

Abstract
This article presents an innovative packaging and evaluation approach for a newly developed Universal Sensor Platform (USEP) based on a system in package RISC-V integrated microcontroller with a top-level functionalized system in package design. Specific functions of the sensor platform are assigned to four different physical levels in the whole integration concept. The technical implementation of the functional requirements requires innovative, technological solutions in the packaging and interconnection technology (AVT) but also new approaches for testing methods and infrastructure across the different levels.Starting from a bare die, inclusion of package co-design, new assembly and interconnection techniques, up to the provision of the evaluation and testing of the platform system, the increasing complexity of this research projects in microelectronics becomes apparent.In the final step of finalizing the system in package solution, the sensors are applied to the functionalized package surface. This enables the system to directly measure various parameters such as temperature, humidity and pressure. The electrical connection of the components is done on a multilayer redistribution layer, which is applied to the mold material of the package and connected to the underlying system core with through package vias. For testing, a modular evaluation board is available, which allows the connection of an FPGA-based emulation environment. Furthermore, various test adapters can be connected to the data bus, thus significantly increasing the modular testability. A test socket detachable from the circuit board connects the manufactured modules with their 256-BGA footprint with all electrical operation and debug signals and plays a central role for the actual chip test because it enables short testing and configuration cycles.

Biography
Carsten Brockmann studied Technische Informatik at the Technical University of Berlin and received his diploma in 2008. He worked as a scientist at the Forschungsschwerpunkt Technologien der Mikroperipherik in the field of wireless sensor nodes until 2014 when he changed to Fraunhofer Institute for Reliability and Microintegration. In different national and international research projects he proceeded with his research work and became the group manager for sensor nodes and embedded microsystems in 2015.

Enabling Assembly and Packaging Material Developments for Next Gen RF Devices, Antennas and Radars

de Wit, Ruud
Business Development Manager EMEA
Henkel Belgium NV

Abstract
Smart Electronics’ market trends like 5G Telecom and Autonomous Driving are leading advanced semiconductor packaging innovations towards higher functionality, enhanced connectivity at higher frequencies, RF signal interference isolation (shielding), smaller form factors (miniaturization) and reduced power consumption. To meet these demands, semiconductor package designs continue to evolve towards MULTIPLE DIE using System-in-Package and Wafer Level architectures. Especially for next generation RF devices, antennas and radars, the thermo-mechanical, thermal resistance and (di)electric properties of the assembly and packaging materials play a key role as well as fast and low temperature processing/curing. This presentation will give an overview of the challenges and solutions from a semiconductor packaging material perspective based on recent customer experiences and ongoing developments to enable new designs. The focus will be on thermal performance of different die and lid attach assembly methods and thermal interface materials, EMI shielding effectiveness of thin silver layers, dielectric constant and loss factors of liquid wafer level encapsulants and underfills at 28-50 GHz and above, etc.

Biography
Ruud de Wit is responsible for managing Henkel's Semiconductor, Sensor & Consumer Electronics Assembly Materials business development within EMEA region. Ruud has a BSc degree in Mechanical Engineering followed by several polymer, sales and marketing courses. Ruud is working for Henkel since 1990 in multiple positions including technical customer support, quality assurance and engineering, and global semiconductor account and product management.

Incorporating Subfab into Factory and Tool Digital Twins

Neel, Michael
Marketing Manager - Intelligent Manufacturing Systems
INFICON

Abstract
The impact that facilities and subfab components has on the performance of process equipment is important at all levels of manufacturing. As part of an Industry 4.0 Smart factory, the ability to sense all relevant parameters, connect the subfab components to the Digital Twins, and predict performance degradation or failure is critical to providing much needed information and enabling better operations and process control.This discussion will focus on multiple integration and interoperability points allowing for: 1) Integrating pump and abatement systems with a factory-wide FDC system to provide better data collection and analysis to the tool-based Digital Twin, 2) Providing process data and state information from the FDC system to the pump control framework to allow for better predictability of future failure, 3) and FDC system providing full health and state information from the equipment and subfab components to the factory Digital Twin and WiP Scheduling system to provide optimal operational efficiency.

Biography
Michael Neel is the Marketing Manager for INFICON's Intelligent Manufacturing Systems (IMS) focusing on process control and factory operations optimization. Michael has worked in the Semiconductor Industry for 26 years of which half has been with INFICON providing leadership in process control and factory optimization software systems. Michael graduated from Texas State University with a Bachelors of Science in Chemistry, Masters in Technology, and a Masters of Business Administration from St. Edwards University.

Challenges for Heterogeneous Integration in Package – Applications driving Materials and Processes towards Diversity

Meyer, Thorsten
Lead Principal Engineer
Infineon Technologies

Abstract
ABSTRACT Challenges for Heterogeneous Integration in Package –Applications driving Materials and Processes towards Diversity by Thorsten Meyer and Klaus PresselInfineon Technologies AG, Regensburg Heterogeneous Integration is a major technology driving force for microelectronic systems. More-than-Moore (MtM), System-in-Package (SiP), as well as 3D high-density integration technologies are a prerequisite for enabling the design of compact microelectronic devices. Heterogeneous Integration refers to the integration of separately manufactured components into a higher level of assembly, which is providing enhanced functionality and operating characteristics. In this definition, components should be taken to mean any unit, whether individual die, MEMS or sensor device, passive component and assembled package or sub-system, that are integrated into a single package (see e.g. Heterogeneous Integration Roadmap published for the first time October 2019). The requirements for integration of the mentioned components are differing strongly depending on application. Integration of power devices requires thick copper with large area connections for thermal properties and current carrying capabilities, e.g. a solution for vertical current flow. For mm-wave applications, precise knowledge of material parameters and dimensions is required to fabricate leading edge devices like radar or LIDAR for future autonomous driving. Logic integration typically requests for many short interconnects, fine line spaces and tight pad pitches in a horizontal arrangement of the contacts. MEMS and sensor devices often require a special protection and are sensitive in handling during production. Packaging often is customized to the application. In addition, the integration of passives, e.g. resistors, inductors, capacitors, as well as shielding capabilities or antennas require special packaging building blocks for an application tailored integration. All these different constraints lead to an extreme diversity of package solutions very difficult to tackle.In this presentation, we will discuss the challenges and introduce potential solutions for different integrated applications. We will highlight the importance of virtual prototyping, chip-package-board/system co-design as well as reliability prediction, which require detailed understanding of material properties and their interfaces. Especially, we will emphasize the increasing importance of knowledge on material physics. For example, investing into physics of advanced failure analysis is a major enabler for faster and more reliable development of innovative devices. We will show examples of building blocks for different areas of integration, which we must develop for the supply of integrated packages for future applications. Heterogeneous integration combined with miniaturization capability, i.e. more functionality in smaller volume, will drive us in future microelectronics.

Biography
Thorsten Meyer is Lead Principal Engineer Package Concept Engineering at Infineon Technologies in Regensburg, Germany, responsible for New Package concepts. Until March 2015 he was leading the Package Technology and Innovation department at Intel Mobile Communications (IMC) in Regensburg. Prior joining IMC, he was overall project leader for the development of Wafer Level Packaging Technologies at Infineon in Regensburg and earlier in Dresden.Thorsten is author of multiple publications and holds more than 150 patents and patent applications in the area of advanced packaging.

Flip-Chip Scale Package(FCCSP) Process Characterization and Reliability of Coreless Thin Package with 7nm TSMC Si

De Mesa, Eduardo
Package Engineer
Intel Deutschland GmbH

Abstract
Advanced silicon nodes are continuously pushing the cutting edge of assembly technology for coreless thin packages used in mobile and electronic products to allow better power delivery, electrical performance, and higher routing capability. This results in a higher number of I/O and integration flexibilities. Furthermore, integration of a large die size in a smaller package with finer bump and ball pitches, increases the reliability risk. Also, typical mobile applications require stacking a memory die within the package without increasing the total package height. These combinations magnify the stress on back-end-of line (BEOL) stack and bump interconnection-especially on a thin coreless substrate which greatly influence extreme low-K dielectrics (ELK) fragility.This paper describes the qualification of the 7nm silicon (Si) BEOL stability on thin coreless embedded trace substrate (ETS) with smaller solder ball pitch and a high die to package aspect ratio. In our previous experience, coreless material is generally prone to warpage due to absence of the core that supports the package rigidity. Therefore, controlling and minimizing warpage at room and elevated temperature is crucial, as the stress propagates into the BEOL, resulting in a significant impact on the chip reliability, especially for ELK structures. Simulation of thermal and mechanical stress in Finite Element Modeling (FEM) was completed to confirm warpage behavior. Shadow Moiré was documented under temperature loading and package coplanarity empirical data was collected.Within the development phase, the package warpage was successfully reduced and coplanarity on thin coreless substrate was within specification. Significant improvement is attributed to mold compound higher coefficient of thermal expansion (CTE) and lower elastic modulus. Multiple reliability tests in accordance with JEDEC standard was conducted. Results confirmed the BEOL stack integrity and all related tests passed.

Biography
Eduardo De Mesa received B.S Mechanical Engineering from Mapua Institute of Technology, Manila, Philippines. Currently, working under Technology Enablement Group engaged in advanced package development at Intel Deutschland Gmbh.

Active Mold Packaging for novel Antenna-in-Package interconnection and manufacturing

Roick, Florian
Business Development Active Mold Packaging
LPKF Laser & Electronics AG

Abstract
IC package designers wishing to benefit from space saving Antenna-in-Package (AiP) technologies rely on an intricate selection of materials and interconnect processes to produce a self-contained integrated module. This paper presents a new way to reduce the production complexities of AIP by introducing a novel homogeneous packaging technology: Active Mold Packaging (AMP). Active Mold Packaging directly establishes electrical connections, such as patch antennas, signal vias, and Electro-Magnetic-Interference (EMI) shields for RF applications on the surface and in the volume of the encapsulating Epoxy Mold Compound (EMC). Advancing the development of multifunctional compact devices, AMP in essence transforms the passive and undeveloped real-estate of the EMC into an active carrier of package functionality.A 2.5D interconnect technology to simplify AiP designs and EMI shielding will be presented. AMP integrates familiar process steps: molding of EMCs, Laser Direct Structuring and direct electro-less and galvanic plating. In combination the processing steps result in a robust scalable manufacturing solution, AMP. AMP is uniquely suited for the production of AiP but also a foundation design platform for other novel IC packages.Critical process attributes of AMP are discussed and used to propose a commercial AMP-AiP model. Measuring the influence of key design elements of an AMP fabricated EMC micro strip antenna and EMI shield within the 5G radio frequencies; sub-6GHZ, mm-wave, and beyond 5G (« B5G ») ISM bands yields strategies for implementing the AMP technology. Consideration is granted to the impact of the LDS activator, the laser structuring parameters, and electroless plating factors on the model devices. Lastly, the proposed commercialization of the AMP-AiP is modelled through a cost-model comparison.

Biography
M. Sc. Florian Roick, Business Development Manager Active Mold PackagingBorn in 1981. He holds a degree as Bachelor of Science in Applied Physics from Dublin Institute of Technology. And a degree as Master of Science in Electrical Engineering with focus on laser systems, laser physics and microsystems engineering from Hochschule Bremen.Since 2006 employed at LPKF Laser & Electronics AG, until 2008 as application engineer for the StencilLaser business unit. Between 2008 and 2019 strategic product manager responsible for aligning the product portfolio with the needs and requirements of the PCB and SMT markets.Since 2019 Business Development Manager for LPKF’s Active Mold Packaging technology. That is to electrically functionalize the real-estate of the epoxy mold compound on the base of LPKF’s patented Laser Direct Structuring (LDS) technology.Co-inventor of the parametric stick-in and co-author of a variety of publications.

AMLS Hybrid implant technology and product

Horn, George
Director
Middlesex Industries SA

Abstract
Automated Material Logistic Systems (AMLS) are the infrastructures of modern manufacturing. In semiconductor factories there have been a) Manual Discrete Lot (MDL), b) Automated Discrete Vehicle (DV), and c) Asynchronous Track (AT) Work in Process transports employed. DV and AT systems span the 200 to 300 mm Wafer format manufacturing. Capabilities and shortcomings characterize each of the above. Integrating the two is superior to either one alone. A new technology c) Hybrid, is the implantation of AT networks into existing DV installations.b) DISCRETE VEHICLE (DV) AMLS. Conceptually simple discrete vehicle delivery is popular. Discrete vehicles delivering wafer lots is easily understood. It is exactly as manual delivery before, but automated. Also easily understood is the dropping of wafer lots from overhead. Therefore, AMSL systems combining these concepts are dominant. They simply automate the manual delivery method. But discrete delivery logistics has no absolute mathematical solution. It works with heuristics. Capacity constraints and system instability, requiring storage, are the draw backs. c) AT NETWORKS. Asynchronous Track AMLS is based on continuous flow of work, massively parallel, and asynchronous. Such networks are always, and immediately available to transport, without capacity constraints. And can respond to load spikes, eliminating instability. And so, reduce fab cycle times. However, they need external hoists to connect to tools.d) DV & AT HYBRID AMLS. Asynchronous Track (AT) network island implants into Automated Discrete Vehicle (DV) AMLS impart greatly increased fab capacity, (balanced process capacities).Ref: Nonlinear growth of Variance in the Process Gaps. A cause of long Cycle times. G. W Horn, W. Podgorski, PhD, CSTIC, 2020

Biography
George W. HornMr. Horn received his BA degree from Harvard University in 1961, and his BS/MS degree in Applied Physics in 1963, also from Harvard University. He spent 7 years working at Ilikon Corporation in space technology. The company was a contractor for the Gemini and Apollo space programs. Later he focused on manufacturing science and statistical process control. He is a past director of the Washington based Automation Forum. During his years at Ilikon he served as Director of Applied Physics (Special Applications of Kinetic Theory). In 1970 Mr. Horn joined Middlesex General Industries as a founder, and served there as Applications Manager. In 1998 He founded Middlesex Industries SA, Switzerland and Middlesex Industries KK in Japan. He now serves as Chairmen for all Middlesex corporations. Mr. Horn has several publications and holds patents related to upper atmosphere simulation, and manufacturing technologies. He has developed the guiding principles for AMHS in Clean manufacturing industries such as Disk Memory Media, Pharma, and primarily Front end Semiconductors, concurrently developing the principles for conveyor based transport of Silicon Wafer Carriers. Globally first, his design was used to build integrated AMHS, direct tool to tool method, in IC manufacturing. His latest studies in AMHS are published in IEEE transactions. He is holder of numerous recent US, China, Taiwan, EU, and Korea patents in AMHS technology.Mr. Horn is a 20-year resident of Switzerland, where he lives today.

Cost-effective automation for legacy factories

Suerich, Doug
Product Evangelist
PEER Group

Abstract
The Industrial Internet of Things (IIOT) and rise of 5G have increased demand for electronics, and have introduced renewed need for automation at existing 200mm facilities. These “legacy” factories already run at full capacity and have little or no room for expansion, so manufacturers are seeking innovative ways to introduce Smart Manufacturing initiatives, increase productivity, and optimize throughput and yield to meet the increased demands. New facilities built to support older nodes sizes also want to capture market share, and have the same needs as their legacy counterparts.Although older node sizes and technologies are back in fashion, that doesn’t mean these facilities are limited to outdated manufacturing paradigms. Ambitious factories are looking at hyper-automated 300mm facilities to learn best-in-class methods for deploying automation and advanced manufacturing techniques. The SEMI® automation standards related to 300mm manufacturing describe efficient ways to implement automation, and these same models can be used in any facility, new or retrofit, to achieve major gains.PEER Group® provides products and solutions (including our PEER FACTORY® Station Controller, PFSC™) to rapidly update factory-wide connectivity, data collection, and control systems and allow any factory to integrate new and existing equipment efficiently. We help customers leverage best practices for factory automation and enable the latest advancements in analytics, scheduling, advanced process control, and predictive maintenance.

Biography
Doug Suerich is Product Evangelist at The PEER Group Inc., the semiconductor industry’s leading supplier of factory automation software for smart manufacturing and Industry 4.0. Doug focuses on big data and remote connectivity solutions that help manufacturers collaborate securely on tools and data in production environments. A passionate advocate for smart manufacturing, Doug serves as an active member of the SEMI® SMART Manufacturing Technology Community, Americas Chapter.Doug has over 20 years of experience leading software teams for a variety of industries including semiconductor, manufacturing, and transportation. Most recently, he was involved in architecting PEER Group’s remote connectivity solution, Remicus™, and he was a champion in promoting the use of cloud computing and latest-generation web technologies.Prior to joining PEER Group, Doug was a software development manager, automation engineer, information systems specialist, and consultant. He has extensive experience designing and integrating robust automation software solutions. Doug holds a Bachelor of Applied Science with Honours in System Design Engineering from the University of Waterloo.

From smart manufacturing vision to Innovative Advanced Service Solutions

Shekel, Eyal

Tokyo Electron Limited

Abstract
AI technology continuously becomes a key enabler for smart manufacturing. We / Tokyo Electron（TEL） see our equipment on a development roadmap from Single Standalone Tool to providing integrated manufacturing solutions enabled by AI. TEL will provide an insight where we see the actual benefits of data analysis in the process from R&D and Ramp Up, to High Volume Manufacturing. (e.g. Process Optimization and Virtual Metrology.)Through TEL SERVICE ADVANTAGE, we can respond to our customers’ requests and technical advancements promptly. An important component is our remote connection and data analysis capability. TEL analyzes equipment data from various sensors without the need of a physical on site presence, and provides solutions matched to customer-specific needs.

Biography
Eyal is a twenty-seven years veteran in the Semiconductors industry. Upon his graduation as a Mechanical Engineer from the Technion (Israel leading technical institute), Eyal has joined Applied Materials. In 1997 he has moved-on to Tokyo Electron, served as the Regional Service Manager of Israel, and soon after appointed as the company General Manager.Since 2005 Eyal has been part of the TEL European senior management, and up to 2019 was responsible for the Service and Support Operations for TEL Europe as a Senior Vice President.Last year, Eyal has transferred this responsibility onwards, and is now SVP for Service Strategy and Excellence. In parallel Eyal co-leads (as two in a box) the corporate Global Service Committee in TEL Japan.

Correct Material Selection and Life-Time Prediction of Elastomer Parts Using FEA Simulations

Gulcur, Murat
Material Development Manager
Trelleborg Sealing Solutions

Abstract
Choosing the right elastomer sealing material has utmost importance to maintain vacuum integrity in semiconductor processes therefore keeping the tool downtimes at minimum. Qualification of a new elastomer sealing material brings some risks for the end user as installing a new material can cause contamination or premature failures which can cause more damage than the benefits of the new sealing material. At this point, it is important for an elastomer part manufacturer to provide relevant data to prove the suitability of the material to the application such as plasma exposure tests in various different process gasses, outgassing, trace metal and extractables analyses results and to help understand other factors like the damping behaviour of the material.During a new material qualification another important topic is to determination of the lifetime of the sealing materials. It is extremely important for semiconductor OEMs to specify the right sealing material and microchip manufacturers to maximize the mean-time between cleans (MTBC). Sealing force created by a sealing part and its decrease over time. By using correct tests on this behaviour for input in advanced Finite Elemental Analysis (FEA), it is possible to predict the lifetime of the sealing parts by simulation. Such an analysis allows to capture the influence of both material properties and seal design on the lifetime. By combining data measured at elevated temperatures, a lifetime prediction for long time scales can be carried out based on test data of short time scales. The FEA will provide a prediction on the loss of sealing force over years and these results allow to estimate how many years the function of the seal can be fulfilled.

Biography
Murat Gulcur is Material Development Manager at Trelleborg Sealing Solutions UK. He has 17 years of experience in the field of elastomer technology and semiconductors, mainly single molecule/organic electronics. He holds a PhD degree in chemistry from Durham University (UK), has co-authored research papers in renowned journals and holds several patents.

Vertical stacking of controller IC on a copper clip attached on MOSFET as a space-saving solution for high current switch e-fuse applications

Attard, Alastair
Sr. Technical Program Manager & Assembly Business Development
United Test and Assembly Center Ltd

Abstract
Recently there has been an increasing demand for high-performance computing, mainly driven by data centers, online storage, cloud-based servers, and online software services. These applications require high computing power which drives high energy consumption, so the power systems employed need to run at extremely high efficiency and have small form factors, whilst offering very high reliability and minimal thermal losses during their deployment. This can be achieved by improving both the power semiconductor device technology, as well as the power packaging technology, such that maximum power performance and reliability can be extracted from the PCB area available.Power MOSFET technology has evolved to reduce switching losses and allow high frequency switching. Power modules have also been developed to integrate MOSFET dies together with a controller IC in a single package to offer a small form factor solution. From an interconnect perspective, copper clip bonding began to replace wire bonding technology due to the lower resistance and parasitic inductances it offers compared to wire bonding. Whereas most multi-die power module packages employ a side-by-side die configuration due to the wire bonding interconnect method, copper clip packages allow for vertical die stacking, which results in a smaller package for the same power rating.In this paper, we propose a QFN power module package solution for an electronic fuse (e-fuse) device in high-performance computing applications, comprised of a controller IC vertically stacked onto the copper clip used to create the interconnect between the MOSFET die and the lead frame. This approach provides a vertically integrated power module solution, offering a significantly reduced form factor versus a side-by-side power module approach or the use of two separate QFN packages for each die. Typical e-fuse applications need two separate QFN packages, for example, a 3mm x 3mm QFN for the controller IC and a 5mm x 6mm QFN for the MOSFET die, occupying a total of 39mm² of PCB area. Comparatively, a vertically stacked power module can be packaged in a 5mm x 5mm QFN occupying a total PCB area of 25mm², resulting in 36% less PCB area usage. The vertically stacked power module also offers excellent thermal performance despite the increased power density of the package. Thermal simulations performed using a 5mm x 6mm e-fuse package structure with 4.1W of combined power dissipation show that a Theta Ja of 25.3 ^oC/W and maximum temperatures of around 128.8^oC for the IC and 123.9^oC for the MOSFET are achieved under still air conditions.The assembly process flow will also be discussed in more detail, with focus on critical process steps such as vacuum reflow to ensure minimum voiding in the solder interconnects between MOSFET and lead frame, and copper clip and MOSFET. Examples of actual devices will also be shown. UTAC’s outlook on more advanced power modules will also be shared, showing proposals for packages with increased complexity using three dies and copper clips in a vertically stacked configuration for smart power stage applications with reduced footprint requirements.

Biography
Alastair Attard is Senior Technical Program Manager and Assembly Business Development at UTAC Group. He has a Bachelor’s degree in Mechanical Engineering and an Executive MBA from the University of Malta. He has over 14 years of experience in the assembly & test of semiconductor devices.Prior to joining UTAC, Alastair worked at STMicroelectronics Malta from 2006 until 2011, first as a Process Engineer on flip chip assembly for SiP and later as a Package Development Senior Engineer for SiP and MEMS packages. He later joined Besi in 2011, where he was Manager of the Process Development group until 2018. At UTAC, he is responsible for Technical Program Management and Assembly Business Development in the European region, with main focus on Automotive, Industrial, SiP, Power and MEMS areas.

Industrial Internet of Things in Western Digital Wafer Operation

Zhang, Feng
Director
Western Digital

Abstract
Industrial Internet of Things (IIOT) is a network of sensors, connections, data storage, data processing, data analytics, and automation. It is an important part of industrial 4.0.WDC HDD Wafer Operation has aged tool bases, many of which are not supported by the vendors any more. To replace the obsolete tools, it would require huge capital investment. At the same time, in order to deliver better performance, every new generation of magnetic head design post more and more challenge on the equipments. IIOT becomes a cost effective solution to address the equipment challenges.We have developed an IIOT infrastructure with standard components, of which leverages the existing factory system and state-of-art IT platforms. The internal IIOT solution considers the scalability, safety, support, latency, and automation. Several hundreds of sensors were deployed in the production. The internal solution is cost effective and significantly improved the yield. We has demonstrated millions dollars of capex and opex savings from IIOT projects.

Biography
Feng is the Directior of Advanced Data Analytics in WDC Wafer Operation. His team works on IIoT and advanced analytics. Feng has more than 15 years experience in magnetic head industry from research, failure analysis, yield engineering, to data analytics. He had a PhD degree in Materials Science from Columbia University in the City of New York.