Kraxenberger, Manfred
Vice President
ABB Switzerland

Biography
Manfred Kraxenberger is currently factory manager for ABB’s BiMOS wafer fab and assembly line in Lenzburg, Switzerland. Manfred Kraxenberger studied physical engineering and started working as process engineer at Siemens Semiconductor in Munich in 1986. Over the last 30 years, he has held several engineering and management positions in manufacturing as well as R&D at Siemens/Infineon/Qimonda and Globalfoundries. Prior to his current position he was in charge of ABB’s Bipolar factory.

MEMS - General and Plasma Dicing Process

Holz, Bernhard
Process Technology Manager
Accretech Europe GmbH

Abstract
MEMS devices such as Pressure sensors, Accelerators, RF-MEMS, Microphones, Bio-MEMS, Printer heads, etc. are very sensitive and hence require gentle die singulation technique. Such technique needs to be very clean, not generating any particles, preventing mechanical stress, vibrations, or ESD damages, and in particular, it should work without any cooling fluids. As well known from conventional diamond blade dicing all these influences may damage fragile mechanical MEMS structures like membranes, micro holes or sensitive chemical coatings. In contrast to blade dicing and other ablation laser techniques, the “ML laser technology” is using a low energy IR laser beam that is focussing into the Silicon bulk. Hereby a so called modification layer with defined punctual stress profile is generated that works effectively as a hyphenation point. The die separation itself takes place by subsequent dicing tape expansion. Since only a very limited interior region of the wafer is processed by laser beam irradiation, mechanical or thermal damages and die edge chipping can be avoided. Latest ML dicing machine generation and its accessory tools combines fully automatic operation, superior die separation quality with high productivity. The latter is achieved by a newly developed multi-beam laser engine that is built on a high speed machine platform allowing dicing feed speeds up to 1000mm per second. The presentation provides an overview about typical MEMS applications for the ML singulation process, its requirements and limitations, as well as about laser dicing process variants like double side laser irradiation of MEMS wafer stacks and laser irradiation through tape (LTT).

Biography
Bernhard Holz has more than 30 years of experience in production of semiconductor devices, especially in mechanical processing technologies like wafer grinding, polishing and dicing. He made a diploma in mechanical engineering at the Technical University Berlin, afterwards he received a PhD in the field of Silicon wafer manufacturing and sub-surface damage analysis at the PTZ Berlin. From 1994 he worked as R&D Manager for a supplier of wafer slicing and grinding machines. He jointed Accretech Europe in June 1998. As Process Technology Manager he is responsible for customer application support for Polish Grinders as well as Wafer dicing machines. As head of the European demo & application center in Munich he further drives blade and laser dicing process developments, evaluations and services for various European Semiconductor as well as MEMS companies.

Kroehnert, Steffen
Senior Director Technology Development
Amkor Technology Holding B.V., Germany

Biography
Steffen Kroehnert is Senior Director Technology Development at Amkor Technology, Business Development Europe. Before the acquisition of NANIUM by Amkor Technology in May 2017, he worked for 20 years in different R&D and management positions at Siemens Semiconductors, Infineon Technologies, Qimonda and NANIUM in Germany and Portugal. Steffen is active member of several technical and conference committees of IEEE EPS, IMAPS, SMTA and SEMI. Since begin of 2016 he is chair of the European SEMI integrated Packaging, Assembly and Test (ESiPAT) Special Interest Group. Steffen is author and co-author of 23 patent filings and many technical papers in the field of Packaging Technology. He received his Master of Science degree in Electrical Engineering and Microsystems Technologies from the Technical University of Chemnitz, Germany, in 1997.

MEMS Sensor Testing - Yesterday, Today and Tomorrow (an OSAT's perspective)

John, Gerard
Sr Director Advanced Test
Amkor Technology Inc

Abstract
The concept of MEMS sensor testing has evolved from a fantasy to a reality over the last two decades. What was once considered impossible in high volume manufacture has now become mainstream in the industry. Initially, MEMS sensor devices were introduced as an alternative to bulky technologies, with lower performances than their predecessors. However, today's MEMS devices with proven reliability and performances have surpassed their predecessors and are competing with their high-cost and high-end counterparts. Examples of such MEMS sensor devices can be seen in the MEMS microphones whose early specifications started off as a simple audio transducer, now has morphed into high-fidelity MEMS device, competing with the high-end studio microphones. Testing such “high-performance” MEMS sensor devices in high volumes at the lowest possible costs with little or no compromises calls for an innovative combination of test techniques and close cooperation between the OSAT and the MEMS design engineers, product engineers and the applications engineers. Areas that are often overlooked are, the form factor of the device under test, the use of test techniques that can provide a higher throughput than electrical testing and the final end application. The ability to include self-test and self-calibration structures into the design will reduce the test burden. The main challenge faced during MEMS sensor test is in the stimulus development, while the electrical testing can be easily accomplished by a low-end tester. When creating MEMS test specifications, a careful balance needs to be drawn between too much and too little test coverage. This keynote focuses on the evolution, challenges, and opportunities for MEMS sensor testing spanning the yesterdays, today and will provide a vision for the future of lower cost MEMS sensor test.

Biography
Gerard joined Amkor in 2005, and has supported and managed hardware and software test development for a variety of Amkor packaging. He currently serves as an advanced test technical expert for MEMS, 2.5D, WLFO, HDFO, fine pitch probe and optical devices, supporting customers in the US and Europe. Prior to joining Amkor, Gerard worked in various semiconductor test positions for Conexant Systems, Flarion Technologies (acquired by Qualcomm) and Motorola. He holds a BA degree in electronics and telecommunications engineering from Osmania University and an MBA from Gainey School of Business in Michigan. He holds multiple patents in the field of MEMS Test.

Requirements for an Adaptable Material Tracking Solution of a 200mm Wafer Fab

Leditzky, Guenter
Senior Project Manager
ams AG

Abstract
The production logistics within wafer manufacturing follows a complex iterative flow through hundreds of process steps until the integrated circuit on the wafer is finished. For fully automated 300mm wafer fabs state of the art solutions for material tracking systems are available, while for 200mm semi automated fabs the original logistics solutions are outdated and no more supported. The functionality of the material tracking system and its integration into the MES environment of the shop floor impacts traceability and productivity and defines the user interface to the operator. Based on ams AG’s 200mm SMIF wafer fab this presentation will give an insight into the requirements for an adaptable wafer tracking and localization solution that supports current and future wafer manufacturing needs.

Biography
Guenter Leditzky was educated in mechanical engineering and physics and received his Ph.D. in solid state physics from Graz University of Technology. In 1995 he joined the process transfer group at ams AG. He could gain comprehensive experience in semiconductor manufacturing as he managed the process engineering group, the deposition module, and production line control at ams’ wafer fabs. In 2006 he founded his company “Technology Consulting and Project Management”. Since October 2007 Günter is employed as project manager at ams, where he has been responsible for Fab extensions and production ramp, the implementation of Fault Detection and Classification and Real Time Dispatching. Currently Guenter is working on the upgrade of the Material Tracking System in ams’ 200mm wafer fab.

Predictive/Preventive Maintenance + Fab-Planning 4.0, via Augmented reality solutions

Bausch, Tobias
Director Sales & Marketing
AP&S International GmbH

Abstract
Imagine the following situation: You need a new wet process tool and therefore a supplier is visiting you in your fab. But he doesn’t show you some catalogues and presentations, but instead brings you a realistic virtual model of the required wet process application and positions it directly in your production hall. From the very first moment during your first supplier meeting you see how the offered wet process tool fits into your fab and which local adjustments are necessary e.g. additional space creation, adaptation of the exhaust system or others. The result for you is an optimized fab planning before the production start or the tool ordering. This great process is offered to you by the AP&S Augmented reality solution. Through a realistic, detailed visualization integrated into the real environment of your fab, you get an outlook to your future fab view. Further advantage of this AP&S solution is an optimized construction process, as the verification of design plans is possible in a very early project phase and via a virtual design review, the system including all subsystems can be viewed and discussed in a comfortable and easy to understand manner. It happens thanks to various simulation options enabling optimized matching of customer needs and supplier suggestions before and during the developing process. But our Augmented reality solution doesn’t end with the delivery of the ordered tool. It continues in the area of predictive/preventive maintenance and brings you time and cost savings in this field. The benefits of our Augmented reality solution are varied, so come and see how it can improve the performance of your fab. I look forward to meet you at the Fab Management Forum.

Biography
Tobias Bausch has been involved in the semiconductor industry since 2005. In 2007 he joined AP&S International GmbH, an international active provider of wet process solutions. In 2015 he moved to his actual function as Director Sales & Marketing. He holds a Master Degree in Technical Management CCI.

UBM Metallization Technology for advanced semiconductor devices

Preisser, Robert
Director Process Technology
AP&S International GmbH

Abstract
As semiconductor device geometries further shrink more devices migrate from wire bonding to flip chip technologies to overcome the technical limitations of the bonding technologies such as electrical resistance or the geometrical dimensions. An under-bump metallization (UBM) is used as an alternative for the different options of device metallization such as Al-, Al-alloys and Cu to act as electrical contact, adhesion promoter and protection layer between this chip metallization and the following solder bump technology. However the UBM deposition incl. pre- and post- treatment of the incoming wafers are critical to the interface stability and to reliability performance of the complete device. Some of this representative aspects has been evaluated, analyzed and assessed under different processing and/or test conditions using different material science and electrical test conditions.

Biography
CV Robert Preisser Director Process Technology AP&S International, Donaueschingen, Germany • Started my professional career at IBM semiconductor development facility in Sindelfingen, Germany as process engineer with a chemical engineering background in 1974. Held several technical lead positions in various fields of SC technologies, including 3 technical R&D assignments (total of 5 years) to the IBM facilities in Burlington and Fishkill. • Joint 1994 the semiconductor high purity chemistry division of Merck, Darmstadt, Germany as senior manager. Responsible for the development, build- and qualification- of high purity chemical supply units including the global high purity chemical service division • 2012 joint Atotech, Berlin, Germany as VP- for the new established semiconductor metallization division. Founded and led for 4 years a new SC- chemistry research approach at CNSE in Albany, NY, USA. The approach included a R&D cooperation (2012) with Case Western Research University in Cleveland, OH for electrochemical research. Retired from Atotech in 2014. • From 2014 until today part time adjunct professor at Case Western Research University in Cleveland and part time director for SC-processing technology at AP&S in Donaueschingen, Germany. >100 publications in Semiconductor processing, SC- and MEMS- material development and application engineering. Patents in SC-metallization technologies

Flexo printing and selective sintering of metal based inks on paper – Optimization of RFID-HF loops for mass production

Thénot, Victor
Research Engineer
Arjowiggins Creative Papers

Abstract
This work examines the potential of paper for the production of printed NFC tags. Paper characterization demonstrates high temperature tolerance and very low roughness enabling the electrical performance of conductive inks to be fully developed. Flexo process was considered for the printing of low-cost electronic devices. Moreover, the electrical performances of silver based inks are studied according to the size of their particles. Indeed, the use of metal nanoparticles can facilitate the activation of atomic diffusion mechanisms. In parallel, microparticles are cheaper. In any case, the coalescence of the metal particles after printing cannot be initiated without a thermal sintering treatment. Sintering is usually carried out in an oven, temperature must therefore remain below the tolerance of the substrate. This leads to limited electrical performances for long duration. To fit with industrial constraints of large-scale production and to achieve the best electrical performance in a short time, deployment of emerging near-infrared (NIR) and intense pulsed light (IPL) photonic technologies is considered. These latter are based on the absorption of light energy by the ink thus causing rapid heating. The important absorption differential between the inks and the substrate allows high heating selectivity which makes it possible to limit the degradation of the substrate while the ink temperatures may be greater than 300 ° C. For each sintering process, the influence of the various parameters on the final electrical performance has been studied by using an in-situ resistance monitoring, allowing sampling frequency up to 250 kHz. Finally, RFID-HF loops were printed, sintered and characterized while an estimate of the production costs was carried out. The obtained results demonstrate the potential of paper, coupled with flexographic roll-to-roll process and NIR technology, enabling the large-scale production of RFID-HF tags at a material cost of the order of 5 euros cents.

Biography
Victor THENOT was born in Paris, France, in 1989. He graduated from PAGORA, the International School of Paper, Print Media and Biomaterials (Grenoble-INP) in 2013. He joined the Arjowiggins group (leading producer of specialty papers in Europe) in 2011 as an engineering apprentice during which time he worked on the development of PowerCoat® paper, a specially designed substrate for the printed electronics market. He received the Ph.D. degree in 2017, for his work on printed RFID tags on papers carried out in partnership with two laboratories: the French Laboratory of Pulp and Paper Science and Graphic Arts (LGP2) based in Grenoble, and the Microelectronics Center of Provence (CMP), part of the Ecole Nationale Supérieure des Mines de Saint-Etienne. His current research is in the area of printed electronics on flexible substrates with a particular focus on printing, sintering and RFID tags design and manufacturing on paper substrate.

Towards Next Generation Architectures

Monchalin, Eric
Head of Machine Intelligence
Atos

Abstract
Difficult though it is to believe, the small, micro, even nano computers we encounter every day are the direct descendants of the von Neumann architecture described in 1945, which gave birth to the general-purpose computing model, and created the software revolution. Future architectures will disaggregate monolithic components like general purpose CPUs, operating systems and middleware, providing the required insertion points, adding flexibility and improving security. Quantum computing will inevitably be delivered with a mixture of general purpose CPUs, Quantum hardware and other accelerators, which will enable application developers to restructure their applications to benefit from the distinct capabilities of each specialized element. But, computing will no longer be restricted to traditional platforms, but will be embedded in almost everything, and interconnected in a way that establishes an unprecedented Computing Continuum. A plethora of sensors, actuators, robots, drones, cars etc. will not just act standalone. They will be part of an all pervading, interconnected network that exhibits enormous complexity, particularly at the ‘edge’ of the ecosystem, creating a cognitive loop. It is driving to the emergence of Swarm Intelligence where the individual computing capacity of the devices at the edge will be complemented and supplemented by their dynamic cooperation with other objects in swarm communities acting as an intelligent whole. It perfectly fits the emergence of the networked connection of people, process, data and things that is exploding, pushed by business models, for which current architectures will not work anymore.

Biography
Eric is Vice-President, Head of Machine Intelligence at Atos. He’s responsible for solidifying new technological and business directions for Big Data Global Business Line. Eric’s career has been mainly built on numerous R&D positions in several companies, with experience in leading 100+ people organizations and managing large projects in international environments. Eric’s best memory is the first Supercomputer Bull delivered CEA end 2005 and which was ranked number 5 worldwide. He was in charge of this multi tens millions Euros project on behalf of Bull R&D: technical presale, design, development and on site bring up. Eric is a technology-minded person who values wide range of skills and technological knowledge focused on customer wishes to turn them into reality.

Electroless ternary nickel alloys for under bump metallization (UBM) on power semiconductors for high temperature process conditions or applications

Walter, Andreas
Electroless Team Manager
Atotech Deutschland GmbH

Abstract
The presentation will show benefits and feasibility results for electroless plating of different ternary nickel alloys in comparison to the standard electroless phosphorous-containing nickel for packaging in growing power electronics or automotive industry. Standard electroless phosphorous-containing nickel for ENEP* or ENEPIG** under bump metallization has the disadvantage that at temperatures above 350°C a phase transition occurs which leads to a layer stress change and may cause cracks in the under bump layer. Ternary nickel alloys reveal no phase transitions up to 600°C, and are an excellent alternative to the standard electroless medium or high phosphorous-containing nickel for high temperature processing post nickel deposition, and high temperature soldering or applications. The paper will showcase results of the advanced properties of three different electroless ternary nickel alloys in comparison to a standard medium phosphor and a low phosphor nickel, with regards to thermal behavior, stress shift, and facture toughness. *electroless nickel, electroless palladium ** electroless nickel, electroless palladium, immersion gold

Biography
Andreas Walter has more than 18 years experience in the semiconductor industry and is currently working as head of application for electroless plating processes for Semiconductor Advanced Packaging at Atotech. Prior to joining Atotech in 2009, he worked for 3 years as an Senior Engineer at Qimonda for process integration of new memory systems, and for 7 years as a Development Engineer at Infineon, where he was responsible for material development and process integration in 300 and 200mm fab for D-RAM and resistive memories. Andreas received his Diploma and PhD in chemistry at the Martin Luther University in Halle, where he started as a scientist for synthesis of OLED dyes and organic semiconductors.

Enhanced Mechanical Properties of Copper for Fan-Out Wafer Level Packaging Applications

Schmidt, Ralf
R&D Manager, Semiconductor
Atotech Deutschland GmbH

Abstract
Redistribution layers are essential to a variety of packaging technologies, as it is with more RDLs that I/O density is increased. Increasing the I/O count allows for more complex, high speed die to be packaged and supports improved reliability performance. Next generation devices for FOWLP require decreasing the RDL pitch down to 2x2µm. Successful formation and plating of such fine features, however, pose a challenge for both suppliers and manufacturers, with the primary plating challenge being the simultaneous plating of ultra fine L/S, large Cu pads, and filling of microvias with a deposition rate that optimizes throughput. Additionally, the mechanical properties and impurity requirements for the Cu deposition become more difficult to control and optimize with sub 10µm L/S: 1) (large) optimum grain size, polygonal Cu crystal structure for high (ductility) mechanical strength and low resistivity which impacts electrical performance; 2) low internal stress for minimized wafer warpage and good adhesion – both of which impact yield; and 3) low organic co-deposition for minimized micro voiding. Electroplating with standard Cu electrolytes results in micro voiding that amass after thermal cycle testing and may lead to failures or breakages in the Cu metal lines. To overcome this, the bath conditions, additives, and current density should be adjusted to optimize their influence on the deposit properties in terms of impurities and grain size. This paper will discuss how the mechanical properties of Cu can enable higher reliability, and will present plating results achieved with a new electrolyte.

Biography
For the past 6 years Ralf Schmidt has held various roles related to R&D at Atotech Deutschland GmbH, wherein he focused primarily on the development of innovative copper plating processes. He was Team Manager for the central R&D team New Methods & Technologies and has recently assumed the role of R&D Manager Semiconductor Advanced Packaging. He started at Atotech in 2011 in the central R&D team, where he focused on a variety of topics including additives for electrolytic and electroless Cu deposition as well as electrolytic and electroless Ni processes. Ralf recieved his PhD in Chemistry at the Julius-Maximilian University of Würzburg, Germany, where he began his career as scientist for the synthesis of dyes for organic electronics.

Mechanical Properties of Copper for Advanced Packaging

Memmert, Ulrich
Senior Scientist Material Science
Atotech Deutschland GmbH

Abstract
Mechanical properties of Cu structures become increasingly important upon shrinking dimensions and increasing complexity of redistribution layers. Such properties, like e.g. ductility, are often discussed in the context of reliability considerations. Commonly, experimental data for free standing films of around 50 µm thickness are used. The influence of the layer thickness and the interactions with the substrate and the surrounding materials are typically unknown. Thin Cu films were investigated as free standing films (Cu thickness 10 µm – 50 µm) by tensile testing. The ductility and the yield strength were determined. Samples were also investigated for Cu thicknesses between 10 µm and 50 µm by a cyclic bending test. From these data the fatigue ductility was determined. For some of the samples, the grain structure was investigated before and after bending by secondary electron microscopy (SEM). Results show that the measured tensile ductility varies significantly with layer thickness. For low layer thickness, it decreases and fatigue ductility decreases with decreasing layer thickness. SEM imaging shows the grain structure for the original layers to be rather independent of the layer thickness. After tensile testing a clear refinement of the grains is found. This paper will discuss the results of the experiment and their impact on advanced packaging.

Biography
Ulrich Memmert studied physics in Berlin and Marburg. After receiving his PhD in 1986 he worked at the University of Western Ontario, Canada, the IBM T.J. Watson Research Center, New York USA, the University Munich, the University Ulm, the research center Jülich, and the University Saarbrücken. He finished his Habilititation in experimental physics in 2001. Since 2001 he is with Atotech Germany in various positions.

Tomorrow's Digital Mobility Experience - Enabled by Semiconductors

Müller, Thomas M.
Executive Vice President, Development Electrics/ Electronics, CarIT
AUDI AG

Abstract
The progressively rising importance of semiconductors in automotive applications is a known fact. Semiconductors will enable a completely new mobility experience and facilitate new business models. New data driven in-vehicle architectures with a secure end-to-end cloud connection as well as the ability to update and upgrade vehicles are just two upcoming applications. How do the automotive and the semiconductor value chain face these challenges? How do these industries need to cooperate and collaborate to ensure speed and joint success in a fast changing global environment of mobility?

Biography
Dr. Thomas M. Müller studied Physics and started his professional career in 1999 at BMW Group in Munich. There he worked internationally in different strategic and operative management positions, for example in the development of electrical and electronic systems. In the area of business IT Dr. Müller accelerated the digitization of business processes. From 2009 to 2012 he was Director Connected Carat BMW Group. Subsequently, Dr. Müller went on to Volvo Car Group as the Vice President Electrical & Electronic Systems Engineering. In 2014 he additionally took over responsibility for the unit E-Propulsion (electric drive) and from 2015 he has held the position of Vice President Electrics/Electronics & Chassis. Since December 2016 Dr. Thomas M. Müller is Head of Electrics/Electronics, CarIT of AUDI AG and drives out of this role the digitalization of the vehicles and mobility services.

Pristauz, Hugo
Vice President, Technical Development Advanced Technology DA
Besi

Biography
Dr. Hugo Pristauz is VP at Besi for technology development and has about 20 years of experience in advanced die attach equipment area, both in R&D and business positions. He started his semiconductor carrier by joining Datacon in 1999, where he was majorly assigned to product management and development of the successful 8800 advanced die attach platform. After acquisition of Datacon by Besi in 2005 Hugo Pristauz was running emerging die attach business in VP position like RFID, flip-chip, thermo-compression and fan-out bonder business. Since begin of 2016 Hugo Pristauz is focusing on technology scouting and networking to support Besi's roadmapping process.

Guerrero, Douglas
Senior Technologist
Brewer Science, Inc.

Biography
Douglas Guerrero received a PhD in Organic Chemistry from the University of Oklahoma, USA. After a post-doctoral appointment at the University of Texas - Dallas, he joined Brewer Science in 1995 and where he is a Senior Technologist in the Semiconductor Materials Business Unit. Dr. Guerrero is a Senior Member of SPIE and currently serves in the SPIE Advance Lithography and the International Symposium on DSA committees. He has over 60 publications and patents in the field of lithography. He is currently on assignment at imec in Leuven, Belgium where he is responsible for patterning process development using immersion, Directed Self-assembly and EUV lithography.

Maintenance Management 4.0

Kinauer, Jochen
Director Channel Sales
camLine GmbH

Abstract
Highly productive, profitable manufacturing must also focus on the automation of maintenance in order to work efficiently, flexibly and sustainably. The purpose of intelligent maintenance is more than just organizing the maintenance staff! - It must analyze process data for predictive maintenance, observe the material flow, keep spare parts, coordinate the maintenance staff and, of course, document maintenance activities. In addition, it is important in a complex production with large plant inventory that the maintenance measures and experiences are documented as best-known methods (BKM). There are different maintenance methods like corrective, predictive or preventive maintenance. Each maintenance type may be used at specific occasions, depending on the impact to the life time of the equipment and production. Predictive Maintenance as the most complex maintenance type requires that equipment data is analyzed with statistical methods like Western Electric rules. About camLine camLine (camLine.com) develops and markets its own software providing powerful solutions to the challenge of "Manufacturing Excellence" in the MOM sector. camLine’s IT-based infrastructure systems are used in the manufacturing of high-tech industries. camLine's priorities are quality assurance with SPC/APC/SQM, process integrity with a recipe management, production logistics, efficiency (OEE), shop floor integration, engineering analytics, machine maintenance, and innovation efficiency. Training and consulting is provided by camLine’s own academy. camLine has been offering its services worldwide for more than 29 years.

Biography
Jochen Kinauer currently serves as Director of Channel Sales and Public Relations at camLine GmbH. In his career, Jochen was responsible for SW Automation Projects for Semiconductor Manufacturing, which includes MES, Equipment Integration, Tool Controls, FDC, APC and SPC. In addition Jochen Kinauer serves as Cluster Manager at Silicon Saxony e.V. for the cluster Advanced Semiconductor Manufacturing Technologies and RFID. As part of his role Jochen organizes an annual RFID Symposium in Dresden, showing new developments and technologies in the area of RFID and Indoor Material Tracking that takes place every year at the beginning of December in Dresden, Germany.

EUV Lithography optics - current status and outlook

Jürgens, Dirk
Program Systems Engineer
Carl Zeiss SMT GmbH

Abstract
The year 2018 is generally perceived as year of breakthrough for EUV lithography. The introduction into HVM is currently being executed by multiple chip manufacturers and thus secures the continuation of Moore's Law far into the next decade. Furthermore, the development of High-NA EUV lithography as the next-generation lithography technology is well underway. This presentation provides an overview of the major performance improvements of EUV lithography optics achieved to until today and how High-NA EUV enables unprecedented resolution at high productivity.

Biography
Dr. Dirk Juergens studied Physics and Applied Optics at the University of Stuttgart, Rose-Hulman Institute of Technology, IN, USA, and University of Konstanz and received his doctorate degree in 2004. He joined ZEISS in 2004 as a scientist and worked on several positions in R&D and in systems engineering. Since 2018 he is Program Systems Engineers EUV in Carl Zeiss SMT GmbH.

Future Computing- the Neuromorphic approach.

Reita, Carlo
Director, Nanoelectronics Technical Marketing and Strategy
CEA

Abstract
Abstract Research activities in the field of brain-inspired computing have gained a large momentum in recent years. The main reason is the attempt to go beyond the limitation of the conventional Von Neumann architecture that is in-creasingly affected by the limitation of the bandwidth and latency of the memory-logic communication. In neuro-morphic architectures, the memory is distributed and can be co-localised with the logic, in particular it is what the new resistive memories technologies could provide. While most of the attention is being directed to implementation of Deep Learning algorithms in large computing system, the impact on device and circuit technology has been mixed. On one hand, advanced standard CMOS technology has been used to develop GPU and specific circuit accelerators without making use of any “bio-inspired” hardware. On the other hand, emerging resistive memory devices (RRAMs) are considered good candidates to emulate a biologically plausible synaptic behavior at nanometer scale, because of the fact that they offer the possibility to modulate their conductance by applying low biases, and can be easily integrated with CMOS-based neuron circuits in a back-end process during the making of the chip. This has opened the way for the realization of compact and energy-efficient computing architectures based on artificial neural networks (ANNs) – mainly using unsupervised learning rules such as the Spike Timing Dependent Plasticity - but that have been restricted mostly to the research community due to the insufficient maturity of the technology. An intermediate, and probably faster to market application of these new memory technologies will be their applica-tion as a slow-nonvolatile cache/fast mass storage as inter-mediate memory level in conventional accelerators. This will allow a reduction of the fast DRAM and SRAM cache areas while still reducing latency to access the mass storage.

Biography
Dr. Reita (M), is currently Director, Nanoelectronics Technical Marketing and Strategy at CEA-LETI. He obtained his Laurea di Dottore in Fisica from Rome University “La Sapienza”. After atwo year post-doc at the Istituto di Elettronica dello Stato Solido of the CNR (Italy) working on a-Si thin film transistors for sensors and displays, he joined the GEC-Marconi Hirst Research Centre in Wembley (UK) as Principal Research Scientist working on poly-Si TFTs for displays and drivers. After a two years assignment as Royal Society Industrial Fellow at Cambridge University Engineering Department, he joined the Laboratoire Centrale des Recherches of Thomson-CSF in Orsay (France) as Senior Research Scientist on poly-Si device physics and circuit design. In 1999 he joined the mask maker Align-Rite which following a merger in 2000 became Photronics. After a period as Sales Manager, he became Technical Marketing Manager in charge of the Joint Developed Programs with the major customers and then European R&D Director. In 2005 he joined CEA-LETI where he is currently in charge strategy definition and technical and scientific interface with industrial as well as institutional partners in the Nanoelectronics domain. He is author or co-author of over 80 refereed papers, several invited and review papers, two books chapters in the fields of electronic devices and lithography and served as member of national and international reviews and advisory committees.

Versatile Silicon Photonic Platform for Datacom and Computercom Applications

Szelag, Bertrand
Head of silicon photonic lab
CEA-LETI

Abstract
The explosive growth of information exchange requires scalable, high-yield and cost-effective integration of microsystems. Silicon photonics is becoming a technology of choice for optical communications. Compatibility with cmos manufacturing process is one key of success since it allows taking advantage of the production capacities of foundries; i.e. big volume and low cost manufacturability [1-2]. Integration of high performances devices is the key of success for these platforms. Today, many silicon platforms are available in foundry with similar device offer aiming to address at least 25 Gb/s applications. CEA-Leti has developed such base line silicon photonic technology with demonstrated results for 50 Gb/s data rate. New technological challenges are explored to improve the capacities of this platform by developing new integration schemes such as multilevel silicon, integration of a silicon nitride level on top of the silicon or heterogeneous materials and specific edge coupling processing. We are presenting here results on 3 add-on developed on our silicon photonic platform: • silicon nitride and hybrid silicon nitride on silicon device • Hybrid III-V on silicon laser • 3D packaging

Biography
Dr Bertrand SZELAG received the Master degree in Physics from the University of Lille in 1994 and the PhD degree in Microelectronics from the University of Grenoble in 1999. He has been a visiting researcher in Tohoku University in 1997 working in the field of sub-100nm CMOS transistor properties. In 1999 he joint STMicroelectronics in Crolles, France to work on BiCMOS platfrom development for Analog/RF applications. Since 2013, he has been with the LETI, MINATEC Institute, Grenoble, France as a Project Manager and senior process integration researcher in the field of silicon photonic devices. His current research activities included high speed silicon modulator, germanium photodetectors and hybrid III-V laser integration in silicon. He is the author or co-author of more than 50 papers in scientific journals and international conference proceedings in the field of CMOS, Bipolar and DMOS transistors and silicon photonic devices.

Full wafer scale NanoImprint and Mask Less Lithography status and synergies for advanced manufacturing and pre prototyping at LETI

Landis, Stefan
Group Leader for Massively Parallel Electron Beam Lithography & Lithography Lab Deputy Manager
CEA-LETI

Abstract
In the lithography landscape, extreme-UV (EUV) lithography technology is now implemented in manufacturing lines. Meanwhile, 193nm immersion lithography, with multiple-patterning strategies, is still widely supporting the industry requirements for advanced-node develop¬ments, despite the tremendous effort required for process controls. Although these two options are suitable for high volume manufacturing, more affordable technologies are still needed for R&D evaluations, pre-prototyping and small scale productions. In such landscape, lithography alternatives maintain promise because they may present competitive compromises for the industry. Massively parallel electron-beam and nano-imprint lithography techniques remain highly attractive, as they can provide noteworthy cost-of-ownership benefits. In addition, directed self-assembly (DSA) lithog¬raphy shows promising resolution capabilities and appears to be an option to reduce multi-patterning strategies, and therefore the associated mask-set budgets. Even if large amount of efforts are dedicated to overcome the lithography side issues of these new patterning solutions, they introduce also new challenges and opportunities for the integration schemes. Through three collaborative R&D programs, IDEAL for Directed Self-Assembly Lithography, IMAGINE for Massively Parallel Electron Beam Lithography and INSPIRE for NanoImprint Lithography, CEA-Leti is currently assessing and boosting the development of these alternative technologies through strategic partnerships and innovative mix of them. In this paper, we will present how the development of the Massively Parallel Electron Beam Lithography may contribute to strengthen the supply chain of the NanoImprint Lithography through master manufacturing capabilities. We will review both Massively Parallel Electron Beam and NanoImprint Lithography technology status at CEA-LETI and then show some realizations.

Biography
Stefan LANDIS, Senior Scientist, received his Master’s Degree in Engineering in Physics and Solid State Physics, from the INPG Grenoble Engineering School and his Master of Science (MSc) in Quantum & Statistical Physics from Grenoble University. After a PhD thesis in patterned magnetic media for ultra-high density recording, he joined in 2001 the Lithography Laboratory of CEA-LETI to develop high resolution Ebeam lithography processes for CMOS devices. Then he has been in charge of the NanoImprint lithography activity for 14 years and recently managed the Multi Electron Beam Lithography Project at LETI for the development and qualification of the Mapper Lithography solution. He is now working on business development for patterning activities and services available at LETI. Author or co-author of more than 70 papers and 30 patents, Stefan Landis has edited two books Nanolithography and Lithography (ISTE-Wiley, 2011) and contributed to Plasma Etching for CMOS Device Realization book (ISTE Press- Elsevier, 2017).

Secure packaging for addressing hardware security challenges

Fournier, Jacques
Senior scientist
CEA Leti

Abstract
The advent of the IoT has put the device on the centerstage of security-related debates. Attacks on the device itself can have a severe impact on the provided services (e.g. attacks on the Philips Hue lamp). Conversely, the device can be an attack entry door for the entire system (e.g. the connected cameras used making a D-DoS on DNS servers). Protecting the device does not only mean that we need to protect the way the device is architectured, the way the embedded applications are implemented but also the way the device is manufactured and packaged. In this presentation, we shall first introduce the underlying hardware security issues before focusing on physical attacks like reverse-engineering, side channel analysis and fault attacks. We shall then explain how some of those issues can be addressed with a secure packaging. We shall provide an overview of existing secure packaging technologies and conclude on the remaining challenges for innovative secure packaging solutions.

Biography
Dr Jacques Fournier is a Senior Scientific Advisor in embedded systems’ security at the CEA Leti which he joined 2009. Prior to that, he held several technical positions in the Security Lab of smart card manufacturer Gemalto from 2001 to 2009. Jacques obtained his “Habilitation” from the University of Limoges (FR), a PhD from the University of Cambridge (UK), an MSECE from Georgia Tech (USA) and an engineering degree from the French Grande Ecole Supélec.

Wireless Embedded Circuits for Intelligent Composites

Johnson, Simon
Electronics Integration Manager
Centre for Process Innovation

Abstract
In this paper we present the results of a study into the successful development of wireless flexible sensor circuits for embedding into carbon fibre composite materials. There is significant interest in many industrial sectors in the use of ultra-thin and flexible sensor circuits for structural health monitoring as well as process and environmental monitoring. The challenges of this requirement include (inter alia) the provision of power to the embedded circuits, the accessing of sensor measurements and the impact of the sensors on the structural integrity of the composite. Development work at the Centre for Process Innovation and the National Composites Centre in the UK has created a number of hybrid flexible circuits which utilise a printed strain gauge and COTS solid state components to monitor strain within a carbon fibre composite. The circuits developed use inductive power transfer combined with RF communications to provide measurement of strain and this could be extended to include other structural parameters such as pressure and temperature. Demonstrator circuits have been assembled into carbon fibre composites and power and data transfer functionality have been successfully demonstrated. The results of the testing of these assemblies will be presented. Mechanical stress testing of the assembled circuits has been performed and the results show that the effect of the embedded circuit is measureable but this can be mitigated by careful selection of the approach to integration. This work has shown that the embedding of wireless sensor circuits within carbon fibre composites is possible providing embedded sensor capability for a wide range of applications.

Biography
Simon studied Physics at undergraduate level, a Master of Engineering in IC Design at Durham and a PhD in IC Failure Mechanisms. He has worked as an IC Design Engineer and spent over 20 years as an academic at Durham University researching various aspects of IC design (including test and reliability, neural-electronic interfacing, self-reconfiguring processors) while teaching electronic devices and circuits. He setup and ran a technology start-up for 7 years which developed and sold an educational audio system for young children, and has worked in electronics instrumentation for radiation detection in industry before joining the Centre for Process Innovation in the UK. He runs an experienced team of electronics and software engineers who work on application for printable electronics at CPI.

SiC Activation and Oxidation Technology and related Production Tools

Schmid, Patrick
Senior Mgr. Process & Technology
centrotherm international AG

Abstract
Wide Band Gap (WBG) semiconductors such as SiC, GaN, diamond and recently Ga2O3 show superior material properties, which allow operation at high switching speed, high voltage and high temperature, enabling lower conversion losses and smaller converter volumes. Driven by these superior properties and propelled by new volume markets like Electrical Vehicles (EV), WBG semiconductors are today at the doorstep from niche to mainstream. SiC is considered the most advanced WBG semiconductor for power, with main application in the medium to high voltage range (> 600V) followed by GaN with good potential in medium voltage range (< 600V). The success of SiC comes also from its generally high compatibility with Si manufacturing technology and Si production lines. However, due to the different physical and chemical properties of SiC, process steps have to be adjusted. For a few process steps, the requirements are so different that they are out of scope for standard Si tools and require special new tools. For instance, for superior thermal gate oxide formation, temperatures up to 1500°C along with NO gas annealing capability are desirable and for dopant activation in SiC, even temperatures up to 2000°C are required. The presentation will mainly touch on SiC specific technology aspects related to dopant activation and thermal gate oxide formation followed by a brief introduction of centrotherm´s SiC dedicated tool set.

Biography
Patrick Schmid has over 22 years of experience in semiconductor industry. For 15 years he was engaged in various technology, R&D and management positions at a leading RTP manufacturing company. When he joined centrotherm in 2011, the scope of his work changed, from Si based logic and DRAM technology, to SiC based power technology, covering positions in technology, R&D, product management and now in Technical Sales.

Artificial Intelligence: A Markets Perspective

Harchandani, Amit
Head of the European Technology Equity Research Team
Citigroup

Abstract
Citi Research provides its clients with fundamental analysis on more than 3,400 companies, representing over 90 percent of the market capitalization of the major global indices. This is provided alongside economic, macro and quantitative analysis of global markets and sector trends. And this presentation will leverage upon the work done by the wider Citi Research team and focus on how markets value the emergence of artificial intelligence. In addition to broader insights by each sub-sector within technology with a specific emphasis on semiconductors, the presentation will also outline stock-specific as well as thematic investment opportunities.

Biography
Amit Harchandani heads the European Technology Equity Research Team at Citigroup. He has been an Equity Research analyst for close to 10 years, moving to Citi Research in 2011 from Nomura (ex-Lehman Brothers). The breadth and depth of his knowledge as well as his thought leadership has seen him positioned as the only financial analyst at a bulge bracket bank heading coverage of both European Technology sectors - Hardware and Software. His work is quoted in industry and financial press, and he has been interviewed by the media on developments in the European Technology space. His sub-sector expertise spans Semiconductors, Semiconductor Capital Equipment, Communication Equipment, Enterprise Software, and IT Services. At present, he covers stocks including ASML, Capgemini, Dassault Systemes, Ericsson, Infineon, Micro Focus, Nokia, Sage, SAP, Siltronic and STMicroelectronics, having previously also covered ARM, CSR, Software AG and Wolfson. In addition to his main role advising institutional clients on the listed names, he also has transaction/capital formation experience. Prior to Equity Research, Amit worked as a Software Engineer/Project Leader in the IT Services industry in India and Japan from 2003 to 2006. His educational background comprises a PGDM (MBA-equivalent) with focus on Finance and Strategy from IIM Kozhikode in India (2006-2008), and an Engineering degree with specialisation in Information Technology from the University of Mumbai in India (1999-2003).

Advanced package test solution for the automotive market

Waldauf, Alex
VP of Platfrom Engineering
Cohu

Abstract
Consumer demand and competitive pressure have pushed automotive manufacturers to build greater intelligence into automobiles and trucks. For example, the Chevy Volt uses nearly 100 microprocessors running about 10 million lines of code in total, placing the Chevy Volt's software content close to that of the Boeing 787 Dreamliner. As with that electric vehicle, mainstream automotive design is increasingly relying on more sophisticated electronic systems. Indeed, advances in automotive technology revolve around five key trend: • Advanced Driver Assistance System (ADAS) and autonomous driving • Advanced Motor Control • Engine/Energy Management Systems • Graphical Interfaces and entertainment • Vehicle System of Systems in the Internet of Things These growing trends require new advanced packages which had not been used to such an extent in harsh automotive environment in the past, e.g. combination of dedicated vision processors, multicore CPUs and vision software. For motor control new MCU and FPGA Solutions, for IOT, new combo MEMS, 5G for wireless external connectivity and extended bus systems for internal subsystem links. Most of these developments were possible by integrating more and more functionality into one package and maintaining the stringent automotive safety and reliability requirements. New Backend test and handling systems had to be developed to address the new package requirements to ensure robust functionality. This breakthrough technology provides: • the lowest CoT for High Volume Manufacturing • Tri-temp for WLP, Fan-out and other small and mid-size packages including vision inspection • Stimuli for Combo MEMS • Fine pitch Kelvin contacting

Biography
Alexander J. Waldauf - Vice President of Platform Engineering Alex Waldauf was one of the founders of Cohu's Rasco subsidiary in 1998 and has been Vice President of Platform Engineering since July 2017. Mr. Waldauf was Vice President and General Manager of Rasco since January 2011, previously responsible for the Test-In-Strip product line, Managing Director of Rasco and global Vice President of Sales and Service. Prior to founding Rasco, Mr. Waldauf spent 6 years at Multitest and held key positions in engineering. Mr. Waldauf has a Mechanical Engineering degree from the Austrian School of Technology in Salzburg (HTL).

Design Enablement for the Next Generation of MEMS Products

Dufour, Christine
MEMS PDK Program Manager
Coventor

Abstract
The semiconductor industry has established integrated design environments based on PDKs (Process Design Kits), standard cell libraries, memory architectures, and IP. This design infrastructure is a key success factor, providing easy access to CMOS technology for IC designers, and increasing the chance of first-pass successful silicon. Can these features and benefits be brought to MEMS product designers? MEMS-based component suppliers want to reduce their time to market and rapidly ramp their designs into high-volume production, by reducing design spins and fabrication cycles. At the same time, a new MEMS design often requires process development not typical in CMOS design. While the prior MEMS rule “one process, one product” has become weaker over the last few years, MEMS design tools must still be very much “process aware” and adaptable to process modifications. Ideally, a design environment and design methodology for MEMS should enable efficient re-use of technology and design knowledge while supporting manufacturing process changes and design optimization. We will present a new methodology for MEMS design that uses MEMS Process Design Kits. These PDKs can be the “golden” container for MEMS technology and design information, and increase the chance for first-pass successful silicon. Based upon proven technologies from X-FAB and CEA Leti, we will share examples of MEMS component libraries that contain multi-physics compact models (rigid or flexible shapes for masses and membranes, electrostatic combs, piezo resistive gauges, suspension beams) and demonstrate how these models and libraries enable the reuse of characterized structures across multiple designs. We will then demonstrate how a parameterized and interactive component library, combined with a MEMS PDK interface, can facilitate the adaptation to foundry specific processes, provide designers with the ability to quickly explore a broad design space, and optimize designs for performance and manufacturing.

Biography
Christine Dufour is MEMS PDK Program Manager at Coventor since August 2016. Christine has more than 20 years of experience in the semiconductor industry, leading process design kit (PDK) development for BiCMOS and CMOS processes in several major semiconductor companies. Christine has also worked as a Product Manager in the RF design environment area. She has extensive experience in PDK development and all aspects of design flow and design tools. She is now collaborating with leading MEMS foundries and MEMS research institutes to develop and promote innovative design platforms for MEMS sensor design & integration with support for PDKs.

Raithel, Stephan
COO Gas Treatment
DAS Environmental Experts

Biography
Stephan Raithel successfully completed his studies of Business Administration with a German Diploma degree and a bachelor of arts with honors in 2004. During and after his studies he was working for a professional trade show organizer and was in total responsible for 3 different products focusing on consumer goods, financial services and creative industries. In 2007 he joined the global semiconductor trade association SEMI in the Brussels office as Senior Manager Operations where he became a key staff in implementing SEMI Europe’s strategy and enlarging SEMI’s presence within Europe. In 2009 he opened a SEMI branch in Berlin, Germany, where he was the Managing Director for SEMI Europe, being at the same time responsible for all direct reports in Berlin as well as filling the role of the CFO for all European activities. Various responsibilities such as the European SEMI Standards program and the development of the International Technology Roadmap for PV (ITRPV) enriched his profile with technical skills in semiconductor and solar manufacturing. In 2016 he joined DAS Environmental Experts – a leading supplier of industrial waste gas and wastewater treatment solutions. Since 2018 he represents DAS as the COO for the business unit gas treatment.

Leveraging a single collaboration platform to achieve higher efficiency and zero re-spins in developing IoT-ready systems-on-chip

Hebert, Jean-François
VP Sales Director for BT Channel
Dassault Systèmes

Abstract
To keep up with dynamic consumer demands in the Age of IoT, Semiconductor companies need to deliver chips and SoCs in ever shorter timeframes. The challenge to meet revenue, profitability and growth targets puts design and manufacturing under increasing pressures in meeting technical demands and delivering devices on time. This presentation shows practical examples and leading practices how semiconductor companies can efficiently manage their products' hardware & software diversity, while protecting IP, mastering product compliance and Manufacturing-For-Design strategies by leveraging the 3D virtual twin for semiconductor manufacturing front-end and back-end processes.

Biography
Jean-Francois HEBERT joined Dassault Systèmes in October 2007. He held several Sales Management positions within BT Channel (serving Large Accounts) as EMEA High-Tech Sales Manager, Diversification and Geo Sales Leader for France/Spain/Portual/Middle-East for the ENOVIA brand. Since January 2016, he is responsible for helping High-Tech companies worldwide adapt to fast-paced market trends and deliver innovative electronic experiences for their end-customers by leveraging Dassault Systèmes’ 3DEXPERIENCE™ platform. He is also driving the impact of the company’s High-Tech Industry on sustainable innovation in multiple other industries through smart products and systems, embedded electronics and software, and IT and communications infrastructures that support cloud based transformation. Prior to joining Dassault Systèmes, Jean-Francois Hébert worked in EDA, Semiconductor and Optronics industries, where he held senior management positions including Alcatel Optronics and Windows Business Division. Before this, he worked in a number of senior-level sales, marketing and business development capacities at Bull EMEA Information Systems and at EDF. Jean-François HEBERT is a graduate of the Ecole National SEA in Cergy Pontoise, France, and completed courses for Sales at Texas Instruments and SAM.

Paper electronics with printed Poly-Si TFTs

Ishihara, Ryoichi
Associate Professor
Delft University of Technology

Abstract
Paper electronics has emerged as a game-changing platform for future applications in display, healthcare, and environmental monitoring devices. The low-cost of paper combined with scalable manufacturability of printing technologies of electronic devices will allow production of a trillion of systems for IoT. Due to its biodegradable and fully-recyclable properties, the paper system paves a way for low carbon footprint and less environmental damages. The technical challenge in the paper electronics lies in the printing of electronic devices. Organic and metal-oxide semiconductors can be printed at low-temperature and hence on a paper substrate. However, carrier mobility and reliability of thin-film transistors (TFTs) using those materials are still much inferior than those for silicon. Silicon as the base material, on the other hand, has advantages in terms of high-mobilities for the both of electron and holes, chemical and electrical stability, and low-power consumption by CMOS circuit configuration. The biocompatibility of silicon makes a good match with paper for the substrate. Silicon can be printed using liquid silicon ink, which is a mixture of polymerized cyclopentasilane (CPS) and a solvent]. Thermal annealing higher than 350oC of this material, however, was necessary, to convert it to solid silicon, which prevented its usage on inexpensive substrates with a limited thermal budget. In this presentation, we review a novel method that we developed for forming polycrystalline silicon (poly-Si) patterns directly on paper using the same liquid silicon with doctor-blade coating and local irradiation of excimer-laser with room temperature process. We review also the process and electrical properties of poly-Si TFTs fabricated on the paper. This technique will break-though the printed electronics by enabling applications such as fast printed electronics that are inexpensive, fully-recyclable, biodegradable and even edible.

Biography
Ryoichi Ishihara is an associate Professor and head of the Quantum Integration Technology in the Quantum and Computer Engineering department in Delft University of Technology (TUDelft). He is currently a principal investigator in QuTech and a member of Kavli Institute of Nanoscience. He is also a visiting professor of Japan Advanced Institute of Science and Technology and a specially appointed associate Professor in Tokyo Institute of Technology. He received the PhD in Physical Electronics from Tokyo Institute of Technology (1996). After moving to TU Delft in the same year, he has established new activity of large area electronics using thin-film transistors (TFTs). He has done and continues research on single-grain and printed silicon TFTs for 3D integration and biodegradable/flexible electronics. His current research in QuTech is growth and integration of diamond nitrogen center qubit for scalable quantum internet and computer applications. He is a co-author of more than 85 journal papers and 120 international conference papers and a co-inventor of 13 granted patent families.

Extend the lifecycle of your industrial IT systems > 20 years

van Hagen, Robbert
Business Development Manager
Detron Lifecycle Services

Abstract
IT components like servers, IPC systems and boards that are used in the semiconductor industry should be robust, secure and of high and constant quality. In addition, systems are used over a longer period of time and redesigning an alternative product results in additional cost and risks. During this presentation, Detron gives insight in its Lifecycle management strategy that helps customers like ASML, Philips and NTS choose/design-in the right IT components and extend the lifecycle of these products for more than 20 years.

Biography
Robbert van Hagen has a strong 20-year background in ICT managed services both in the IT and Telecom domain, acting as a sparring partner in the field of mobility, Internet of Things and Lifecycle Management.

Laser-Direct-Structuring of Flexible Textile Circuits

Linti, Carsten
Project manager
Deutsche Institute für Textil- und Faserforschung DITF

Abstract
Textile conductive substrates are drapeable, highly flexible, and more insensitive to reversed bending fatigue compared to conventional rigid or flexible printed circuit boards. Despite this the surface mounting of microelectronic devices is not solved retaining the textile properties. Textile Circuits using conductive yarns are limited by textile patterning, printing of conductive inks often does not meet mechanical properties. Using LPKF-Laser Direct Structuring Process (LPKF-LDS) user defined circuits can be structured on the surface of special polymers, usually on injection Moulded Interconnect Devices (MID). Here textile fabrics made from LDS-polymers, the following metallization with the LDS-process, and the mounting of SMD was studied. Integrated Circuits on textile sheets preserving textile properties have been manufactured with LDS technology. For this purpose multifilament yarns have been produced by melt spinning of LDS modified polymers. These yarns have been processed to woven textile bands. These could be surface activated by laser. The activated areas could be copper plated chemically. These conductive circuits can be mounted with e.g. with SMD by soldering. In this study we could show that LDS-yarns can be produced with a special spinning process which can be processed with textile technologies. The LPKF-LDS-process can be applied to the fabric forming conductive circuit structures. The solderability and functionality of electronic parts on LDS-textiles was shown. The textile properties could be retained. The application as flexible circuit especially for the design of interfaces between hard and soft substrates shall be explored in future. Financial support (Laserstrukturierte textile Schaltungsträger) from the BMBF, grant number 16SV5064, is gratefully acknowledged.

Biography
Degree in Mechanical Engineering with focus on precision engineering and biomedical engineering at the University of Stuttgart. Since 1994 research assistant and project manager at DITF in the research group for biomedical engineering with focus on textile implants, micro-injection moulding of bioresorbable polymers. Since 2000 additional in "Smart Textiles", textile and textile-integrated sensors for the monitoring of physiological parameters e.g. in Sensory Baby Vests, Ambient Assited Living and Sensory Protective Clothing.

Reliability Investigation of Wafer Level Chip Scale packages under thermal cycling condition and validation using simulation methodology

Nandhivaram Muthuraman, Balaji
Package & Material Simulation Engineer
Dialog Semiconductor GmbH

Abstract
In this paper, reliability investigation of Large Wafer Level Chip Scale package of size 54 mm2 with different die thickness and underfill conditions is discussed. Test vehicles were constructed based on the design variation using different silicon chip/die thicknesses and different underfill conditions. To assess the device reliability, extensive Board Level Reliability Temperature Cycling Tests (BLR-TCT) were carried out with a temperature load variation between -40°C till +85°C until significant solder joint fatigue failures are observed. It is evaluated that the failure mode in underfill package is different than the package without underfill. Devices with no underfill showed solder joint bulk cracks under thermal cycling condition, whereas the devices with the underfill experienced cracks on the intermetallic layer between the silicon chip and redistribution copper layer. To investigate and validate BLR-TCT reliability measurement data, Finite Element Method (FEM) simulations were carried out. Parameters like Aluminium Pad thickness and the routing method of Redistribution layer – Aluminium pad interconnection is evaluated using numerical techniques. Significant parameters were investigated in the numerical simulation model to understand the effect of package structural variation on the failure mechanism shift observed in Board level reliability (BLR) measurement tests. Results from the numerical simulation study validate the failure modes observed in BLR temperature cycling tests. Large WLCSP devices with underfill experienced a higher delamination stress on the metal interface. After design optimization study, relevant solutions have been found and illustrated. This research work can serve as a guide towards reliability assessment involved in large-scale WLCSP packages and necessary stress reduction techniques to be implemented in such smart devices.

Biography
Balaji Nandhivaram Muthuraman is working as Packaging and Material Simulation engineer in Dialog Semiconductor GmbH, Germany. He obtained his Bachelor's degree in Aeronautical Engineering from Anna University, Chennai,India. Followed by, Master's degree in Computational Mechanics of Materials and Structures from University of Stuttgart, Germany. His current area of working interest are Board level reliability of electronic packages, Developing fatigue model for reliability assessment of Dialogs products.

Solutions for processing SiC wafers and slicing SiC ingots with high speed and cost reduction

Klug, Gerald
General Sales Manager
DISCO HI-TEC EUROPE

Abstract
DISCO Corporation is a leading manufacturer for equipment and tools for wafer thinning and dicing. Silicon carbide has become an alternative to Silicon when it comes to manufacturing high-power devices. However, singulating SiC wafers is challenging due to its hardness. The main challenge is maintaining high speed processing and best die quality at the same time. DISCO proposes suitable solutions for SiC processing with significant time and cost reduction and best quality. We introduce ultrasonic dicing and stealth laser for singulation and KABRA for ingot slicing. Processing SiC with standard dicing blade at a high speed causes chipping and cracks. Ultrasonic-wave dicing is a technology capable of reducing the processing load by applying ultrasonic vibrations in the blade radial direction. Lower processing load in ultrasonic-wave dicing enables the selection of a blade with smaller grit size improving the processing quality. SD is a technology that forms a modified layer by focusing a laser beam below the surface of a workpiece and then separating the workpiece into chips by breaking. SD is capable of processing SiC at a speed higher than that of ultrasonic-wave dicing, but both technologies prevent burr of metal layers and offer high die strength. So far, producing SiC wafers from an SiC ingot was a big cost issue, which hampered the development of SiC power devices. Slicing by wire saw requires a lot of time and is not cost-efficient. With KABRA, DISCO is introducing the new generation of SiC wafer production with high-speed ingot slicing. The KABRA slicing method forms a flat light-absorbing separation layer at a specific depth by irradiating a continuous, vertical laser from the upper surface of the SiC ingot. . By KABRA slicing, processing time is cut significantly while increasing the number of wafers per ingot. All of the above mentioned processes are offered by the Dicing-Grinding Service at DISCO HI-TEC EUROPE with its facilities close to Munich airport.

Biography
Gerald Klug studied business engineering at the University of Siegen and graduated in 1998 as Dipl.-Wirt.-Ing., completing his thesis at BMW in Munich. He started his career as a designer of coil processing lines for nearly 3 years at a German machine manufacturing company, Heinrich Georg GmbH. At the end of 2000, he joined DISCO as a Sales Engineer for the area of Scandinavia. Meanwhile he has been almost 18 years at DISCO, nowadays operating as General Sales Manager for the whole of Europe.

A new ADAS Chip Design in 22 nm FDSOI Technology for Automotive Computer Vision Applications

Benndorf, Jens
Managing Director, COO
DreamChip Technologies

Abstract
The presentation explores the European collaboration for a System-on-Chip development for Advanced Driver Assistance Systems (ADAS) in a brand new 22nm FDSOI low power technology implementation from Global Foundries. The presentation will elaborate on the history of the project, the partnership of the German consortium, the technology itself as well as on the target System-on-Chip implementation and the different applications within future ADAS devices. According to market analysis’s more than 60% of the cars sold today are equipped with different driver assistance systems and this number will grow over next years further. Because of growing demand, but also because of the very fast growing complexity and performance requirements of such systems cost reduction and power consumption become more and more important. Both requirements are addressed by the new architecture. A special focus will be put on HW/SW codesign trade offs to address flexibility, low power consumption and high performance requirements. The presentation will highlight ADAS applications like 360o top view cameras, Camera based automotive mirror replacement, massive CNN processing and the chip reference board demonstration of the final system.

Biography
Jens Benndorf has a PhD. from Moscow University (1991) where he researched DSP technologies for use in high speed voice band modems. Jens’ passion for DSPs continued within international blue chip companies including Alcatel, BridgeCo, Infineon and Silicon Image. He built and led teams developing products for early DSL and complex imaging applications. In 2010 Jens cofounded DreamChip Technologies GmbH and now leads the company in his role as MD and COO. DreamChip specialise with 80 engineers team in multi processor system on chip designs for automotive camera and imaging applications. The company is based in Hannover and Hamburg, Germany and is a member of the Silicon Saxony network.

High Performance Thermal Conductive Substrates for Power Module Packaging

Im, Sejin
Global Segment Leader
DuPont

Abstract
Increased adoption of hybrid and electrical vehicles as well as renewable energy systems are driving the innovation in power module packaging. Thermal substrate, one of the major components of power modules, is not an exception, and technological advancements are necessary to meet increased reliability requirements. Herein, we show that a high-performance power electronic substrate can be designed with newly developed highly thermally conductive polyimide film to address potential issues industry strives to solve. The most widely used ceramic based substrates tend to degrade severely with prolonged thermal cycles, a typical requirement of EVs and HEVs, reducing the reliability and lifetime of the power electronic device. Also, common design of the power module requires many layers that adds thermal resistance at each bonding surface. DuPont’s new Temprion™ Organic Direct Bond Copper (ODBC) has been developed and designed to address aforementioned problems, increasing thermal durability and reliability as well as enabling system layer suppression. Temprion™ ODBC’s dielectric layer, Temprion™ DB film will absorb thermo-mechanical stress from the metals due to CTE mismatch, dramatically improving durability of the system. In addition, various kinds of metals including Cu and Al can be easily bonded to Temprion™ DB films through simple process. There are no thickness limitations on bonding metal sheets and metal attached at the bottom can be used as an integrated heat sink/baseplate. This presentation will provide an overview of the power module market, highlighting current challenges and alternative solutions to address them.

Biography
Sejin has over 10 years of experience in the automotive and chemical industry in various disciplines including business planning and strategy, product management and engineering. Currently he works at DuPont with teams and partners to help the industry solve one of its biggest challenges – thermal management – with DuPont’s latest technology. Sejin holds a BSME from University of Wisconsin at Madison and an MBA from Kellogg School of Management at Northwestern University.

Polyester Film Substrates for Flexible and Formable Electronics

Gough, Thane
Business Development Manager
DuPont Teijin Films UK Ltd

Abstract
Developments in flexible electronics technologies in application areas such as OLED displays, OPV modules, In-Mould-Structural-Electronics, HMI (Human Machine Interface) and sensors, have presented challenges to device manufacturers relating to the properties of flexible substrates. To improve yield and efficiency there is a need for materials that exhibit excellent dimensional stability and clean defect-free surfaces, and in some applications a requirement for additional functionality such as UV stability and Flame Retardancy. Proposed solutions to these issues include the use of novel co-extrusion techniques, optical modification of surfaces, and the incorporation of non-halogen flame retardant materials into a polymer matrix. Increasing interest and activity in flexible hybrid systems, foldable displays, and wearable devices, will require further modifications to substrate properties, and drive the development of flexible materials with new diverse properties and specifications. This presentation will review the latest developments in polyester film processes and technology, including an update on substrates designed for ultra-high barrier use in Displays and OPV applications, and thermoformable films for use in In-Mould-Structural-Electronics.

Biography
Thane is a Business Development Manager in DuPont Teijin Films. He has worked in the polyester films market for nearly 40 years, in a range of roles including R&D, Technical Support,and New Product Development in Packaging Films. He is now responsible for the development of polyester substrates that meet the needs of emerging applications in printed and flexible electronics.

Exploring a digital future: Where academia and industry meet (2019 SEMI Member Forum, Bristol, UK)

Czerniak, Michael
Environmental Solutions Business development Manager, Edwards
Edwards

Abstract
We live in a rapidly changing world and we are faced with important global and local challenges; from climate change and global warming to resilient cities and sustainable communities, future solutions will require innovative thinking and approaches but also strong partnerships between academia and industry. The Nanoelectronics Industry is already exploring the future, enabling almost every modern technology: Artificial Intelligence (AI), Deep Learning, Autonomous Vehicles, Space, Supercomputers, the Internet and the Cloud, Wearables and so on. They are all enabled by state-of-the-art electronic components and systems. Two examples are remotely operated vehicles (ROV) used in marine research into microplastic pollution, and satellite imagery combined with supercomputers used to track climate change and influence policy-makers. Designing and manufacturing electronics use many fields of technology: Physics, Chemistry, Engineering, Computing, Data, Operational Research etc. This will be a 2-day workshop for students to find out more about the exciting opportunities the nanoelectronics and digital industry in Europe and around the world, including a face-to-face recruitment café with representatives from leading industry players.

Biography
Mike gained his PhD in Electrical Engineering at Manchester University (UK) in 1982. Starting his professional career with Philips, initially in their UK R+D labs & subsequently in the fab in Nijmegen, Holland. He had subsequent marketing roles at UK-based OEMs Cambridge Instruments, VSW and VG Semicon before joining Edwards 21 years ago. He has held various technical and marketing positions before beginning his current role 2 years ago. Mike has numerous published articles and patents to his name, co-chairs 2 SEMI standards committees, participates in the IRDS, is a UK PFC “expert” on the UN IPCC (Intergovernmental Panel on Climate Change, and now is a lead author) and has authored the chapter on Vacuum and Environmental issues in the Handbook of Semiconductor Manufacturing (2nd edition). He has been a Visiting Industrial Professor in the School of Chemistry at the University of Bristol since September 2017. Mike has been married for 39 years and has 2 grown-up children.

Atomic layer deposition for the synthesis and integration of 2D materials for nanoelectronics

Bol, Ageeth A.
Associate Professor
Eindhoven University of Technology

Abstract
Graphene and other layered 2D materials have been the focus of intense research in the last decade due to their unique physical and chemical properties. This presentation will highlight our recent progress on the synthesis and integration of 2D materials for nanoelectronics applications using atomic layer deposition (ALD). ALD is a chemical process that is based on self-limiting surface reactions and results in ultrathin films, with sub-nm control over the thickness and wafer-scale uniformity. Two of the critical issues in unlocking the potential of graphene are the ability to deposit ultra-thin high-K dielectrics on grapene and fabricate low resistance contacts to graphene. Technologically, it is desirable to use atomic layer deposition (ALD) for this purpose. The inert nature of graphene however has made ALD on graphene very challenging. This presentation will give an overview of ALD techniques that were developed in our lab to initiate oxide and metal ALD on graphene to form ultrathin dielectrics and low-resistance contacts, without deteriorating graphene’s electrical properties. In addition, ALD might prove as a key enabler for tackling the current challenge of large-area growth of 2-D materials with wafer level uniformity and digital thickness controllability. We have implemented plasma-enhanced ALD to synthesize large-area MoS2 thin films with tuneable morphologies i.e. in-plane and vertically standing nano-scale architectures on CMOS compatible SiO2/Si substrates. The large scale 2D in-plane morphology has potential applications in nanoelectronics, while the 3D nanofin structures could be ideal for catalysis applications such as water splitting.

Biography
Ageeth Bol is associate professor of Applied Physics at Eindhoven University of Technology, the Netherlands. She received her MSc and PhD in Chemistry from Utrecht University, the Netherlands. After obtaining her PhD degree in 2001 she worked for Philips Electronics and at the IBM TJ Watson Research Center in the USA. In 2011 she joined the faculty of Eindhoven University of Technology. In 2012 she received a prestigious VIDI grant from the NWO (Netherlands Organization for Scientific Research) and in 2015 she was awarded a Consolidator Grant by the ERC (European Research Council). Her current research interests include the fabrication, modification and integration of 1-D and 2-D nanomaterials for nanodevice applications and catalysis.

GaN - the future for rectifiers.

Schmidt, Odd Roar
Project director r&d
Eltek A/S

Abstract
New devices based power converters and systems Keywords—Wide band Gap semiconductor used in rectifier with focus on GAN transisitor When dealing with power conversion in a data center, the efficiency and cost-effectiveness is key! Due to the size and capacity of a modern data center, even small efficiency improvements in the power conversion from the incoming AC to the server load have great impact in terms of cost saving. Over time, Eltek has been exploring wide band gap technology, using GaN transistors instead SiMoS Fets in order to achieve higher efficiency and reliability. Together with Infineon, Eltek have for more than 2 years participated in an EU research program which now has resulted in a new 3kW/48Vdc rectifier with a peak efficiency of 97,8%. The combination of Eltek’s proven High Efficiency (HE) technology and Infineon’s GaN transistors has enabled a truly cost effective rectifier in the Super High Efficiency range. With modern silicon devices it is feasible to raise efficiency in the 230Vac-48Vdc conversion step to 98%, but based on the experience from our extensive research we are convinced that this efficiency can better be achieved by utilizing the GaN technology; simpler, more reliable and more cost effective. In our Super High Efficiency rectifier, we have been using totem pole topology with a lot of different technical issue. The PFC has a peak efficiency of approx. 99% and the rectifier has peak efficiency of 97.8% Totem pole PFC This paper will describe how and why GaN is the key to achieve reliable 98%+ efficiency.

Biography
Odd Roar Schmidt(m): R&D Project Director with Eltek. MSc in power electronics from NTNU. He has an extensive experience, 37 years,from industrial R&D and industrialisation of power converters. Formerly, director for Telecom division in Power-One where he was responsible for System, Controller and Rectifier/Converter technology and products. He has also been technical director for Power-One and Eltek.

A New Collaborative Approach to Reliability Challenges in the Automotive Industry

Amade, Antoine
Regional Senior Director EMEA
Entegris

Abstract
By 2030, 50% of the car costs are expected to be SC components related. While it is an exciting source of growth for the complete supply chain, the car industry sets a great challenge for all of us: reaching the ppb level in failure rate at the component level. Material purity and contamination control could play key enabler roles. However it requires a new collaborative approach to validate expectations and identify the most adequate investments to meet the “zero defects” goal. From the list of potential material options, there is an increased value to tackle the non-visible particles that are sources of latent defects. Actually, the defectivity monitoring challenges in terms of limit of detection create a “Black Box”. The industry is here in the 3rd generation of contamination control strategy where base line and excursion control could be improved with an adequate contamination management strategy. A collaborative engagement model exists where device makers and experts in purity work together in task force mode. This is the “New Collaborative Approach”.

Biography
Mr. Amade joined Entegris in 1995 as an Application Engineer in its Semiconductor business. In his current role as EMEA Sr. Regional Director, Mr. Amade’s primary responsibilities include growing the semiconductor business in Europe and Middle East through market strategies, and in the management of a sales, customer service and marketing team. Mr. Amade held leadership positions at Entegris which included: gas microcontamination market management, strategical account management and regional sales management. Mr. Amade has a degree in Chemical Engineering from ENS Chimie Lille and he is a member of Semi Electronic Materials Group for Europe.

Yield Improvement by Abrasion Reduction

Lundgren, Jorgen
Senior Field Application Engineer
Entegris

Abstract
This presentation will describe different polymers and their technical attributes and functions in products used for bare die and wafer handling and processing applications. Polymers used in wafer handling and processing has to have a low level of organics which can potentially outgas (outgasing) and low level of anions, cations and metals. Some polymers are required to have ESD (electro static dissipative) properties where different forms of carbon is added to achieve the required ESD specification. Another critical physical attribute is abrasion resistance. Specific polymers have a high abrasion resistance to avoid particle generation. Temperature resistance is another important factor for many Semiconductor applications.

Biography
Senior Field Applications Engineer with electronic engineering degree from Sweden. Been working for Entegris for the last 21 years supporting the Semiconductor Industry in many different technical roles with focus on wafer and reticle contamination control during handling, processing and shipping of sensitive devices. Heading up projects and product qualification of 200mm and 300mm fabs in Europe. Contributor to Entegris/CEA–Leti collaboration FOUP polymer contamination/decontamination Project. Partner in the European TSV-Handy wafer handling Project. Active SEMI participant.

Collective Die Bonding Technologies for Heterogeneous Integration in Advanced Packaging

Uhrmann, Thomas
Business Develoment Director
EV Group

Abstract
As die area is constantly reduced especially for small package sizes and heterogeneous integration with high interconnect density becomes crucial. For large packages sizes heterogeneous integration and die segmentation gets an increasing role of processing applications. Here, heterogeneous integration leads to an overall increased yield, mainly as smaller dies generally can be produced with higher yield. In the same time and most importantly, memory, processors, sensors and such from different sources can be combined using heterogeneous integration. Aforementioned yield improvements by splitting dies into several parts and improving the performance cost. Combining the segmented dies in an advanced package can be done by two different bonding technologies, namely sequential die bonding or a collective die bonding approach. For the collective bonding, individual dies are populated and tacked either on an interposer or a so-called handling carrier, depending on the bonding technology applied. In case of tacking die face-down on an interposer or other active silicon die, bonding is usually being done by thermal bonding. Here, heating and cooling of the substrates are only done once, considerably reducing process cost and thermal budget of the underlying substrate. The second case is tacking the dies face up on a carrier substrate. This reconstructed dies on a carrier can now be processes again on wafer scale, this means preprocessing steps such as direct bonding can be done before bonding the wafers using fusion or hybrid bonding. In this presentation we will show different integration approaches for collective die bonding for both thermal bonding as well as fusion / hybrid bonding. For both processes, results in terms of die placement and sequential alignment accuracy of the integrated process will be compared and discussed, together with current and potential applications of these processes for future devices.

Biography
Dr. Thomas Uhrmann is director of business development at EV Group (EVG) where he is responsible for overseeing all aspects of EVG’s worldwide business development. Specifically, he is focused on 3D integration, MEMS, LEDs and a number of emerging markets. Prior to this role, Uhrmann was business development manager for 3D and Advanced Packaging as well as Compound Semiconductors and Si-based Power Devices at EV Group. He holds an engineering degree in mechatronics from the University of Applied Sciences in Regensburg and a PhD in semiconductor physics from Vienna University of Technology.

Next Generation of Powerful Intralogistics Automation for 200MM Semiconductor Fabs

Esser, Heinz Martin
Managing Director
Fabmatics GmbH

Abstract
Existing 200mm semiconductor fabs can master the challenges of a 24x7 production under highest cost and quality pressure by implementing intralogistics automation solutions. In the previous years many companies operating mature fabs understood that older does not mean obsolete and started or continued their journey towards higher automated production. For this reason a variety of automation solutions in the fields of material identification and tracking, storage, transport and handling were developed. After the first generation of these automation systems entered the fabs, left the prototype level and have been running in production for a couple of years the customer needs and requirements changed. Focused the first material handling automation solutions on general feasibility the trend now develops towards continuous improvement, stability, performance and cost of ownership, which creates new and different challenges for next generation automation systems. In his presentation Heinz Martin Esser will explain the newest trends of customer requirements for automation of mature fabs and how these challenges drive and influence the development of the 2nd generation of 200mm intralogistics automation systems, which will give customers the opportunity to further stretch the current limits of fab performance.

Biography
Managing Director of Fabmatics GmbH and President of Silicon Saxony e.V. Heinz Martin Esser, born in 1955, completed his studies of supply engineering at the university of applied science in Cologne with diploma in 1981. In 1985 he got an additional university degree in business administration. He gained a wide experience in detailed engineering and project management for large and complex investments for nuclear industry and beverage and food industry. Later he was assigned as branch manager to build production clean rooms and facilities in semiconductor and pharmaceutical industry. In 1999 he was appointed as CEO of Roth & Rau - Ortner GmbH, Dresden (formerly Ortner c.l.s. GmbH). The company provided automated transport, storage and handling systems, RFID components and special products for cleanroom applications as well as complex systems expertise in AHMS installation and qualified services for the international semiconductor industry. Since the merger of Roth & Rau - Ortner GmbH and HAP GmbH Dresden into Fabmatics GmbH in September 2016, Heinz Martin Esser has been managing the company together with Dr. Steffen Pollack. With Fabmatics Heinz Martin Esser is responsible for “Sales & Marketing”, “Customer Service” and “Administration”. Since 2001 Heinz Martin Esser has been a member of the board of directors of the high-tech network Silicon Saxony e.V. In 2009 he was assigned to be the speaker of the board. Since 2008 he has been a member of the European Advisory Board of the worldwide industry association SEMI as well.

Flexible electronics: From lab to fab to the next generation of products

Socratous, Josephine
research engineer
Flexenable Ltd

Abstract
Flexible electronics will play a pivotal role for enabling flexible displays and sensors that will break form factor constraints and unlock new product use cases. The transistor is the fundamental building block for electronic devices, so a flexible transistor is the frst step to turning this vision into a reality. Organic-based transistors (OTFT) have always been seen as the most flexible transistor option, and this talk will explain how the performance of OTFT has now exceeded amorphous silicon ensuring that product designers no longer need to compromise performance to achieve flexibility. For example, in terms of mobility, manufacturable OTFTs are now at least three times better than amorphous silicon, whilst having leakage currents nearly 1000X lower – both of which bring direct performance benefts to the device electro-optical performance alongside the benefts of flexibility. In particular, OTFT technology opens a new avenue for flexible displays and sensors on commodity plastics – it enables glass-free, thin, light and conformable devices, combined with a low manufacturing cost that is driven directly by the uniquely low temperature process (sub 100ᵒC) afforded by OTFT. The process has been designed so it can be easily transferred into existing display factories providing a quick route to high production capacity and yields. FlexEnable is now working across the supply chain to establish the infrastructure necessary to bring the next generation of products to the market.

Biography
Josephine Socratous holds a B.A. and M.Sci degree in experimental and theoretical physics from the University of Cambridge. She did here Ph.D. in the Optoelectronics Group, Cavendish Laboratory, University of Cambridge where her thesis focused on amorphous metal oxide semiconductors for thin-film transistor applications. She has been a Research Engineer with Flexenable Ltd since 2015. Her focus is on improving the performance and reliability of organic thin-film transistors together with managing grant-funded and customer projects.

Pelka, Joachim
Deputy Director
Fraunhofer-Gesellschaft

Biography
Dr. Joachim Pelka is the Deputy Director and Strategy Advisor of the business office for the Fraunhofer Group for Microelectronics. He studied electrical engineering, with an emphasis on semiconductor technology, at Berlin's Technical University and was awarded a doctorate there for his work on semiconductor components. He has been with the Fraunhofer-Gesellschaft since 1983. After several years of Research in process simulation, he was heading the Business Office of the Fraunhofer Group for Microelectronics from 1996-2018. As managing director he was responsible for strategic planning and for the coordination of work in the microelectronic institutes of the Fraunhofer-Gesellschaft. In keeping with deepening European integration, Dr. Pelka today functions as the main contact person for other European research facilities such as CEA-Leti, CSEM, IMEC and VTT. He represents the Group, complementing the Chairman of the Group, in the Heterogeneous Technology Alliance HTA and in the Electronics Leaders Group of the European Commission. Dr. Pelka is a member of the AENEAS Scientific Council.

Towards R2R Manufacture of Flexible Hybrid Electronics – Technology Roadmap at Fraunhofer EMFT

Landesberger, Christof
Group manager
Fraunhofer EMFT

Abstract
Sensors and electronics need the functionality of micro-controller ICs for data collection, data processing, digitization and data transfer to a host system. Therefore, any flexible electronic system will require a technical solution for embedding and interconnection of ultra-thin microprocessors in a bendable film based package. The presentation will first explain the technological requirements for integration of thin IC on or in flexible film substrates. Key elements here are the manufacture of robust thin semiconductor devices, the preparation of very fine line metal patterns and adequate chip bonding and interconnection techniques. Latter topics can be realized in two different ways for chip orientation: face-down (flip chip) or face-up die bonding. In the second case, interconnects must be aligned with respect to I/0 contact pads of ICs. As the distance between two contact pads may be in the range of just 20 µm to 40 µm the resulting alignment accuracy of dies with respect to the interconnect lines has to be less than 5 µm. When using flexible film substrates as integration platform and roll-to-roll (R2R) equipment for manufacture this requirement represents a challenging task due to possible shrinkage or expansion of the film roll. Thin chip foil packages with embedded microcontroller ICs were demonstrated successfully by Fraunhofer EMFT using single sheet film substrates. In order to achieve the next major step towards R2R manufacture we are currently setting-up a laser direct imaging (LDI) system for R2R lithographic patterning of interconnects and wiring schemes. Key advantage of such laser imaging system is its capability to correct the UV exposure process locally and, if necessary, individually at any chip position. Such “adaptive lithographic patterning” is supposed to bridge the gap between alignment requirements and geometric distortions in the web substrate. First results will be shown at the conference for the first time.

Biography
Christof Landesberger received the diploma degree in physics from Ludwig Maximilian University in Munich. He joined Fraunhofer Institute in Munich in 1990 and is now heading the research group “Thin Silicon” within the department “Flexible Systems” at Fraunhofer EMFT. He has been working in the field of ultra-thin silicon since more than 15 years and prepared more than 20 patent applications in the field of handling and processing techniques for ultra-thin semiconductors. His current research topics are focusing on packaging technologies for ultra-thin semiconductor devices, including self-assembly and flexible chip foil packages.

Recent Developments in Multifunctional Integration

Guttowski, Stephan
Head of Technology Park »Heterointegration«
Fraunhofer FMD

Abstract
New device technologies and applications with their ever increasing performance and functionality are driving the requirements and innovation for assembly and packaging. The technology boundaries between semiconductor technology, packaging and system design are becoming blurred. As a result chip, package and system designers will have to work closer together than ever before in order to drive the performance for future microelectronic systems. In addition heterogeneous integration will be an integral aspect for all future advanced electronic applications.

Biography
Dr.-Ing. Stephan Guttowski studied electrical engineering at TU Berlin, focusing on measuring and automation technology, and then went on to do a doctorate in electromechanical compatibility. He then did a post-doc at the Massachusetts Institute of Technology (M.I.T.) in Cambridge. After returning to Germany, Guttowski first worked in the electric drive research lab at DaimlerChrysler AG and, in 2001, moved to the Fraunhofer Institute for Reliability and Microintegration IZM. Here, he was initially chairman of the Advanced System Development group before taking over the System Design & Integration department. Since June 2017, Guttowski has been technology park manager in the FMD and, within this role, works towards cross-institute cooperation.

Predictive Probing: A novel approach to minimize efforts at final test

Schellenberger, Martin
Group Manager Equipment and APC
Fraunhofer IISB

Abstract
Quality control plays a crucial role in the manufacturing of premium products. Measures for quality control are implemented, on the one hand, right after crucial process steps to ensure single process quality. On the other hand, the application of sophisticated test procedures during final test guarantees high quality of the final product. For instance, in LED manufacturing, high effort is spent to probe every single LED chip: in dedicated probing equipment, ultra-thin needles are used to contact an LED and measure its brightness, color and electrical properties. With thousands of LED chips to be tested per wafer, this is a time-consuming and expensive step. Predictive probing aims at significantly reducing the probing time and effort in final test and follows two objectives: (1) Identify a limited set of chips that have to be tested. (2) Reconstruct the parameters also from those chips that were not probed; this includes the detection of defect chips. To achieve these objectives, up-stream metrology data is utilized. A set of machine learning algorithms (including a neural network) takes these data to identify critical chips and to predict probing results. This concept was developed and demonstrated in a 3-years R&D project together with an LED manufacturer. As a result it is possible now, to omit the measurement of 93% LED chips on a wafer, which leads to a drastic decrease in overall measurement time and cost, and still predict the brightness, color and electrical parameters of all LEDs – with an accuracy that fulfils the specification of the manufacturing partner. The principles of the approach and the knowhow gained during the development can be transferred and applied to other applications and industries, where predictive probing can significantly lower cost and efforts in quality control.

Biography
Martin Schellenberger received the diploma in electrical engineering in 1998 and a Ph.D. in electrical engineering in 2011, both from the University of Erlangen-Nuremberg, Germany. From 1998 to 2006, he was a Research Assistant with the Fraunhofer Institute of Integrated Systems and Device Technology (IISB). Since 2007, he is Group Manager at Fraunhofer IISB, responsible for equipment and advanced process control. His research interests include equipment development and optimization for semiconductor processes, manufacturing science solutions for quality control, predictive methods for process control, equipment automation and productivity enhancement.

Wide Band Gap Semiconductor Materials - Status and Challenges

Friedrich, Jochen
Department Head
Fraunhofer IISB

Abstract
Wide band gap (WBG) semiconductors (SiC, Ga2O3, GaN, AlN, diamond) have certain outstanding physical properties which make these materials so attractive for power electronic, optoelectronic and rf applications. However, the growth of bulk crystals with large diameters and with high quality and yield and the manufacturing of substrates from these crystals are much more complicated in comparsion to the very mature materials Si and GaAs. In the presentation the difficulties in growing bulk and epitaxial WBG semiconductors will be introduced and technical solutions will be shown which have been developed to overcome the existing obstacles. Special focus is put on SiC, GaN and AlN. The status of these materials is compared in terms of avaible crystal size, totally produced wafer area and typical crystal defects. An outlook will be given to the next scientific and technological steps which must be solved in order to accelerate the commercialization of the materials further.

Biography
Dr.-Ing. Jochen Friedrich studied Materials Science at the Friedrich-Alexander University of Erlangen-Nuremberg (FAU), Germany. After receiving his Dr.-Ing. degree from the FAU in 1996 he joined the Fraunhofer Institute of Integrated Systems and Device Technology (IISB). Since 2004 he is head of the Department Materials at IISB which was formerly named Crystal Growth. Together with his colleagues Dr. Jochen Friedrich received several awards: “Wissenschaftspreis des Stifterverbandes für die Deutsche Wissenschaft 2003”, Award of the „Gesellschaft für Mikroelektronik, Mikro- und Feinwerktechnik (GMM) des VDI/VDE“ 2005, Best Lecture Award of the International Workshop on Crystal Growth Technology 2008, Microelectronics Innovation Award 2009, and EMRS-Symposium W Best Poster Award 2016. He was also president of the German Crystal Growth Association (DGKK) from 2012 to 2016. His department is doing applied research for its industrial partners on bulk growth and epitaxy of semiconductor materials (Si, Ge, GaAs, InP, SiC, GaN, AlN).

ALD/CVD applications, equipment and precursors in high volume manufacturing

Sundqvist, Jonas
Group Leader
Fraunhofer IKTS

Abstract
Research by Fraunhofer IKTS and TECHCET LLC, an advisory services firm providing electronic materials information, has shown that strong growth in IC fabrication demand for atomic-layer deposition (ALD), chemical-vapor deposition (CVD) should result in a combined global market size of US$1.3 billion by the year 2023. Metal precursors are expected to see a compound annual growth rate (CAGR) of 6.2 percent through 2023 starting from $460 million in revenues for this year. The market for dielectric materials is forecasted to be $465 million this year with CAGR of 8.2 percent through 2023, as detailed in the latest CMR. Plasma enhanced CVD and ALD processes drive increasing demand for silicon precursors, used in depositing the 32-72 layers and more of 3D-NAND chips and in self-aligned multiple patterning for advanced logic and memory chips. In addition, the research see a need for more advanced ALD/CVD precursor production in China, to support more leading-edge logic and memory fabs ramping production there. Cobalt (Co) metal is being used to encapsulate copper on-chip multi-level interconnects in the most advanced logic fabs for both foundries and IDMs. Intel is using full cobalt interconnects to replace some of the copper levels in its newest logic chips. The conservative demand forecast for cobalt metal in the form of ALD/CVD precursors for logic IC fabs is $25 million in 2018, with considerable growth to $70 million by 2023. Due to the competitive demand for cobalt needed for the lithium batteries used in EVs, and due to conflict issues in the supply-chain, cobalt metal pricing is volatile and reliable forecasting is correspondingly difficult. To anticipate supply-demand imbalances, the research also tracks ALD and CVD precursor demands in competing high volume manufacturing industries such as flat-panel display, photovoltaics, MEMS, and LED as well as emerging semiconductor ALD/CVD applications, equipment and precursor developments.

Biography
Jonas Sundqvist received his PhD in inorganic chemistry from Uppsala University, Department for Materials Chemistry at The Ångström Laboratory in 2003 where he developed ALD and CVD processes for metal oxide ALD and CVD processes using metal iodides. In 2003 he joined Infineon Memory Development Centre (MDC) as a process engineer for development of high-k and metal nitride ALD processes. Later at Qimonda (2006) he was a member of the Materials Management team for precursor procurement and acquisition with special focus on ALD precursors for DRAM development and production. In 2009 he joined Fraunhofer Center Nanoelectronic Technologies (CNT) as an expert for thin film deposition with special focus on high-k dielectrics and electrode materials for DRAM, eDRAM, BEOL MIM Cap and HKMG technologies. In 2010 he founded ALD Lab Dresden together with TU Dresden and in 2013 he became Group Leader of High-k Devices Group at Fraunhofer CNT which at the same time became a business unit of Fraunhofer IPMS. In 2014 Jonas foundSr. Technology Analyst of TECHCET— covers ALD and CVD precursors and related technologies, and is the co-chair of the Critical Materials Council (CMC) Conference. His over 20 years of work experience includes group leader of the High-k devices group at Fraunhofer’s Center Nanoelectronic Technologies (CNT), which included 28nm node work for GLOBALFOUNDRIES Fab1. While there, he founded the ALD Lab Dresden together with TU Dresden. At Infineon Memory Development Centre (MDC) he developed high-k and metal nitride ALD processes, and at Qimonda he was a materials manager focused on the ALD / CVD precursors supply-chain. He is the founder of BALD Engineering, an independent blog and networking platform for ALD. He holds a Ph.D. and a M.S. in inorganic chemistry from Uppsala University, Sweden, a B.S. in electrical and electronics engineering from Lars Kagg, and nine patents.ed BALD Engineering AB, an independent Networking Platform for ALD. Since 2016 Jonas is leading the Thin Film Technology Group within the System Integration and Technology Transfer Department of Fraunhofer IKTS in Dresden Germany. He is also a part time Sr. Technology Analyst of TECHCET— covers ALD and CVD precursors and related technologies, and is the co-chair of the annual Critical Materials Council (CMC) Conference. Dr. Sundqvist has over 10 years experience, holds 10 patents and authored or co-authored more than 30 publications in the fields of ALD and CVD process development.

Towards on-chip 3D all-solid-state lithium-ion microbatteries

Zybell, Sabine
Project Manager
Fraunhofer IPMS

Abstract
The upcoming Internet of Everything (IoE) devices demand miniaturized rechargeable batteries, who distinguish themselves through a high level of safety as well as increased energy and power density per footprint area. Thin-film all-solid-state lithium-ion batteries deposited on highly structured silicon substrates are ideal candidates to match these requirements. The technical transition to solid-state electrolytes means significant improvement of battery safety. Three-dimensional (3D) battery concepts, including deposition on structured surfaces with high aspect ratio, have been shown to improve both capacity and rate performance of all-solid-state batteries. At Fraunhofer IPMS-CNT we are driving the development of functional layer stacks by atomic layer deposition (ALD) allowing direct integration into microsystems. ALD enables conformal, pinhole-free deposition of nanometer thin films and composition control on an atomic level. However, deposition of lithium-containing materials by ALD is a challenging task. In order to make the entire 3D battery by ALD, single layers, interfaces, and the whole layer stack have to be tailored. For semiconductor compatible design and production we manufacture on 8 inch silicon wafers using standard industrial thin-film deposition equipment. For battery integration into silicon technology lithium-ion diffusion into the silicon substrate must be inhibited. Undesired lithium-ion outdiffusion would result in poor cycling stability and failure of neighboring devices. In order to enable deposition on nanostructured silicon substrates, there is demand for as thin as possible non-active battery layers. In this work, lithium-containing functional layers and ultrathin lithium- ion diffusion barriers for on-chip 3D batteries were investigated.

Biography
RESEARCH Fraunhofer Institute for Photonic Microsystems (IPMS) - Center Nanoelectronic Technologies (CNT), Dresden, Germany Atomic layer deposition of Li-containing layers for thin film batteries Energy devices for microelectronic systems, since 2015 Technische Universität Bergakademie Freiberg, Germany Semiconductor optics, 2013-2014 EDUCATION Helmholtz-Zentrum Dresden-Rossendorf, Germany Technische Universität Dresden (TUD), Germany Ph. D., Physics, 2015 Dissertation: Relaxation dynamics in photoexcited semiconductor quantum wells studied by time-resolved photoluminescence Friedrich-Schiller Universität Jena, Germany Diplom, Physics, 2006 Lund University, Sweden Physics, 2002-2003

Photonics for Next Generation Computing

Tekin, Tolga
Group Manager
Fraunhofer IZM

Abstract
Main bottleneck to the realization of next generation computing systems for all big-, secure-data applications and related industries, including System-in-Package and System-on-Chip based solutions, is the lack of off-chip (off-core) interconnects with low latency, low power, high bandwidth, and high density. The solution to overcome these challenges is the use of photonics. Photonics as an underlying technology is addressing the following main technological challenges of the next generation computing systems such as i) Off-chip interconnects, ii) Massive switching matrix, iii) Disruptive system architectures, iv) Cooling concepts, v) New peripheral component interconnect express, vi) Memory fabric, vii) Novel computing functions in order to enable Quantum- & Neuromorphic Computing, AI. Next Generation Photonics Platform will enable the disruptive computing technology and photonics enabled architectures, leading to faster, cheaper, power efficient, secure, denser solutions for applications and industries. Further, generic co-integration with all building-blocks of computing technology will be possible, since photonic based standard interfaces between building blocks are introduced and implemented.

Biography
Tolga Tekin received the Ph.D. degree in electrical engineering and computer science from the Technical University of Berlin, Germany. He was a Research Scientist with the Optical Signal Processing Department, Fraunhofer HHI, where he was engaged in advanced research on optical signal processing, 3R-regeneration, all-optical switching, clock recovery, and integrated optics. He was a Postdoctoral Researcher on components for O-CDMA and terabit routers with the University of California. He worked at Teles AG on phased-array antennas and their components for skyDSL. At the Fraunhofer Institute for Reliability and Microintegration (IZM) and at Technical University of Berlin, he then led projects on optical interconnects and silicon photonics packaging. He is engaged in photonic integrated system-in-package, photonic interconnects, and 3-D heterogeneous integration research activities. He is group manager of ‘Photonics and Plasmonics Systems’ and coordinator of ‘PhoxLab - Independent Platform for Photonics in Data Centers (PIH)‘ at Fraunhofer IZM . He is coordinator of European flagship project ‘PhoxTroT’ and European H2020 project ‘L3MATRIX’ on optical interconnects for data centers.

Are Materials still key to successful manufacturing of Semiconductors?

Weiher, Susan
Sr. Director TD, GLOBALFOUNDRIES Fab 1
GLOBALFOUNDRIES

Abstract
Semiconductors remain a fast growing market worldwide. Since 30 years, there has been revenue increases by ~ 10% yoy. Looking at the segments, memory/logic remain strong, while sensors and opto-electronics are growing. Technology scaling towards smaller structures and larger wafers is driving up costs and investments, and many semiconductor manufacturers cannot afford to pursue the smaller scale. In memory, consolidation of manufacturers who drive DRAM and Flash developments is done. Also, regionally China and America are growing, Japan and Europe are losing share. The focus of this paper is the impact materials play in this changing business. Interestingly, no technology or wafer size has disappeared from the manufacturing landscape in the last 20 years. Due to product longevity and the addition of new features and functionalities to those existing bases, high voltage, non-volatile memories, RF, Si photonics, to name a few, the products meet the demand but it is clear that these new emerging applications will drive specific demands on material development. Another perspective is that increased quality in yield and reliability drives material suppliers to provide enhancements in defectivity and quality controls. A minor quality loss can lead to massive wafer supply risk if reliability or yield is impacted. And Europe’s semiconductor industry faces a competitive disadvantage over other regions of the world. Europe’s EHS compliance and chemical legislation (EU REACH, RoHS) regulate materials differently to other manufacturing geographies. In some cases, this EU regulatory landscape drives the development of alternative materials. As China brings the mega-fabs online with the advantages they have (funding, regulations, captive customers), we will be forced to make the solutions cost effective. The demand for new materials, the requirements for superior qualify and necessity of solutions for EHS pressures will drive inventive solutions at the forefront of this business.

Biography
Dr. Susan Weiher received her PhD from Stanford University in 1991 in Chemical Engineering, focused on Substrate driven reactions in vacuum environments. she chose a career in the Semiconductor equipment manufacturing right after completing her degree and at the beginning of significant advances in technology capability and Silicon Chip demand. In 1994 she move to Europe, specifically Germany. After 22 years in the equipment side of the business, she took on the opportunity to move to the manufacturing of chips, and managed the Manufacturing Engineering team of a major European Semiconductor fab in Germany. Since January 2018, she holds responsibility for the technology development (TD) group within Europe's largest foundry.

Acceleration in packaging development through 5G and mmWave applications

Goetze, Christian
Member of Technical Staff
GLOBALFOUNDRIES

Abstract
The next network generation will enable high bandwidth applications like Ultra HD videos for mobile devices and at the same time support wireless Virtual Reality (VR) gears. Smart city and smart home applications are requiring a high flexibility in integration of different devices into the network. IoT and wearables are less demanding in terms of data rate, but mean a tremendous increase of connected devices and at the same time a strong demand for super low power. Beside these applications, advanced health care, connected cars and autonomous driving are emerging. These mission (?) critical applications are requiring a high data rate together with the absolute reliability of the systems. GLOBALFOUNDRIES’ new 22FDX-mmw technology is targeted to serve ultra low power, digital data processing and analog IP integration and allows system architects to design IP into one single SoCs. To package these mixed signal SoCs, our industry is facing complex challenges by a high number of digital I/Os, sophisticated power and ground networks and highly sensitive RF signal routing. The packaging integration of millimeter Wave, in combination with high frequency antennas needs new levels of chip-package-co-design and thorough usage of advanced packaging materials. In this presentation, we will show the challenges associated with mmWave based mobile networks, packaging solutions that can be adopted and how the design flow can improve system integration and overall performance.

Biography
Christian Goetze is Member of Technical Staff in the global Packaging Technology Integration group at GLOBALFOUNDRIES, based in Dresden, Germany. He is leading several RF-packaging development projects for 5G, mmWave and IoT applications incorporating advanced silicon technology nodes such as 45RFSOI, 28nm and 22FDx. In this role Goetze is the main interface to RnD institutes and supports lead customers in the network industry in product enablement. Christian Goetze joined Globalfoundries in 2010 and managed multiple packaging development and qualification programs with close collaboration to global Assembly and Test houses. Prior to joining Globalfoundries, Goetze worked as process and integration engineer at NOKIA-SIEMENS-Networks, Qimonda and Infineon. In these positions he worked on the second level assembly process development and optimization for memory modules and communication boards. Christian Goetze received a Master of Science degree in Electrical Engineering from the Dresden University of Technology, Germany. In his Master’s work, a cooperation of TU Dresden and SIEMENS, he studied the interfaces in Pb-free second level interconnects and their influence to the board level reliability.

Emerging Memories - Foundries Are Taking the Lead

Müller, Johannes
MTS
Globalfoundries

Abstract
During the last two decades of emerging memory R&D a slow but distinct paradigm shift from stand-alone to embedded application targets is observable. For nearly all new memory concepts, independent of their time of introduction and pace of maturing, the first ambitious goals to replace highly specialized standalone memories, such as commodity DRAM or NAND-FLASH, were quickly shattered. The inability of emerging memories to intercept high density stand-alone memories is mainly caused by a slower scaling insufficiently compensated by the "value add" they provide in this particular application space. In the embedded memory world bench-marking the competitiveness of a memory solution is markedly different. Here the application focus is mainly on code-storage and the boundary conditions for the cost per bit are not solely driven by scaling, but are set by the CMOS-platform and the integration complexity required to add a memory solution. Key advantages of emerging memory concepts, such as low power and ultra-fast write when compared to FLASH as well as their non-volatility when compared to DRAM, are now weighted differently. As a consequence, CMOS-foundries are ringing in the final round for emerging NVMs to compete for a place amongst the main-stream memory solutions. In this talk the status of embedded memories utilizing ferroelectric and ferromagnetic domain reconfiguration will be reviewed. Namely the two long term NVM contender magnetic random access memory and ferroelectric field effect transistor. In recent years both concepts overcame their scaling limitations by major breakthroughs in material development and device design. The revival of ferroelectric memory devices was led by the discovery of CMOS-compatible and scalable ferroelectric hafnium oxide. In the case of magnetic memory devices the introduction of spin transfer torque as well as material and interface engineering to provoke perpendicular magnetization paved the way for a new generation of devices.

Biography
Dr. Johannes Müller is a member of the eNVM technology & development team at GLOBALFOUNDRIES Dresden and currently acts as the responsible overall integrator for STT-MRAM in Fab1. Prior to joining GLOBALFOUNDRIES he was heading the group for Non-Volatile Memories at Fraunhofer IPMS. His research & development interests are primarily focused on the device physics, material development and integration strategies of embedded memory solutions, with a special interest lying in the exploration of emerging ferroelectric and ferromagnetic device concepts. Dr. Müller holds a diploma degree in Applied Natural Science from the Technical University Freiberg and a PhD degree in Electrical Engineering from the Technical University Dresden. To date Dr. Müller has authored/co-authored more than 90 peer-reviewed journal papers, patents and contributions to international conferences, including invited presentations at e.g. IEDM, ECS, NVMTS, SSDM and SISC. In addition to several scientific paper recognitions, he was awarded the "Georgius-Agricola-Medal" in 2008 and the “Heinrich-Barkhausen-Award” as well as the “Hugo-Geiger-Award” in 2015. He is an active member of IEEE and served as an expert and contributing author for ferroelectric memories and devices in the Emerging Research Devices Working Group of the ITRS.

Automotive & advanced manufacturing

Balderson, Nicholas
Director of Quality
GLOBALFOUNDRIES

Abstract
With the rapidly increasing demand for semiconductor devices in vehicles driven by the electrification of the drive train and by the vision of self-driving cars, the semiconductor manufacturers are challenged to elevate advanced technologies to automotive standards much earlier in the technology life cycle. At the same time the need for ultra-low power and high performance devices requires the usage of advanced transistor architectures and smaller nodes. GLOBALFOUNDRIES 22FDX technology has been developed to offer ultra-low power and high performance devices coupled with RF integration. NVM offerings are currently being added and directly target Grade 1 applications. The boundary conditions for automotive applications have been built in right from the beginning of the development process. Besides the AEC Q100 temperature and reliability requirements the technology also needs to pass more stringent and tighter variation controls than consumer grade technologies. Bundling together advanced manufacturing detection & control methods, reliability proven technologies, automotive specific services, and consequent risk mitigation throughout the entire lifecycle, the GLOBALFOUNDRIES AutoPro Service Package provides the right approach to master the new automotive challenge. In our presentation we will show that this requires a holistic approach for technology development and qualification that drives beyond regular reliability tests and must include the specific manufacturing process characteristics and implementation in the fab. Special effort must be spend to ensure very early maverick or variation detection during processing as well as process variation reduction and control using advanced techniques.

Biography
Nicholas Balderson is the Director of Quality at GLOBALFOUNDRIES in Dresden, Germany. He is responsible for ensuring the Advanced Quality Execution System to go above and beyond Customer expectations. Dresden's quality success includes full Automotive Certification as well as delivery according to GLOBALFOUNDRIES AutoPro standard. Nic joined GLOBALFOUNDRIES in 2015 and quickly took over Quality leadership. Prior to that, he spent 5 years with AREVA Nuclear Power in various project management roles, and 10 years with Infineon/Qimonda in program management for package development. Nic is a Magna Cum Laude graduate of Virginia Commonweatlh University and holds a degree in electrical engineering as well as a Masters in Business Administration from Wayne State University.

Zimmermann, Andre
Executive Board Member
Hahn-Schickard

Biography
André Zimmermann was born in Schweinfurt, Germany, in 1971. He studied chemistry and crystallography at Julius-Maximilians-Universität Würzburg as well as materials science with specialization in mechanical engineering at Technische Universität Darmstadt. After several stays in the USA at NIST and University of Washington he received his PhD in 1999 at Technische Universität Darmstadt. He held positions as group manager at the Max-Planck-Institute for Metals Research, Stuttgart, and as senior manager for electronic packaging within the corporate research and development of Robert Bosch GmbH in Waiblingen. Since January 2015, he is professor for micro technology at the Institute for Micro Integration (IFM) of the University of Stuttgart. Simultaneously, he is the head of the Institute for Micro Assembly Technology at Hahn-Schickard in Stuttgart.

Highly customizable process for fast manufacturing of thin flexible polyimide based circuit carriers and its application for a flow sensor using low-cost passive components

Janek, Florian
Research Associate; M. Eng.
Hahn-Schickard-Gesellschaft für angewandte Forschung e.V.

Abstract
Commercially available flexible printed circuit boards are manufactured by using adhesives for bonding thick copper foil on polyimide in a lamination process. For realization of thin foil systems without adhesives we present a highly customizable, additive process using polyimide foils, PVD technology and a maskless direct imaging process to manufacture flexible polyimide based circuit carriers in short time and small lot sizes. First, polyimide foil is used as substrate for sputtering a thin Cr/Cu metal layer. Then photoresist is applied on the metalized foil by conformal coating. Structuring of the resist is carried out by direct imaging and subsequent developing of the resist. After applying of copper electroplating for enhancing the opened tracks, the mask is stripped off and the metal layer is etched until the base PVD metallization is completely removed. Finally a suitable metal finish for assembly processes is applied on the copper tracks by electroless plating of nickel and gold. With these base substrates a thermal direction sensitive mass flow sensor element was realized using low-cost passive SMD components such as a resistor as a heater and NTCs as temperature sensors on both sides of the resistor. The development of the read-out circuit as well as the characterization of the low cost flow sensors are in progress. The presented process chain combines the advantage of maskless lithography with its short preparation time on one side and batch processing for an industrial approach on the other side. The process offers thin, flexible and individualized sensor elements with easily scalable size and configurable layout without additional adhesives.

Biography
Florian Janek received his Master degree in Microsystems- and Nanotechnology from the University of Applied Sciences Kaiserslautern, Germany, in 2015. His interest is in the field of functionalized and sensorized flexible systems made of foil and textiles. After his studies he began working for Hahn-Schickard and joined the group of Prof. Dr. Zimmermann as a PhD candidate in the laboratory for systems-in foil applications at the University of Stuttgart, Germany, in 2016. His research is focused on embedding ultra-thin chips into flexible packages forming system-in-foil applications.

Innovative Adhesive Developments for Next Gen Sensing Modules

Wu, Kily
Product Development Manager
Henkel Electronic Materials

Abstract
As electronics industry enters a new era of IoT devices, more and more sensing modules are becoming essential to make devices “smart” and "intelligent". Representative ones are camera modules, proximity and ambient light sensors, biometric (3D ID) sensors and MEMS devices. As signal sensing and processing become more advanced and demanding, the adhesives used need to meet more stringent requirements of process flexibility, application accuracy, adhesion strength, drop test and reliability. Henkel evolves together with leading sensing module makers by further developing specialized adhesives for them. For example, in camera modules, low temperature cure and low shrinkage are critical for active alignment and enabling ultra-high image quality. Hybrid resin and curative designs enable cure below 80°C while achieving ultra-low cure shrinkage and excellent adhesion to various substrates. A versatile chemistry toolbox - incl. epoxy, acrylate, silicone and hybrid resins - is used to develop new adhesives for MEMS with a wide modulus range (1 MPa up), stable modulus during operation and high toughness. Through catalyst selection, different UV and/or thermal cure mechanisms are entailed to enable different application processes with higher output. For each chemistry, the adhesive rheology must be tailored to fit challenging aspect ratios using needle dispensing, jetting, printing or laser assisted transfer. For image sensor, lid, cap and stiffener attach and grounding, various levels of electrical and/or thermal conductivity are incorporated by specially developed resin and filler systems. Finally, adhesive FILM is getting preferred over liquids due to advantages in bond line thickness control, tight keep-out zone, low warpage and low stress by low temperature cure, latent catalyst selection and B-stage processing. This presentation will give a clear overview of the sensor assembly challenges AND innovative adhesive solutions to enable Next Gen Sensing Module developments.

Biography
Kily Wu is Product Development Manager with Henkel Electronic Materials and based in Shanghai. His team is developing specialized Semiconductor Die Attach and Sensor Assembly adhesives. Kily has a Master degree in Chemistry with “Macromolecular Chemistry and Physics” as major.

Adhesive & Encapsulation Developments for Advanced Semiconductor Packaging

de Wit, Ruud
EIMEA SU Head Semiconductors
Henkel Electronic Materials NV

Abstract
Electronics market trends continue to drive innovation for higher functionality with smaller form factors and reduced power consumption. To meet these demands, the design of semiconductor devices is changing more and more from traditional wire bonded packaging to so called “advanced semiconductor packaging“ based on Wafer Level, Flip Chip and 2.5D/3D Stacking technologies. Fan-In and Fan-Out Wafer Level Packaging (WLP) and Through Silicon Vias (TSV) for instance are successfully replacing proven wire bond technology today. This has a significant impact on the typical assembly materials being typically used in the Back End Of Line (BEOL) production of semiconductors. For instance, there’s often no need for die attach adhesives and traditional transfer mold compounds anymore being currently widely used in SO, QFN, QFP and BGA type of lead frame and laminate devices. This presentation will give a high level overview of the relative new and different assembly materials being developed, qualified and used in “advanced semiconductor packaging“ as such. This includes very thin “Wafer Applied Underfill Films” for 3D Stacking of thin TSV Wafers, specialized “low stress and low warpage” adhesives/underfills for Flip Chip and Interposers and low shrinkage and ultra-low warpage wafer encapsulants for Fan-In and Fan-Out devices. As the proven wire bond technology will certainly continue to be used in high reliability and automotive semiconductors and sensors, also new adhesives with higher thermal conductivity, lower temperature cure, ultra-low modulus and pre-applied “B-stage” capability will pass by ….

Biography
Ruud de Wit is responsible for managing Henkel's Semiconductor Materials business in EIMEA. Ruud has a BSc degree in Mechanical Engineering followed by several polymer, sales and marketing courses. He's working for Henkel since 1990 in multiple positions including technical service, quality engineering and global semiconductor account and product management.

Unmet Material Needs in New Applications for Printed Electronics

Neumann, Christian
Head of Digital Printed Electronics
Heraeus

Abstract
Interesting new markets like Smart Textiles and In-Mold Electronics appear at the horizon for flexible printed electronics. These new applications pose new challenges to both manufacturing and material performance needs. In this talk we address unmet needs in each application and suggest possible material solutions to overcome these obstacles.

Biography
Christian Neumann heads the Heraeus activities in Digital Printed Electronics. With a strong technological background he was responsible for the implementation of Corporate Technology Scouting and Corporate Venturing activites for Heraeus. He joined Heraeus in 2007 being responsible for development of basic materials for fused silica before starting a group devoted to the development of new porous carbon material system. He studied physics at Justus-Liebig-University in Giessen and the University of Washington in Seattle before earning his PhD with the synthesis of novel optoelectronic materials by epitaxy.

Light-assisted integration of electronic components

Chiappini, Francesca
Scientist
Holst Centre - TNO

Abstract
Following a current consumer trend, the demand for high-performance and highly-integrated multifunctional flexible systems has significantly increased in recent years. This has generated the need to develop hybrid systems in which printed circuitry is combined with silicon-based integrated circuits or surface mounted device (SMD) components. Flip-chip (FC) assembly of (opto)electronic components is a key technology in system packaging and integration because of the advantages it offers over the most commonly used wire bonding technique. With decreasing chip size, the density of interconnects increases, which demands advanced high-resolution interconnection technologies. Furthermore, with large-area flexible electronics on low cost polymer foils gaining significant attention lately, the compatibility of the interconnection technology with the carrier substrate has become more significant than ever. At Holst Centre, we have developed two complementary technologies that enable fast and high-resolution integration of FC assembly components onto flexible foils using light. The interconnect material (lead-free solder pastes as well as electrically conductive adhesives) is deposited onto flexible printed circuitries at unprecedented high speed using a laser-assisted digital deposition technology. In this talk, we will present the deposition of an array of 10 000 dots of conductive adhesive (< 100 µm in diameter) within less than a second. The interconnect process is then completed by soldering the components to the substrate using a novel roll-to-roll compatible soldering technology (photonic soldering), which exploits intense pulsed light generated by conventional flash lamps. In contrast to convection reflow soldering (the industry standard technology), photonic soldering is fully compatible with the integration of components on low-cost flexible substrates such as PET, while reducing the soldering processing time down to few seconds.

Biography
Francesca Chiappini has obtained her PhD from the Radboud University (Nijmegen, The Netherlands) doing research on the electronic properties of graphene. She then joined TNO (Delft, The Netherlands) working in several projects addressing some of the challenges faced by the semiconductor manufactory industry. In particular, she worked on the topics of contamination control and subsurface AFM imaging. Currently, she works as scientist at Holst Centre (Eindhoven, The Netherlands) in the hybrid printed electronics domain. She focusses her research activities on novel interconnect technologies for flexible systems.

New perspectives creating radical innovation

Van den hove, Luc
President and CEO
imec

Abstract
The era of digital transformation brings endless opportunities for businesses and society: opportunities powered by the advances in nanoelectronics and digital technology, opportunities that require cross-linking of expertises. Radical innovation can only happen by approaching the challenges our society is facing from new perspectives, with an open mind that gets inspired from unexpected fields. Radical innovation can happen. Innovation that will transform our health, mobility, environment, … Innovation that will transform our data-driven society into a sustainable data-driven society for everyone.

Biography
Luc Van den hove is President and CEO of imec since July 1, 2009. Before he was executive vice president and chief operating officer. He joined imec in 1984, starting his research career in the field of silicide and interconnect technologies. In 1988, he became manager of imec’s micro-patterning group (lithography, dry etching); in 1996, department director of unit process step R&D; and in 1998, vice president of the silicon process and device technology division. In January 2007, he was appointed as imec's EVP & COO. Luc Van den hove received his PhD in electrical engineering from the KU Leuven, Belgium. He has authored or co-authored more than 200 publications and conference contributions.

Materials and Processes for 3D Heterogeneous Integration

Beyer, Gerald
Program Manager
IMEC

Abstract
3D heterogeneous integration opens new paths for System On Chip (SOC) and System In Package (SIP) to integrate computing, storage, in and output and other functions in a system efficiently. As interconnect requirements between the various components differ in terms of bandwidth and energy per bit, 3D technologies need to provide different interconnect solutions within a system. In order to realize significant wire length savings of a partitioned processor, small interconnect pitches below 1µm are required. Connections to off-processor memory are longer and have wider pitches. In this presentation, the co-existence of these different 3D interconnect technologies and their need for new materials and integration solutions is discussed.

Biography
Gerald Beyer has been working in the field of 3D Technologies since 2012 as the technology program manager of the 3D System Integration Program of IMEC. Prior to this he was the interconnect program manager and group leader of BEOL integration. He received a PhD in materials science from Imperial College, London and a MSc from Thames Polytechnic, London.

Dekoster, Johan
Program Manager
imec

Biography
Johan Dekoster received the M.S. degree in Exact Sciences (Physics) in 1988 from the KU Leuven, Belgium. In 1993 he received the Ph.D. degree (Physics), also from the KU Leuven. From 1993 till 1999 he held postdoctoral fellowships from the Research Council and the Fund for Scientific Research at the Institute of Nuclear and Radiation Physics of the KU Leuven. In 1999 he joined the OTN business unit of Siemens. He was project leader for several hardware firmware development projects for data, voice, video and LAN. In 2007 he became program manager OTN at Nokia Siemens Networks. In April 2008 he joined imec as R&D manager of the Epitaxy group with responsibility on epitaxial deposition of group IV and III-V semiconductor materials. Since November 2012 he is program manager for equipment and materials suppliers collaborations at imec.

Towards wafer-scale Qubits

Mongillo, Massimo
Device Engineer
IMEC

Abstract
In this talk I will present the recent progress made by IMEC in the fabrication and integration of basic quantum circuits targeting qubits into a 300mm FAB. Quantum Computing holds promise for solving complex computational problems which are intractable by classical calculators. The basic ingredient for the implementation of a quantum computer is the availability of a two-level system mimicking the classical bit “0” and “1”(the qubit), on which we can encode the basic information. The exceptional computation power of a Quantum Computer originates by the quantum-mechanical property of superposition, according to which the qubit state is defined as an arbitrary linear combination of the two constituent bit states. At the qubit level, two main solid-state implementations are currently explored at IMEC. They are based on individual spins in Silicon and Superconducting circuits. Spins in silicon have demonstrated the longest coherence time in any solid-state device as a result of the lack of hyperfine interaction coupling the spins of the nuclei and the electronic spins. Another approach makes use of Superconducting devices, which, to date, represent the most advanced solid-state implementation of a qubit. Although this technology has proven to be mature for the implementation of basic Quantum Algorithms, it presents unique challenges in term of integration of a large (millions) array of qubits, necessary for error-correction. Given the rather large foot-print of an elemental Superconducting qubit, this platform need to demonstrate its viability in terms of up-scalability. In the long term, both qubits platform need to be integrated into a larger system comprising the control electronics routing the necessary signals to the physical qubit layer. In IMEC we are pursuing these research lines leveraging the extended know-how in terms of large-scale integration and system architecture.

Biography
Massimo Mongillo holds a Master degree in Physics from University of Naples in 2005 and a PhD in Nanophysics from University Joseph Fourier in Grenoble in 2010. His research has focused on the physics of Silicon nanoscaled devices, Quantum Transport and Superconductivity. In 2015 he has joined IMEC to develop devices based on two-dimentional materials. Since 2017 he is in the Quantum Computing group for the integration of Superconducitng and spin Qubits.

Perspectives for disruptive 200mm/8-inch GaN power device and GaN-IC technology

Marcon, Denis
Sr. Business development manager
IMEC

Abstract
Today, GaN-on-Si is accepted as a break-through power electronics technology. The favorable materials characteristics and the e-mode lateral HEMT device architecture have led to disruptive device performance. Issues with trapping effects and reliability that plagued early versions of the technology have been addressed and first products are in the market. Today imec is focused in further increasing the performance and reliability of its 200mm/8-inch GaN-on-Si e-mode devices for 200V and 650V applications. Next to improving GaN-on-Si e-mode technology, imec is also investigating the next generations of GaN technologies that will provide: higher level of integration (GaN-IC), higher performance and larger voltage rating Particularly attention is dedicated to GaN-IC that allows to unlock the full potential of the fast switching GaN-based power devices. Indeed, monolithic integration of a half-bridge, co-integration of the GaN drivers, and free-wheeling diodes offer a way to reduce parasitic inductances, while on-chip temperature sensors and protection circuits increase the robustness. Such power GaN-IC’s pave the way for unprecedented compact high-end power systems. In this talk, imec will review the status of GaN-on-Si e-mode device technology as well as its recent progress on technologies for GaN-IC.

Biography
Denis Marcon received a M.S. degree from the University of Padova in 2006. Subsequently, he received the degree of Doctor in Engineering (Ph. D.) from the Catholic University of Leuven and imec with the thesis entitled “Reliability study of power gallium nitride based transistors” in 2011.He is leading author or co-author of more than 50 journal papers or conference contributions. Currently, he is a Sr. business development manager in imec, Belgium, and he is directly responsible for the partnerships with imec in the field of GaN power electronics and on dedicated development projects of Si-based device and sensors.

2D materials integration: The long journey from a lab-to-fab environment

El Kazzi, Salim
Senior Scientist
IMEC

Abstract
During his memorizing lecture “There's Plenty of Room at the Bottom” in 1959, Richard Feynman predicted that surface tension and Van der Walls Forces will be crucially important in the future nanoscale applications. After nearly 60 years, the discovery of Graphene and its related 2D materials are surprisingly confirming these predictions. The use of this family of materials is opening a new era of research innovation in different fields. The imagination of researchers has allowed them to use 2D materials for water treatment, clean energy, (bio)sensing and interesting optical applications. 2D materials are also expected to help in the expected convergence of 5G communications with the Internet of Things (IoT) where faster and connected computers can be achieved by reducing the size of their circuits. All this fantastic work is however stopped at the proof of concept levels. If these materials would ever see mass production and foundries would accept to have them in their machines, technological solutions to integrate 2D on large area surfaces are fundamental requirements. In this talk, we will share on our journey to bring these 2D materials from the lab to the fab. The discussion will be first focused on the growth and transfer of 2D materials and how we are trying to understand and solve the main challenges of these Van der Walls materials. An emphasis will be given to the role of surface tension and interface engineering in the making of the 2D-based devices. In a final part, the talk will cover our strategy to integrate 2D materials in a fab production environment while using the learnings from the lab. This work is expected to offer insights on both the main challenges and solutions of MX2 integration for future CMOS technology

Biography
Salim El Kazzi received his Ph.D. degree in micro and nanotechnology, acoustic and telecommunication from IEMN-University of Lille 1 in 2012. His research was focused on the growth of III-(As, Sb) on large area commercial substrates by MBE. After a postdoc position with the MIT-Singapore alliance SMART, he joined IMEC in 2013 as a research scientist responsible on the III-V epitaxy and gate stack deposition by MBE for tunneling devices. In 2015, he started the growth of MX2 semiconductors where he developed the first growth of MX2 by gas-source MBE. He is currently responsible for the large-scale MO-CVD growth of MX2-based materials for beyond CMOS technology

International talent at imec

Beenders, Chris
Talent Acquisition Manager
Imec

Abstract
In this presentation, we will focus on two main topics: 1.About imec: expertise, people and culture 2.How imec tries to tackle the workforce challenges in the global digital economy of today,

Biography
In 2007, Chris graduated as a master in Political Science at the Catholic University of Leuven. One year later she received her second master degree in Human Resource Management at the University Antwerp Management School. Chris started her professional career as a recruiting consultant where she headhunted for different companies. After 3 years, she moved towards internal recruiting at Cegeka Belgium, a European IT consultancy company. Here, she was promoted to Talent Acquisition Manager after two years. In this role she introduced an innovative recruitment strategy and successfully led the recruitment team. One of her main achievements was the foundation of the Cegeka school, where non-IT profiles are being trained to work in the business of Cegeka. In 2017, Chris took on a new challenge as a Talent Acquisition manager at imec Belgium, where her team is responsible for over 350 hires per year on average. She ensures Imec’s growth in a candidate driven labor market by defining a pioneering recruitment strategy and innovative employer branding activities.

CMOS technologies for all solid state micro- and macro-batteries

Onsia, Bart
Business Development Manager
imec

Abstract
Rechargeable Lithium ion batteries are key to cut the cord or the carbon emissions in various applications from Internet of Things, power tools, automotive, to balancing tomorrow’s smart grid. These applications are ever more demanding in terms of capacity, charging rate, safety and battery life. Historically progress has primarily been achieved thanks to material innovations. But the materials are only part of the story. An electrochemical cell is a heterogeneous system. The interface is where it all happens, and where many of the issues such as limited lifetime and charging rates find their origin. As the industry is transitioning to solid electrolytes the interfaces become even more important. In CMOS technology, interfaces are controlled at the atomic scale. This contrasts heavily with the micron thick interfacial layers in batteries due to electrolyte and electrode decomposition. This talk will illustrate how CMOS materials and processing are put to use in thin film 3D microbatteries and how these microbatteries can be practically integrated in microsystems. We’ll also show how thin film model systems allow to study interface-reactions independently; yield understanding of charge transport at interfaces; and can model particle to particle interaction. And we’ll show how these insights drive innovation for large capacity powder-based solid-state batteries for automotive applications.

Biography
Bart Onsia is Business Development Manager at imec in the research lines of All Solid State Li-ion Batteries and Thin Film PhotoVoltaics. Bart Onsia holds a Master in Industrial Sciences (Chemistry) from KU Leuven. He spent 2 years with Bayer as an production manager in aTiO2-plant before joining imec in 1999 as a researcher in microelectronics cleaning process, and surface preparation for e.g. high-k gate oxides, Germanium surfaces, .... In 2007, he moved towards a Business Program Manager role in which he was responsible for creating impact with the local industry in the Flemish region, in the field of energy (photovoltaics, batteries). From 2017, he is developing the business for imec’s thin film photovoltaics and solid state battery activities.

How Infineon Dresden attracts Generation Z

Quaas, Torsten
Senior Engineer Maintenance
Infineon Technologies Dresden GmbH & Co. KG

Abstract
It is getting more and more difficult to attract young people for manufacturing jobs – not only in general, but especially for industrial and craft activities. Thus, Infineon Dresden improved its training concept and reinforces public participation. Our new training workshop offers a central training facility for our mechatronics trainees in the first year. Important basic knowledge and skills will be taught based on real repair orders. After the practical training the trainees are well prepared for their specialized training in the different departments. Also, our micro technology trainees have the possibility to practice soldering on circuit boards. Today, they produce their own test chip over the period of six weeks. Purpose is to introduce the upcoming micro technologists into production departments, facilities and processes. Hands-on facilities like our training workshop also make Infineon Dresden more attractive especially for pupils. We are now able to offer a trial internship if they are 14 years and older to give an insight into the semi-conductor industry. To attract pupil’s attention, we stage student’s internships, “SCHAU rein”, Girl’s Day, and “genialsozial” – work against poverty, at Infineon Dresden. Therefore, we are in close exchange with educational institutions. At the training, job and new business owner fair “KarriereStart” 2018, representatives of the HR department, training supervisors and trainees informed about training and career opportunities at Infineon Dresden. Visitors of the Dresden Science Night 2018 had the chance to find out more about our products and see or try them in real life. At our first career and training day about 850 visitors used the chance to get an insight into one of Infineon’s biggest production sites. Our visitors were able to find out more about nearly every step of semiconductor production.

Biography
Torsten Quaas is maintenance engineer and project manager at Infineon in Dresden and team leader for about 60 employees and 3 trainees. Torsten Quaas was born on September 2, 1968 in Dresden. As a trained maintenance mechanic, he finished his studies as a state-certified technician in Dresden in 1993 – specializing in electrical engineering majoring in data technology. Since September 1994 he is employed at Infineon Dresden in areas of equipment engineering, production controlling, and industrial engineering. 2002 he completed his studies to become a qualified industrial engineer. Since then, he took over the responsibilities for headcount planning operations and maintenance. In 2015 he became responsible for the Maintenance Engineering group at Infineon Dresden.

Capraro, Bernie
Research Manager, Silicon Technology
Intel Research and Development Ireland Ltd

Biography
Bernie received a Masters Degree in Engineering (MEng) from Newcastle upon Tyne Polytechnic (now University of Northumberland) and has been working at Intel for the past 21 years holding various Engineering and Management roles across the wafer fabrication facilities. Bernie is currently responsible for all silicon nanotechnology research involving Intel Ireland, helping to deliver potential solutions to Intel for materials, devices, equipment and processing techniques required for the future technology nodes in collaboration with Research Centres, Academia and Industry across Ireland and Europe. Bernie’s semiconductor career spans 31 years, with other Process and Equipment Engineering positions held at Telefunken GmbH (Ge), Nortel/Bell Northern Research (UK/Canada), Applied Materials (UK) and Newport Wafer Fab (UK). In addition, Bernie is instrumental is developing Intel Ireland's relationships with third level Education Institutions, working on Policy, Talent pipeline and Research initiatives.

Industry 4.0 driving business model transformation in Advanced Manufacturing Facilities

Kennedy, Barry
CEO
Irish Manufacturing Research

Abstract
Though the semi-conductor industry can rightly claim to have led the charge in the development and implementation of the technologies driving the Industry 4.0 revolution, it is now seeing wider affects happening with new business model transformation and emerging manufacturing technologies transforming the ways businesses are managed and run. This is driven by the products the Semiconductor industry make and the relentless drive to deliver these products with more capability and less cost allowing the wider manufacturing base to design these technologies into their manufacturing plants. Are these emerging technologies now being used back in semiconductor facilities or is there opportunities to engage with them. This paper will put a mirror onto the industry.

Biography
Barry is currently CEO of Irish Manufacturing Research, Irelands leading cutting edge industrially focused research centre for advanced manufacturing. Barry qualified with an MSc from University of Dublin, Trinity College Dublin in 1996. He has worked as New Business and Strategic Program director for Ireland Fab Operations in Intel. Prior to this he has held many senior management roles in Failure Analysis, Process Integration, Device, Process Control and Statistics, Yield Analysis, Quality and Reliability, Yield Q&R. He started his career in Intel working in many senior engineering roles as senior Process Integration and Failure Analysis engineer. Barry has worked in a research environment in Trinity College Dublin for 10 years before commencing work with Intel.

Ultra-Thin, solid-state rechargeable battery with vertically integrated solar cell

Berland, Brian
Chief Science Officer
ITN Energy Systems

Abstract
ITN Energy Systems and ENrG Inc. have developed and demonstrated a promising new thin, flexible solid state lithium rechargeable battery (SSLB) for flexible electronics, smart wearables, and medical devices. Combining ITN’s SSLB technology with ENrG’s ultra-thin flexible ceramic solves the capacity and packaging issues that have thus far limited the thin film battery technology to limited niche markets. With a capacity greater than 20 mAh in a thickness less than 250 microns, including hermetic packaging, the new SSLB enables energy density greater than 1,000 Wh/l while maintaining the long recognized benefits of enhanced safety and durability provided by the all solid state chemistry. Results are also presented for a new Flexible Integrated Power Pack (FIPP) that add in-field solar recharging by combing the SSLB with Lucintech’s high efficiency CdTe solar cells. The new SSLB and FIPP products support operation across a wide range of duty cycles including high current pulses required for many wireless, display, and medical device applications. Results are presented for the battery and FIPP performance, including environmental and safety compliance testing.

Biography
Dr. Brian Berland, Chief Science Officer— Dr. Berland serves as the Chief Science Officer for ITN Energy Systems. In this role, he directs both technology and business development activities with a focus on moving technologies from the lab to commercialization. Over the last twenty years, he has led research and development activities in flexible electrochromic and low-e window films, flexible lithium solid state batteries, redox flow batteries, alternate energy generation and storage materials, environmental barrier coatings, as well as gas and liquid separation membranes. In his time at ITN, he has been an integral member of a team to successfully bid and execute over $30M in R&D programs with corporate and government partners, including leading teams commercializing ITN’s SSLB with leading worldwide corporate partners. He has been active in all aspects of product development for these technologies including cost-modeling, development of strategic partnerships, and definition of product performance requirements/market identification to support successful commercial transition and scale-up. Prior to joining ITN Energy Systems, Dr. Berland was a postdoctoral research associate at the University of Colorado in the labs of Professor Steven George, a world leader in ALD chemistry. He holds a BS in Chemistry from Carleton College and a Ph.D. in Chemistry from the University of Colorado.

Fine Pitch Plating Resist for High Density FO-WLP

Serrand, Jerome
Technical packaging manager
JSR Micro NV

Abstract
Abstract— Due to large topographic gaps between the chips and mold substrate, the next generation of high density FO-WLP will require fine RDL plating resists that can achieve as low as 2um line/spaces(L/S) with a wider common depth of focus (DOF) margin. In order to meet these requirements, we developed a novel chemically amplified positive tone resist. In this study, we focused on photo acid generators (PAGs) which are one of the major components of chemically amplified resists. We found that controlling the acidity of the generated acid from PAGs after exposure was a key approach to get good profiles on Cu sputtered substrates and wider DOF margins. Keywords—Plating resist, FO-WLP, fine RDL, photo acid generators.

Biography
Packaging Technical Manager, Jerome joined JSR in 2002. He is located near Grenoble the French Silicon Valley from where he can give full technical support to many different key customers in Europe. Keeping close contact with the R&D department in Japan and Belgium, he manages and supports several on-going projects at different European customers.

Digitalization and Innovation Transforms Manufacturing and Construction

Maris, Peter
CEO
Kinetics

Abstract
We’ve developed some new game-changing technologies leveraging 3d computer-aided design, augmented reality, virtual reality, and sophisticated human-machine interfaces. We can discuss how these technologies are changing the way facilities and equipment are designed, built, and operated.

Biography
Peter Maris, Kinetics Systems, Inc. CEO An accomplished business leader with over 19 years’ experience in the high-technology industry, Peter heads the global business operations for Kinetic Systems, Inc. Peter left a successful 10-year career in the commercial banking industry to join Kinetics in January 2000, first working in Malaysia for its Asian operations. He continued his leadership path shortly thereafter taking over as president for Europe/ME and Asia, before assuming the role of president and CEO in 2010. He is accredited for consolidating Kinetics’ international operations and establishing its Saudi Arabian business units. His strategy to drive the business into a process-driven company has transformed Kinetics into “The Process People” it is today, positioning the company as a global leader in total process solutions. Peter’s fluency in four languages and strong finance background gives him an edge in working with people and finding common sense solutions in an engineering-driven industry. Under his leadership, the company has continued to deliver double-digit profitable growth over the last few years. Peter holds a BS in economics.

Enabling Productivity, Performance and Organization Efficiency Through Equipment Intelligence™

Della Pia, Marcello
Fab Productivity Director
Lam Research

Abstract
Industry 4.0 is the current trend of automation and data exchange in manufacturing technologies. It includes cyber-physical systems, the Internet of things and cloud computing. Industry 4.0 creates what has been called a "smart factory". Which implies computerization and digitalization of all processes. This changes makes manufacturing more attractive enabling a higher level of efficiency allowing more precise and faster decision. The impact is on human resources as well since the job content became more interesting and might require a higher level of qualification in some function. At the same time it might make the production less impacted by turn over. Lam Vision for Equipment Intelligence is to be the Customer Choice For “Smart Tools Of The Future, Lam’s existing capability (sensors, data management & analytics) enables most of the Industry 4.0 potential, enabling process tools to deliver market leading process & productivity with a significant optimization in human resources. Six main components constitute the essence of Lam Research path to enabling smart tools in the semiconductor industry, which have been addressed through: Big data Machine Learning Platform: an Integrated scalable distributed big data and machine learning platform supporting fast algorithm development and customization. Automation: New robotics and platform design to increase productivity and enable lights out operation, including Monitoring & Self-Tuning. Sensors & Process Control: In-Situ & Integrated sensors monitor system and wafer status during process at high sensitivity and data rate providing greater productivity, Improved variability and Expanded process window Virtual Processing: Computational etch and virtual fabrication SW enabling fast learning & process development reducing development cost & time Advanced Productivity Solutions: Ecosystem of software and services built designed to drive improved OEE and Productivity, leveraging data

Biography
Mr. Della Pia is a semiconductor professional with 23 years of experience in high tech industry. He started his career working for Texas Instrument. When Micron Technology acquired the DRAM division of TI, he joined Micron technology. In Year 2000 he moved to China, being among the first to join the foundation of the first cutting-edge IC Foundry in China (SMIC), actively participated to the construction of semiconductor industry in the Mainland. Mr Della Pia advanced to various leadership roles across multiple Fabs and corporate position for SMIC. In 2013 He joined Lam research and currently is working as Director in the Customer Support Business Group of Lam Research, leading a team focus on Productivity Solution for Semiconductor Fabs. Mr. Della Pia is also responsible for Big Data project for Lam Research in the EMEA region. Mr. Della Pia holds a master degree in Chemical Engineering.

Which skills and competencies enabling Europe to meet the future

Fama', Fabrizio
VP of HR & Corporate Affairs
LFoundry

Abstract
“Micro- and nano-electronics, including semiconductors, are essential for all goods and services which need intelligent control in sectors as diverse as automotive and transportation, aeronautics and space. Smart industrial control systems permit more efficient management of electricity generation, storage, transport and consumption through intelligent electrical grids and devices” states the communication from the European Commission about the importance of the Key Enabling Technologies for society and economy. We, at LFoundry, develop the technologies that are behind the development of the industries of interest for Europe, for the new frontier of the Digital Economy and some of the niches, like the Big Science, that can show a dramatic downstream in important sectors for the society, like the medical applications. Having the right set of skills and competencies is the pre-requisite to participate successfully in the development of the economy for our future in Europe and for the role that Europe will play in the world. In the speech we will talk about this tool set and how skills and soft competencies are both necessary to drive and adapt for a future which development must be built by ourselves, imaging the vision we’d like.

Biography
Fabrizio Famà earned his degree in Physics from the University of Pisa (Italy), on 1990. After spending several years on technical fields, for a stainless steel company and then in the semiconductor business (Texas Instruments and Micron Technology), on 2004 he joined the HR team leveraging on personal interests we was developing over the years. On 2008 he started-up the General Affairs team in Italy, aimed to manage the funding projects and the relation with the institutions. He has been involved on the integration in Italy of Numonyx after the acquisition by Micron. He has been assigned as HR Manager of the sites of Catania and Naples. After the spin-off of Avezzano’s site from Micron on 2013, he joined the management team buy-out in joint venture with LFoundry. On 2014 he has been appointed as member of the board of the new LFoundry, till 2016, when SMIC bought the majority of the shares. Fabrizio is member of the board of the European Semiconductor Industry Association (ESIA) since 2011.

Reaching next level of semiconductor manufacturing productivity in a digitalizing world

Burkacky, Ondrej
Partner
McKinsey & Company

Abstract
- Advanced analytics and artificial intelligence methods make their way into more and more manufacturing environment - Semiconductor manufacturing with its large available datapool is best predestined to benefit at scale - In this briefing update I will give an overview on the most promising use cases and key lessons learned from various implementations

Biography
- Based in McKinsey & Company's Munich office since 2007 - He is part of Digital McKinsey - He leads McKinsey's Embedded Software initiative and Software Service Line in Europe - He is also a member of the Advanced Industries Practice, specifically automotive and semiconductor industry with focus on product development

Agile performance transformation in semiconductor and beyond

Knochenhauer, Christian
Junior Partner
McKinsey & Company

Abstract
The semiconductor industry has always been one of the most innovative industries, driven by super compressed roadmaps and endless customer demand for new products and technologies. On the other hand, due to the maturing industry, and the increasing complexity of players, many organizations have by now become large, increasingly inflexible and sometimes slow. Agility today is the main theme of creating and transforming businesses, and therefore most organizational transformations. While agility is very natural in startup, business building, or digital environments, it is much less obvious to implement in large, complex operations like semiconductor manufacturing. However, a successful agile transformations can enable a sustainable performance and health improvement of the organizations. In this talk, we present our perspective on agile performance transformations. We believe that successful transformations need to combine a stable core of traditional processes with agile elements in selected core areas that are crucial to driving performance. Based on selected examples from successful agile transformation within and outside the semiconductor industry, we outline the key principles and success factors. We conclude with an outlook on further optimization potential and methods.

Biography
Christian Knochenhauer is an Junior Partner in McKinsey's Advanced Industries practice. He focuses on semiconductor and electronics industries, serving clients from the entire value chain, in particular on transformation and strategy topics. He has been co-authoring several of McKinsey's articles on the Internet of Things and the semiconductor industry. Christian holds a Dr.-Ing. degree in RF analog circuit design for optical communications technology, authoring several publications in major IEEE journals and a patent on high-speed integrated circuits for 40Gbit/s optical communications. He studied Electrical Engineering at TU Dresden and General Engineering at Ecole Centrale Paris.

Innovations in photoresists and photopolymers for 2D / 3D micro and nano fabrication

Voigt, Anja
Business Unit Manager Photoresists
micro resist technology GmbH

Abstract
Different methods for the manufacture of high resolution 2D and 3D features require a wide range of material solutions based on innovative photoresists and photopolymers. As a commercial resist supplier, micro resist technology aims at providing such solutions tailored for diverse lithography processes, comprising both materials and technology support. The following highlights will be presented: E-beam lithography is a versatile patterning method for the generation of high resolution nano-patterns. Combining stepwise greyscale exposure and pattern reflow with a positive tone resist results in greyscale patterns of small dimensions. Greyscale UV lithography of up to 100 micron thick resist films, either by direct laser writing or by conventional mask aligner exposure and a greyscale mask, can generate very deep greyscale micro-patterns. Both very thick films, and considerably smaller pattern features including sharp tips have been successfully fabricated using this technique. Laser interference lithography is another method which allows the manufacture of nanoscale and periodic patterns even on very large substrates. Whereas two photon absorption (2PA) allows the generation of real 3D patterns at micro and nanoscale. The development of photoresist and photopolymer materials tailored to meet the requirements of the specific technologies will be presented.

Biography
Anja Voigt received her diploma in 1993 and her PhD in 1998 in Photochemisty at the Humboldt-Universität zu Berlin. Since 1993 she has been a scientific co-worker with micro resist technology GmbH and responsible for R&D and production of negative photoresists. She has been the product manager for negative photoresists since 2005, and the business unit manager for photo resists at micro resist technology GmbH since 2012.

How New Macro Defect Inspection Technologies Are Becoming Essential to Increasing Yield and Reducing Wafer Fab’s Costs

LaTorraca, Mike
Chief Marketing Officer
Microtronic, Inc.

Abstract
As semiconductors and intelligent devices are adopted into all areas of modern society it’s critical that the inspection processes in manufacturing fabs keep pace. Traditionally, semiconductor wafer manufacturers rely on sampling - at both the die and wafer level. Although sampling speeds up the inspection process, there is obvious risk of missing defective wafers due to sampling. While fabs will probably always rely on sampling to some extent, there are now new macro defect inspection applications that can be added to the wafer production environment to deliver dramatic improvements in many areas. These areas include: recipe-less defect detection; reduction of manual inspection costs; root cause analysis; shipping die with latent defects, excursion control, customer returns, and comprehensive automotive zero-defect strategy enablement. This presentation focuses on why automated macro defect inspection is becoming essential to fabs as they are challenged to improve their quality in the already highly demanding semiconductor manufacturing environment. Exploding markets such as automotive and mobile devices make it necessary for fabs to provide better quality at lower costs. For example, detection of macro defects in-line, prior to final inspection, allows manufacturers to take corrective action at an earlier, less expensive point in time to address any defective die and to prevent die with a high probability of carrying reliability defects, from entering customer products – including automotive devices. Additionally, automated macro defect inspection is ultra-fast and can inspect 3,000 wpd while delivering an actual high-resolution full-wafer color image. The macro defect inspection approach creates a complete, trackable “waferbase” with defect lists and defect maps along with each wafer’s OCR number, image and slot position to help identify production problems fast and take corrective action quicker.

Biography
Mike LaTorraca is the Chief Marketing Officer of Microtronic, Inc., the US-based manufacturer of EagleView - the semiconductor industry's most yield enhancing macro defect inspection system and winner of the 2017 Semicon West Best of West new product of the year award.

Multicomponent Assembly on Flexible Material in Reel-to-Reel Process

Niklas, Gerald
Business Development
Mühlbauer GmbH & Co. KG

Abstract
Mühlbauer introduces a complete solution for the Reel-to-Reel production of multicomponent products on flexible substrate in the area of LED, active RFID, sensor labels etc. The solution consists of systems that are capable of high-volume manufacturing processes. The upstream production process comprises the production of a flexible circuit, whereas the subsequent process attaches different components to the substrate which is the electronic portion of the final product. The flexible substrate production technology is a completely new development. Starting with the attachment of LEDs, the process was continuously extended to a multicomponent process. Further progress was achieved in the component attach and curing technologies according to different end applications and the substrate material selection between aluminum and copper for flexible substrate production in relation to their respective areas of use. For example, with Mühlbauer’s Reel-to-Reel RFID Antenna Production machine ACS 20000, the low cost materials PET and aluminum can easily be transformed into aluminum antennas on PET. After the launch of the flexible LED production line TAL 15000_LED in 2015, Mühlbauer further developed the assembly process towards a universal system: the Multicomponent Line. Besides the standard jetting of adhesives, the dispensing of ICPs and solder paste is now also possible. As a result, new curing requirements like the integration of an inline reflow oven, were developed. Furthermore, the component attachment has been simplified and enlarged so that now, a high variety of components can be attached: SMD, sensors, capacitors or even Flip Chips and other electrical components, which meet any future trend in flexible electronics.

Biography
Gerald Niklas is active in the Business Development for Semiconductor Related Products at Mühlbauer GmbH & Co. KG. Mr. Niklas has been with the company for more than thirty years and has been deeply involved in the development & implementation of products in the areas RFID, Flexible Solar, as well as Multicomponent Applications like LED-based Flex production solutions. With his international experience & engineering background, he built a worldwide network of industry related companies, and is globally active for the Mühlbauer Group.

Printing high aspect ratio narrow silver lines using nanoparticles

Zhang, Zhiyi
Senior Research Officer
National Research Council Canada

Abstract
In printable electronic device, narrow metal lines with low electrical resistance are essential. Commercial gravure, flexography or inkjet systems on the market can produce 30-100 µm wide lines by properly choosing the ink and substrate, this feature size is still about one order of magnitude larger than what is required in many electronic device applications. Other R&D printing technologies like high throughput gravure, reverse-offset printing, and electrohydrodynamic jet printing can achieve a linewidth of 1-5 µm at the expense of line thickness, which is normally characterized by a very low thickness-to-width aspect ratio, often far less than 0.05. Currently, it is very challenging to print narrow metal lines with high thickness-to-width aspect ratio and thus low resistance. In this work, we report a method of obtaining 4.6 µm wide printed silver lines with an elliptical cross-section and an aspect ratio of 0.7. The silver lines were obtained by jetting a silver nanoparticle-based ink onto an SU-8-coated PET substrate to form well-defined silver lines, and then heating the lines to transform them into high aspect ratio narrow lines through ink dewetting and receding. The simultaneous dissolution and redistribution of SU-8 by the ink results in a concave structure, which prevents the lines from bulging and allows the lines to sink into the SU-8 film. The sheet resistance of the obtained 4.6 µm lines was measured to be 0.05 ohm/□, and using special pattern designs, the method can also be used to get 0.5 µm wide silver lines, with an aspect ratio of 1.0. The obtained wires are suitable for printing high-performance electrical devices.

Biography
Dr. Zhiyi Frank Zhang received his Ph.D. in polymer chemistry from Zhongshan University. He worked with universities and companies before joining National Research Council Canada. His previous research included polymers and polymer composites, sol-gel, polymer-gas systems, photonic components and packaging, biomicrofluidics, sensors. In recent 6 years, he is working on printable electronics with a focus on materials, process, sensors and electronic devices.

Fuelling the AI Revolution with Gaming

Lowndes, Alison B
AL DevRel | EMEA
NVIDIA

Abstract
Artificial Intelligence is impacting all areas of society, from healthcare and transportation to smart cities and energy. AI won’t be an industry, it will be part of every industry. NVIDIA invests both in internal research and platform development to enable its diverse customer base, across gaming, VR, AR, AI, robotics, graphics, rendering, visualisation, HPC, healthcare & more. Alison’s talk will introduce the hardware and software platform at the heart of this Intelligent Industrial Revolution: NVIDIA GPU Computing. She’ll provide insights into how academia, enterprise and startups are applying AI, as well as offer a glimpse into state-of-the-art research from world-wide labs & internally at NVIDIA, demoing, for example, the combination of robotics with VR and AI in an end-to-end simulator to train intelligent machines. Beginners might like to try our free online 40-minute class using GPU’s in the cloud: www.nvidia.com/dli

Biography
Artificial Intelligence DevRel | EMEA After spending her first year with NVIDIA as a Deep Learning Solutions Architect, Alison is now responsible for NVIDIA's Artificial Intelligence Developer Relations in the EMEA region. She is a mature graduate in Artificial Intelligence combining technical and theoretical computer science with a physics background & over 20 years of experience in international project management, entrepreneurial activities and the internet. She consults on a wide range of AI applications, including planetary defence with NASA, ESA & the SETI Institute and continues to manage the community of AI & Machine Learning researchers around the world, remaining knowledgeable in state of the art across all areas of research. She also travels, advises on & teaches NVIDIA’s GPU Computing platform, around the globe. Twitter: @AlisonBLowndes.

Two side molded WLCSP

Kamphuis, Tonny
Assembly Industrialization Manager
NXP

Abstract
Increasingly WLCSP are used as solution for packaging, especially when the area needed for I/O matches the area needed for the function. Industry trend is to go thinner devices and smaller pitches. The mechanical integrity of WLCSP’s is stressed not only in the application, but also during board assembly at the customer. The breakthrough technology presented provides protection for both the top and bottom of the product, thus protecting the 8 corners of the device during handling at manufacturing and customer. Different material sets and molding technologies for encapsulation of the WLCSP were investigated, each with their own merits. The challenges experienced to create the two side encapsulated concept and way forward to overcome them will be shared. First results on Board Level Reliability will be shared. The encapsulation concept to achieve full encapsulation is demonstrated at supplier site and the building blocks towards a true industrial solution is shared. Balancing the front and back side thickness of the compound enables reduction of the overall height while at the same time improve the BLR performance compared to more well-known 5 side protected WLCSP in the same package thickness.

Biography
Tonny Kamphuis received his master in Mechanical Engineering at Twente University in 1986. The same year he joined Philips Semiconductors in the field of IC assembly equipment. He worked in Kaohsiung Taiwan from 1991 to 1992, after which he joined the discrete assembly equipment development department in Nijmegen. He has developed die bonders, wire bonders, molding machines as well as all type of handling equipment for both reel to reel and strip to strip based industrializations. Since the year 2000 he is focusing on assembly process development and industrialization for IC again. In 2007 NXP was founded, at NXP, he has filed several patents related to wafer processing, package concepts and process improvements.

Revolution of Automotive Architectures through IT and Network Infrastructure Concepts

Singer, Stefan
Fellow & Director, EMEA CAS Automotive
NXP

Abstract
The Automotive Industry is seeing more dramatic changes in the next few years than in previous decades combined. Vehicles are becoming always connected and part of the internet. Drive trains evolve from combustion engines to mixtures of hybrid and electric vehicles with new challenges (e.g. for reach). Most dramatic is the change to more and more assisted driving up to future level 3-5 automated vehicles. All of those factors result in the development, that existing E/E architectures are not capable of supporting those requirements. Instead of small evolutionary changes some more dramatic departure is required. While the new functions demand new solutions, many of the existing functions in a vehicle (e.g. body comfort functions, …) do not require new features and therefore a new architecture, that allows the reuse of many legacy ECUs without changes can have a huge economic benefit. The presentation will show how concepts from IT and Network Infrastructure Solutions can be brought into Automotive while taking automotive specific requirements (e.g. startup times, thermal management) into consideration. The presentation will touch on several of the attributes and consequences, e.g. of different functions into one box (Virtualization, Isolation, Validation) and Communication schemes for such an architecture. Additionally we need to consider, that cars are an attractive Target for Hackers. In highly networked cars we need to be concerned about protecting privacy, increasing safety and preventing unauthorized access. Connected vehicles create a multi dimensional challenge to address vehicle safety (Zero accidents by human error), security (Zero accidents by system hacks), functional safety and also device reliability. Another topic is, that such a new architecture requires rethinking of conventional wisdom for functional safety.

Biography
Stefan Singer is a Technical Fellow at NXP Semiconductors in Munich, Germany. He leads the European Automotive Field Applications Team and has held a number of positions at Motorola Semiconductor, Freescale and NXP in the US and Germany. Stefan holds a Dipl.-Ing. degree from the Technical University in Munich. Due to his personal background in communication, networking and Automotive he has passion for automotive networking architectures (especially Ethernet) and Computing.

Semiconductors for the Connected World - Safe, Secure and Smart

Sievers, Kurt
Executive VP and General Manager of the Automotive business, NXP Semiconductors & chairman of electronica board
NXP Semiconductors

Abstract
The Internet of Things is transforming our personal lives – and the semiconductor industry. As everything gets connected, new levels of security are required to prevent manipulations and attacks. Next to security, Artificial Intelligence is a key ingredient for realizing this transformation. On the market side, several of the traditional growth drivers of the past years, such as PCs, Smartphones, and Tablets, have slowed down, ensuing a wave of industry consolidation. Automotive remains a highly attractive market, as increasing autonomy, electrification, and connectivity will result in tripling the semiconductor content per car. Kurt Sievers’ keynote speech will address the technological requirements, challenges, and opportunities on this route, while providing insights into the IoT, Automotive, and Cybersecurity markets.

Biography
Kurt Sievers is executive vice president and general manager of the Automotive Division of NXP Semiconductors, the world’s largest semiconductor supplier for the automotive industry and a leader in cybersecurity solutions. He is also managing director at NXP Germany GmbH. After getting his master’s degree in physics and Information Technology, Kurt Sievers began his career in 1995 at Philips Semiconductors in product marketing, later he became general manager of the car radio business. After the founding of NXP in 2006, he was responsible for strategy and business development in the Automotive & Secure Identification business. Since 2009, Kurt Sievers has headed the worldwide automotive business of NXP and has served as a member of NXP’s board of management. Kurt Sievers also serves as a member of the Executive Board of the Central Association of the German Electrical Engineering and Electronics Industry (ZVEI). He heads up the advisory board of the Messe electronica and, as member of the supervisory boards of Aeneas and Penta, he is playing a key role in shaping European private-public R&D programs in the field of microelectronics.

Advanced substrates for MEMS and photonic applications

Lempinen, Vesa-Pekka
Senior Manager, Customer Support
Okmetic Oy

Abstract
Requirements for lower cost and higher volumes are driving towards miniaturization of MEMS and photonic devices. Requirements for reliability and performance improvements on the other hand drive for improvements in precision of BSOI materials, and use of hermetically sealed structures enabled by Cavity SOI (C-SOI) wafers or wafer level packaging. Following examples of advanced substrate-based solutions are shown and discussed: • Use of thick SOI or C-SOI for manufacturing released MEMS structures. Comparison of different SOI substrates from process integration and manufacturing complexity point of view. Benefits of SOI and C-SOI based approach for flatness and dimensional precision of the released structures. • Combination of C-SOI based MEMS and wafer level packaging by patterned capping wafers with poly Si TSVs. Properties of advanced C-SOI and TSV substrates. • C-SOI based approach for high performance inertial sensors, with benefits in process integration, reliability and performance optimization. • Thick SOI based optical waveguides using E-SOI substrates for maximum efficiency. Okmetic’s new turnkey solution of providing full C-SOI process flow, from silicon crystal growth to cavity patterning and SOI wafer manufacturing, from one source is introduced. Fully in-house C-SOI processing allows an industrial-scale solution to C-SOI manufacturing, and enables the sensor manufacturers to focus on their core competencies in the directly sensing-related parts of the manufacturing process. Integrating the reliability-critical fusion bonding part of the MEMS process as a part of starting wafer manufacturing enables also streamlining of the manufacturing process flow, simplified process integration, and improved long- term reliability of the MEMS devices. In-house crystal growth and substrate wafer manufacturing enable full customization of material properties, such as Si layer resistivity and orientation, of each layer of the C-SOI structure.

Biography
Mr. Lempinen received his M.Sc. in Materials Physics from Helsinki University of Technology in 1999. Mr. Lempinen has over 15 years of experience in Silicon based material engineering. He has worked for Okmetic since 2000 and held various positions related to R&D, process engineering and applications support. Currently he is working as Senior Manager, Customer Support being responsible for the company’s global technical customer support organization. Prior to his time at Okmetic, Lempinen was involved in photovoltaic research in Electron Physics laboratory of Helsinki University of Technology, Finland and Microelectronics Research Center of Iowa state University, U.S.A.

Design of a 10kW Three Phase PFC with Silicon Carbide

Paglia, Massimo
Application Engineer
ON Semiconductor gmbh

Abstract
A typical On Board battery Charger application for electric vehicles consists of a power factor correction stage (PFC) and a DCDC converter stage, both require the highest efficiency possible in order to deliver as much power as possible to the battery pack. Focus of this work is the 3 phase 10 kW PFC based on Silicon Carbide Mosfet which regulates the output voltage to 700V starting from a nominal input voltage of 230Vrms at 50Hz. Three parameters measure the performances of the system: total harmonic distortion, power factor and efficiency. Ideally they should be zero, one and 100% respectively. The configuration selected is typically known as inverter, made by 3 half bridges with each central point connected to a dedicated boost inductor, and each high side drain and low side source connected to the bus capacitor. 1200V SiC MOS 80m devices were used together with the recently released ON Semiconductor dedicated SiC gate driver, NCV51705. A digital control has been adopted by means of a mid-range microcontroller. The implemented strategy is based on a field oriented control approach where the rotating DQ domain has been selected aligning the D axes with the input voltage space vector. The selected HW together with the digital implementation represents a bidirectional system, therefore power can flow either ways by modification of the D axis reference current sign. The control strategy works on an interrupt running at 20 kHz using one ADC, 12 bits 1Mbs and one sample and hold. PWM frequency set to 70kHz. Experimental results demonstrate that the PFC was able to achieve as high as 98.7% at 6.6kW with a consistent efficiency above 98% at higher power output. THD was well below 5% from 3kW onwards and PF is above 0.99 from 4kW. All evaluated at nominal input voltage, 230Vrms.

Biography
Massimo Paglia received his B.Sc and M.Sc degree in Electrical Engineering from University of L'Aquila in 2004 and 2008 respectively. From 2009 to 2014 he was with the R&D team at Whirlpool Europe where he worked on the development of 3 phase motor control algorithms. In 2014 he joined ON Semiconductor as part of the Solution Engineering Center supporting the European Sales & Marketing group. His actual assignment is development of smart algorithms for three phase systems in power applications.

Sharing Data for reliable Automotive industry: A win-win between Semis, Tier1s & OEMs

Glotter, Dan
Founder & CEO
Optimal+

Abstract
In recent years almost 90% of innovations in cars are based on electronics. Radar, Lidar, Sensors, Cameras, Dashboards, Driver assist systems and so on, have turned the car into the world’s most complex mobile computer system. Last year Audi stated that they are “seeing 24 cars roll off the assembly line and fail test at zero KM, due to electronics component failure”. Because of this, companies like Audi are demanding quality levels measured in Defective Parts Per Billion, or in some cases, they are simply counting “incidents”. According to NHTSA 2016 Recall Data, in the last 4 years there is an increase of 3X in Electronics related recalls. In 2016 BMW claimed that 22% of their warranty cost are related to the electronics < b >And the situation is only going to get worse.</b> In phase 2&3 of the autonomous cars , there is going to be even more < b >mission critical electronics</b> going into cars. The cars themselves will be on the road much longer due to a shift to car sharing. Meaning that reliability problems will manifest themselves faster. That is why data of billions of electronic components need to be analyzed to see what might go wrong - and not just report it but prevent bad products from reaching the market. And yet, the same time, we also help them significantly increase their efficiency, reduce costs, and get to market faster - That is all about lifecycle analytics for reliable electronics. Thus, data from across the supply-chain needs to be assembled and thoughtfully shared without compromising IP of each party… data from Chip manufacture, board assembly, ECUs, systems and end-products, and also collect and analyse product return data. (RMA’s) Once the product lifecycle data is available we can start sharing data through a trusted 3rd party. I will give an example how we helped a Tier-1 manage the incoming material AND manage its own quality for higher yields & better qualities - < b >The outcome was a Win-Win</b>.

Biography
Dan founded Optimal+ (formerly named OptimalTest) in 2005 and was among the pioneers of Big Data Analytics for the Semiconductor industry and lately for the Electronics industry as well. Before founding the company, Dan held various senior positions in semiconductor and test operations at Intel from 1994 to 2004.During his tenure at Intel, Dan has received the Intel Achievement Award and the Intel Quality Award. Dan holds a BS in Engineering from the Technion and an MBA in Finance from Bar-Ilan University.

Advancing Atomic Layer Deposition and Atomic Layer Etching

Knoops, Harm
Atomic Scale Segment Specialist
Oxford Instruments Plasma Technology

Abstract
Atomic scale processes such as atomic layer deposition (ALD) and atomic layer etching (ALE) are increasing in popularity with more and more applications requiring or benefitting from atomic level control. ALD and ALE provide the control they do because they are based on self-limiting surface processes. This contribution will discuss the basics for both techniques and discuss how they can be further advanced. For ALD two trends will be discussed: i) controlling the ion energy in plasma ALD to tune material properties. Generally processes are optimized to have minimal ion energies to avoid potential damage. Interestingly, for these low damage plasma sources, the ion energy can be increased by substrate biasing providing additional knobs for tuning film properties. Key examples are stress-control of oxides such as achieving near-zero stress in TiO₂ and reduction of the resistivity of conductive nitrides (e.g. for TiN, HfN_x, and NbN). ii) Usage of novel plasma gases. For instance H₂S plasma gas mixtures have been shown to allow growth of 2D-MoS₂ at low temperatures and SF₆ plasma was found to allow ALD of AlF₃, which could be of interest as an optical coating or for batteries. For ALE the basics will be discussed and how these can be used for applications. More and more processes are being developed (e.g. ALE of GaN, AlGaN, Si, SiO₂ & 2D materials). Interestingly besides the exact control of etch depth, other aspects of ALE might turn out to be more important for certain applications. For instance ALE of AlGaN was found to reduce the surface roughness, while generally plasma etching would increase the surface roughness somewhat. Other advances for both ALD and ALE are expected to be in the form of combinations with other techniques. Therefore clustering of ALD and ALE tools with 2D materials growth can allow precise control of interfaces and allow avenues into selective growth, surface cleaning and etching.

Biography
Dr.ir. Harm Knoops is an Atomic Scale Segment Specialist for Oxford Instruments Plasma Technology (OIPT) and holds a part-time assistant professorship position at the Eindhoven University of Technology. His work covers the fields of (plasma-based) synthesis of thin films, advanced diagnostics and understanding and developing plasma ALD and similar techniques. His main goals are to improve and advance ALD processes and applications for Oxford Instruments and its customers. He has authored and co-authored more than 40 technical papers in peer-reviewed journals.

Plasma etch and deposition solutions for SiC and GaN devices

Dineen, Mark
Technical Marketing Manager
Oxford Instruments Plasma Technology

Abstract
Silicon Carbide (SiC) and Gallium Nitride (GaN) are becoming increasingly important materials for RF and Power devices.Find out how plasma process solutions are used to enable these devices and maximise their performance.

Biography
Dr Mark Dineen graduated from Cardiff University with a PhD on ‘Plasma etching of Gallium Nitride’ and joined Oxford Instruments in 2000. Firstly as a Process Engineer working on etching of III-V materials, then moving into Product Management and more recently marketing Mark has a wealth of experience related to Compound Semiconductor device processing.

Liquid system component cleanliness testing at 20 nanometres

Green, David
Applications Engineer
Particle Measuring Systems

Abstract
Fluid handling components such as valves, pumps, filters and degassing modules are common sources of contamination in high purity liquid distribution systems. This contamination can eventually reach the processing environment either in the form of solid particulates or, through chemical reactions, as a form of ionic contamination. Due to the significant cost associated with yield impacts, it is of vital importance to ensure that fluid handling components are sufficiently clean before they are used in the production environment. A simple testing program has been established that uses an optical particle counter to characterize the initial and long-term cleanliness of critical fluid handling components for particle sizes down to 20 nanometres. The testing program allows the relative cleanliness of components constructed out of different materials and from different manufacturers to be evaluated. This can save both time and money in the production environment by ensuring that the best components are selected for the designated task.

Biography
David Green graduated from University College London in 2002 with a bachelors degree in Physics. David has spent most of his career designing, building and testing novel particle analysis equipment. Since 2013 David has represented Particle Measuring Systems across the EMEA region as an Application Engineer.

Scaling up to big data volumes

Suerich, Doug
Product Evangelist
PEER Group

Abstract
The market is demanding faster throughput, smaller feature sizes, and higher quality. The fuel that drives these improvements is data – from more sensors, faster sampling, and greater integration of different sources. Collecting larger data volumes allows for deeper insight into critical process and production metrics, as well as the possibility of using advanced analytics and machine learning to speed defect analysis and reduce repair times. However, this explosion of big data can overwhelm traditional data sharing and storage mechanisms. Join us as we discuss cutting edge approaches to managing your data including new storage solutions, best practices for where your data should live, and methods for sharing that data with your analysis systems and global experts.

Biography
Doug Suerich is Product Evangelist at The PEER Group Inc., the semiconductor industry’s leading supplier of factory automation software for Smart Manufacturing and Industry 4.0. Doug focuses on big data and remote connectivity solutions that help manufacturers collaborate securely on tools and data in production environments. A passionate advocate for Smart Manufacturing, Doug serves as an active member of the SEMI® Smart Manufacturing Advisory Council and Smart Manufacturing SIG, Americas Chapter. Doug has over 20 years of experience leading software teams for a variety of industries including semiconductor, manufacturing, and transportation. Most recently, he was involved in architecting PEER Group’s remote connectivity solution, Remicus™, and he was a champion in promoting the use of cloud computing and latest-generation web technologies.

Arnold, Michael
Managing Director
PEER Group GmbH

Biography
Dr. Michael Arnold, Managing Director, has been responsible for PEER Group´s European operations since 2003. He established a strong services position in the global semiconductor manufacturing market. Michael is the account manager for several of PEER Group’s top customers in Europe. He has served as a member of the SEMICON Europe technical program committee since 2009 and currently chairs the European chapter of the SEMI Smart Manufacturing Technology Community. In 2017, Silicon Saxony appointed Michael as a Board Member. Prior to joining PEER Group, Michael was the operations manager of TRW’s European Manufacturing Solution Business Unit in Dresden, Germany, where he was also responsible for service delivery. Before this he worked for a variety of companies, developing software solutions and implementing industrial vision systems and factory automation solutions for European productions sites. Michael holds a Diploma degree in Physics and a Ph.D. from the Friedrich-Schiller University Jena.

Innovation needs People Power

van der Burg, Glenn
Founder
People Power

Abstract
What can make a real difference between you and your competitor? Cutting edge technology? A strong brand? Cost efficiency? Especially in this era of super fast tech development, the one thing that we need to thrive is People Power. Innovation, creativity, customer intimacy, they all rely on engaged people that cooperate to be better everyday. Probably nothing new, but why is it so hard to create a workplace that is bursting with energy? In this talk, Glenn van der Burg will take you on a trip into the drivers for human behavior. What motivates us to be the best version of ourselves? What's happening to people in meetings? What sparks people's creativity? And what takes away all the energy? With insights from science, examples of innovative organisations and actions to start innovating your workplace tomorrow. And at least one guaranteed laugh!

Biography
As founder of People Power, Glenn van der Burg is striving for people-centric organizations for better performance and happy people. He facilitates groups of leaders and professionals that want to make a leap forward in making their organization people centric. Every monday Glenn hosts his radioprogram "People Power" with experts and best practices in people-centric organizations. And he is the author of two management books. His favourite quote is by prof. Gary Hamel: “You can not build an organization fit for the future if it is not fit for human beings."

Moore for Medical

Dekker, Ronald
Research
Philips Research

Abstract
Gradually electronic devices are finding their way towards the human body. Body patches are being designed that provide continuous monitoring. Intelligent catheters assist during minimal invasive surgery, and tiny implants stimulate nerves with the aim to replace traditional medicines. Despite their apparent potential progress is however slow, certainly compared to the non-medical electronic industry. One of the reasons is the lack of scalable open technology platforms. In this presentation a selection of promising emerging in- and on-body electronic will be reviewed. Large European consortia supported by ECSEL and PENTA, are developing and implementing not only the essential open technology platforms, but also the necessary manufacturing infrastructure. The recently established Health.E lighthouse will further promote the open technology platform concept for medical devices to realize the “Moore for Medical” vision.

Biography
Ronald Dekker received his MSc in Electrical Engineering from the Technical University of Eindhoven and his PhD from the Technical University of Delft. He joined Philips Research in 1988 where he worked on the development of RF technologies for mobile communication. Since 2000 his focus shifted to the integration of complex electronic sensor functionality on the tip of the smallest minimal invasive instruments such as catheters and guide-wires. In 2007 he was appointed part time professor at the Technical University of Delft with a focus on minimally invasive devices and Organ-on-Chip. He published in leading Journals and conferences and holds in excess of 60 patents.

MEMS and Semiconductor Applications for Wafers from Glass and Quarz

Seibert, Christian
Account Manager, Sales
Plan Optik AG

Abstract
Microelectromechanical systems (MEMS) and Sensors provide the magic that makes today’s devices from our everyday life smart. MEMS consist of tiny mechanical and electrical devices such as membranes, mirrors and valves, as well as sensors, actuators and integrated circuits. Without MEMS or sensors, we would not have smartphones, smart homes and wearable smart watches, as well as a huge range of industrial and medical devices that require the functionality provided by MEMS and sensors. This presentation will show different possibilities of using glass in MEMS and Semiconductor Industry, for example as glass carrier wafers, that enable handling and processing of ultra-thin semiconductor wafers that are needed to manufacture chips for smartphones and electronics. Furthermore the use of glass wafers and dies in applications such as automotive lighting and sensing using wafer level packaging (WLP) technology will be shown as well as sneak peak into glass microfluidics and special applications for Silicon/glass compound wafers.

Biography
Christian Seibert is Sales Account Manager for Plan Optik AG, leading manufacturer for high quality wafers from glass, quartz and glass-Silicon. At Plan Optik AG Christian is responsible for customers in US and Canada, helping them to find best wafer solutions and exceed requirements for their MEMS applications and Semiconductor processes. Additionally he is working on product development for Plan Optiks’ stock products and OTS (off the shelf) wafers as well as technical documentation. Previous to this position Christian graduated as M. Eng. in Technical Sales from a dual study in cooperation between THM (Technische Hochschule Mittelhessen) and Plan Optik AG, working in Sales Department on establishing analysis and controlling of Sales. Prior to that Christian finished his first dual study as B. Eng in Electrical Engineering in cooperation between THM and LTI Motion GmbH, provider of high dynamic and precision automation and drive solutions, working on various projects in departments such as application engineering, project- and product management and R&D.

Predictive maintenance for plasma tools

Klick, Michael
CEO
Plasmetrex GmbH

Abstract
Plasma processes are widely used in the semiconductor industry, they are completely distinct from mechanical manufacturing. Plasma processes are running in vacuum chambers and there are opened every month or quarter for maintenance. Each maintenance measure at a production chamber causes costs in the order of some 10 k€. Therefore, the prediction of the right time for maintenance can reduce manufacturing costs dramatically. On the other hand, plasma processes are usually treated as black box due to their complexity. All important process parameter as uniformity, rate, selectivity, and stability depend of the plasma’s parameters as flux of ions and reactive species. Thus, the main peculiarity of plasma processes can be compressed is one sentence: ‘The plasma is the tool’. Beyond this we have to take into account that plasmas can run in different modes, can oscillate, cause breakdowns at the chamber wall and depend on the state of the chamber wall. In particular the chamber wall changes its surface properties by the deposition of byproducts. So the only realistic approach for the predictive maintenance for plasma tools must be based on the plasma’s properties. It will be shown how plasma parameter can describe plasma and so also the effective chamber state, chamber differences and show undesired instabilities as arcing and wear of chamber parts. The early detection of changes and undesired effects are here the key for predictive maintenance. Examples show the early detection of process faults, real-time process characterization, and preconditions and methods for chamber matching.

Biography
Objective: CEO, Plasmetrex GmbH Education: Ph.D. in Plasma Physics, Ernst-Moritz-Arndt-University Greifswald, 1992 Dipl.-Ing., Technology of Electronic Devices, 1987 Grants and Fellowships: Lecturer at Ruhr University Bochum since 2010: Plasma technology for semiconductor, MEMS, and PV applications Research and manufacturing skills: Plasma etch process development Nonlinear Modeling of industrial RF Plasmas Development of Plasma Sensor Systems for Etch and Deposition 20 years experience in joined projects with semiconductor fabs

Establishing smart plasma process control in production lines

Schütte, Thomas
President / CEO
PLASUS GmbH

Abstract
While metrology tools are getting more advanced and providing plenty of valuable data of process and product, there is still a lack in evaluating and combining these information for an integral process analysis and real-time control. In plasma processing optical emission spectroscopy is well known and often established as a process monitor by observing a single emission line e.g. to detect an endpoint or to survey the process stability. However, using the spectroscopic plasma monitoring technique all acquired spectroscopic data is evaluated simultaneously and in real-time and thus, provides a more comprehensive insight in the plasma chemistry, the composition of the plasma and its temporal evolution. Combing the spectroscopic plasma monitoring data with other real-time plasma metrology data will complete the picture of the plasma process. In order to scope with the more complex and advanced processes for next generation products it is essential to interconnect the metrology tools and its data and data analysis as it is addressed by IoT or Industry 4.0. In an example from solar cell production the benefits of the advanced spectroscopic plasma monitoring technique are illustrated and the advantages of combining metrology tools are outlined.

Biography
Dr.-Ing. Thomas Schütte studied Electrical Engineering at the Technical University Munich and the University of Southern California in Los Angeles and received his Diploma and MSEE, respectively. During his PhD at the University Stuttgart he specialized in plasma physics and plasma spectroscopy and in 1996 he established the company PLASUS where he acts as CEO and technical director of PLASUS GmbH now. He was and still is dedicated to develop and realize plasma monitor and process control systems for production lines for all types of plasma applications.

Internet of things and smart mobility

Donoval, Martin
Director of R&D projects
POWERTEC ltd.

Abstract
Internet of Things (IoT) is the internetworking of physical devices, vehicles, buildings and other items embedded with electronics, software, sensors, actuators and network connectivity that enables these objects to collect and exchange data. IoT represents the next step towards the digitization of the society and economy, where objects can be interconnected through simply attachable and low power consumption communication networks and report about their surrounding environment. Mobility is a strong domain of industry with potential to employ IoT solutions in huge extent with many possible use cases. Development of IoT systems oriented towards smart mobility is therefore a big and challenging field. Network of IoT systems is based on low power consumption and long lifecycle of the products as the purposes of use can require years of operation in e.g. hermetically sealed casing. In specific cases, an intercommunication of IoT nodes is required. Design, development and production of such systems requires experience and specific skills in different areas, as are the power management, communication, self-test, antennas, casing and others. Among different IoT systems there are many subgroups of mobility sensing elements – static or dynamic, with individual connection to network or mesh connection, oriented towards monitoring of traffic, parking, position of carrier etc. The speech will be devoted to different attitudes to electrical design of static sensors and dynamic sensors based on example of comparison of static parking occupancy sensor for ground integration with at least over 5 years functionality and an hobby unnamed aerial vehicle (UAV) monitoring in 3D and intercommunication of the aerial vehicles.

Biography
Martin Donoval is experienced in area of electronic circuits and application level. Besides development of electronic devices for IoT applications and integration of devices into smart-systems he is responsible for R&D projects management in a field of microelectronics applications - bio-electronic smart-systems, mobility systems and other end user electronics. He participates in implementation and testing of new prototypes and dedicated electronics and prepares new testing routines. He finished his master and PhD theses at Slovak university of technology in Bratislava, Slovakia. He participates at the education process at STUBA.

Quality Assurance in High-End Semiconductor Production

Holzapfel, Mathias
Business Development Manager Semiconductors
Precitec Optronik

Abstract
PRECITEC is worldwide the preferred supplier and partner of high-end standard and customized optical sensor solutions for quality control in production processes of semiconductor and consumer electronics. Using our non-contact and non-destructive technology, deviations in essential steps of the manufacturing process can be detected. Thus, we enable not only a significant increase in the quality of subsystems and finished goods, but also a reduction of time and cost in the assembly processes. PRECITEC equipment is currently used in application scenarios in the semiconductors such as: • In-process wafer thickness measurement (grinding, CMP, etc…) • Fast warpage inspection • Bumps and micro-bumps inspection • Laser dicing groove inspection • In process dicing laser autofocus • And many others

Biography
Mathias Holzapfel is a Business Development Manager at Precitec Optronik with a focus on the Semiconductor industry. His responsibility encompasses Precitec’s worldwide Semiconductor sales. Upon completing his engineering degree in "Photonics and Image Processing" Mathias began his career as a technical sales and applications engineer in the field of diode array spectroscopy. Later he moved on to industrial image processing were he further developed his software and application expertise. These skills and experiences lead him to his current position at Precitec Optronik.

Artificial Intelligence - The next big growth driver for the semiconductor industry

Schadt, Tanjeff
Principal
PwC Strategy&

Abstract
In its bi-annual Global Semiconductor Report, PwC analyzes market development, key drivers and growth opportunities for the global semiconductor market. The presentation will provide insights into the next edition of the report series with a spotlight on Artificial Intelligence (AI) and the digitization of semiconductor companies. We will elaborate on AI as the next big growth driver in the semiconductor market: What are new "AI-driven" top target markets and applications? How will the AI ecosystem evolve and what is the role of semiconductor companies? Will AI democratize the innovation in the industry creating a new uprise of semiconductor startups? What is driving value most in the digitization of semiconductor companies? What are resulting potential opportunities and risks for European semiconductor companies?

Biography
Tanjeff Schadt has 8 years of experience in management functions in the industry (R&D project and product portfolio manager) and 6 years of experience in strategy consulting. He specializes in go-to-market strategy as well as innovation and R&D excellence. He is an integral part of PwC's semicon practice and was especially running various projects for semiconductor companies on innovation and operational topics in Europe and Asia. Tanjeff Schadt holds a Master of Business Administration (MBA) at FOM Hochschule für Oekonomie & Management Munich and Pfeiffer University of Charlotte (NC), USA. Previously, he graduated from the University of Applied Sciences Darmstadt with a diploma in optical technologies and digital image processing (Dipl.-Ing.).

Smart Manufacturing enabled by Silicondash

Iung, Stephane
Customer Program Director
Qualtera

Abstract
With the increasing complexity of manufacturing processes and the multiplication of integrated multi-chip modules (MCM) and 3D stack, the amount of manufacturing and test data becomes overwhelming, making virtually impossible with traditional tools and methods the extensive and systematic analysis and detection of all quality and yield issues . At the same time, the need to respond in real-time, to detect, prevent, predict and control quality and yield issues throughout the supply chain and also bridge the gap between analytics and action has dramatically grown. Smart manufacturing, enabled by Big Data, promises to boost devices performances, industry productivity and ensure full and automatic control of the supply chain. The poster presents a large-scale industrial Big Data solution implemented at high-volume global manufacturing Supply Chains. The solution, called Silicondash, collects manufacturing and test data in real time from the entire supply chain and executes in real-time hundreds of algorithms to produce analytical results, reports, alerts and control signals that are automatically fed down-stream and up-stream in the supply chain to improve the critical operational KPIs. Keywords—Smart Manufacturing, big data analytics, machine learning, test and manufacturing data analysis, data mining, yield, quality, real-time data collection, multi-chip modules, 3D stack.

Biography
Stephane IUNG is currently Customer Program Director at Qualtera, in charge of overseeing existing projects and developing new opportunities. He began his carrier in the semiconductor industry 20 years ago after graduating from Ecole Supérieure d’Electricité (Paris, France). Starting in the foundry world as Yield and Characterization Engineer at IBM semiconductors, he then moved to STMicroelectronics, taking the role of Test and Product Engineering in charge of high volume products in advanced technologies for Set-Top-Boxes market. He joined Qualtera in 2011.

Development, Upscaling and Production of Printed Supercapacitors

Edberg, Jesper
Research scientist
RISE Acreo

Abstract
There is an ever-growing interest in sustainable and renewable energy sources such as solar, wind and water power. The rapid development in this field will require new ways of storing and balancing this energy. The power output from solar cells not only varies with the 24-hour rhythm of the sun, but also on shorter timescales with the passage of clouds. The intensity of wind also varies on different timescales, and this leads to large power fluctuations in the grid. To balance the power grid, intermediate energy storage on massive scales is necessary. This energy storage must not only have high enough power density to smoothen the power spikes, but it should also be environmentally friendly and sustainable, just as the renewable energy sources. We have developed a scalable paper-supercapacitor system based on the conductive polymer PEDOT:PSS and cellulose. The cellulose forms a large surface area for the conductive polymer to self-organize onto, as well as a porous network which facilitates high ionic conductivity. We have also shown how the charge storage capacity can be further enhanced by organic forest-based redox-molecules. Furthermore, we have developed new methods of producing the active material, as well as the other device components, in a large area and high throughput manufacturing processes capable of satisfying the future demand for green energy storage.

Biography
Jesper Edberg received his Ph.D. in applied physics at the Laboratory of Organic Electronics at Linköping University, with the thesis title 'Flexible and Cellulose-based Organic Electronics'. He started working at RISE Acreo in 2017 at the department of Printed and Organic Electronics where he is working on cellulose-based electronics and energy storage devices.

Richter, Thomas
Vice President of the Wafer Fab 150 / 200mm & MEMS
Robert Bosch GmbH

Biography
Thomas Richter, since July 2015 Vice President of the Wafer Fab 150 / 200mm & MEMS at BOSCH Reutlingen, was born 1974 in Chemnitz. Working for SIEMENS, INFINEON, QIMONDA and MELEXIS he now has about 23 years of experience in the semiconductor industry. He holds a Diploma in Micro Technology of the University of Applied Sciences Zwickau (WHZ).

Denes, Istvan
Senior Expert
Robert Bosch GmbH

Biography
Dr. Istvan Denes (Ph.D.) is a senior expert of the Robert Bosch Company, responsible for the team: CT3 Connectivity - Functional Integration of Sensors. In 2010 – 2015 he coordinated various corporate activities as well as publicly funded projects on electroactive polymers. His research field concerns the technological and economic aspects of polymer based electro-mechanical systems. Istvan Denes got his M.Sc. in mechanical engineering and holding a Ph.D. in power electronics being supervised by the IEEE Fellow Prof. Istvan Nagy. In 2012 he was completing his studies at the Steinbeis Business Academy receiving the MBA title. He is a member of the IEEE Dielectric and Insulation Society and the European Scientific Network for Artificial Muscles (ESNAM). He is a referee for project proposals of the funding announcement “Innovative Elektrochemie” of the German Ministry of Science (2016).

MEMS – One Product one process?

Gómez, Udo
Senior Vice President
Robert Bosch GmbH

Abstract
The demand and variety of applications for MEMS sensors has been growing steadily since the first series applications in the automotive sector in the early 1990s. Especially since the rise of fast-moving consumer markets, quick and efficient design has become increasingly important. However, in particular for MEMS, the strong interaction of product design and manufacturing processes is a major challenge. The growing number of applications for sensing of various physical and increasingly chemical parameters, often require specific solutions in MEMS production, chip level packaging and component testing as well. Fast and market-driven product development is only possible through innovative design concepts and the provision of modular process building blocks. A deep understanding of the interrelationships and the development of corresponding simulation tools are further key competencies. As market leader in MEMS sensor business and one of the first MEMS pioneers, BOSCH is continuously pushing forward the development of MEMS technology. The extension of our process platform originally defined for automotive applications to consumer products opens up new possibilities in the realization of complex 3D structures. This enables new product designs that are reflected in high-performance sensors for both automotive and consumer electronics applications. The presentation gives a short overview of the different requirements on MEMS technology compared to standard IC design and manufacturing. It provides insights into the future development in the field of surface micromechanics and highlights challenges and solutions of MEMS technology development and manufacturing as well as design methodology. In addition, we give examples of new design and product concepts and finally question: Does the old MEMS law "one product, one process" continue to apply?

Biography
Dr. Udo-Martin Gómez Senior Vice President Sensor Engineering, Robert Bosch GmbH Dr. Gómez is Senior Vice President of Robert Bosch GmbH. He is heading the Sensor Engineering at Bosch Automotive Electronics (AE/NE-SE) in Reutlingen, Germany, the world’s largest MEMS supplier serving the Automotive, Consumer Electronics and IoT industry. Having completed his doctorate in physics, Dr. Gómez started his career at Robert Bosch GmbH in 1999 at Corporate Sector Research and Advanced Engineering (MEMS technology). Before joining Bosch Automotive Electronics in April 2018, he worked in various management positions at Bosch and also held the position of Chief Expert for MEMS sensor technology. From 2013 to March 2018, he was Chief Technical Officer of Bosch Sensortec GmbH - a fully-owned subsidiary of Robert Bosch GmbH, responsible for research and development of micro-electro-mechanical sensors (MEMS) for consumer electronics, smartphones, security systems, industrial technology and logistics. Since 2014, Dr. Gómez is Deputy Chairman of the Board of VDE/VDI-Society Microelectronics, Microsystems and Precision Engineering (GMM). Since 2015, he is also member of the GSA (Global Semiconductor Alliance) EMEA Leadership Council.

Yield & Process Improvement by Data Analysis along the Supply Chain

Rapp, Roberto
Director of Manufacturing Process Integration, Deputy Technical Plant Manager/Reutlingen
Robert Bosch GmbH

Abstract
Along the semiconductor supply chain an increasing amount of production data are generated and are waiting to be used for continuous process-, yield- and quality-improvements. To classic SPC and data analysis, done by engineers, a variety of new applications were added over the years. Keywords are FDC, APC, ADC, data lakes, data mining - just to name a few. Looking at the supply chain from wafer start up to electrical wafer test (EWS) traceability is a given. Other than ASICs many MEMS elements can’t remember their origin, like wafer number or x/y position. So it is important to make use of data from different steps in production. In this presentation examples for automatic analysis of inline defectivity and EWS are shown. Also the successful implementation of traceability, from final product test of MEMS sensors to inline production data.

Biography
Roberto Rapp has been employed at Robert Bosch GmbH since 2009 as Director of Manufacturing Process Integration, where he is responsible for the implementation and production of the ASIC, Sensor and Power technologies. In parallel he is deputy technical plant manager of the Bosch Semiconductor Plant in Reutlingen, Germany. He studied physics at the University in Heidelberg, Germany and joined IBM in 1985, starting his professional career as Process Engineer in the Wafer-Fab in Böblingen, Germany. 1988 he worked in the first 200mm IBM Wafer-Fab in Burlington VT, USA. Working for IBM, SMST, Philips and NXP he has now over 30 years of experience in the semiconductor industry for consumer and automotive. Since 1995 he held different management positions in Engineering, Quality and Production.

Direct Imaging Solutions for Advanced Fan-Out Wafer-Level and Panel-Level Packaging

Goeke, Mark
Manager Product Engineering
SCREEN SPE Germany

Abstract
In recent years, the increasing use of smartphones and other mobile devices has created a demand for even higher integration, speed and miniaturization of devices. As scaling according to Moore´s Law is slowing down, the industry is focusing to boost device performance by advancing in 3D integration and packaging. This trend has motivated SCREEN to develop an entire line-up of direct imaging systems for both application spaces - Wafer-Level and Panel-Level Packaging. This talk will outline the specific challenges an exposure tool has to cope with in the packaging arena. A unique method of image creation by using a proprietary spatial light modulator will be presented as well as image correction functions, that automatically adjust exposure data to prevent alignment errors. This feature resolves the previously challenging issue of positional deviation when rearranging the individual dies for fan-out processing.

Biography
Mark Goeke received his Master of Science in Photo Engineering from the University of Applied Science, Cologne in 1994. After holding various positions in lithography engineering he started working with Dainippon Screen Mfg.Co. (now Screen SPE, Germany) in 1999. Here he moved to hold the position of the Europen Product Engineering Manager, responsible for engineering, technology and product marketing for Screen´s product lines of lithography and single wafer processor equipment.

Weiss, Bettina
Vice President Global Business Development
SEMI

Biography
As Vice President of Business Development and Product Management, Bettina Weiss supports the diverse product needs of association members, as well as assesses strategic emerging opportunities for member company engagement in the extended global manufacturing supply chain. Weiss joined SEMI in 1996 and held a variety of positions in SEMI’s International Standards department, including department lead, until 2008. From 2008 to 2012 she had global responsibility for SEMI's Photovoltaic/Solar Business Unit which then expanded into a broader business development role including the integration of SEMI Strategic Association Partners FlexTech and MEMS & Sensors Industry Group. In addition, since 2017, Weiss has been responsible for developing strategy and global implementation plans of SEMI’s Smart Transportation vertical platform, with its current emphasis on the automotive electronics supply chain. Prior to joining SEMI, Weiss worked in sales and marketing positions at Metron Semiconductor and Varian Semiconductor in Munich, Germany. She holds a BA from the International School for Applied Languages in Munich, Germany, and is a certified translator for Anglo-American Law and Economics.

SEMI Standards: Update on Fan-Out Panel Level Packaging Standardization

Amano, James
Sr Director, Int'l Standards
SEMI

Abstract
Fan-Out Panel Level Packaging (FO-PLP) technology is an enhanced packaging technology, embedding die in a low-cost substrate which is patterned to allow higher density of IOs than would otherwise be supported by the chip size. A number of different formats – including circular and rectangular – have been proposed for the panels into which the die are embedded, with a large number of different rectangular sizes. This wide range is delaying broad acceptance of FO-PLP technologies, as the tools must be customized for each different format. Panel substrates today range from 300 mm to 920 mm. Cost advantages depend on package and substrate size, and lack of standardization is a barrier to high volume manufacturing. Despite its advantages, fan-out packaging has challenges to overcome. To address these issues, the SEMI Standards Fan-Out Panel Level Packaging Task Force is currently developing standards focusing on panels, targeting dimensions, ID marking and orientation, edge exclusion, and other parameters such as total thickness variation (TTV), bow, and warp. Created in 1973, the SEMI International Standards Program brings together industry experts to exchange ideas and work towards developing globally accepted technical standards. SEMI provides the forum for the essential collaborations that must be achieved to move new and existing markets forward efficiently and profitably.

Biography
James Amano has led the SEMI International Standards Program since 2008. Prior to joining SEMI, he worked as the Silicon Valley sales engineer for Matsusada Precision, and as a trade specialist for the Japan External Trade Organization (JETRO). He holds degrees in Economics and Environmental Conservation from the University of Colorado at Boulder.

2018 Semiconductor Equipment and Materials Market: Have we Reached an Inflection Point?

Chamness, Lara
Senior Market Analyst Manager
SEMI

Abstract
Coming off of a record year in 2017, 2018 started out promising, with many analysts increasing their mid-year revenue projects over initial forecasts. However, concerns around inventory, memory pricing and trade tensions are starting to cloud the year’s once optimistic outlook. This presentation will discuss the 2018 fab, equipment and materials markets and provide a forecast through 2019 for these markets.

Biography
Ms. Lara Chamness is a Senior Manager Market Analysis at SEMI® and is responsible for SEMI’s data collection programs for equipment and materials. This includes leading interactions with SEMI’s participating companies, partners and subscribers. Ms. Chamness has 18 years of industry experience and has BA/MS degrees in environmental sciences and a MBA degree from Santa Clara University.

The Evolving Landscape of the Secondary Equipment Market & Fab-Supplier Interactions

Salmon, Tom
VP, Collaborative Technology Platforms
SEMI

Abstract
This talk will include an overall market view of secondary equipment activities, both in Europe and globally, as well as an update on the Fab Owners Alliance (now part of SEMI) and how companies in Europe can engage.

Biography
As Vice President of Collaborative Technology Platforms, Tom Salmon works with SEMI’s staff to ensure that members, standards users, and volunteers worldwide receive maximum value from their association with SEMI. Additionally, he manages a number of SEMI’s business and technology communities, including the Fab Owners Alliance, SEMI’s Smart Manufacturing initiative, the Electronic Materials Group, Advanced Packaging, and Secondary Equipment and Applications groups. Before joining SEMI, he held several management positions in manufacturing, logistics, customer relations, and sales. Salmon is a member of the Heterogeneous Integration Roadmap Committee, the IEEE and the American Society of Association Executives, and holds a BA from the University of Minnesota and a Level One Proficiency Certificate from Japan’s Ministry of Education.

Demircan, Emir
Sr Manager Advocacy and Public Policy
SEMI Europe

Biography
Emir Demircan, Sr Manager Advocacy and Public Policy at SEMI, is a professional in government affairs. At SEMI, he is responsible for leading EU advocacy initiatives and coordinating relations with the EU. Before joining SEMI, he worked at other advanced manufacturing-related associations in Brussels, the European Commission and Sun Chemical. He has a background in international political economy.

High-sensitivity detection of electrically active non-visual defects

Tallian, Miklos
project manager
Semilab

Abstract
Detecting defects as early as possible is one of the most important needs in semiconductor device production, and there are plenty of methods and tools available to identify defects using visible or ultra-violet light with a variety of dark-field and bright-field techniques during manufacturing. High-throughput electron-beam inspection is also available to catch near-surface defects. However, sub-surface crystalline defects in the active device region, such as dislocations, stress-induced slip-lines, precipitates caused by heavy metal contamination, and similar problems can only be detected after testing, failure analysis and fauilt isolation. We present a novel method, which uses infrared imaging to capture light emitted by the defects themselves in response to an excitation. We show that using this method, certain types of yield-critical defects can be detected and potentially identified early in the front-end process, and corrective actions can be implemented immediately, thus saving valuable time during ramp-up phase. We show that the method is especially suitable for the set-up and control of processes that have a high risk of causing extensive damage in silicon, such as ion implant procedures, or aggressive etch processes.

Biography
Miklos Tallian graduated from the Budapest University of Techology and Economics. He is with Semilab since 2008. His main responsibilities include managing joint European R&D projects, and providing technical support for business development activities.

Robust Magnetic Sensors for Condition Monitoring in availability-oriented Product Service Systems

Slatter, Rolf
CEO
Sensitec GmbH

Abstract
Globalization, Industry 4.0 and increasing price pressure are only a few impact factors influencing the competition in the capital goods industry. There is a trend for machine builders to differentiate by creating individual bundles, consisting of technical products and lifecycle-oriented services, called Product-Service Systems (PSS). Smart sensors are a key enabling technology for availability-oriented PSS. Within the German state-funded R&D project “InnoServPro”, Sensitec GmbH is working with a number of partners to develop innovative service products for individualized, availability-oriented business models. One use case studied concerns the condition monitoring of the primary conveyor belt of a potato harvester. A specially-developed magnetic MEMS sensor, based on the magnetoresistive (MR) effect, is capable of identifying damage to steel rods, which are a major component of the conveyor. This information is used to estimate the remaining useful life of the conveyor, in order to plan maintenance optimally and so increase machine available. These new technologies are already progressing to industrial applications. In tobacco cutting machines the cutters are typically re-sharpened at fixed periods. A new MR-based magnetic sensor is capable of monitoring the sharpness of the cutters to allow local, in-process re-sharpening of the cutters without stopping the machine. This solution provides significant benefits, in terms of increased machine availability due to reduced down-time for re-sharpening the cutters. There are also unexpected additional benefits for the machine builder. The magnetic measuring principle can recognize original OEM-cutters so preventing machine down-time due to use of lower quality, non-original components. New magnetic sensors, based on the MR effect, combined with new software functions for smart signal processing are proving an essential enabling technology for new product-service-systems that benefit both end-users and machine builders.

Biography
Dr. Rolf Slatter gained his PhD in Mechanical Engineering at the Imperial College of Science, Technology and Medicine, University of London. From 1988 to 2006 he was employed at Harmonic Drive AG in Limburg as Production Manager, Sales Manager and ultimately as Director for Sales & Marketing. He also co-founded and was Managing Director at Micromotion GmbH in Mainz from 2001 to 2006. In 2007 he started at Sensitec GmbH in Lahnau as CTO and has been CEO and Managing Partner since 2010. He is also owner of ITK Dr. Kassen GmbH in Lahnau. Furthermore, Dr. Slatter is Chairman of the Board of the Innovation Platform for Magnetic Microsystems INNOMAG e.V., Member of the Board of AMA Association for Sensors and Management and is a member of the Council for Technology of Rhineland-Palatinate.

Challenges in detecting and achieving highly reliable microelectronic products. Support by physical and chemical analysis.

Dallmann, Gerald
Division Manager Microelectronics
SGS INSTITUT FRESENIUS GmbH

Abstract
Current microelectronic products achieve failure rates in the low-ppm region. But the requirements for field failure reduction are still increasing as more and more microelectronics products like sensors, actuators and integrated systems are introduced in smart vehicles. Autonomous driving will create a new level of unacceptance of system failures. On the other hand, chip and microelectronic product test and qualification procedures are still similar to the old procedures of the AEC Q100 standard with very limited statistics and use conditions. The talk will show examples of failures not covered by qualification and production tests as well as some approaches to improve reliability assessment process. The physical and chemical analysis methods and tools (like XPS, AES, TOF-SIMS) are highly developed to analyze materials and failure modes in semiconductor and system level technologies. The application of these analysis techniques after climate, voltage or mechanical stress application can create a much deeper view inside chip and system weaknesses and failure modes. The talk shows some typical failure mechanisms found in a lab as service provider for many different companies. Some weak spots are discussed with recommendations for improvements.

Biography
Division Manager at SGS Institut Fresenius GmbH in Dresden, Germany, since 2009. Main focus on material and failure analysis of semiconductor devices of client companies. 1995 Director for technology development at Siemens, Infineon, Qimonda, responsible for process integration, yield enhancement and material and technology development of DRAMs. 1990 Product manager microelectronics at Institut Fresenius in Dresden. Main Focus on failure analysis of semiconductor devices. Department manager electron microscopy at Zentrum Mikroelektronik Dresden (ZMD). 1986 Diploma in Microelectronics Technology and Semiconductor Devices.

Siconnex BATCHSPRAY Technology: Case studies for cost- and space improvements

Wörndl, Fabio
Global Director Sales & Marketing
Siconnex customized solutions GmbH

Abstract
Siconnex BATCHSPRAY technology is used, if a high throughput on a small footprint, as well as a low chemical consumption matters. In a case study, that was done together with a European customer, the benefits of moving from a wetbench or single wafer track to a BATCHSPRAY equipment in terms of money and cost savings are shown.

Biography
Fabio Wörndl started at Siconnex in 2011 as Service Engineer. After a technical sales support role for the US market, he became Account Manager in 2016. Since July 2017, Fabio is Global Director of Sales & Marketing at Siconnex and manages the sales structure around the globe. Fabio has a degree in electronics and a diploma in industrial engineering and economics.

Radu, Ionut
Director
SOITEC

Biography
Ionut Radu is Director of Advanced R&D at Soitec being responsible for research and development efforts in the field of advanced substrate technologies. Prior to being appointed to his current position, he held various technology management positions with responsibility in development of new substrate technologies for advanced electronic devices. Ionut is currently involved with industrial and academic research collaborations to support strategic developments of advanced substrate materials for semiconductor industry. Dr. Radu obtained his B.S. in physics from University of Bucharest in 1999 and Ph.D (Dr. rer. nat.) in physics from Martin-Luther University Halle-Wittenberg in 2003. He has co-authored more than 70 papers in peer-reviewed journals, conference proceedings and reference handbooks and holds more than 40 patents in the field of semiconductor technologies. Dr. Radu is senior member of IEEE society and involved in Technical Program Committees of international conferences (ESSDERC, VLSI-TSA) and industrial forums (Semicon Europa).

Innovative Compound Semiconductor Based Engineered Substrates for Photonics, Power, Solar and RF Applications

Guiot, Eric
Product Development Manager
Soitec

Abstract
The Smart Cut ™ technology applied to the fabrication of SOI, is used in volume manufacturing by SOITEC, serving digital, RF, power and photonics markets. Application of this technology using ion implantation to transfer thin films of compounds semiconductors has also been developed. The Smart Cut ™ process has technical and economical advantages. Transfer of thin layers onto many various materials with both a good thickness homogeneity and a high crystalline quality has been demonstrated. From an economic point of view, the possibility of reusing the remainder of the implanted substrate helps to reduce costs, especially for the III-V materials. We will focus on the application of the Smart Cut ™ technology for two different materials, InP and GaN. InP is widely used for the optoelectronic market. The Smart Cut ™ technology, has been tuned to this material. In addition to the cost advantage of the recycling, different receiver substrates such as GaAs, Sapphire or Si have been evaluated to enable new functions: receiver lift off, lower fragility, better integration. Using the InP-on-GaAs engineered substrate combined with direct wafer bonding, Soitec together with Fraunhofer ISE and CEA Leti have demonstrated wafer bonded 4-junction solar cells with highest conversion efficiency of 46.1 %. We will discuss also how the Smart Cut™ technology can enable the use of InP for RF 5G products. Regarding GaN, Smart Cut ™ technology enables the layer transfer of up to 1 µm thick GaN films either from bulk GaN or GaN on sapphire. We have demonstrated up to 3 cycles of reuse of the GaN donor substrate. Different receiver substrates such as Sapphire, Molybdenum and polycrystalline Aluminum Nitride have been evaluated. Through this innovative engineered GaN substrate, we have demonstrated a 20µm GaN epi growth. This breakthrough could enable new vertical GaN devices for high power application such as electric vehicle powertrain and RF power products serving the 5G market.

Biography
Dr. Eric Guiot, Materials Science Doctor (Ph.D. from Paris University, Pierre et Marie Curie), now is product development manager for compound semiconductors in Soitec. He is graduated from the Ecole Centrale engineering school in France. He made his PhD on the development of epitaxy of iron oxide targeting giant magnetoresistance materials. He then joined Corning Fontainebleau Research Center in France for the development of integrated optics devices for telecommunication. In 2002 he joined Soitec in France. He has been working on the development of advanced engineered substrates targeting various applications covering digital application at advanced nodes and optoelectronics. He is now leading the product development group focused on compound semiconductor engineered substrates targeting power, solar, photonics and RF application.

Engineered Substrates: a powerful co-innovation platform

Mazure, Carlos
EVP and CTO
Soitec

Abstract
Numerous systems like automotive, IoT and many more require low latency, data processing efficiency, low power requirements, and meta-data transmission. Machine learning must occur at the sensing node. Edge and very edge computing are essential to maintain the high efficiency of a given system, as well as the mechanism to control the overwhelming data generation and subsequent flows. The sequence of sensing, processing the information, learning, and transmitting/receiving data is the sequence that builds on smart microelectronics and smart engineered substrates. The urgency with which the different applications must innovate imposes a renewal in how the supply chain industry has treated R&D, sampling and solution development. Co-optimization of architecture-technology-engineered substrate made possible the success of RF-SOI for 4G, establishing RF-SOI technology as the incumbent technology. In order to shorten the overall R&D cycle from substrates through systems a co-innovation approach is needed. In a co-innovation strategy the key actors collaborate in early stage at several levels of the value chain to maximize synergy, converge on the substrate-system solutions enabling the fastest time from development through product. This talk will discuss co-innovation, engineered substrate infrastructure and examples of substrate innovations.

Biography
Dr. Carlos Mazure, CTO & EVP, Head of Corporate R&D at Soitec since 2001. Chairman and Executive Director of SOI Industry Consortium since July 2014. IEEE Fellow, 30 years of experience in Semiconductor Industry. Prior to Soitec, Carlos headed the ferroelectric FeRAM program at Infineon (Munich, Germany), and initiated Infineon/Toshiba FeRAM Alliance. Earlier he worked for IBM/Infineon DRAM Alliance (Fishkill, NY); and before at APRDL, Motorola (Austin, Texas). Carlos holds two doctorates (University Grenoble, France; Technical University Munich, Germany). Authored/co-authored 120+ technical papers, holds 100+ US patents. Member of several international advisory committees and company boards.

Advanced Packaging Solution for High Performance Computing and AI

Wang, Yu-po
Sr. Director
SPIL

Abstract
For years the IC industry has been driven by the demand of Smartphone and tablet. IoT was most expected as the next growth engine but all of sudden, high performance computing (HPC) and AI have emerged as the major driving forces thanks to the booming of crypto-currency mining and both cloud computing and edge computing. There are assembly challenges for HPC and AI, first of all, to achieve high computing performance, the logic IC is bigger and generates high thermal dissipation. And the bigger the die size, the lower the manufacturing yield rate. Secondly, the interconnection between logic IC and the memory needs to be very quick so it won’t slow down overall system performance. Finally, a variety of SiP are required to realize AIoT (AI of Things) To properly address those assembly challenges, a variety of advanced packaging solution are in development. For high power consumption, advanced silicon node is applied for large FCBGA to save the power, and advanced thermal interface material (TIM) with higher thermal conductivity is in development for more thermal dissipation. Furthermore, one big IC can be redesigned as several identical smaller ones with higher manufacturing yield rate, and by utilizing 2.5DIC technology, an interposer with fine lines is introduced for homogeneous integration. As for heterogeneous integration between logic IC and the memory, they are packaged together with 2.5DIC technology or Fan-Out MCM based on fine line requirement for faster interconnection. As for SiP, not only for small form factor, but also better EMI and antenna in SiP are in development for better and faster wireless communication. In this paper, technical risks of each advanced packaging solutions mentioned are reviewed, and possible actions of each risk are explored. And with the ready of these advanced packaging solutions, HPC and AI are off and running.

Biography
Dr. Yu-Po Wang Director CRD Center SPIL Education: Ph.D., Mechanical Engineering, State University of New York at Binghamton, New York, U.S.A. Experience: 1997-1998 Gintic Institute of Manufacturing Technology, Singapore 1998-Present SPIL, Taiwan

Optimising Surface Chemistry After Plasma Dicing (SPTS Technologies & Versum Materials US, LLC)

Hopkins, Janet
Etch Applications Manager
SPTS Technologies Ltd

Abstract
Authors: J. Hopkins, O. Ansell, R. Barnett (SPTS Technologies) & M. Phenis, D. Pfettscher, R. Peters, M. Sistern (Versum Materials US, LLC) Plasma dicing has shown many benefits over other dicing techniques such as increased die strength, smaller/thinner die and reduced cost of ownership. This dicing process uses the established Bosch Process, with alternating etch and deposition steps to etch through the silicon wafer. The nature of the process means that there will be F residues remaining at completion due to the CF_x polymer layer deposited on the wafer surfaces^[1]. This can be removed by an O₂ plasma however when solder bumps are present and subjected to the same dicing/Bosch process, the bumps can react with F radicals to form SnF₂ which cannot be removed by an O₂ plasma alone. An additional plasma process can be performed to reduce the F levels further, however, this still leaves F present. Studies are underway to determine whether this is an issue for subsequent steps or indeed whether the presence of F may help solderability^[2]. However, in this work, the effectiveness of post-dicing wet cleans to remove the SnF₂, and avoid any potential issues, is investigated. Tests were carried out comparing plasma DAG (dicing after grind) processes with different post residue treatments. A screening test was carried out using several different wet etch formulations, and two suitable formulations were identified. Further tests were carried out to optimise the conditions and check the tape compatibility. The F levels, measured by EDX, were reduced to <1% at a level comparable to the control sample (with no plasma dicing). The work has shown that a wet chemistry post plasma dicing treatment is capable of removing F residues and is compatible with the plasma dicing process flow. References 1. “Method of Anisotropically Etching Silicon” F. Lärmer, A. Schilp, , German Patent DE4241045 2. Hosoda et al, Proceedings of ECO design 2003, Tokyo, Japan, December 8-11, 2003, p 710-713

Biography
Janet Hopkins is the Etch Applications Manager at SPTS Technologies, currently focusing on plasma dicing. Janet joined the company in 1995, as Process Engineer in the Si etch group. During her career, she has worked in developing different plasma sources and processes, including early commercialisation of the Bosch Process for deep silicon etching of MEMS. She is the author of many papers and patents. She holds a BSc in Physics and Chemistry of Materials from The University of Durham and a PhD in Plasma Surface Modification.

Advances in doped AlN deposition techniques for next generation Piezo-MEMS

Barker, Anthony
PVD Product Manager
SPTS Technologies Ltd

Abstract
In BAW and Piezo-MEMS devices based on released membrane structures, AlN film stress state is of utmost importance and to maximise yield, manufacturers look to minimise stress variation across the wafer. When Sc is added to the film the problem becomes more demanding, as stress range tends to worsen with increased Sc content. Previous methods to control stress reach a limit of capability, impacting yield or compromising device design and performance. The problem is compounded when variations in Sc content exist in the film centre to edge, either as a result of chamber geometry, or sputter target homogeneity, impacting resonator film properties, such as coupling coefficient. In addition to stress control, a related issue presents itself when Sc is added to an AlN film. During deposition, crystallites can form within the AlScN. Effectively defects in the film, the crystallite presence degrades resonator properties - dead volume amongst the piezoelectric bulk. Formation is abundant in areas of tensile stress, hence the relation to stress control. As with stress profile, crystallite density increases with Sc content so management of crystallite formation becomes another requirement for the PVD process, to ensure coupling coefficient yields are maximised. In this paper we present a novel solution providing symmetrical control and adjustment of stress for AlN films with different Sc content, demonstrating excellent WIW stress performance, the ability to locally tune stress to compensate for centre to edge variations in Sc, and approaches to prevent formation of crystallite defects, maximising yield

Biography
Dr Anthony Barker joined Surface Technology Systems (STS) in 1997 as Etch Process Engineer. He went on to manage STS’ non-Si based etch and deposition process groups. After leaving STS he joined Trikon as Etch Process Engineer in 2005, which became Aviza Technology and then merged with STS in 2009 to form SPTS Technologies. Most recently Anthony worked as Principal Process Engineer in R&D Accounts group before joining SPTS's PVD Product Management team in May 2017. Before STS, Anthony worked as Thin Film Process Engineer at Gems Sensors. Dr Barker has a B.Eng Honours degree in Materials Engineering and a Ph.D in Electronic Materials in association with Rolls Royce, both from Swansea University.

Impact of Plasma Dicing Singulation Techniques on Die Breakage Strength and Robustness

Parker, David
Project Manager
ST Microelectronics

Abstract
For all end applications where a semiconductor device is used, there is a constant demand for improved performance under all environmental conditions. One such application, which we all use regularly, is the smartcard chip. This secure microcontroller can be found predominantly in our bank or travel cards and passports, where it may receive much physical punishment in normal usage. The demands for severe robustness criteria for these card-based applications are continually increasing to ensure that the packaged chips are able to withstand more rigorous treatment without breaking. Key to achieving these exacting standards is the singulation of the chips in a way that does not generate any inherent mechanical weakness. The standard blade sawing process has so far met existing requirements but the technology roadmap for such devices has presented new challenges with the deployment of fragile ultra-low k BEOL dielectrics. This has prompted the introduction of laser grooving before dicing to minimise damage to these materials caused by the sawing blade but this, in combination with mechanical dicing can itself cause weakening of the die and a higher risk of failure. This paper will examine the relationship between die strength and some new approaches to die singulation with a strong focus on plasma dicing, in which die separation is achieved by etching the silicon in the scribe lane. As there is no mechanical element we should expect significant improvements in die strength so we will explore the inherent performance with this method as the etching output parameters and masking steps are varied. Additionally, this technique requires that the silicon is exposed in the scribe street, which must be free of metals and dielectrics before etching. Again laser grooving can be used to meet these conditions and we will describe how sequential laser grooving and plasma etch processes affect the die strength and reliability performance versus the more severe test criteria.

Biography
Mr Parker graduated in Chemistry from The University of Manchester, UK in 1981. Since the start of his career in semiconductors with Inmos Ltd the following year he has spent over 30 years with ST Microelectronics both in Agrate, Italy and Rousset, France. Beginning as a process engineer, mainly in deposition and patterning, he has extensive experience of front-end operations, including device engineering, process integration and technology transfer. In recent years he has taken on a project management role to lead ST's interests in plasma dicing within the Back-end Manufacturing and Technology R&D team that is based in Grenoble.

From Lean Manufacturing to Lean everywhere

Ardesi, Olivier
Lean Office Director
ST Microelectronics

Abstract
ST Microelectronics started its Lean journey 10 years ago, in two of its main Front-End fabs. The approach covered the classical Lean tools & methods (that had to be adapted to cope with semiconductor manufacturing specificities) but also the Management system and practices in order to really bring a change in mindset & behaviors and deeper engage all employees. After 3 years,the results on the key industrial indicators were improved but more over the culture of the site had been transformed as recognized by main customers. The approach was thus expanded to all Front-End fabs, then Back-End plants, always taking into account the local context, specificities and culture. The question then arose whether this Lean approach could also be applied and bring similar improvements in non-manufacturing areas such as Technology and Product development, but also Business support functions and Sales ? How to convince organizations whose efficiency is less easily measurable and subject to continuous improvement that there really was an added-value for them to change their way-of-working with Lean ? And finally, how to make Lean a key ingredient of ST culture ? Today, 75% of ST organizations are engaged into Lean initiatives among which Technology R&D, Product development, HR, Purchasing, ICT, Sales & Marketing… In this talk, Olivier Ardesi, in charge of ST Lean office, will show how ST is following a proliferation strategy through experience sharing and a balanced mix of bottom-up and top-down approach to deploy Lean in every domain and make it part of its Leadership culture. What are the actual and foreseen benefits and what are the challenges will be part of the discussion.

Biography
Olivier Ardesi, Lean Office Director of STMicroelectronics, coordinates Lean proliferation all across ST organizations. After 10 years and various manufacturing roles in ST Rousset Front-End fab, he led the first Lean Manufacturing program in ST started in 2008. Three years later, he was in charge of deploying Lean approach among the other ST Front-end fabs. He then started to support Lean initiatives in non-manufacturing organizations, exploring how Lean principles could apply in R&D, Human Ressources, purchasing, etc.. He graduated with an engineering degree from Ecole Centrale Paris and holds an Executive MBA from EM Lyon business school.

Fully Roll To Roll Printed 2-Bit Controller For Inexpensive Nfc Sensor Tag

Shrestha, Kiran
Researcher
Sunchon National University

Abstract
Youshin Kim, Bijendra Bishow Maskey, Hyejin Park, Prince Weseley, Sajjan Parajuli, Pravesh Yadav and Gyoujin Cho* Sunchon National University, Printed Electronics Engineering Department, Suncheon-si, South Korea Presenting author: Kiran Shrestha *Corresponding author: gcho@sunchon.ac.kr An inexpensive NFC-sensor tag has been highly demanded as a smartphone can communicate with packaged items via NFC (13.56 MHz) carrier. The NFC-sensor tag can host one or a couple of sensors such as thermistor, pH, gas, humidity, salt, etc. for real-time monitoring the quality of items in the packaging. To put the NFC-sensor tags on all packaging, a cost issue is always drawback for its practical realization of a smart packaging. In this presentation, we would like to present a way of developing the inexpensive NFC-sensor tag by replacing expensive Si chip controller by simplified all R2R gravure printed 2-bit controller where optimized logic circuits, all electronic inks and R2R gravure system to integrate all printed transistors on plastic roll will be introduced as well.

Biography
Kiran Shrestha is a second-year Printed Electronics Graduate student at the Sunchon National University in South Korea. He received a bachelor’s degree in Electronics and Communication engineering in 2014 from Tribhuvan University in Nepal. His current field of research is dedicated to design and optimization of the printed electronic devices. He is interested in design, optimization and simulation of the digital electronic systems.

Non-contact metal layer thickness and sheet resistance measurement on process wafers

Klein, Marcus
Managing Director
SURAGUS GmbH

Abstract
Thickness measurement is a crucial yet challenging endeavor in many industries. Processes such as sputtering, plating, polishing or selective etching among others benefit from instant metal thickness measurement. To date, indirect measurements on test wafers often lead to uncertainties resulting from a selective measurement of samples. They also cause additional costs for processing test wafers and consuming tool time. Furthermore, high-resolution measurement near edges enables integrity assessment of near edge areas. These near edge areas receive broader attention these days as they still provide significant potential to increase the yield and decrease costs per chip. Novel tool integrable measurement technology is required to adapt to these challenges and to assure accurate, non-contact and reliable measurements of the layer thickness even at high wafer handling speed. Therefore, non-contact sensors for intool monitoring and detailed offline imaging have been developed based on eddy current technology, a well-known method for layer characterization, and have been adapted to the challenges of in process and edge area measurements. A sophisticated evaluation enables a precise interpretation of the obtained data, including near edge areas. It is shown that the received results are equivalent to destructive thickness and contact 4PP measurements. Eddy Current, though, is a much faster method. In contrast to other approaches, this non-contact method erases impacts of insufficient homogenous contact qualities and therefore leads to a higher repeatability. Examples will be given where the eddy current measuring method has been applied on top of structured multi-layer systems or obtaining precise thickness measurement near edges. This talk is dedicated to initiate a discussion on the shift from measurement on test wafer to measurement on process wafers.

Biography
Dipl.-Wi.-Ing. Marcus Klein has been managing director of SURAGUS GmbH since 2010. He got his master degree in Business and Engineering from University of Technology Dresden focusing on microelectronics and electronic packaging. Past working experiences include Siemens Pte Singapore, Wacker Chemie, Advanced Mask Technology Center and Fraunhofer Institute for non-destructive testing Dresden. He is member in several research projects and expert for eddy-current based measuring solutions for thin films, coated glass, carbon fiber and graphene.

Driving automotive Innovation – comprehensive design

Huhnke, Burkhard
Vice President Automotive Strategy
SYNOPSYS

Abstract
What an exciting time we live in: self-driving cars, fully electric and always connected to the internet to provide the user a seamless transportation experience. Many announcements around the mobile phone on wheels have been made. Some of the most exciting innovations happening in our cars: cars are becoming our co-pilots as intelligent technologies make them safe and secure, more comfortable, and more autonomous. And with full connectivity the car becomes the new gold mine, a big data collector processing real time traffic data and millions of miles per day. To enable smart, connected and autonomous vehicles, the car’s electronic architecture, its supporting soft and hardware design and release processes must be adjusted. Any failure in the field results in very high cost and liability to the car manufacturer. Requirements for a robust, comprehensive design of a fault tolerant system must be newly formulated. A holistic view of the system failure rate along the supply chain, lifecycle of automotive development and production is necessary. Consequently, robustness, safety, and security of self driving systems must be significantly increased and be monitored continuously. Robust design begins in the early phase of car concepts. Automotive IP centers of excellence have been created, to ensure automotive compliant intellectual property for faster, smarter, low-energy chips reducing risk and development time. Automotive SoC design is meeting the highest safety integrity levels (ASIL) providing ADAS IP as design basis for the new advanced driver assistants architecture. By providing a simulation platform based on the processor models, early virtual prototyping, emulation, and functional verification from modelling to test bench deployment becomes possible. Software experts will be required to ensure fault tolerant, highly reliable, functionally safe and secure software along the automotive lifecycle.

Biography
Dr. Burkhard Huhnke is the Vice President of Automotive Strategy at Synopsys. He joined Synopsys earlier this year. Prior to Synopsys, he was SVP of Product Innovation & E-Mobility at VW, based in Silicon Valley. He was responsible for synchronizing VW's innovation activities and alliances to identify new concept ideas, business models and partners in the US and had end-to-end ownership of the electric vehicle platform in North America. Prior to that, he held several positions both in the US and Germany, including Senior GM, Electronics System Integration and Whole Vehicle Integration. Dr. Huhnke studied electrical engineering, at the University of Braunschweig. His dissertation about optical distance measurement was awarded with the International Measurement Prize. Dr. Huhnke serves as Research Fellow the Hult Business School in San Francisco, and is a member of the Board of Advisors at the College of Engineering at University of Tennessee Knoxville and at the College of Engineering and Computer Science at University of Tennessee Chattanooga.

SystematIC: Innovation in Integration

Visee, Richard
CEO
SystematIC Design B.V.

Abstract
SystematIC designs and develops advanced custom IC’s for sensor and power applications in the analog mixed signal domain. In SystematIC’s products optical and magnetic circuits are often designed for a high voltage environment with low power requirements to the IC’s. Trends we observe in the market are towards more integrated functionality, internal diagnosis and testability, minimum external component count at the lowest possible cost. Systematic circuit design techniques are applied in modern mixed signal CMOS IC processes for the product developments to excel in technical performance. Design for testability on waferprobe and final test are important requirements in the chip development. Lead frame customization leads to custom products in a standard assembly production lines. Examples of innovative products are presented in HV, optical and magnetic domain, as innovation in integration is advanced technology in actual products.

Biography
Richard Visée received his Electrical Engineering degree (MSc) at the Electronics department of the Technical University Delft. He proceeded to develop his skills in electronic design at the same department in a two-year in-depth study on the design of low-noise microphone amplifiers. After working as an analog design Engineer for three years, with a strong focus on RF circuit design, he joined SystematIC as a co-owner. Besides working on many various IC design projects in sensor readout and power conversion, he developed SystematIC’s Japanese business relations and now represents the company in projects for Japanese customers. He is also involved in collaborations with European research institutes and guides electronics development for space-related research.

New automatic transient thermal analysis equipment to inspect the quality of sintered interconnects

Bhogaraju, Sri Krishna
Scientific Research Assistant
Technische Hochschule Ingolstadt

Abstract
The ability to test the quality and reliability of interconnects of semiconductor packages conclusively through non-destructive tests gains importance with increased requirements. Sintered interconnects depend critically on the surface quality of the contact pads and metallic sinter particles. Unstable chemistry of the paste can also cause failures. While X-Ray or acoustic microscopy hardly detect these, thermal methods are sensitive to identify these failures. By TTA measurements the transient thermal impedance Zth is obtained and the thermal resistance Rth is calculated as per JEDEC51-14. But the measurement and data evaluation is time consuming and often requires experts. The relative thermal resistance measurement method is applied in the paper using the automatic tester to evaluate the thermal path and the thermal resistance, wherein the sensitivity and thermal load are not measured but are obtained by thermal path normalization to good samples whose values are known. LEDs are sintered on substrates, measured initially (0-hour quality) and subsequently after hours/cycles of accelerated stress testing (reliability) using the automated TTA tester. The measurement electronics are mounted on a movable 3-axis system to enable use of short cables with low parasitic inductance. To resolve the thermal resistance between the LED die and substrate the forward voltage of the LEDs after current switching needs to be measured well below 10μs. The developed current source allows very fast switching within 100ns and stabilize the detection current within 5μs. In addition an In-Situ tester measures thermal impedance providing additional data to support analysis. In this paper automated TTA test equipment and In-Situ tester are presented which enable to measure the transient thermal impedance and by that identify the thermal integrity of the interconnect after assembly and within accelerated reliability tests. By known good reference samples failures are automatically identified.

Biography
Sri Krishna Bhogaraju Scientifc Research Assistant - IIMo - Technische Hochschule Ingolstadt Education: 2010-2012 - Master of Engineering - International Automotive Engineering, University of Applied Sciences, Ingolstadt, Germany. 2006-2010 - Bachelor of Engineering - Mechanical Engineering, University Visvesvaraya College of Engineering, Bangalore University, Bangalore, India. Work Experience: Jan 2018* - Scientific Research Assistant - IIMo - Technische Hochschule Ingolstadt. Feb 2016 - Dec 2017 - Process Design Specialist - Corporate Rules & Standards, Corporate Quality & Environment, Continental AG, Hannover, Germany. Apr 2014 - Jan 2016 - Project Co-Ordinator & On-Site specialist - ContiTech Power Transmission (Sanmen) Ltd., Sanmen, P.R.China. Nov 2013 - Mar 2014 - Project Co-Ordinator - Roulunds Rubber Korea Co. Ltd., Busan, South Korea. Oct 2012 - Oct 2013 - Project Co-Ordinator - ContiTech Power Transmission Ltd., Sonepat, India. Mar 2012 - Sept 2012 - Product Manager - Asia - ContiTech Fluid Shanghai Co. Ltd.

Advanced Packaging Developments—Where Are We Going?

Vardaman, Jan
President and Founder
TechSearch International, Inc.

Abstract
The semiconductor industry packaging and assembly business continues many changes. The smart factory is the new industrial revolution, driving sensors, machine-to-machine communication, as well as data storage and analysis. The adoption of 5G and ADAS changes the package designs and materials. Growing demand for datacenters and artificial intelligence or machine learning is pushing us to the next semiconductor nodes at a faster rate. The adoption of the next advanced semiconductor nodes will present challenges that must be met with new package developments. In addition, the next 10 years is likely to see new drivers for advanced packaging. This presentation describes some of the applications and the challenges for advanced packaging.

Biography
Jan Vardaman is the President and Founder of TechSearch International,Inc., which has been providing licensing and consulting services in semiconductor packaging since 1987. She is co-author of Nikkan Kogyo’s How to Make IC Packages (in Japanese), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a member of IEEE CPMT, IMAPS, MEPTEC, and SEMI.

Per aspera ad astra - innovation in a mature fab

Urban, Alexander
Unit Manager
Texas Instruments

Abstract
It will be shown, that innovation in a mature fab needs a combination of neccessity, good leadership and people with the proper mindset. All items will be discussed in detail with examples.

Biography
Alexander started 1999 as a photo process engineer at Hitachi Semiconductor. He joined Texas Instruments in the same position in the year 2000. In 2009 he took over the position of an engineering section head for photo and yield enhancement. In 2016 Alexander extended his leadership to process engineering, equipment engineering and manufacturing of photo, epi and implant. Alexander holds several patents and is responsible for driving innovation in Texas Instruments Freising fab.

Enhancing Automated Driving through IoT

van den Ende, Bram
Project Manager
TNO

Abstract
Automated driving requires the vehicle to establish a high degree of situational awareness as well as smartness in its decision making algorithms, while maintaining functional safety in all situations. A vehicle’s sensor suite is essential in this respect as it generates the vehicle’s world model, but has range limitations and also comes at a price. The connected vehicle concept allows to exploit the availability of information external to the vehicle to basically enhance the vehicle’s world model (virtual sensors) facilitating tactical level path planning. It also makes it possible to involve the vehicle in automated driving oriented service concepts. If we then take Internet of Things (IoT) concepts to the drawing board, the emerging IoT ecosystem becomes and enabler and quite powerful functionalities can be developed. In the European AUTOPILOT project TNO works together with partners in the Dutch Brainport Pilot to demonstrate and evaluate how automated driving can be accelerated and enhanced using connected car and IoT technologies. In our presentation we will explain how these concepts are turned into real applications, for example to conduct smart platooning on national roads. We will explain how the vehicles are wired into the Brainport IoT ecosystem set up in this project and how vehicles make use of a cloud based Platooning Service to get engaged in highway platooning. Sensor data from roadside cameras is processed to generate data with which the platoon’s world model can be expanded. We will show how this enables a formed platoon to better anticipate traffic situations further ahead. We will also discuss how AUTOPILOT is hooked into international standardization on IoT protocols and data models and present which application enhancements are on our project roadmap.

Biography
Ir A.H. (Bram) van den Ende has a degree in Electrical Engineering (1989) and has been employed at TNO almost the entire period (except from short periods at Philips (1990) and at Siemens (1999). Bram has lead numerous research based consultancy and innovation projects in the ICT domain since 2000. His main focus is on digital infrastructures, particularly in the context of national or international policy making or policy issues, but he also has had management responsibilities in FP7, H2020, Eurostars and EIT innovation actions. Specific topics are broadband access developments, spectrum issues, net neutrality and the application of mobile networking (5G) in Smart Mobility and PPDR verticals. Current engagements in the smart mobility domain are AUTOPILOT and 5G-MOBIX (new).

High-rate and durable Li-ion batteries by Spatial-Atomic Layer Deposition

Meulenkamp, Eric
Program Director
TNO-Holst Centre

Abstract
The wide implementation of electric vehicles is at the moment hindered by (amongst others) the lack of intrinsically safe battery technology that could provide sufficient energy density as well as fast charging for many charge/discharge cycles. The battery industry heading towards solid-state configurations. The key challenges in next-generation all-solid state Li-ion battery technology development are related to the required energy and power densities, fast charging constraints, battery lifetime, and at the same time keeping the cost low by high-volume production. Such technology criteria require superior electrode as well as electrolyte materials (pinhole-free), and processing techniques enabling even advanced 3D designs. We report on innovative materials and 3D architectural approaches that can disrupt current Li-ion batteries, especially combining high-capacity with fast-charging capability. However, newer architectures demand newer processing techniques. A technology researched a lot in this respect is the Atomic Layer Deposition (ALD), which is well-known for its superior material quality and layer conformality over ultrahigh aspect ratio topology. But, in applications outside the advanced micro- and nanoelectronics industry, ALD technology is impeded by the economics of the low film deposition rates. Here, the scalable atmospheric pressure Spatial-ALD (S-ALD) holds the best promise for sufficient deposition rates and large-area roll-to-roll processability, which is key to battery industry. Presented will be the results on high-rate 3D Li-ion battery electrodes using S-ALD, which show charging rates of few minutes. Highlighted will be the development of new high-performance battery electrode materials (in-situ doped) by engineering material properties at the nanoscale. Next to it, we will present about the first-ever S-ALD based solid-state LIPON electrolyte material (<100 nm thick). More about our research and capabilities will be presented during the seminar.

Biography
Eric Meulenkamp received his PhD from Utrecht University in the fields of luminescence spectroscopy and electrochemistry in 1993. Joining Philips Research in Eindhoven, Netherlands, he continued to work in the fields of (nano-)materials, electrochemistry and applied physics, being project leader for polymer OLEDs for display applications from 2000-2004. The next 8 years he was Department Head of various groups in Philips Research in the Netherlands and the USA in the domains of solid state lighting and healthcare. From 2013 he was R&D manager at Philips OLED Lighting in Germany, and became Managing Director of the entity after its acquisition by OLEDWorks LLC. He joined TNO Holst Centre in Nov. 2017 as Program Director, having responsibility for batteries, spatial ALD, OLED lighting and various thin-film deposition technologies.

Advanced imaging of novel low-dimensional nanostructures

Shmeliov, Aleksey
Research Fellow
Trinity College Dublin

Abstract
Low-dimensional nanostructured materials such as organic and inorganic nanotubes, nanowires and platelets are potentially useful in a number of areas of nanoscience and nanotechnology due to their remarkable mechanical, electrical and thermal properties. However, difficulties associated with their lack of processability have seriously hampered both. In the last few years dispersion and exfoliation methods have been developed and demonstrated to apply universally to 1D and 2D nanostructures of very diverse nature, offering a practical means of processing the nanostructures for a wide range of innovative technologies. To make real applications truly feasible, however, it is crucial to fully characterize the nanostructures on the atomic scale and correlate this information with their physical and chemical properties. Advances in aberration-corrected optics in electron microscopy have revolutionised the way to characterise nano-materials, opening new frontiers for materials science. With the recent advances in nanostructure processability, electron microscopes are now revealing the structure of the individual components of nanomaterials, atom by atom. Here we will present an overview of very different low-dimensional materials issues, showing what aberration-corrected electron microscopy can do for materials scientists.

Biography
Education 2009-2014 DPhil in material science, St. Edmund Hall, Oxford University, UK. DPhil thesis: "Transmission electron imaging and diffraction characterisation of 2D nanomaterials". 2005-2009 First class honours degree in “Physics and Chemistry of Advanced Materials”, Trinity College Dublin, Ireland. 2002-2005 Leaving Certificate, Secondary School, St Joseph’s CBS, Drogheda, Co. Louth, Ireland. Employment 2014-currently Research Fellow, Trinity College Dublin, Dublin 2, Ireland. Specialisation in structural characterisation of nanomaterials using transmission electron microscopy. Teaching 2014-currently Assisting Prof. Nicolosi in the preparation of the lecture and tutorial teaching materials for the 2nd year undergraduate course “Thermodynamics” and delivering two special tutorials (Foundation Scholarship and End of Year). One of the senior supervisors for 3rd year undergraduate practicals in Nanoscience course. Lecturer for post-graduate course “Introduction to Transmission Electron Microscopy”. 2011-2012 Tutoring Engineering Applications of Polymers and Microstructure of Polymers for the second year undergraduate students in the University of Oxford.

Bartha, Johann W.
Professor
TU Dresden

Biography
Prof. Dr. Johann W. Bartha received a Diploma and PhD. degree in solid state physics at the University of Hannover, Germany. He was two years Post Doc at the IBM T. J. Watson Research Center Yorktown Heights, N. Y. were he investigated Metal Polyimide interfaces for applications in multi layer ceramic packaging. 1985 he joined the IBM German Manufacturing Technology Center (GMTC) at Sindelfingen Germany as staff member and became responsible for plasma based technologies in semiconductor processing as a senior staff member. 1994 he accepted a C3 professorship at the University of Applied Sciences at Münster, Germany where he established a laboratory for micro manufacturing. 1999 he accepted a C4 professorship as head of the chair for Semiconductor Technology at the Technische Universität Dresden (TUD). Since March 2003 he is director of the Institute of Semiconductor- and Microsystems Technologies at TUD and established a strong collaboration between the Dresden University and the local semiconductor Industry. The research focus at his chair is BEOL processing, 3D integration including electrical and optical TSVs as well as Silicon thin film PV. The search for ultrathin conformal Cu barriers as required in damascene technology initiated the interest in ALD. In the meantime, the materials studied include high-k dielectrics, moisture barriers, metals, nitrides and graphene. Specific focus is on in-situ and in-vacuo analysis of the nucleation and growth within the ALD processes.

Towards Smart Integrated Photonic Building Blocks

Smit, Meint
Professor Photonic Integration Group
TU Eindhoven

Abstract
Indium Phosphide is today’s major technology platform for fabrication of Photonic ICs (PICs). InP foundries processes provide all the building blocks required in modern telecommunication and datacommunication systems, including lasers, modulators, detectors, and a variety of passive components. While telecommunication is the dominant market, InP PICs are increasingly finding application in many kinds of sensor systems, medical diagnostics, metrology and automotive. R&D efforts are directed towards improvement of building block performance and building block descriptions, in order to support accurate PIC design. An important next step is integration and co-design of photonic and electronic functionality, e.g. lasers and modulators with their electronic driver circuits, and providing integrated photonic-electronic modules as building blocks in the library. This will release designers from the need to design complex drivers which match the specifications of the photonic circuits and enable them to use the components as smart black boxes. Integration of monitor diodes will extend the capabilities of the smart modules by integrating feed-back circuitry. In the presentation progress in photonic-electronic integration will be described and its potential for Smart Integrated Photonic Building Blocks will be discussed.

Biography
Meint K. Smit started research in photonic integration in 1981. He invented the Arrayed Waveguide Grating and he was closely involved in the introduction of MMI-couplers, both key components in Photonic ICs. In 2000 he became the leader of the Photonic Integration group at the COBRA Research Institute of TU Eindhoven. His current research interests are in InP-based Photonic Integration and integration of InP circuitry on Silicon. He is the founder of the JePPIX platform, the Joint European Platform for Photonic Integration of Components and Circuits and strongly involved in the development of the InP-based photonic foundry system in Europe. Meint Smit is an IEEE Fellow. In 2012 he received an ERC Advanced Grant and in 2016 the Rank Prize for Optoelectronics.

Atomic Layer Processing of Oxides: Area-Selective ALD and Selective ALE of ZnO

Roozeboom, Fred
Professor
TU Eindhoven & TNO-Holst Centre

Abstract
Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE) provide Ångström-level film thickness control. Here, we focus on Area-Selective ALD (AS-ALD) and ALE of ZnO processed at 100-250 oC. AS-ALD of ZnO was done on SiO2 seed layer patterns on H-terminated Si substrates, from diethylzinc and H2O as reagents. In-situ spectroscopic ellipsometry and SEM/TEM electron microscopy with EDX revealed improved selectivity at higher deposition temperatures. By combining the experimental results with Density Functional Theory, we conclude that the trend in selectivity with temperature is due to a strong DEZ or H2O physisorption on the H-terminated Si at low deposition temperature. This makes temperature a process parameter to improve selectivity. Recent ALE research has focused on 1) ion-driven plasma etching yielding anisotropic (= directional) etch profiles, and 2) thermally-driven etching for isotropic material removal. Here, we will show that one can also obtain isotropic etch profiles in plasma-based ALE of ZnO, which is radical-driven and utilizes acetylacetone (Hacac) and O2 plasma as reagents. In-situ ellipsometry revealed self-limiting half-reactions with etch rates of 0.5-1.3 Å/cycle at 100 - 250 oC. The process was shown on planar and on 3D substrates made up by a regular semiconductor nanowire forest conformally covered by ALD-grown ZnO. TEM studies on these nanowires before and after ALE showed the isotropic nature and the damage-free characteristics of the process. In-situ infrared spectroscopy was used to study the self-limiting nature of the ALE half-reactions and the reaction mechanism. During the Hacac etch reaction that produces Zn(acac)2, acac-species adsorbed on the ZnO surface are the probable cause of the self-limition. The subsequent O2 plasma step resets the surface for the next ALE cycle. High etch selectivities (~80:1) over SiO2 and HfO2 were demonstrated. Preliminary results indicate that this process can be extended to other oxides such as Al2O3.

Biography
Fred Roozeboom is a Professor at Eindhoven University of Technology, The Netherlands and Senior Technical Advisor at TNO-Holst Centre in Eindhoven, The Netherlands After his MSc from Utrecht University and PhD at Twente University in The Netherlands, he continued his career in catalysis with ExxonMobil in Baton Rouge, USA (1980-1982). In 1983, he joined Philips Research (since 2006: NXP) in Eindhoven, The Netherlands, to work on thin-film technology for III-V and Si semiconductors and for soft-magnetic materials. From 1997-2009 he led a team on 3D passive Si-integration. For this work he received the Bronze Award for ‘NXP Invention of the Year 2007’ and became NXP Research Fellow. In 2007 he became part-time professor at TU Eindhoven. In 2009 he joined a team at TNO Eindhoven specializing in spatial ALD and ALE. In 2014 he became Fellow of the Electrochemical Society. Fred is co-/author of 200+ publications (h-index: 33), 5 book chapters, 35 granted US patents, and co-/editor of 40 conference proceedings on semiconductor processing. Fred has been or is active in organizing committees of several conferences (Materials Research Society, Electrochemical Society) and is a member of the SEMI Europe Semiconductor Technology Programs Committee. Topics of interest: ultrathin-film technology, plasma processing, spatial ALD, reactive ion etching, 3D passive and heterogeneous integration, RTP, microsystem technology, Li-ion micro-batteries, sensors, displays and EUV optics lifetime.

Front-to-Back Alignment and Metrology Performance for Advanced Packaging

Kenyon, Gareth
Senior Applications Engineer
Ultratech

Abstract
Foundry customers and makers of leading-edge devices have established TSV for next-generation 3D and 2.5G packaging. Scaling the diameter of TSV’s is a major driver for improving system performance and cost but requires tighter back-to-front overlay. The transmission of IR wavelengths through silicon is utilised for embedded feature alignment and subsequent metrology. IR alignment can also be used for die to wafer, wafer to wafer bonding and photonics applications that are gaining in traction. Via Last applications enable distinct advantages for process integration, minimising the impact on BEOL processing and removing the requirement for TSV reveal processing. The Via Last TSV process introduces a requirement for lithography alignment, typically through thinned silicon to embedded targets. Performance enhancements can be realized by scaling TSV’s and landing pads, creating a critical parameter for overlay. In contrast, photonics devices require front alignment through full thickness silicon to marks on the back surface to a high degree of tolerance. The lithography system used in this investigation has a top IR alignment package with wavelengths that support back-to-front side alignment and metrology applications through full thickness 300mm silicon wafers. This paper details system methodologies used for both alignment and overlay metrology including routines to diagnose and compensate for measurement error due to focus and for Tool Induced Shift (TIS), critical for determination of system measurement error. We also discuss alternative use cases borne from the development including die-to-wafer misalignment. The in-line optical registration data was then correlated to detailed electrical measurements performed on the same wafers at the end of the process to provide independent assessment of stepper self metrology accuracy. Long term experimental overlay data was collected to determine robustness and repeatability of experimental wafer lots over a two month period.

Biography
Gareth is a Senior Applications Engineer based in Scotland, supporting customers worldwide. He has been employed with Ultratech for 26 years with an active involvement in the semiconductor industry for some 35 years, observing plenty of changes in that time! He has authored numerous publications on lithography & process technology. A graduate of Glasgow University, Gareth achieved an MBA with merit. When spare time permits, he is a keen golfer with a passion for Highland pursuits such as hiking and whisky.

Future Directions for Phosphorescent OLED Displays

Hack, Mike
VP of Business Development
Universal Display Corporation

Abstract
OLED displays are now in commercial production for a range of products from cell phones, tablets, UHD TV’s, and newly emerging applications such as AR/VR headsets and wearable devices. OLEDs offer excellent visual performance, and through the use of phosphorescent OLED (PHOLED) technology, lower power consumption than AMLCDs. OLEDs possess novel features such as transparency and flexibility, which will further increase their market potential over the next few years, and provide a much greater differentiation from current technologies. UDC is a pioneer in the development and supply of phosphorescent OLED technology and materials for both display and lighting applications. In this talk we will review the current status of OLED technology and discuss its potential for exciting new products over the next few years. In addition we would like to report on our recent work to develop a solvent-less, mask-less printing technology for depositing patterned small molecule organic materials to manufacture large area side by side R-G-B OLED displays. Commercial manufacture of large area (TV), side-by-side RGB OLED displays is currently challenged by lack of a suitable methodology for the patterned OLED deposition. Fine metal masks used for mobile OLED displays have not been proven to scale to greater than Gen 8, and scanning smaller shadow masks across a large area has not provided acceptable yield. Inkjet technology has been in development for many years and has yet to provide sufficient performance for volume manufacturing. Organic Vapor Jet Printing (OVJP) has been developed to print patterned OLED layers for large area displays, while avoiding issues arising from the use of fine metal masks and use of solvents. In this presentation we outline how we are ensuring that our PHOLED technology meets the ever more demanding performance requirements of future products, and we will outline how our technology can further improve their performance and lower cost.

Biography
Dr. Michael Hack, is Vice-President of Business Development at Universal Display Corporation. He is responsible for developing and commercializing advanced high efficiency next generation OLED products, with a special focus on flexible display applications and solid-state lighting. Prior to joining UDC in 1999, he was associated with dpiX, a Xerox Company, where he was responsible for manufacturing flat panel displays and digital medical imaging products based on amorphous silicon TFT technology. Dr. Hack received his Ph. D. degree from Cambridge University, England in 1981 and in 2007 Dr. Hack was elected a Fellow of the Society for Information Display. In 2014 Dr. Hack was nominated to serve on the board of the U.S. OLED Lighting Coalition to promote the advancement and commercialization of OLED lighting.

GaN power HEMT reliability research within the POWERBASE ECSEL project: from failure physics to industrial evaluation

Zanoni, Enrico
Professor
University of Padova

Abstract
The POWERBASE project (“Enhanced substrates and GaN pilot lines enabling compact power applications”, 2015-2018) is an EU ECSEL project aimed at demonstrating reliable enhancement-mode GaN-on-Si power technologies, including new engineered substrates, improved materials and optimized device structures. Within POWERBASE, a significant effort has been devoted to the study and demonstration of device reliability, as failure modes and mechanisms of GaN power devices were initially still unknown and testing methods and tools had Si power devices as unique reference. POWERBASE greatly helped in developing an evaluation methodology specifically tailored for GaN: it promoted a detailed study of device failure physics, leading to the derivation of acceleration laws and to the industrial implementation of systems and tools for the assessment of GaN HEMT reliability. Origin of dispersion effects has been identified by means of pulsed and transient characterization of dynamic Ron, and improved devices have been fabricated, showing zero dynamic Ron both at 600 V DC, 150°C and under 20 A hard-switching conditions. Backgating and drain-substrate vertical breakdown effects have been studied, and mechanisms of leakage current have been identified. Due to high electric fields inherent to power switching operation, main failure mechanisms include time-dependent breakdown (TDDB) of the p-gate and of the drain-substrate epi layer, while hard switching may induce hot-electron degradation resulting into on-resistance increase and threshold voltage shift. A lifetime of 55 years 100 ppm (15 years 1 ppm) @125°C has been demonstrated for production-level 70m devices (a 3 X safety margin with respect to JEDEC standard for Si devices). Devices adopting a Schottky contact over the p-type gate can survive 10 years at 150 °C, VG=6.4 V without undergoing breakdown. Concerning GaN-on-SOI devices rated for 200 V operation., a 10 years lifetime was reached at 470 V, 175°C.

Biography
Enrico Zanoni is professor of Microelectronics at the Department of Information Engineering of the University of Padova and a IEEE Fellow. He and his group are involved in research on the characterization, modeling and reliability of Gallium Nitride electronic and optoelectronic devices since 1999. The facilities of the microelectronics research group at the University of Padova include a laboratory for the DC, rf and pulsed characterization of GaN HEMTs, high-voltage current Deep Level Transient Spectroscopy, accelerated testing in a wide range of environmental conditions, failure analysis using electroluminescence spectroscopy and microscopy techniques, AFM and electron microscopy. Recent studies on GaN material and devices at the University of Padova include the analysis of the effects of material defectivity and deep levels on GaN HEMTs, the correlation with dynamic on-resistance measurements, the study of breakdown mechanisms, the analysis of the reliability and of the physical failure mechanisms of GaN LEDs and lasers. Enrico Zanoni is coauthor of more than 500 publications on the modeling and reliability physics of silicon and compound semiconductor devices and 4 patents.

From Data to Disruption - How Tech Talents shape our world

Böhler, Dominik
Head of Entrepreneurship & Tech Education
UnternehmerTUM

Abstract
Today's technical talents habe an immense power to customize products & services at very low costs. How can we harness their motivation and skill to shape the world we want to live in?

Biography
Dominik is Head of Entrepreneurship & Tech Education at UnternehmerTUM. He is responsible for the entrepreneurial and technology-oriented teaching activities for students. This includes curricular courses (Tech Talents) and personal development programs (Manage&More) at TUM and beyond. Focal fields are personality development, design thinking, technology development, and business modeling. Dominik and his team put emphasis on developing new methods in teaching and delivering prototypes in a flipped classroom setting. He received a diploma in business administration and a PhD in information systems from the University of Erlangen-Nuremberg (FAU).

Organic Nanofibers as Next Generation Chemical Sensors for Real-time Process Monitoring

Later, Douglas
President and CEO
Vaporsens, Inc

Abstract
Early detection of gas phase chemicals can ensure product integrity, and human safety. New types of chemical sensors are being developed that are sensitive, selective and rapid for direct vapor detection of hazardous chemicals. These next generation chemical sensors are based on novel organic nanofiber materials that demonstrate photoconductive and chemiresistive responses to surface adsorption of chemicals. The nanofibers are prepared via self-assembly of building-block, core molecules that are uniquely functionalized with a variety of tail and head groups that enable sensitive and selective binding and electron transfer interaction with different chemical analytes. When placed on a substrate, nanofibers form a porous super-net structure with large surface area and high porosity that can capture target molecules from the air through molecular diffusion and surface adsorption. Upon capture the electron density associated with the nanofiber structures can either increase or decrease resulting in an observable change in electrical conductivity that signals a detection event. For enhanced selectivity nanofibers of different chemical functionality can be deployed in sensor arrays. In addition to selectivity, the nanofiber sensors are also highly sensitive. Certain chemical species have been detected at the low parts per trillion (ppt) level. Nanofiber sensors are particularly sensitive to amines, aldehydes, volatile organic compounds, and toxic industrial chemicals. Vaporsens, Inc. has developed autonomous nanofiber chemical microchip sensors and sensor arrays that can be deployed in small portable detectors and/or fixed distributed networks. Nanofiber chemical sensors can deliver lower limits of detection and faster response times than other commercially available chemical sensors.

Biography
Douglas Later is a business leader and Ph.D. analytical chemist with 30 years of experience in both small and large businesses, including several high-tech startup companies. Doug's corporate leadership roles and experience are in the areas of business development, research and development, design and engineering, manufacturing, quality assurance/quality control, regulatory compliance, customer service, marketing, and sales in analytical instrumentation and chemical manufacturing settings, as well as a service laboratory environment. His experience also includes international and national expertise in collaborative research and development, engineering, technology licensing, distributor agreements, marketing, and joint-venture business development. Dr. Later has proven communication skills with more than 250 technical and business publications and several hundred technical and business presentations in the various fields of chemistry and biology including book chapters, journal publications, published proceedings, government reports, regulatory methods, as well as conference, seminar and symposia presentations. He has also been a principal investigator and project manager of government and commercial grants and contracts from federal agencies such as the U.S. Department of Defense, National Science Foundation, U.S. Environmental Protection Agency, U.S. Department of Agriculture, U.S. Department of Energy, U.S. National Institute of Health, and U.S. National Cancer Institute.

A modular and scalable approach for autonomous driving

Wang, Kai
Director, ADAS Technology
Visteon

Abstract
Technology development drives the realization of autonomous driving. Complexity, diversity and cost-efficiency are the main challenges. A platform with modularity and scalability is key to shorten time to market and to enable future reusability.

Biography
As director of ADAS technology, Kai Wang is responsible for providing overall leadership in ADAS Architecture, establishing and maintaining technology roadmaps and representing all key technology disciplines in Visteon. He is one of the key contributors of DriveCore^TM concept which is a unique, open, scalable centralized domain controller for autonomous driving. Before DriveCore^TM, he was system architect and key contributor of SmartCore^TM, the industry-first automotive grade cockpit domain controller solution offered by Visteon. Before joining Visteon, he focused on core R&D area in mobile communication, connectivity and ASIC design in world leading technology companies, such as Nokia and Datang.

One-Shot, nm-precise metrology for in-line applications

Taudt, Christopher
researcher/PhD student
Westsächsische Hochschule Zwickau

Abstract
The manufacturing of power chip technologies, semiconductors and thin-film structures demand quality, precision and reliability regarding the manufacturing processes. Therefore, appropriate in-line ready, integrated and fast characterization methods are required. One of the key requirements for such a system is the ability to gather e.g. precise topography data without the need of mechanically moving parts in order to ensure a fast data acquisition and minimal uncertainties. Within this work an alternative approach based on a white-light interferometer is presented which is designed to comply with these requirements. The interferometer is equipped with a supercontinuum white-light source and defined dispersion over the given spectral range. Due to the known dispersion characteristics, it becomes possible to calculate the surface profile with nm-precision from the phase-varied spectral data. In a two-dimensional approach the surface profile is encoded in one dimension as spectral modulations (z-coordinate) while the second dimension holds information about the spatial distribution of the profile (y-coordinate). The talk explains the data analysis model, calculations of theoretical resolution as well as the experimental setup and its results. Experimental results are presented from samples such as a precision height standard, Si-wafers, MEMS pressure sensors and spin-coated polymer layers. It could be shown that the resolution in the z-coordinate during the experiments was in the order of 2 nm while the resolution in the y-coordinate was in the range of 5 µm. The results of the interferometric measurements where furthermore evaluated with other techniques such as a confocal scanning microscope. Additionally experiments under varying temperature conditions proved a high stability with only 0.15 nm/K drifts. The interferometric method has advantages in fast, in-line metrology applications as it has shown high accuracy and robustness during different experiments.

Biography
My name is Christopher Taudt. I`ve received a Bachelor’s degree in Mechanical Engineering from the Institute of Technology Sligo, Ireland as well as a diploma degree in Mechanical Engineering from the University of Applied Sciences Zwickau, Germany. Furthermore, I successfully completed a research period in the USA (University of Pittsburgh) and did freelance work in programming for the automotive industry. Currently I’m a PhD student at the University of Applied Sciences Zwickau and the Technical University Dresden, Germany. Additionally, I`m a team manager at the Fraunhofer Application Center for Optical Metrology and Surface Technologies in Zwickau, Germany. My main working area is optical metrology, especially low-coherence interferometry. In this research area I’m mainly interested in the characterization of materials such as semiconductors and polymers during the different processing steps. This can include topographic, optical and other properties of the aforementioned materials. One of the most important aspects in my research is the strong cooperation with industrials partners in national and international projects.

The cultural transformation of X-FAB to become a customer oriented company

Schoder, Henryk
Vice President Human Resources
X-FAB Group

Abstract
In 2014 X-FAB started a global journey on a cultural transformation process to become a true customer oriented company. To show and live customer orientation as a core Value of X-FAB a comprehensive workshop program (Vision & Values Events) with each employee at each X-FAB location was established as a basis that everybody understand the Vision and Values of X-FAB. During the workshops the focus was on everybody´s personal responsibility in the job to make X-FAB a customer oriented company. The results in our employee engagement survey from 2016 showed significant improvements in several areas compared to 2013 which can be seen as an indicator of the success of the program.

Biography
Henryk Schoder, X-FAB’s global VP HR, was born and raised in the Thuringian town of Jena, where he also completed his Masters in Psychology. Prior to joining X-FAB in January 2014, Henryk worked as HR Manager at Infineon’s Dresden site, as Recruitment Consultant in Brighton (UK), Singapore and Dubai as well as HR and IT Manager for Masdar PV.

The MEMS production challenge: How to manage an increasing MEMS production and complex R&D activities within a combined CMOS-MEMS foundry fab?

Herbig, Volker
VP BU MEMS X-FAB Group
X-FAB MEMS Foundry GmbH

Abstract
How the CMOS foundry business model runs is well understood: a process technology is developed, a corresponding PDK is created and given to customers, followed by the product development at their side. At this point many customers can be served at the same time. This helps to achieve a high level of fab utilization and to minimize costs and risks. This model does not apply exactly for MEMS – the MEMS business model is different. Process as well as product development are very mostly customer specific and take place simultaneously for different customers within a running foundry production fab environment. On the one hand this is the key to short time to market and to robust production processes as no extra industrialization stage is needed after technology development. On the other hand this is generating various special challenges. This presentation especially talks about those challenges the fab team has to address besides the ongoing CMOS and MEMS production: - tool dedication and tool stability / matching in relation to production and empty costs - advanced metrology concepts including PCM and automatic optical outgoing inspection - process engineering support model in complex and fast running MEMS development projects … and many more. These challenges can be mastered by a deep process understanding and good process integration schemes, both based on intensive collaboration of production and development departments.

Biography
Volker Herbig, VP BU MEMS at X-FAB, oversees all MEMS activities within the X-FAB Group. Before assuming his current role, Volker worked as Director Product Marketing at X-FAB. Previously he held also engineering, marketing and management positions at Siemens, Inkjet Technologies and Carl Zeiss where, among other activities, he developed MEMS inkjet print heads and was responsible for setting up a manufacturing facility for those. Volker Herbig holds a master’s degree in physics from Humboldt University, Berlin, Germany.

Wafer Foundry Solutions for Smart Mobility Systems

Muffler, Alexander
Business Line Manager Automotive
X-FAB Semiconductor Foundries AG

Abstract
This presentation will show the challenges seen from the viewpoint of a silicon foundry for analog/mixed signal devices developed and manufactured for Smart Mobility Systems. Smart Mobility Solutions require a wide range of semiconductor solutions. In addition to the main processing units and software solutions multiple sensor interfaces and actuator drivers are required in Smart Mobility Systems which are the interface to the analog world. These interface chips need to be designed on robust and highly reliable semiconductor processes. Such devices have to cope with the harsh automotive environments and often have to include high voltage, non-volatile memory (NVM) and extended temperature ranges on one chip. This needs to be considered not only already by the foundry at semiconductor process and NVM IP development stage but also during manufacturing in automotive certified semiconductor factories. To enable IC designers developing such high reliable products specific foundry support with simulation models which behave as close as possible to the real silicon, but also tools for lifetime calculation based on user defined mission profiles are available as well as memories with built-in ECC are just a few examples what the foundry has to offer in addition to a very close collaboration between the foundry and its clients to ensure highest possible quality with zero incidents during lifetime.

Biography
As Business Line Manager Automotive, Alexander Muffler is responsible for the development of product marketing strategies for Automotive semiconductor processes as well as NVM IP for integrated circuit technologies. Prior to joining X-FAB, he worked for Chartered Semiconductor as EDA Manager Europe. Earlier, Alexander worked as an ASIC design engineer at Thesys GmbH. Alexander has more than 25 years of semiconductor technology and design experience. He holds a Master’s degree in Telecommunication Engineering from the University of Applied Science in Konstanz, Germany.

Interpretation and Application of Test Socket and Probe Head Specification

Brost, Bert
Product Manager
Xcerra

Abstract
Decisions should be supported with verifiable and repeatable performance data. This is true when selecting contactors, test sockets, and probe heads for test. This intent of this paper is to describe and define the data used to specify contactors, test sockets, and probe heads for test. This includes the source methodology and process for developing the lab data describing the performance of contactors, test sockets, and probe heads for test. With this the paper will lead the way to interpret and apply the statistically predicted field performance of the test probe as qualified in a test lab. Presented will be lab data describing the performance of several mainstream probe architectures for contacting Wafer Level Chip Scale Packages (WLCSP). The goal of this paper is to create a common understanding of how to read, interpret, and communicate data for selecting the right probe technology for WLCSP test applications. The paper goes beyond the probes and speaks to other factors that contribute to the overall performance of the contactors, test sockets, and probe heads for test. For example, the probe head housing design and materials used are important aspects that need to be understood for optimized performance. The success of the data-driven probe selection approach is reliant upon the quality of the supplier data. The paper will describe the reports provided including the WLCSP Metrology reports. Focus Content: • Interconnect technologies for improved performance and reliability • The role of material, and material development for higher reliability • Metrology and inspection methods

Biography
Bert Brost Biography Bert is a Senior Product Manager for Xcerra Corporation. With more than 35 years of experience in backend test, Bert has held senior management positions with Johnstech International and Control Data Corporation. Bert started his career in engineering with Micro Component Technology (MCT) designing test electronics and later worked as an engineer for Sick Optik Elektronic GmbH. Bert holds several undergraduate degrees and a MBA from the University of St. Thomas, Minnesota.

Cockburn, Peter
Senior Product Manager - TCI
Xcerra Corporation

Biography
Peter Cockburn has worked in the ATE industry for over 28 years at Schlumberger, NPTest, Credence, LTX-Credence and now Xcerra. After developing real-time and GUI software for ATE systems, he moved into product marketing and launched several new SOC ATE systems and analog test options as well as providing marketing and sales support in USA, Asia and Europe. As Senior Product Manager of the Test Cell Innovation team, he is now responsible for defining and delivering complete test cells to customers that reduce cost, increase uptime and improve quality when testing semiconductors including pressure and motion sensors, microphones and wafer-level packages. He has an Engineering degree from the University of Southampton, UK.

Challenges of mounting magnetic materials in electronics

Müller, Jens
Coordinator Innovation Projects
XENON Automatisierungstechnik GmbH

Abstract
Automotive electronics will show an annual 2-digit growth until 2025. One driver of this development is the increasing number of sensors and actuators in vehicles. This is not only due to additional functions of driver assistance systems, but also due to the demand for lower-emission and more efficient drive systems. New sensor functionalities also require new or diversified sensor designs with partly new components and materials. Here, magnetic materials also play an important role. The results are heterogeneous systems, which require new manufacturing technologies. The classic back-end sensor packaging is facing new challenges. The processing of magnetic materials creates several problems. These are among other things the clean feeding of magnets and a damage-free handling. Adhesive technologies must be adapted to different materials, including a desired short curing time. Despite the processing of roughly tolerated magnetic materials, a high accuracy in the placement must be achieved. Furthermore, the automation concept should enable a high production rate with short cycle times and continuous data tracking during the packaging process. XENON has many years of experience in the development of product-specific equipment, especially for sensor and actuator mass production. In the context of an EU-funded project "IoSense", preliminary studies were carried out for special technologies to produce magnetic sensors, how process safety can be realized together with high quality requirements. Some results will be presented.

Biography
Dr.rer.nat. Jens Müller Studied Physics (including doctorate on CIGS thin film solar cells) in Germany and worked thereafter as postdoc in the field of X-Ray diffraction at NIST, Boulder USA. Work in the industrial sector included semiconductor reliability and reliability of thin film solar cells. Actual position at XENON Automatisierungstechnik GmbH includes work as project coordinator for the funding acquisition and supervision of R&D projects.

How battery pack evolutions create opportunities for power electronics companies

Rosina, Milan
Senior Analyst, Energy Conversion and Emerging Materials
Yole Développement

Abstract
The market for Li-ion batteries for e-mobility and stationary energy storage is strongly growing, driven mainly by electric and hybrid electric vehicles (EV/HEVs). According to Yole Développement estimates, for the largest Li-ion battery market segment - battery electric vehicles (BEVs) - the market value will reach almost $52 billion by 2023. There is no big technology breakthrough expected in coming years regarding battery cells. The product differentiation will be sought on the battery pack level, by optimizing the battery pack design and its components. The existing solutions from other applications will be modified to fit the EV/HEV requirements, such as low Electromagnetic Interference (EMI) issues and vibration resistance to vibrations. The bigger changes are associated with the battery pack voltage trends towards 800V for BEVs and towards 1,500V for stationary energy storage for grid applications. The use of higher battery pack voltage will impact the choice of electronic components in Battery Management System (BMS) and in car converters and inverters and battery chargers. Silicon IGBTs or SiC MOSFETs rated at 1,200V will be used with 800V vehicle battery packs. The electrical interconnections and connectors and safety devices such as fuses and contactors must also be adapted for higher voltages. The energy capacity of battery packs will continue to increase, resulting in needs for faster charging capability. Ultra-fast chargers providing charging power up to 350kW have already been developed. The power electronic components and systems rated for high currents will enable fast vehicle acceleration. The battery pack as the key element of an electric vehicle is closely interlinked with other elements such as inverters and converters, and motors. The synergies between different sub-systems and mechatronics solutions are sought more than ever, to obtain compact, lightweight and reliable solutions and to reduce the system costs.

Biography
Dr. Milan Rosina is a Senior Analyst for Power Electronics and Batteries at Yole Développement. Before joining Yole, he worked as a Research Scientist and a Project Manager in the fields of photovoltaics, microelectronics, and LED. Dr. Rosina has more than 15 years of scientific and industrial experience with prominent research institutions, an equipment maker, and a utility company. His expertise includes new equipment and process development, due diligence, technology, and market surveys in the fields of renewable energies, EV/HEV, energy storage, batteries, power electronics, thermal management, and innovative materials and devices.

Wafer for More than Moore applications is becoming a major market

Eloy, Jean-Christophe
President and CEO
Yole Développement

Abstract
Wafer demand (including MEMS & sensors, CIS, and power, along with RF devices) for More than Moore (MtM) reached almost 45 million 8-inch eq wafers in 2017. Wafer demand is expected to reach more than 66 million 8-inch eq wafers by 2023, with an almost 10% CAGR2017 - 2023. Numerous megatrend market drivers will contribute to MtM devices’ growth : 5G (wireless infrastructure & mobile), mobile (including additional functionalities), voice processing, smart automotive, and Augmented Reality/Virtual Reality (AR/VR), artificial intelligence. Regarding semiconductor material, although silicon is by far the most dominant, alternative non-silicon-based substrates like SiGe, GaAs, GaN, and SiC are increasing their importance within the MtM industry. Choosing the right substrate technology will strongly depend on the technical performance associated with the megatrends’s requirements, as well as the cost.The presentation will highlight the market trends and the impact on the wafer start for the different wafer substrates.

Biography
Jean-Christophe Eloy is CEO and Founder of Yole Développement, the "More than Moore" market research and strategy consulting company. Since 1991, he has been involved in the analysis of the evolution of MEMS markets at device, equipment and also materials suppliers’ level. Jean-Christophe Eloy is also board member in several organisations in Europe and in North America.

5G - Who has the most to win (and lose)?

Troadec, Claire
Division Director
Yole Developpement

Abstract
5G will totally redefine how the radio frequency (RF) front-end interacts in-between the network and the modem. Indeed, new radio frequency bands, sub-6 GHz, and mm-wave (as defined in 3GPP release 15) pose big challenges for the industry. However, with these challenges comes opportunity to disrupt the market’s leadership. LTE evolution has led to complex architecture in today’s mobile phones, mostly due to carrier aggregation. Meanwhile, RF’s board area and available antenna space have been reduced, leading to a densification trend with more handset OEMs adopting power amplifier modules and implementing new technics, i.e. antenna-sharing between LTE and WiFi. In the low frequency band, the inclusion of the 600 MHz band (for which T-Mobile recently acquired licenses) will pose new challenges for low-band antenna design and antenna tuners. 5G will add even more complexity, with new radio bands released in ultra-high frequencies (N77, N78, N79). Band re-farming (early bands are N41, N71, N28, N66, with more to come) with dual connectivity will also contribute to increasing constraint for the front-end. More densification in front-end modules will be required to enable new band integration, which is the approach followed by Broadcom with its innovative mid/high band module. On the sub-6 GHz side, the current front-end leaders (Broadcom, Qorvo, Skyworks, and Murata) have already begun adapting to these changes. Along with sub-6 GHz, the mm-wave front-end module will completely disrupt the front-end industry, representing a completely different technology mindset that could create a new path to high data-rate access. In our presentation, we will define and analyze the RF Front-End ecosystem for cell phone. We will provide market and technology trends and illustrate who has the most to win (and lose) with 5G.

Biography
Claire Troadec is Director of the Power & Wireless division at Yole Développement, part of Yole Group of Companies. These activities are covering power electronics, batteries & energy management, compound semiconductors and emerging materials, RF devices and technologies. Based on her valuable experience in the semiconductor industry, Claire is managing the expansion of the technical and market expertise of Power and Wireless team. Daily interactions with leading companies allow analysts to collect a large amount of data and cross their vision of market segments’ evolution and technology breakthroughs. Claire Troadec holds a Master’s degree in Applied Physics specializing in Microelectronics from INSA (Rennes, France). She then joined NXP Semiconductors, and worked for 7 years as a complementary metal-on-silicon oxide semiconductor (CMOS) process integration engineer at the IMEC R&D facility. During this time, she oversaw the isolation and performance boosting of CMOS technology node devices from 90 nm down to 45 nm. She has authored or co-authored seven US patents and nine international publications in the semiconductor field and managed her own distribution company before joining Yole Développement in 2013.