microDICE - TLS-Dicing Technology for Wafer Separation

Neubert, Ronny
Sales Manager Europe
3D-Micromac AG

Abstract
TLS-Dicing is a laser based cleaving method to separate brittle materials. TLS (Thermal Laser Separation) uses thermal induced mechanical stress. A combination of heating (by laser) and cooling (by a very small amount of DI water spray) induces mechanical stress pattern into the wafer. This mechanical stress field guides a well-defined crack through the brittle material. The cleave needs for initiation a small local defect, called I-Scribe. This scribe can also be used, to extend the range of applicable products, e.g. by removing metal from the street [1]. TLS-Dicing shows manifold advantages in comparison to mechanical sawing and ablative laser processes: The cleaving speed is up to 300 mm/s (mechanical sawing speed for SiC is 7 mm/s). The material is not affected by chipping - consecutively no particles are generated. The process causes no negative residual thermal impact or stress pattern on the device. In opposite to stealth dicing TLS separates the material completely in one pass over the whole vertical thickness. Even thin backside metal is separated at the same time without any delamination. TLS requires no limiting design rules and can also be applied with metal in the street by using a preparing laser step. These benefits make TLS the perfect dicing method for SiC-based products [2]. Hence the focus for process development was first on SiC. The presentation will give an introduction in TLS-dicin in general, followed by a case study for the dicing costs of a given SiC-wafer. It will be concluded with an introduction of the new generation of the dicing tool microDICE. [1] H.-U. Zuehlke, "Thermal laser separation for wafer dicing," in Solid State Technology, 2009. [2] K. O. e. A. Dohnke, "Comparison of different novel chip separation methods for 4H-SiC (Infineon Technologies AG)," in ECSCRM, Grenoble, 2014.

Biography
Ronny Neubert was born in 1975. He studied business informatics at Hochschule Mittweida. He joined 3D-Micromac in 2002. Now, Ronny is working as Sales Manager Europe. 3D-Micromac is one of the leading solution providers for laser micro machining.

Novel 3D real-time visualizations for industry

Wojcik, Henry
CEO
3D Interaction Technologies GmbH

Abstract
Today's hard- & software enable a new era of visualization even on conventional laptops and tablets: 3D realtime visualization solutions are the future state of the art for industrial applications and customers. Typical products are 3D- configurators, virtual exhibits and 3D-viewers as part of planning software, from small pumps to complete factories that are actually to be built. For instance, a physical exhibit cannot show different options and is not available anywhere/ anytime, particularly if it's gigantic, or not even built. With a conventional static picture or video, however, one is fixed to perspective and timeflow: One cannot interact, zoom inside, arbitrarily move around, just like we know it from the real world. That makes it often hard for end customers to understand technical products. Also, raw CAD (computer aided design) data requires complex software and hardware and is therefor not the right choice for marketing or standalone industrial solutions, e.g. a control panel. We use raw data that is typically available from construction (CAD). However, we then combine advantages of 3D computer game engines with those of video and computer graphics. Additionally we use our own software tools to achieve high performance (on simple hardware + mobile devices), interface access (SAP, ERP etc.), as well as partially automated CAD import. The resulting solution is, generally spoken, video and interactive real-time 3D model in ONE. The spacial, technical and visual understanding for end customers or equipment users is much higher, their involvement is higher and thus the presentation is more convincing, or the application is easier to handle, respectively. 3D-solutions are available at the place and the time desired by the end customer, and run on local or mobile devices, even plugin-free in the web. Also, the final software product may contain interfaces to the construction or data base of companies, which saves money.

Biography
Born in Dresden, Germany Age: 35 Education: Electrical Engineering, PhD in Semiconductor Manufacturing Technology Experience: 7 years R&D BEoL, 5 years in leading a software business (started with 4 people in 2010) Other: songwriting and artist performance (piano, voc)

In Situ, High Resolution 3D Metrology for Real-time Quality Control in Flexible Electronics

Novak, Erik
Director of Bus. Dev.
4D Technology

Abstract
As more flexible electronics products enter large-scale production, focus is increasingly moving from simply demonstrating technological capability towards higher yields, longer lifetimes, and superior performance. To improve profitability and market size of offerings, critical features that can affect performance must be monitored, including surface roughness, defect density, and defect size and slope. Ideally, in-situ metrology can be employed in roll-to-roll equipment to allow real-time process control of these key parameters. Barrier film permeability, circuit performance, and overall yield may all be better controlled via real-time measurements from within the roll-to-roll processing equipment. This paper will present a compact, low-cost, large-field 3D metrology module for in-situ measurements of flexible electronic substrates. The module is capable of sub-nanometer vertical resolution and micrometer-scale lateral resolution for accurate roughness and defect height determination . Substrates moving at up to 3m/min may be imaged with 2micrometer feature resolution. Modules can be arrayed to provide scalable areal coverage based on each customer's specific needs and are vacuum compatible, vibration-immune, and are unaffected by the film backside or roller characteristics. We will present data from a variety of samples measured while in motion and correlate results with off-line metrology systems of similar capabilities.

Biography
Dr. Erik Novak is Director of Business Development at 4D Technology. He has been developing instrumentation for precision metrology for more than 19 years in applications including displays, optical components, plastic films, MEMS, telecommunications, photovoltaics, and medical devices. He received his PhD from the University of Arizona Optical Sciences College in 1998. Erik has received four R&D 100 awards, holds numerous patents, and has more than sixty publications and book chapters related to surface measurement and industrial process control.

Modern robustness challenges in wind-scale power modules

Iannuzzo, Francesco
Professor
Aalborg University

Abstract
Reliability challenges in power electronics for modern wind power generation system are pointed out, together with state-of-the-art testing and modelling techniques adopted for robustness assessment of IGBT and SiC power modules under abnormal conditions.

Biography
Francesco Iannuzzo earned his M.Sc. (laurea) degree cum laude in 1997 and his Ph.D. degree in Electronics and Information Engineering from the University of Naples, Italy, in 2001, with a study on the reliability of power MOSFETs during diode operations. He is primarily specialized in the field of power device modelling. He has been Researcher since 2000 with University of Cassino, Italy, where he became Aggregate professor in 2006 and he is currently Associate professor since 2012. In 2014 he got a contract as professor in Reliable Power Electronics at the Aalborg University, Denmark, where he is also part of CORPE (Center Of Reliable Power Electronics, http://www.corpe.et.aau.dk). He is author or co-author of more than 90 publications on journals and international conferences. His research interests are in the field of reliability of power devices, including against cosmic rays, power device failure modelling and testing of power modules up to MW-scale under extreme conditions, like overvoltage, overcurrent and overtemperature. Dr. Iannuzzo was the Technical Programme Committee co-Chair in two editions of ESREF, the European Symposium on REliability and Failure analysis. He is a senior member of the IEEE (Reliability Society, Industrial Electronic Society and recently Industrial Application Society) and a member of ECPE (European Center for Power Electronics) and AEIT (Italian Electric, Electronic and Telecommunication Association). He permanently serves as expert and peer reviewer for several conferences and journals in the field, like: APEC, ECCE, ESREF, IECON, Microelectronics Reliability, IEEE Transactions on Industrial Electronics, Transactions on Industrial Informatics and Transactions on Power Electronics.

Kraxenberger, Manfred
VP
ABB Semiconductors

Biography
Manfred Kraxenberger is currently factory manager for ABB's BiMOS wafer fab and assembly line in Lenzburg, Switzerland. Manfred Kraxenberger studied physical engineering and started working as process engineer at Siemens Semiconductor Munich in 1986. Over the last 25 years, he has held several engineering and management positions in manufacturing as well as R&D at Siemens/Infineon/Qimonda and Globalfoundries. Prior to his current position he was in charge of ABB's Bipolar factory.

Silicon based devices for demanding high power applications

Kopta, Arnost
Head of BiMOS R&D
ABB Switzerland Ltd, Semiconductors

Abstract
This presentation gives an overview of future requirements and recent progress of silicon based semiconductor devices and packaging technologies for very high power applications. The first part provides an outline of future trends in the areas of power transmission and power consumption and the resulting requirements on device design and performance. The second part elaborates on the recent advances of power devices and the corresponding packaging technologies used in these high power applications.

Biography
Arnost Kopta is currently heading the BiMOS R&D Department at ABB Semiconductors in Lenzburg, Switzerland. In this position, he is responsible for development of high voltage IGBT and diode chips as well as the power modules where these chips are packaged. Arnost Kopta studied engineering physics at the University of Lund in Sweden and acquired a PhD dealing with IGBT short circuit ruggedness from the University of Bremen in Germany.

Best Cost Solution and Performance Improvements of Flip Chip Underfill by De-Void System

Chih Horng Horrng, Auger
Founder and President of AblePrint Technology Co.,Ltd (APT)
AblePrint Technology Co.,Ltd (APT)

Abstract
Authors: CHIH HORNG HORNG, CHUN AN LIN, CHAN LU SU, AblePrint Technology Company, Taiwan Abstract: With ever increasing needs for more I/Os and the miniaturization of electronics due to the increased use of handheld applications, flip chip packaging is encountering severe challenges as the pitch and gap are constantly shrinking. These challenges must be addressed in order to meet not only the higher reliability requirements but also cost demands, the so called Total Cost of Ownership (TCO). TCO not only includes aforementioned but also enhance process yield through decreasing process complexity and difficulties for mass production. APT foresees this trend and dedicated itself in offering a solution to address these technical difficulties. This paper describes de-void system, State-of-art Void Terminator System (VTS), achieves flexibility in managing its process of Capillary Underfilling(CUF), so that high performance and reliability standards for emerging products toward mass production. By using the unique features of the APT de-void system to cure the CUF even extremely large voids can be eliminated with excellent void free performance and very favourable productivity achieved with boosting up dispensing (UPH). Meanwhile, this paper also disclose how APT simplifies CUF flip chip assembly process by passing flux residue cleaning, carrier pre-baking and even plasma cleaning.

Biography
AUGER CHIH HORNG HORNG, is the Founder and President of AblePrint Technology Co.,Ltd (APT). Over 20-year semiconductor experience, he is an expert to work closely with its customers through a clear understanding of their needs and objectives, figure out the essential requirements, assess their needs and deliver the right solutions using a big picture approach. Prior to establish APT, he was the manager of POWERTECH TECHNOLOGY INC. in Taiwan responsible for process improvement and R&D research on advanced packaging. He holds a Master's Degree in Electrophysics, National Chiao Tung University.

NEW Wafer Handling Solutions for high vacuum and glovebox applications.

Maas, Andreas
Project Manager
ADENSO GmbH

Abstract
Substrate handling in vacuum environment often based on using carriers which means a lot of additional weight for the robot arm. Also substrates with large dimensions as like as FPD flat panel displays generates a high load for the handling robot. Oversized gate valves cause high investment cost and operating costs due to high volumes. Additionally a limited travel range of the robot arm restricts the design of the process areas. The presentation touches these challenges by the example of Adenso WHR Wafer Handling Robot solutions.

Biography
Andreas Maas is an expert in automation, handling and testing substrates and devices. He has extensive experience in the vacuum business, special purpose machinery manufacturing and semiconductor equipment.

Ainslie, Stuart
Director Business Development
Advantest Europe GmbH

Biography
With over 25 years experience in the semiconductor industry Stuart Ainslie has been with Advantest for 19 years and is currently Director of the business development group located in Munich. In Advantest Stuart worked as an applications engineer before joining the marketing group in 2000. Stuart originally studied Electronics and Electrical Engineering in his native Fife Scotland and in 2008 was awarded an MBA from the Open University (UK). Stuart is married with two children and lives in Munich.

Testing IoT devices, the next ATE challenge

Mancosu, Adriano
Business Development Manager, SoC Test Business Group
Advantest Europe GmbH

Abstract
The "Internet of Things" - IoT is becoming ever present in our lives. With this, we are also seeing a huge increase in semiconductor devices being developed and manufactured, specifically for this market. For semiconductor test, many of these devices pose new challenges, which need to be addressed by test solutions. Some of these challenges will be discussed. How Advantest's V93000 Single Scalable Platform is ideally prepared to address such new requirements will be presented.

Biography
Adriano Mancosu is business development manager in the SOC business group of Advantest. He has worked in the ATE industry for over 19 years, starting his career at Schlumberger. Over the years he held various different positions in application engineering and marketing. Adriano is a graduate in electronic engineering at the Politecnico di Milano, Italy.

Smart basestation antenna for next generation mobile communication

Meyer, Peter
Managing Director
Airrays GmbH

Abstract
Driven by the rise of smartphones and the mobile internet, the transmitted data volume is doubling every eighteen months while the revenue of the operators remains flat. Airrays addresses this problem with a game changing radio technology for mobile communication base stations. Instead of broadcasting a signal to a complete cell, Airrays antennas are focusing the radiated signal directly to the user leading to 10 fold lower radiated power. Additionally multiples of such beams can be created from the same antenna leading to a 10 fold better capacity of the cellular system. Airrays has found a unique modular approach to create these complex antennas which can be connected to the network via a digital interface. Airrays is planning to create, produce and sell complete antennas units or its key components to antenna manufacturers or cellular infrastructure provider. This new kind of base station antenna can already be used now but will ultimately replace current systems when the next generation mobile standard, 5G is deployed. This will become a multi-billion euro market. Airrays is currently in the seed phase and will create a first prototype within one year and a sellable product one year later. Revenue will be around 3 Million Euro in 2018 and reach more than 100 Million Euro in 2020 when 5G will start to be deployed. The Airrays team consist of serial entrepreneurs that have already done two other start-up companies in the field of wireless communication and have up to 25 year experience in this field as well as in semiconductors. These experiences founders are supplemented by three PhD graduates from the Vodafone Chair of the Technical University of Dresden. It is planned to grow the team to 30 employees within the next two years.

Biography
Before founding Airrays, Peter worked as managing director and VP of the Dresden Design Center at Intel Mobile Communications. He was co-founder and managing director of Blue Wonder Communications GmbH where he and his team developed leading edge LTE IP before the company was acquired by Infineon and later by Intel. Having held leading positions at Intel, NXP, and Philips, Peter brings more than 25 years' experience in wireless communications and digital signal processing to Airrays. He received his diploma and PhD both in physics from University of Göttingen in 1983 and 1987, respectively.

Toennis, Andreas
CTO
Aixtron SE

Biography
Andreas Tönnis joined AIXTRON in 2012 as Chief Technology Officer responsible for Product development later on adding Product Marketing. Since late 2014 he took over the responsibility for the New Technology business including OLED material deposition, Thin-Film Encapsulation and CNT/Graphene deposition solutions in addition to his corporate charter as CTO. Andreas came to Aixtron from the Silicon Valley where between 2001 and 2012 he held various executive management Functions at Mattson Technology Inc. including business responsibility for the Thermal Products Group. Prior to joining Mattson, between 1992 and 2001, he held different operational management responsibilities within Steag Electronic Systems in Germany and Austin, TX in the US. Andreas was awarded an MS degree in Chemical Engineering from University of Karlsruhe (KTI) and has gone through executive educational programs at Stanford Business School and USW in Germany.

COST-EFFICIENT OLED MANUFACTURING ENABLED THROUGH PROPRIETARY PROCESS TECHNOLOGIES OVPD® AND OPTACAP***

Kreis, Jürgen
Director Business Development
AIXTRON SE

Abstract
The ability of OLEDS for conformality, transparency, lightweight, just to name a few, enables applications, where such features are mandatory. Potential fabrication on plastic substrates further increases possibilities. In comparison to incumbent technologies such as LCDs and LED-based luminaires , OLEDs still are struggling with cost disparities. Being vulnerable to water and oxygen exposure, OLEDS additionally require barrier systems as part of the device architecture, which adds additional costs. AIXTRON has developed a number of proprietary technologies which simplify scale-up, increase throughput, and ultimately address lowering manufacturing cost. Two technologies shall be discussed in the presentation. Organic Vapor Phase Deposition (OVPD®) utilizes the advantages of an inert carrier-gas for the deposition of organic stacks based on small molecule materials. Originally developed by Prof. S. Forrest at Princeton University, OVPD utilizes inert carrier gas for material deposition. AIXTRON added its proprietary Close Coupled Showerhead® (CCS) technology and novel source technologies for efficient evaporation. These core components enable precise deposition with excellent thickness uniformity, high material utilization efficiency and throughput. The approach realizes cost advantages by scale of economies. The second technology to be discussed is about deposition of barrier films. The proprietary OPTACAP™ process yields SiNx-based thinfilm exhibiting high flexibility and excellent barrier properties at very attractive manufacturing costs. The process yields low surface stress and the respective film shows high flexibility. OPTACAP™ utilizes a PECVD concept based on linear source technology, which allows for scaling towards large substrate size with sufficient throughput, thus further lowering manufacturing costs of OLEDs. We will provide an overview about the basic concepts of both technologies. Examples for scaling and shall be discussed.

Biography
Short CV Juergen Kreis - obtained a master degree in electrical engineering (Dipl.-Ing.) at Technical University of Karlsruhe (today: KIT), Germany in 1993 - obtained a master degree in business engineering (Dipl.-Wirt.Ing.) at Fernuniversitaet Hagen, Germany in 2006 - since 1993 he held several executive positions in international companies serving the flat panel display and electronics industry, for optical systems, metrology, and automation - 2010 joined AIXTRON SE, a world leading manufacturer for MOCVD equipment, as Director Business Development, with special focus on the portfolio for organic material deposition solutions. He is responsible for worldwide marketing and sales of the respective systems. - since 1993 various publications and papers about the characterization of electro-optical devices, manufacturing and design of optical components and devices, numerical optimization of displays, computers and networks, process automation, et al.

Sensors for the Industrial IoT as an Opportunity for Electronics Manufacturers

Simmons, Thomas
General Manager
AMA Association for Sensors and Measurement

Abstract
The industrial Internet of Things (IIoT) combines global reach with directed action and control in the physical world, including for machines, factories and infrastructure. The past 15 years have extensively redefined B2C industries through the Internet. For the industrial sector, the coming 10 years will bring us an even more comprehensive evolution. The magnitude is rising from a billion interconnected persons to an additionally interconnected 50 billion machines. Associated buzzwords are Advanced Manufacturing, Smart Factory, Industrie 4.0, etc. Many challenges arise, including mastering complexity, adding new functionalities, supplying dependability and security, and simultaneously ensuring real time capability. Mastering these often requires additional and new types of sensing. The World Economic Forum has identified availability of suitable sensors as an important field of action towards a viable IIoT. For years, AMA Association for Sensors and Measurement has been registering a growing need for industrial sensors. Global demand for sensors is doubling every five years. The industrial sensor and measuring sector's revenue is growing by more than 6% annually. German members of this sector enjoy an excellent reputation worldwide and are quite successful, with a global market coverage exceeding 30% by revenue. On the technical side, one observes a trend towards new sensors with increased integrated functionality, complex real time signal processing, high resolution fast AD converters, digital signal processors, highly integrated electronic components, and more. The sector invests roughly 10% of its revenue in research and development. At the same time, specialized foundries now provide manufacturing services for sensing elements, allowing more small and medium-sized enterprises to successfully engage in sensor manufacture. In all, sensing and measuring technology provides excellent opportunities for innovators. We encourage you to actively participate.

Biography
Dr. Simmons was born 1958 in Jugenheim Germany. He studied physics at the University of Texas at Austin and at Freie Universität Berlin, where he earned his doctorate in experimental solid state physics. After a post-doctoral position at the Fritz Haber Institute of the German Max Planck Society, he has held several industrial positions, including founding and CEO of Novaville AG, a digital distribution provider, and building up and heading international sales activities for Aktiv Sensor GmbH. In 2007 Dr. Simmons accepted his position as general manager of AMA Association for Sensor Technology.

An Intelligent Temperature Sensing Application Circuit in Eradicating Temperature Induced Variance on Performance Board Hemispheres

Landicho, Lloyd Charles
Test Development Engineer/ Professor-Lecturer
AMS-Asia

Abstract
This paper presents a circuit application of a temperature transducer. An application circuit used to sense the variance of temperature level between performance board hemispheres. The temperature level is linearly converted into micro-amperes (uA). Moreover, the circuit design has the capability of sensing the variance between hemispheres where different test sites were mapped. A site to site variance was observed due to heating of performance board used in 150 degree Celsius testing. This event was solved with the aid of equipoise temperature sensing between performance board hemispheres. The application circuit provide the most precise feedback through its 1uA/K linearity, and display the most accurate result to be used in monitoring parametric readings. This application will use an on-the-fly performance board temperature calibration. A threshold temperature was set to greater than 80 degrees Celsius. Once this threshold temperature is exceeded, the application should execute an on the fly temperature calibration to define a site-specific correction factor. A performance board checker also performs a thermal equilibrium check of about less than 0.1% before proceeding with 150 degrees Celsius testing. Through implementing the application circuit, performance board is being stabilized.

Biography
During Design for Manufacturability (DFM) consideration, temperature consistency is considered on performance board designs. This consideration is limited only up to certain temperature level due to characterized performance of the materials and components used during hardware design. However, due to uncontrolled heat transfer the resistivity levels of board design could be affected. The said resistivity level has a direct relationship on the current and differential voltage level during the manufacturing run. A deviation on parametric measurement was seen, when a certain Device-Under-Test (DUT) is exposed and soaked from a boiling point temperature up to 150 degrees Celsius. A drift on digital levels was observed and yield loss becomes gross. This causes an unexpected fall on unit per hour (UPH), which can be converted into a negative cost. On the other hand, the solution made on the said event was to have a precise and real-time feedback on board hemispheres temperature. Dictate the system on the hardware condition drift due to rise on board hemispheres temperature. Provide a stop and deliver a signal that would restore the equipoise ambient temperature expected on both hemisphere of the board.

Expertise in Mixed-Signal ICs Testing

Cantagrel, Pierre
Hardware engineer
Analog Power Lab

Abstract
Currently, because of the omnipresent breakneck technical development, we observe the surge of ICs complexity. Therefore, the necessity of efficient automated test equipment, able to provide an optimum broad spectrum of test, is revealed. In order to gain productiveness, the measurement methods need to be adapted to this market tendency. Owing to the application of a "customized rack", we are able to face automation challenges. Unlike frozen functionalities, this rack can be custom-made and reusable thanks to instrumentation modules. The added value of this solution is the capacity to test the Device Under Test directly on Evaluation module, and to automate the major part of mix-signal measurements. Furthermore, the friendly user interface allows the customer to use it independently, at his locations. Last but not least, Automation solutions developed by Analog Power Lab minimize the time allocated to the validation and reduce the cost due to stored generic sequences.

Biography
Pierre Cantagrel is an expert in electronic/micro-electronic development, hardware testing and validation. He has 12 years of experience in these domains. P. Cantagrel obtained his Bachelor of Science degree in Microelectronics in 2004, at POLYTECH'SOPHIA. He had been acquiring valuable skills in Electronics development in different high-tech companies. Afterwards, he joined Texas Instruments France as Mixed-Signal Validation Manager and works for major phone OEM's during more than 7 years. This strong professional experience enabled Pierre Cantagrel to co-found the company Analog Power Lab, an electronic laboratory in Sophia Antipolis. At Analog Power Lab, he manages full-validation IC's projects.

Smart Metering-Monitoring and Control

Dahlheimer, Bernd
Director Marketing
Anvo-Systems Dresden GmbH

Abstract
Smart Meter - Monitoring and Control In our everyday lives smart metering, is becoming more and more important, very much like the Internet of things (IoT). So far the focus has been on electricity meters, however, other applications and use models are evolving quickly. In addition to other meters, such as water, gas or heat meters, there is also a wide range of data loggers. All these systems require safe and secure data storage. In case of power fluctuation, or even power loss, the data must be saved securely. This challenging requirement can be addressed with nvSRAMs from Anvo-Systems Dresden, the best choice for very fast and secure data storage. These nvSRAMs can, even at complete power loss, automatically save configuration information, the last system state, or processed data from sensors or actor nodes and concentrators. The technology of these devices and possible use models with highly reliable nvSRAM Memories from Anvo-Systems Dresden will be discussed.

Biography
Bernd Dahlheimer Director Marketing, Anvo-Systems Dresden Bernd Dahlheimer has more than 20 years experience in international sales management, tactical and strategic marketing, business development and business unit management in high tech companies in the fields of Semiconductors (ASSPs, sensors, mixed signal non volatile memories), Optoelectronics, LED technology and Solid State Lighting. After completing his Masters of Electronics Engineering in Darmstadt, Bernd Dahlheimer´s professional experience includes working for Jermyn, a semiconductor distributor (today part of Avnet www.avnet.com ), Hewlett Packard´s Semiconductor Products Group www.hp.com , Agilent Technologies www.agilent.com and ZMD www.zmdi.com . In his role as Marketing Director for Anvo Systems http://www.anvo-systems-dresden.com Bernd Dahlheimer´s extensive knowledge of the semiconductor markets combined with his international management experience and network will be instrumental in rapidly achieving business results for Anvo Systems in the non volatile memory market, which is getting more and more important to fulfill today´s and future requirements for data and system security.

Sampling Optimization For 450mm Wafers

Kaizerman, Idan
Machine Vision Group Manager
Applied Materials

Abstract
The challenge of the inspection companies is to maintain roughly the same per-wafer inspection or defect review time for 450mm wafers as for 300mm wafers. Since the only reason for 450mm conversion is reducing manufacturing cost, if wafer review time will increase with the wafer size - the 'cost reduction' challenge will not be achieved. One of the obvious solutions is simply trying to speed-up review time. This solution however almost always requires sacrificing other parameters, such as repeatability and sensitivity, in exchange for speed. However, previous trends in this industry showed that in order to achieve sensitive process control, repeatability and sensitivity must improve, not worsen. One can think of additional methods for maintaining the current time for defect review; Optimization of the sampling plan (explained below) is the most appealing one, as no additional investment in hardware is needed. Somewhere along the process chain, some of the wafers may be delivered temporarily to an inspection or review unit. This unit reviews defects and sends the data to the host. Usually, this unit has no function in wafer processing; it is there merely to ensure that the process is working correctly. Process control is based on sampling, there is no need to review every defect to maintain control. Today the sampling plans (e.g., how many review locations represent a wafer and how many wafers represent a lot) are fixed, and are set off-line according to the worst case process step sensitivity. By exploiting the fact that these units already collect data by themselves, sometimes a great deal more than is needed by the host, they may have the ability on their own to decide how frequently sampling should be performed, by introducing a sampling optimizer module inside the defect review unit itself. The goal of this work group is to demonstrate, by incorporating statistical algorithms into review tools, a smart in-tool sampling mechanism which will improve overall throughput.

Biography
Idan Kaizerman is the manager of machine vision algorithms group in Applied Materials Process Diagnostics and Control business unit. Idan, who holds a M.Sc. in Electrical Engineering from Ben-Gurion University, joined Applied Materials in 2007 and filled a number of key roles in the development of various detection and classification algorithms for wafer inspection and defect review tools. Idan is now managing the group responsible for development of computer vision algorithms combining state of the art procedures for image processing and machine learning. He is also responsible for academy collaborations in these domains and leads the Metro450 sampling optimization work group.

Wafer Metrology in the 300 - 450 mm / sub 10 era

Naftali, Ron
CTO
Applied Materials

Abstract
Wafer inspection tools are used to detect the location of defects on silicon wafers during process development, ramp and high volume manufacturing. The goal of this inspection is to control process stability and improve yield. A significant area of the wafer is scanned by an imaging system which may be based on optical (DUV) or electron (E beam) technology. These systems are characterized by their sensitivity to defect detection, driven by resolution, and by their productivity, driven by throughput. The drive for high productivity process and process control equipment (e.g. 450 mm silicon wafer diameter) drives the development for high throughput wafer inspection tools. At the same time the required defect detection resolution has decreased towards the sub 10 nm device manufacturing node. The presentation will discuss the challenges associated with high throughput and nanometers scale resolution requirements for next generation wafer inspection tools. Some of the challenges include: a faster motion system; smarter sampling methods; a rapid computing platform and new imaging methods.

Biography
Ron Naftali, chief technology officer of Applied Materials Process Diagnostics and Control Group holds a bachelor of science degree with honors in electrical engineering, a bachelor of arts degree in physics and a master of science degree in electrical engineering from the Technion-Israel Institute of Technology. Ron is an Applied Materials Fellow, a title he has earned for his multiple breakthrough product developments. He holds 58 active patents and patent applications worldwide, including 29 U.S. patents.

Latest trends in subfab energy consumption reduction and emissions control

Neuber, Andreas
Managing Director Subfab and Environmental Systems
Applied Materials GmbH

Abstract
The availability of energy-saving technologies and products can have a significant positive impact, and they are widely recognized as useful methods to reduce energy consumption. Variable-frequency ICs to drive pump motors are one example. Another is the synchronization of fab and subfab operations to optimize subfab resource consumption with no risk to the manufacturing process or throughput. Energy savings will assume an even greater importance in the years ahead because the requirements of many regions in these challenging times dictate that power and resource consumption, and emissions, must stay at an even level as production capacity increases. To make matters worse, this is occurring as cost-reduction pressures in all phases of semiconductor manufacturing are stronger than ever. The good news is that energy conservation, reduction of greenhouse gas emissions (GHGs) and cost reductions do not necessarily contradict one another. For example, the high operating costs to effectively abate environmentally harmful perfluorocarbon (PFC) gases can be reduced by using fab / subfab synchronization systems to reduce resource consumption and generation of typical by-products such as NOx and VOC.

Biography
Andreas Neuber, PhD Head, Subfab & Environmental Products, Equipment Products Group Applied Global Services EDUCATION University of Technology Dresden, Diploma (MS)/Dipl.-Ing./PhD/Dr.-Ing Chemical Engineering PROFESSIONAL EXPERIENCE 2011 - Today Applied Materials Head, Subfab & Environmental Products, Equipment Products Group 2008 - 2011 Applied Materials, Managing Director Environmental Services 1991 - 2008 M+W Zander FE, Vice President Manufacturing Technology, Environmental engineering and contamination control consulting 1986 - 1990 University of Technology Dresden, Institute of Chemical Engineering, Research Assistant

Sprey, Hessel
Manager cooperative programs and university contacts
ASM International

Biography
Hessel Sprey received his M.Sc. in experimental physics from the University of Leiden (The Netherlands) in 1989, and joined ASM in 1990. He has been active in equipment and process R&D at various ASM locations for almost all of ASM product lines, since 1996 in project and team leader positions. He has been project and workpackage leader for several European projects, is (co-)author of more than 60 scientific papers and conference contributions on deposition processes, equipment and applications, and holds 10 patents and patent applications. He is currently responsible for the coordination of ASM's activities in European cooperative programs and for university contacts.

Selective Deposition as Enabler for Shrinking Device Dimensions

Haukka, Suvi
Executive Scientist
ASM Microchemistry Ltd.

Abstract
The shrinking device dimensions in semiconductor manufacturing call for new innovative processing approaches. One of these considered is selective deposition which has gained increasing interest among semiconductor manufacturers today. Selective deposition would be highly beneficial in various ways, for instance, it would allow a decrease in lithography and etch steps reducing the cost of processing and enable enhanced scaling in narrow structures making bottom up fill possible. Chemical vapor deposition (CVD) and especially atomic layer deposition (ALD) as very surface sensitive techniques are considered enabling techniques. In most of the selective deposition schemes of today a passivation is used for the surface on which no deposition is desired. The most known method is to use SAM´s (self-assembled monolayers) which are silicon compounds with long carbon chains. Depending on the type of SAM one can passivate either the metal oxide, metal or silicon surface. Thus, the use of SAM allows for instance a metal layer be selectively deposited on metal surface over dielectric surface. Furthermore, it has been shown that without SAM a dielectric layer can selectively be deposited on hydrophilic polymer over a more hydrophobic polymer. In this paper, the various selective deposition approaches and passivation means are reviewed. In addition, results from the selective deposition of metal on metal over dielectric surface in a Cu capping application and from selective strengthening of DSA (direct self-assembly) layers are presented.

Biography
Dr. Suvi Haukka is currently employed as an Executive Scientist for ALD applications for ASM International, and she is based in Helsinki, Finland where the R&D site of ASM, ASM Microchemistry is located. For over twenty years she has worked in various capacities, including Research Scientist, Catalyst Technology Manager, Process Development Manager and R&D Manager, which all have been related to atomic layer deposition (ALD). In particular, her work has focused on ALD and applications of it for semiconductor equipment, processes, and devices as well as development of ALD apparatus. Over the course of her career, she has been an author on over 70 scientific papers, primarily concerning ALD processes, applications and apparatus. In addition, she is an inventor of more than 100 ALD patents and patent applications in the field of semiconductor fabrication. In 1994 Suvi Haukka earned a Doctor of Philosophy degree from the Laboratory of Analytical Chemistry, University of Helsinki, Finland.

Lithography roadmap to enable cost effective shrink for future technology nodes

Jenkins, Peter
Vice President Marketing
ASML

Abstract
Lithography has been a key enabler of Moore's law through continued progression to shorter wavelengths, higher NA optics and increased productivity. This presentation will address ASML roadmap for continued productivity scaling, HVM introduction status of the next wavelength, 13.5nm EUV, together with the opportunity for extension to higher NA, and resulting outlook for continued scaling of cost/function per Moore's law.

Biography
Peter Jenkins joined ASML in 1991 where he has held various product and commercial management positions including international assignments to South Korea in 1996 and Hong Kong in 1999. Mr. Jenkins returned to The Netherlands as Vice President of Marketing in 2005. Prior to joining ASML, Mr. Jenkins gained extensive experience in Lithography and Semiconductor processing at LSI Logic and Plessey Research in the United Kingdom. Peter studied BSc Economics at Bath University, England.

Imager Testing, Solutions from Wafer Level Test up to Camera End of Line Testing

Verhoeven, Marcus
Co-Founder and Managing Director
aSpect Systems

Abstract
Testing is not a negligible cost factor in the image sensor world. Compared to other semiconductor products it requires on top of the mixed signal test system optical resources which yield into much more complex test setups. The ATE market offers solutions for consumer imager with significant volume, but these test systems are a cost overkill for niche markets and products with medium volume. aSpect Systems offers cost effective test solutions for all types of high end imager and medium volume camera chips. The presentation will give an brief overview about the necessary core components for image sensor testing (Test Head, Illuminator and Software). Further it will contain test setup examples for Wafer-, Final- and Camera End of Line Testing.

Biography
Marcus is Co-Founder and Managing Director of aSpect Systems. aSpect is a vendor for image sensor test services (wafer- & final test), test- and illumination equipment, prototype package- and camera development, as well as production equipment for lens adjustment. Marcus started his professional career as a lab assistant in 1987 at Spectro Analytical Instruments, a vendor for optical spectrometers. He studied physics at the University of Wuppertal. From 1998 he headed for five years the semiconductor test floor of Silicon Vision. In 2003 Marcus founded together with Philipp Gottesleben aSpect Systems GmbH.

A New Reliable Adhesion Enhancement Process for Directly Plating on Molding Compounds for Package level EMI Shielding

Kim, Kwonil
Senior R&D Engineer
Atotech USA Inc

Abstract
Plating on molding compound is a relatively new field which could open up new package designs. One major application is conformal self EMI shielding of ICs (package level shielding). This is currently done mainly by metallic cans, however, this technique also increases the space requirements and reduces flexibility of component layout on the PCB, that would not be suitable to handset products. An alternative and more space saving approach is "Conformal Self EMI Shielding (package level shielding)". Also this metal layers can perform not only for EMI shielding but also for good heat spreader, compared to metal cans. A popular method to provide a metallic seed layer for "Conformal Self EMI Shielding" is sputtering and conductive paste, however, in order to make it more cost effective and feasible for mass production; there is a need for classical electroless plating metallization along with adhesion enhancement process. While in some instances conductive paste and sputtering metallization will provide adequate adhesion - it has the technical drawbacks of poor sidewall coverage and limited metal layer thickness that would not fulfill for lower frequency noise shield. As a result, scale- up for mass production is relatively difficult and costly. Classical electroless and electrolytic plating metallization are much more desirable but have been so far limited by insufficient adhesion by existing chemical treatment. In this paper we will present a new approach, where components encased by molding compounds are directly coated with an electroless copper or nickel plating layer. By this method spatial requirements are minimized.

Biography
After receiving a bachelor degree for Metallurgical Engineering from Inha University in Korea, K.Kim joined MacDermid Korea as a technical service engineer for PCB industry plating in 2001. He joined Atotech Korea in 2004 and was in charge of technical sales of plating technology to organic interposer and mother board suppliers in Korea until 2007. He joined Surface Technology Team of Atotech and developed 'Non-Etching Adhesion Promoter' in China until 2012. Currently he has been developing adhesion promoter for plating on molding resin materials since 2012 when he joined Molecular Adhesion Technology team of Atotech, located in USA.

Automotive Megatrends, Challenges and Solutions - an OEM Perspective

Abelein, Ulrich
Quality Manager, Semiconductor Quality & Analysis
Audi AG

Abstract
The field of automotive electronics went through an impressive change over the last 20 years. Starting from a purely mechanical system with some electric parts a modern vehicle turned into one of the most complex mobile electronic devices used today in our modern society. Electronics made cars safer, greener, more comfortable and easier to handle. Most innovations we have seen in vehicles over the last decade were either directly or indirectly enabled by electronics. This development lead to completely new challenges for the automobile industry. Electronics knowledge became a core competence for a car maker and semiconductors have a essential influence on overall quality targets. Treating innovation and quality as a unity is therefore absolutely necessary for the use of state-of-the-art technologies in automotive applications. The megatrends of the upcoming decade will even intensify these effects further. Car-to-X solutions, advanced driver assistance systems or e-mobility are just some examples of upcoming functions based on a highly integrated electronic systems. The realization of such complex systems under automotive conditions makes it necessary to move the unity of innovation and quality to the next level. This talk will give an overview of the challenges and chances of modern automotive electronics. It will highlight the general boundary conditions of the automobile industry with respect to electronics and their consequences for semiconductor development, qualification and manufacturing. Furthermore some new approaches to deal with current and future tasks in the field of high quality automotive electronics will be sketched.

Biography
Ulrich Abelein is responsible for semiconductor quality and failure analysis within the AUDI AG. His responsibilities include the Audi semiconductor failure analysis lab and the strategic development of the fields of qualification and quality strategies for automotive semiconductors as well. He studied microelectronics and economics at the Technial University of Munich and the University of Hagen respectively. 2003 he joined the group of Prof. Eisele at the University of the Federal Armed Forces in Neubiberg/Munich. There he worked in the in the field of novel device concepts on silicon and process technology development. In 2008 he took over his current position at the AUDI AG.

Good Reasons to go with CMOS based Camera Technology

von Fintel, René
Head of Product Management
Basler AG

Abstract
Sony will discontinue their CCD sensor line! This was "shock" in the industrial camera market. But not only this is a good reason to consider CMOS based camera Technology. Get an insight about the latest sensor Technology and what Advantages you will have when designing or choosing a new Vision System based on CMOS technology.

Biography
René von Fintel is responsible for the Basler ace camera platforma department in the Product management and coordinates the market launch of new technologies such as USB3 Vision. After completing his studies in industrial engineering, he worked for eight years in sales and marketing for a well known German medical technology company. Since 2012 René von Fintel has been employed in product management at Basler.

Innovation for independence

Westerlund, Hanna
Sales Operations Coordinator & Mealtime Consultant
Bestic AB

Abstract
Bestic AB was founded in Sweden, 2004 by Sten Hemmingsson who himself was in need of a good assistive eating device due to complications from Polio. The company has so far been privately funded and our main product, the eating assistive device Bestic®, was launched in 2012. As of today, we have sold approx. 250 units and have distributors in 7 European countries and also sell directly to customers in the US. According to the EU project "SILVER"; 0.2% of the population need mealtime support and have difficulties eating independently. Being dependent has a negative impact on one's confidence, dignity and appetite. Research shows that eating difficulties lead to malnutrition, which is a serious problem for patients and society as a whole. Statistics show that the healthcare costs for treating malnutrition are as high as the costs for treating obesity. Bestic is a small, well-designed robotic solution that can support most mealtime situations for those who desire independence. It is easy to use and easy for nursing staff to manage and offers a whole new concept and generation of mealtime support. The price of Bestic is 5 300 EUROS which corresponds to approx. 1.7 EUROS/meal (based on eating three times per day during three years). In comparison, the cost of being fed by a caregiver is approx. ten times more: 18 EUROS/meal.

Biography
About Sten Hemmingsson: MBA. Senior management positions in engineering companies in the transport and materials handling sectors. Project director for major installations of railway safety and control systems. Entrepreneur. Born 1938. About Hanna Westerlund: Sales Operations Coordinator & Mealtime Consultant. Project manager with experience within marketing, implementing innovations and sales at both universities and companies. Born 1980.

REAL-TIME DEFORMABILITY CYTOMETRY: HIGH-THROUGHPUT CELL MECHANICAL PHENOTYPING

Otto, Oliver
Postdoctoral Researcher
Biotechnology Institute / TU Dresden

Abstract
The mechanical properties of cells have long been considered as a label-free, inherent marker of biological function in health and disease. Wide-spread utilization has so far been impeded by the lack of a convenient measurement technique with sufficient throughput, sensitive to cytoskeletal changes. To address this unmet need, we introduce real-time deformability cytometry (RT-DC) for continuous mechanical single-cell classification of heterogeneous cell populations at rates of several hundred cells per second. Cells are driven through the constriction zone of a microfluidic chip leading to cell deformations due to hydrodynamic stresses only. Our custom-built image processing software performs image acquisition, image analysis and data storage on the fly. The ensuing deformations can be quantified and an analytical model enables the derivation of cell material properties. Performing RT-DC on whole blood we highlight its potential to identify subsets in heterogeneous cell populations without any labelling or extensive sample preparation. We also demonstrate the capability of RT-DC to detect lineage- and source-specific mechanical phenotypes in primary human hematopoietic stem cells and mature blood cells. Finally, we find that different stages of the cell cycle possess a unique mechanical fingerprint allowing the distinction between cells in G2 and M phase, which is not possible using standard flow cytometry approaches. In summary, RT-DC enables marker-free, quantitative phenotyping of heterogeneous cell populations with a throughput comparable to standard flow cytometry for diverse applications in biology, biotechnology and medicine.

Biography
2015 - Spin-off ZellMechanik Dresden GmbH i.G. since 2013 - Postdoc Biotechnology Center, TU Dresden, Research Group of Prof. Jochen Guck 2008 - 2012 - PhD in Biophysics, Cavendish Laboratory, University of Cambridge (UK) 2002 - 2008 - Diploma in Physics, University of Leipzig (Germany) 2006 - 2008 - Student Trainee at Bosch (China) 1999 - 2002 - Diploma in Information Systems and Business Administration, University of Cooperative Education Mannheim (Germany)

Cyber-Physical-Production-Systems at the BTU Model Factory

Stecklina, Oliver
Project leader of the Innovation Centre Modern Industrie Brandenburg
Brandenburg Technical University of Cottbus-Senftenberg

Abstract
Recently, significant efforts are under way in the development and implementation of Cyber Physical Production Systems (CPPS) by exploiting fast and highly connected production systems and combining them with novel industrial communication and control strategies. This paper addresses the need for reconfigurable approaches in production planning, logistics as well as in Manufacturing Execution Control (MES) to address induced complexities under the umbrella of Open Innovation and Industry 4.0. A fast reconfigurable and adaptive production monitoring and control approach has therefore been proposed in several industrial application sectors. It encompasses the configuration of manufacturing setups to enable co-development in a distributed production environment, exploiting ICT technologies to produce mass customized products and eventually presents advanced human-robot-collaboration systems. The methodology and physical building blocks and components are being tested and validated in several research and development projects related to open innovation and factories of the future.

Biography
Oliver Stecklina received his Diploma of Computer Science in 2003 from the Brandenburg Technical University of Cottbus. He presented the results of his Diploma Thesis on the 8th IT Security conference of the BSI and received the Best Student Award. After his study he worked as a consultant and later a senior consultant at the secunet Security Network AG. During his time there he was involved in research and development projects in IT network and operating system security, and high security hardware. He was also part of the SINA development team. In 2009 he was employed at the IHP Microelectronics research institute. He became part of the "Sensor networks and middleware group" and worked on national and internal research projects. During his time there he published about 20 conference and journal papers. He was part of the GI section Security Management. In 2015 he started working at the BTU Cottbus-Senftenberg and is project leader of the Innovation centre of Modern Industry Brandenburg.

Reliability of SiC Power Devices

Brosselard, Pierre
CEO
CALYTechnologies

Abstract
Silicon Carbide is a very attractive Semiconductor for Power Electronics. Today, diodes and transistors in the range of 1200V-1700V are commercially available. Among them, SiC MOSFETs are very interesting as they are normally off devices and requires small modification of their driving circuit. However, this type of device can presents some problems regarding the reliability aspects. Today, applying the standard HTGB test like, the electrical characteristics of the SiC MOSFET changes. As an example, the driving voltage VGS must be adjust to avoid any drift of the threshold voltage VTH, possibly resulting in short-circuits in a standard power inverter. Furthermore, devices characteristics can be strongly affected while operating in hard conditions (inductive clamping switching, overloads, reverse conduction trough the body diode, short circuits ...). More over, the SiC MOSFET is also very attractive to increase the frequency of the different converters. For that, the implementation of SiC device in applications must be optimized. CALYTechnologies is a spin-off from AMPERE Laboratory in Lyon, France, offering services on reliability stress and analysis. CALYTechnologies is a key partner for custom development of new generations power converters implementing SiC transistors. In a first part of this presentation, we will present you the state of the art of SiC-MOSFET technology, the performances of those devices, and finally some problems that anyone could face and solutions to avoid or bypass them. In a second part, we will presents latest results obtained on SiC MOSFET, focusing on stress analysis performed on commercial devices. We will conclude this review with lifetime estimation of such device depending on their application and operating condition.

Biography
P. Brosselard today is CEO co-founder of CALYTechnologies. Pierre has presented his PhD on "5kV SiC JFET and thyristor" at the end of 2004 in Ampere Lab. After, he joined the Power electronic Group at CNM in Barcelone up to 2008 when he came back to AMPERE Lab. as Assistant Professor. During the 13 years, he has worked on high voltage SiC devices (diodes, JFET, MOSFET, Bipolar Junction Transistor and thyristors). Since october 2014, he has co-founded CALYTechnologies. CALYTechnologies is an innovative Wide Band Gap (WBG) specialist company, dedicated to support customers in their development of WBG power electronics activities. CALYTechnologies, founded in 2014, is a spin-off from Ampere-Lab at INSA de Lyon, France.

Solution Processed Organic Transistors at Low Operating Voltage, Integrated Circuits and Organic Photodetectors

Dartnell, Nick
Senior Scientist
Cambridge Display Technology Ltd (Company Number 02672530)

Abstract
Traditionally organic thin film transistors have high operating voltages, typically around -30 to -40V due the low dielectric constant of the gate insulator used. This material is typically a fluorinated dielectric which can be coated on top of the organic semiconductor (OSC) without disrupting the OSC structure and hence impacting the mobility. In this presentation we will present results for top gate OTFTs operating in the -5 to -10V range, showing that for channel lengths of 10 µm, average mobilities of >2 cm2/Vs can be achieved without compromising other performance parameters such as on/off ratio, sub-threshold voltage slope or stability to bias stress. The use of a top gate architecture gives lower contact resistance between the accumulation layer and the electrodes at shorter channel length and improved mobilities as compared to bottom gate devices. We will show the impact of using these low voltage OTFTs in integrated logic circuits and present data for organic photodetectors that have high responsivity across the visible and NIR spectrum with EQE>40%. These devices are solution processable in air and so compatible with plastic substrates for thin conformable devices. This lends itself to simplified routes to the integration of different printed electronics components on a single flexible substrate.

Biography
Dr Nick Dartnell received his Master degree in Natural Science from Cambridge University and his PhD from Southampton University, in 1993, on the mechanisms and control of the plasma etching of semiconductors. Subsequent industrial work has provided broad experience of thin film coating, device fabrication and manufacturing on flexible substrates whether for microfluidic devices or third generation solar cells and more recently with CDT developing All Printed OLED and printable OTFT.

High-NA EUV Lithography Optics Enabling sub 9nm Resolution

Heil, Tilmann
Director Lead Systems Engineering
Carl Zeiss SMT GmbH

Abstract
The semiconductor industry's first production platform for extreme ultraviolet (EUV) lithography, ASML's NXE:3300B, features an all-reflective ZEISS optical system with a numerical aperture (NA) of 0.33, full field size and a 4x magnification. The excellent imaging behavior of this system underlines the extension potential of EUV lithography. Using the well-known formula for resolution Res. = k1 * wavelength / NA and assuming a process factor k1 > 0.3, one can estimate that a NA 0.33 optics configuration eventually enables single shot pattering down to 13nm resolution. Beyond that point, a higher NA is needed to continue the semiconductor shrink roadmap. For example, single shot patterning below 9 nm resolution requires the NA of the projection optics to be substantially larger than 0.45. However, the NXE:3300 EUV projection optics configuration cannot be extended to such a high NA. The increased chief ray angle together with the higher NA at reticle lead to increased shadowing effects and hence unacceptable contrast loss and mask efficiency. Therefore, a solution providing a projection optics with NA >> 0.45 has to be found without increasing the angles at reticle. In this paper, we demonstrate that the best solution for a sub 9nm resolution optical system with optimized productivity is a direction dependent, so called anamorphic magnification of 4x / 8x. We show that this configuration enables a half field imaging of 26 x 16.5 mm² using a 6'' mask. We discuss potential optical solutions for such an anamorphic high-NA lithography system. In particular, we focus on the impact on the optical design as well as on the needed technology to manufacture such a system. Finally, we investigate the imaging behavior of such an anamorphic optical system, and we demonstrate very good imaging of these designs.

Biography
Dr. Tilmann Heil is currently Director Lead Systems Engineering at Carl Zeiss SMT GmbH. He joined Carl Zeiss in 2002 where he started his career in the field of lithography optics as a scientist for imaging applications. Subsequently, he held several positions in systems engineering, technical marketing, and R&D cooperation program management. He received his Diploma and PhD in Physics from Darmstadt University of Technology in 1997, and 2001, respectively.

The best ways to use the new GaN devices and technical challenges to solve

Perichon, Pierre
Power electronic expert
CEA

Abstract
Power converters are essential for the management of energy especially in embedded applications. We are constantly looking to improve performances: better efficiency, lower size and lower mass, lower cost. New large gaps components, including GaN, promise exceptional performance. But what are the best ways to use them and what are the technical obstacles to be overcome: at the component level, but also the system level. Some examples of potential uses will be shown including transport: aerospace and automotive.

Biography
After an engineering degree in electronics and computer engineering from Central Lille, he has worked for 17 years in Schneider Electric France on electronic breakers and power converters for low-voltage grid. Since 2005, he belongs to the CEA organization and has worked for 5 years on photovoltaic systems (protection, power inverter, system), then on electric car and now on power electronic using GaN devices. He is an expert in power electronics, electrical system and protections systems for DC and AC network (arc detector, breakers, ground fault protection). He holds more than 40 patents.

Patterning of large-area & flexible polymer photovoltaic modules by laser ablation

Barbot, Anthony
Postdoctoral Researcher
CEA

Abstract
Even though the efficiency of plastic solar cells has considerably been improved at the laboratory scale, the fabrication of large area modules remains a challenge. One of the most important tasks relates to the serial association of multiple cells in modules since the interconnection areas do not participate in the power conversion. In order to reduce the "dead" regions and increase the Geometrical Fill Factor (GFF), which is defined by the ratio of the active area on the total area of the system, the patterning of photovoltaic modules must involve precise techniques. However, the low resolution of the classical coating technologies has not allowed the achievement of GFF over 80% yet. Using laser ablation to structure the different layers, which were previously deposited on the whole surface, is therefore a promising alternating technology to manufacture high-GFF solar modules. This processing has already been used successfully to develop thin film photovoltaic modules such as CIGS solar cells but few attempts have been performed to make organic photovoltaic systems. And yet laser patterning could seriously impact the industrialization and commercialization of these new photovoltaic products since it is potentially compatible with both sheet-to-sheet and roll-to-roll processes, and would additionally allow for a rapid scribing of various high-resolution structures. Here, we propose to present our advances in development of polymer photovoltaic modules structured with a commercial picosecond laser. Different laser-patterned structures, materials (including but not limited to P3HT) and coating processes were investigated and efficient modules from 5x5 to 15x15 cm² with GFF over 90% were obtained. Opportunities, challenges, issues and performance will be discussed with the support of various electrical and optical characterization techniques such as contact resistance measurements, microscope images and calculation of power losses caused by the interconnections.

Biography
In 2011, Anthony BARBOT received an engineer diploma in physical chemistry from the Graduate School of Chemistry and Physics of Bordeaux (ENSCBP). He then joined the XLIM institute for a PhD under the supervision of Dr. Bruno Lucas. He studied the doping of organic semi-conductors for photovoltaic applications and obtained his PhD degree in electronic and material sciences from the University of Limoges in 2014. He is currently a postdoctoral researcher at the Atomic Energy and Alternative Energies Commission (CEA) and works on the development of large-area and flexible photovoltaic modules.

Technological developments in infrared imaging : a fast growing market

SIMOENS, François
Marketing & Strategy Manager - Imaging Sensors
CEA-LETI

Abstract
First developed for defense applications, infrared imaging technologies have rapidly matured and come into the civilian market for security and surveillance, industrial process controls, science and enhanced vision system both military and civil. The growing variety of applications has stimulated innovation driven by the SWAP3 criteria: Size, Weight and Power, Performance and Price. For example, running development of CMOS-based Single Photon Avalanche Diodes paves the way to Time-Of-Flight-based near-infrared 3D imaging suitable for many consumer applications. Advances in heterogeneous integration of III-V on silicon to build InGaAs photodiodes arrays allow one to envisage active eye safe shortwave IR imaging operation for improved safety in automotive and aviation transportation. Today, infrared imaging technologies offer from Near-IR (0.7 - 1.4µm) to Far-IR (>14µm) improved sensitivity, embedded image processing, advanced functionalities like 3D vision or hyperspectral information, but also significant cost reduction as illustrated by the recent introduction of thermal imagers for smartphones. Thanks to these advances, infrared imaging technologies can now address a fast growing commercial market -in particular home automation, EVS for transportation, robotics- and take its first step into the mass-consumer market. This talk will present and illustrate this current trend of infrared imaging to spread in our daily lives.

Biography
Dr François Simoens received his PhD degree in electronics from the French Pierre & Marie CURIE University (Paris 6) in 2002 in the field of particle accelerating cavity. He first got involved in electromagnetic compatibility modeling at ONERA, microwave and ultra-sound radar prototyping in ESCPI (Paris High school) and optoelectronics for phased-array antennas in Dassault Electronique. After seven years of research in the accelerator field at CEA Saclay, he joined CEA-Leti in Grenoble in 2003, where he was first involved in the development of the sub-millimeter PACS focal plane array (for the ESA Herschel satellite) and then in uncooled infrared bolometer technology with the French company ULIS. In 2005, he became project manager (FP7, Euripides projects) before taking the position of program manager and expert in infrared and THz detection. Since the beginning of 2015, he acts as the Marketing and Strategy Manager for the Imaging Technologies and systems developed at Leti from X-ray to Far-Infrared.

Challenges for the introduction of DSA lithography into manufacturing

Servin, Isabelle
lithography research engineer
CEA-Leti

Abstract
Density multiplication of patterned templates by directed self-assembly (DSA) of block copolymers (BCP) stands out as a promising alternative to overcome the limitation of conventional lithography. Using the 300mm pilot line available at LETI and Arkema's materials, the main objective is to integrate DSA directly into the conventional CMOS lithography process in order to achieve high resolution and pattern density multiplication, at a low cost. This work will present recent achievements at LETI. The potential of DSA will be investigated to address contact and via level patterning, by using the graphoepitaxy of PS-b-PMMA block copolymers. Lithographic performances are both evaluated for contact shrink and contact doubling. Furthermore, in order to prevent from design restrictions, this approach may be extended to more complex structures with multiple contacts and non-hexagonal symmetries. These results show that DSA has a high potential to be integrated directly into the conventional CMOS lithography process in order to perform high resolution contact holes.

Biography
Isabelle Servin is currently 300mm track leader dedicated to multibeam & DSA projects and since 2014, she is responsible of process-integration leader of industrial consortium IMAGINE dedicated to the development of multibeam lithography with MAPPER lithography BV. In 2007 she joined CEA-Leti research center at Grenoble, France working on double patterning lithography and on optical masks. She started her career at ST Microelectronics in the field of optical lithography process for CMOS applications. She received her PhD on polymer chemistry from Paris VI in 1998.

Technologies and architectures for low power data processing

Reita, Carlo
Director Technical Marketing and STrategy, Nanoelectronics
CEA-LETI

Abstract
CMOS Technology is approaching both the physical and the economical limits of scaling with only a couple of nodes left before hitting major roadblocks. On the physics side, patterning, variability and material uniformity looks very difficult to control below 7nm. Economically the consolidation of the industry, the growth rate and the cost of new processes are producing a slowing down in the introduction of real area shrinks. As a results the number of R&D options is increasing again with new materials, new devices architectures, and new memory types being proposed as solutions to the various issues. On the other hand the drivers of the industry are always the same: more data processing power, more data storage density, more data rate transmission, less power per operation. In this paper will be presented an overview of the options chosen by CEA-LETI to maintain the growth in the capability of data processing systems even in the case of an end to scaling

Biography
Dr. Carlo Reita obtained his Laurea di Dottore in Fisica from Rome University "La Sapienza". After a two year post-doc at the Istituto di Elettronica dello Stato Solido of the CNR (Italy) working on a-Si thin film transistors for sensors and displays, he joined the GEC-Marconi Hirst Research Centre in Wembley (UK) as Principal Research Scientist working on poly-Si TFTs for displays and drivers. After a two years assignment as Royal Society Industrial Fellow at Cambridge University Engineering Department, he joined the Laboratoire Centrale des Recherches of Thomson-CSF in Orsay (France) as Senior Research Scientist on poly-Si device physics and circuit design. In 1999 he joined the mask maker Align-Rite which following a merger in 2000 became Photronics. After a period as Sales Manager, he became Technical Marketing Manager in charge of the Joint Developed Programs with the major customers and then European R&D Director. In 2005 he joined CEA-Leti where he is currently Director Technical Marketing and Strategy for the Nanoelectronic sector. He is author or co-author of over 80 refereed papers, several invited and review papers, two books chapters in the fields of electronic devices and lithography and served as member of national and international reviews and advisory committees.

Mourey, Bruno
CTO
CEA / Leti

Biography
Graduate from Ecole Supérieure de Physique et Chimie (Paris) and PhD in Electronic and Instrumentation (Université de Paris VI) Bruno Mourey had different positions in relation with display applications from research to manufacturing in the Thomson group. He was Managing Director of Thomson LCDs for more than 10 years He joined CEA/LETI in 2003 as Program manager for multimedia applications (display, optical recording.), In 2006 He was in charge of the start of a 200mm technological platform for Microsystems applications From 2009 to 2014 He was Vice president, managing Mems division followed by Photonics division Since 2015 he is CTO of CEA /LETI

FD-SOI a new era for energy efficiency

Thomas, Olivier
Project leader
CEA Leti

Abstract
Abstract- As electronic devices become increasingly integrated into our everyday environment, the design of energy efficiency from component to system becomes more important than ever. This talk will first present the research work performed in CEA Leti to design energy efficient computing systems and Ultra-Low-Power (ULP) Internet of Things (IoT) devices in 28nm FD-SOI technology. Then Silicon Impulse, the new Leti initiative to accelerate the development and the production of innovative industrial design solutions powered by leading edge technologies, will be introduced.

Biography
Olivier THOMAS received the M.S. Electrical Engineering degree from ISEN in 2001 and the Ph.D. degree from the Telecom ParisTech in 2004. He joined the CEA-LETI Laboratory in the Center for Innovation in Micro & Nanaotechnology (MINATEC), Grenoble, France in 2005. From 2005 to 2014 his research work was focused on advanced low-power digital and memory design in leading edge SOI technologies (PDSOI, FDSOI) and heterogeneous technology co-integration (ReRAM, 3DVLSI). From 2010 to 2012, he was a visiting researcher at Berkeley Wireless Research Center (BWRC) of University of California at Berkeley. He worked on methodologies to characterize on large-scale static/dynamic SRAM performances. From 2012 to 2014, he launched and led the Leti's advanced memory design activity. Since 2015, he is the project leader of Silicon Impulse for Leti. He is author or co-author of 75 articles in international refereed journals and conferences and 25 patents.

Low power image sensors at CEA LETI : from mature to advanced process nodes

Verdant, Arnaud
Analog design
CEA LETI

Abstract
In the last decade, CEA-LETI has investigated the fields of low power image sensors in the context of highly power constrained environments for surveillance applications. With power budgets as low as 100µW and below, new read-out and processing strategies has been developed for always-on visible CMOS image sensors. The recent and fast growing market of IoT offers new opportunities for this technology adoption. Although these strategies were oriented towards a drastic reduction of the amount of data to process by adapting the resolution of the acquired image, recent works tend to explore the benefits of event-driven asynchronous readout modes with multiple wake up levels. These acquisition concepts are also closely linked to the technological target and integrations schemes. In this presentation, we will show developments conducted at CEA-LETI in relation to the state of the art and future perspectives.

Biography
Arnaud Verdant joined the CEA LETI in 2008 at the Circuit Design, Architecture & Embedded Software Department. His works focus on analog design for CMOS image sensor, including analog to digital converters and low level image processing. He is involved in several project dealing with medical imaging (X-rays and acousto-optic) . He received the PhD degree from the Université Paris Sud in 2008. He is the author and co-author of 15 publications and 10 patents.

Silicon photonic technology developments towards higher 2D and 3D integration level with microelectronics

Kopp, Christophe
Head of the laboratory of CMOS Photonics
CEA, Leti

Abstract
Optical communications are definitively playing a major role in high speed interconnects in servers, datacenters, and supercomputers. In these systems, copper cables have been replaced by active optical cables in order to deal with data rate typically above 100Gbps per module. Mainly based today on optical sub-assembly modules using VCSEL emitters, optical links remain an expensive solution. As a result, the next generation of optical components must meet the challenge of high speed, low cost, low energy consumption, and high -volume manufacturing. Silicon photonics appears as a unique opportunity to cope with this challenge, leading also to a convergence between photonics and electronics in terms of fabrication foundry, design tool environment, and circuit co-integration. However, on this path towards the photonic and electronic convergence, integration challenges still remain. From die-to-die, to die-to-wafer and wafer-to-wafer integration. We present the main approaches we consider using copper pillars, trough silicon vias, and copper-copper direct bonding technologies in order to reach higher density with even smaller electrical interconnect pitches. The implementation of these integration technologies are then illustrated through various packaging scenarios applied to optical communication modules.

Biography
Dr. Christophe Kopp received the Ph.D. degree in photonic engineering from the University of Strasbourg, Alsace, France, in 2000, in the field of diffractive optics. Since 2001, he has been with the CEA, LETI,MINATEC Institute, Grenoble, France, where he is engaged in developing micro-optoelectronic devices. He has participated in several national and European collaborative projects (ODIN, HELIOS, WADIMOS MICROS, SILVER, MINAPACK). In connection with industrial companies (Intexys Photonics, IIIV-lab Mapper lithography), he has been responsible for several R&D projects. To support national SMEs (ULMER, SES, Wavelens, LGE, AEROTEC), he participated in appraisals. He is the author or co-author of more than 30 papers in scientific journals and international conference proceedings, one scientific book, and more than 30 patents. Currently, he is at the head of the laboratory of CMOS photonics with 30 research engineers/technicians and 6 PhD students.

Di Cioccio, Lea
scientific director
CEA, LETI - Minatec

Biography
Lea Di Cioccio received the degree in physics engineering from the Institut National des Sciences Appliquées, Rennes, France, the M. S. degree in metallurgy and material science from Paris VI university, Paris France, in 1985, and the Ph. D. degree in material and semiconductor physics from the Institut National Polytechnique de Grenoble, France in 1988. In 1990, She joined the Commissariat à l'Energie Atomique /Laboratoire d'Electronique et de Technologie de l'Instrumentation , Grenoble where was first engaged in characterization such as Transmission and Electron Microscopy. She is currently a specialist in semiconductor heterostructures , 3D integration using various processes such as epitaxy , wafer bonding and thinning and power deivices SiC and GaN . She is author and co author of more than 180 publications and 30 patents.

Scene-driven pixel-individually auto-sampling image sensors

Posch, Christoph
CTO
Chronocam

Abstract
The mode of operation of state-of-the-art image sensors is useful for one thing: photography, i.e. for taking an image of a still scene. Exposing an array of pixels for a defined amount of time to the light coming from a static scene is an adequate procedure for capturing its visual content. However, as soon as change or motion is involved, the paradigm of visual frame acquisition becomes fundamentally flawed. If a camera observes a dynamic scene, no matter where you set your frame rate to, it will always be wrong. Because there is no relation between scene dynamics and the chosen frame rate, over-sampling or under-sampling will occur, and both will usually happen at the same time. As different parts of a scene have different dynamic contents, a single sampling rate governing the exposure of all pixels in an imaging array will naturally fail to yield adequate acquisition of these different scene dynamics present at the same time. The solution is an image sensor that samples parts of the scene that contain fast motion and changes at high sampling rates and slow changing parts at low rates - with the sampling rate going to zero if nothing changes. Unfortunately, the information about where in a scene, and at which speed, things change and move is usually not known beforehand. A way to solve this problem is to let each individual pixel adapt and optimize its own sampling rate to the visual input it receives by autonomously reacting to the temporal evolution of light incident to its photosensor. As a consequence, (a) the image sampling process is no longer governed by a fixed timing source but by the signal to be sampled itself and (b) image information is not acquired and transmitted frame-wise but continuously and conditionally only from parts of the scene containing relevant information. These sensors are able to combine ultra-high-speed operation at wide dynamic range with low data rates, outperforming conventional image sensors in many areas of machine vision.

Biography
Christoph Posch is Research Professor at Université Pierre et Marie Curie, Paris VI and founding CTO of Chronocam. He received the M.Sc. and Ph.D. degrees in electrical engineering and experimental physics from Vienna University of Technology, Vienna, Austria, in 1995 and 1999, respectively. From 1996 to 1999, he worked on analog CMOS IC design for particle detector readout and control at CERN, the European Laboratory for Particle Physics in Geneva, Switzerland. From 1999 onwards he was with Boston University, Boston, MA, engaging in applied research and mixed-signal integrated circuit design for high-energy physics instrumentation. In 2004 he joined the newly founded "Neuroinformatics and Smart Sensors Group" at AIT Austrian Institute of Technology (formerly Austrian Research Centers ARC) in Vienna, Austria, where he was promoted to Principal Scientist in 2007. Since 2012, he is co-directing the Neuromorphic Vision and Natural Computation group at the Institut de la Vision in Paris, France and has been involved in founding of two high-tech start-up companies, Pixium Vision and Chronocam. His research interests include neuromorphic analog VLSI, CMOS image and vision sensors, biology-inspired signal processing and biomedical devices and systems. Dr. Posch has been recipient and co-recipient of eight IEEE awards including the Jan van Vessem Award at the IEEE International Solid-State Circuits Conference (ISSCC) in 2006, the Best Paper Award at ICECS 2007, and Best Live Demonstration Awards at ISCAS 2006, ISCAS 2010 and BioCAS 2011. He is member of the Biomedical and Life Science Circuits and Systems, the Sensory Systems and the Neural Systems and Applications Technical Committees of the IEEE. Christoph Posch has authored more than 90 scientific publications and holds several patents in the area of artificial vision and image sensing.

Towards the use of CMOS detectors for space applications

Bardoux, Alain
Head of department
CNES

Abstract
For 20 years, optical instrument of satellites have been using CCD detectors for all applications Earth observation, Astronomy, and also for the star trackers that serve to know the satellite attitude. CCD's exhibit good performances and event very good ones for backthinned devices. But they suffer of degradation under radiations, inherent to space environment, and require quite complex proximity electronics (high voltage bias, clock drivers, signal processor). The incoming of CMOS detectors in the 90's have push a new paradigm, allowing the design of detectors customized for each application, and making possible some mission that we cannot envisage before: high speed readout, windowing, smart pixels, and more. Performances of the pixels, that were relatively poor in the beginning of the story become more and more better, so that CMOS detectors are now used for satellite flight models productions both for star tracker and optical telescope. Two types of detectors are used: COTS for medium performance missions, where cost is the driver, and custom devices where performances are the key elements. Obviously, the choice of the foundry is very important in the case of custom devices, to ensure the required performances, and also to guarantee the procurement. A few criterions of choice will be given.

Biography
Alain Bardoux has been working for 15 years as Head of "Detection chain " department , dealing with optoelectronic detectors and associated electronics for all wavelength from X-ray to submm., for Space mission in which CNES is involved : High resolution Earth remote sensing, Atmospheric sounding, Astronomy, planetology Formerly, He has been responsible for the development and the procurement of flight models for several space missions: SPOT 5, Helios 2 Corot. Today, he manages particularly the setting up of CMOS detectors European supply chain, and large/very large infrared large format detectors

Gavillet, Jerome
European program Manager
COMMISSARIAT A L'ENERGIE ATOMIQUE (CEA)

Biography
Dr. Jérôme GAVILLET received his PhD on material physics & surface processing from l'Ecole des Mines de Nancy (F) in 1996. As a researcher, he worked on hydrogen embrittlement of stainless steels for the petrol industry at the Federal University of Rio de Janeiro (B), on zircaloy alloy coatings for the French nuclear industry and on copper interconnects for the semiconductor industry at the University of York (UK). He spent 7 years in microelectronics working as a process engineer for equipment suppliers in Cardiff (UK), Sunnyvale (US) and Grenoble (F). He joined CEA-Liten in 2005 as a project manager in the field of Renewable Energies and Nanomaterials, working on surface energy and thermal management topics. Since 2012, he works as an European program manager, contributing to the management of CEA-Liten's EU projects portfolio and setting up new business opportunities in the fields of materials, renewable energies, energy efficiency and information & communication technologies. He has authored 10 patents and over 40 publications (H-index=9, August 2015).

Camera systems for ADAS applications

Punke, Martin
Manager - Camera Technology
Continental AG

Abstract
Today's traffic environment, such as traffic and information signs, road markings, and vehicles, is designed for human visual perception. This is done by different shapes, colors, or a temporal change of the signals. It is therefore a good choice to use a system similar to the human eye for machine perception of the environment. Camera systems are ideal candidates as they offer a comparable spectral, spatial, and temporal resolution. In addition to the "replica" of human vision, specific camera systems can provide other functions, including imaging in infrared spectral regions for night vision or a direct distance measurement. This presentation covers details on specific applications of camera-based driver assistance systems and the resulting technical needs for the camera system. Use cases covering the outside and inside of the vehicle are shown. Basic camera architectures including mono and stereo systems are presented.

Biography
Dr. Martin Punke is leading the Camera Technology group at Continental. He is working on concepting, engineering and productization of forward looking camera systems for ADAS applications. In his previous positions at Nokia he was responsible of camera, flashlight and illumination technologies in mobile phones. Martin received the Dipl.-Ing. and Ph.D. degrees in electrical engineering and information technology from the University of Karlsruhe, Germany, in 2003 and 2007, respectively. In his Ph.D. thesis he worked on organic semiconductor devices for microoptical applications.

How to run a successful MES selection in MedTech

Proehl, Steffen
Managing Director
CONVANIT GmbH & Co. KG

Abstract
In times of Industry 4.0 a seamless tracking of all relevant information starting from enterprise planning down to logistics and the production itself becomes more and more important for MedTech companies too. Today most MedTech companies are naturally using ERP systems to take care of their customer orders and the necessary logistics. But when it comes down to tracking and control on shop-floor level many of those companies are still using paper. At the same time a paperless production offers substantial advantages in terms of seamless traceability, logistics and planning interaction as well as quality assurance. This is the point where Manufacturing Execution Systems (MES) come into the picture - systems that are standard in other industries e.g. semiconductor. But how to successfully select a MES, especially for MedTech? There are many systems on the market offering a wide range of functionalities and usually a project budget is given - so what are the criteria to select "the right system" and how to choose the "right" partner? How long does it take to come to the "final" decision? Based on long term experiences with various MES selection activities across different industries the presentation offers an approach for the MES selection, outlines and discusses selection and decision criteria and provides best practices for this process.

Biography
As an IT expert Steffen started his career at an IBM Global Services company. In 2000 he joined Infineon Technologies as member of a team to ramp up the first 300mm semiconductor Fab in the world. During this time Steffen became a Manager within the Infineon global MES competence center. As part of this work he was involved into all major MES activities world wide, starting with the MES selection up to the rollout and migration of the "ready-to-go" product to varoius Infineon Frontend and Backend sites. In the year 2006 Steffen joined Qimonda as Senior Manager IT Production Automation responsible for core MES functionalities worldwide. For the fully automated production of a 300mm Qimonda Frontend site he was a key member of the automation core architecture and development project team. Based on his long term experience in MES and automation - and with the background of various successful projects in Europe, the USA and Asia - Steffen started his own IT automation business in 2009. Together with 2 other colleagues he founded CONVANIT in 2010 - a company that specializes in the combination of Yield Management and IT automation. Despite the fact that the background of the company lies in the high-tech area of semiconductor CONVANIT today serves many customers outside semiconductors successfully transferring best practices into their industries too.

Behavioral modeling of cross-wafer chip-to-chip process induced non-uniformity

Clark, William
Semiconductor Process/Integration
COVENTOR

Abstract
As technology continues to scale feature sizes the across wafer non-uniformities become a significant contributor to variability. Being able to model and predict these effects are key to limiting variability with adaptive process control and the reduction of total measurement error. Additionally these effects will become more pronounced as we increase the wafer footprint. In this presentation we discuss use of the SEMulator3D ™ tool to predictively model the across wafer non-uniformities induced by various fabrication processes Including deposition and etch steps

Biography
Dr Clark has worked in all phases of Semiconductor Technology and Device integration for over 36+ years with contributions in research and development through manufacturing. After a 36 year career with IBM in VT, USA he joined COVENTOR in 2014 at the Paris, FR office as a Semiconductor Process and Integration Engineer. Dr Clark received his Ph'D in Material Sciences from the University of Vermont. He holds 60 patents and has authored and co-authored numerous presentations. Dr Clark is a senior member of the IEEE.

Barriers to Progress

Bird, David
Principal Scientist
CPI

Abstract
The use of organic electronic materials, combined with the desire to produce lightweight & low cost flexible devices, raises the need to develop a commercially viable technology which limits the impact of the organic material's intrinsic environmental instability. CPI has been involved in the area of barrier film and encapsulation development for many years and with its recent acquisition of a roll-to-roll Atomic Layer Deposition capability is actively engaging with the industry to meet this technology need. This presentation reviews the existing technologies highlights the barrier and associated metrology technologies being developed at CPI's National Printable Electronics Facility. The challenges of testing an ultra-barrier material over large areas are significant, as are identifying defects of significant size; holes or coating defects in an optically transparent, <100 nm thick layer are difficult to find and measure without making a functional device, taking days, then testing it with accelerated ageing, which can take weeks. Data from the EU-FP7 projects NanoMend and R2R-CIGS documents the developments from a temporal-ALD batch process to a roll-to-roll spatial-ALD process. The aim of this work is to reduce costs and improve the manufacturability of these materials for a commercial/industrial environment.

Biography
Dr David Bird has 11 years experience working with film substrates and barrier materials. David completed an Engineering Doctorate in 2008 sponsored by DuPont Teijin Films on nano-scale coatings on films for flexible electronics. Joining CPI in 2008, he is now a Principal Scientist at the UK's National Printable Electronics Centre, focussing on vacuum-deposition of barrier materials. In 7 years at CPI David has 23 IP submissions (for Patent, Publication or internal Know-how), 17 of which relate to Barrier Materials and their integration to functional devices.

Prospects of Emerging 2D Transition Metal Films for Applications in Electronics

Duesberg, Georg
PI
CRANN, Trinity College Dublin

Abstract
The reduction of dimensionality has revealed exciting properties in 2D materials such as graphene and Transition Metal Dichalcogenides (TMDs). The potential for their applications in electronics, has been demonstrated, however, most of these studies have been carried out on individual devices, often relying on time consuming low yield techniques such as mechanical exfoliation and electron-beam (e-beam) lithography. Furthermore, the stability of TMDs and their integration with existing semiconductor technology is a major challenge for their successful incorporation into useful applications. Reliable large scale synthesis, functionalisation and passivation of this new class of materials will be discussed in this presentation. Firstly, the synthesis of large scale TMD films via two methods compatible with semiconductor production lines will be presented. Thermally Assisted Conversion (TAC) of various metal layers to their sulfides and selenides is shown. The samples are produced on silicon chips and were subjected to structural and spectroscopic characterization. TAC allows good control over their thickness and morphology. Secondly, we report on the direct CVD growth on SiO2 of TMD monolayers in a micro-reactor set-up. These highly crystalline TMDs were tested in simple transistor configurations. The deposition of subsequent layers on top of the TMD for gating and passivation by Atomic Layer Deposition (ALD) has also been achieved. This process involves chemical functionalisation of TMD layers on silicon; a crucial step for device integration. With this large scale processes at hand, it is possible to structure and electrically address the TMD films in a manner similar to SiO technology yielding simple devices such as transistors, diodes and sensors. This integration of 2D materials into hybrid devices with conventional semiconductors processes allows us to retrieve electrical performance data in such processed TMD channels.

Biography
Prof. Georg S. Duesberg graduated in Physical Chemistry from the University of Kassel, Germany in 1996. He was researcher at the Max-Planck-Institute for Solid State Research, Stuttgart and Trinity College Dublin from 1997 - 2001 after which he received his PhD from the University of Tübingen in 2001. From 2001 - 2005 he worked at the Infineon AG, in the Corporate Research Department in Munich. From 2005 - 2007 Prof. Duesberg was in the Thin Films Department at Qimonda AG, Dresden. In 2007 Georg took on a position in the School of Chemistry of Trinity College Dublin and as a Principal Investigator in CRANN. Since 2011 he is Professor and Director of Research in the School of Chemistry. Prof. Duesberg has co-authored more than 165 publications with more than 9000 citations (H-index 43) and has filed more then 25 patents. Prof. Duesberg´s research focuses on making novel devices to exploit the unique properties of low-dimensional structures. These Hybrid devices have applications in ICT, sensing and bio-chemistry as well as energy conversion and storage. For example novel electrodes, switches, sensors are developed and integrated with state-of-the-art silicon processing techniques. Recently Professor Duesberg's team focuses on the synthesis and integration of novel 2D materials for electronic applications.

Medium Voltage SiC Transistor Development at Cree in 2015

Casady, Jeffrey
Business Development & Program Manager
Cree, Inc.

Abstract
From 2.5kV to 15kV, SiC has long been known since the 1950's, if not earlier, to have inherent advantages for simpler, more efficient, more compact, and more reliabile solid-state power electronics. Today, after nearly five years of SiC MOSFETs in the commercial market at voltages up to 1700V, the time is now rapidly approaching to discuss the development status of medium voltage SiC power transistors. In this presentation, development status of SiC MOSFETs from 2.5 to 15kV will be presented, including on-state and switching performance, reliability data to date, and expected relationship of this class of SiC MOSFETs with the commercially available lower voltage SiC MOSFETs. Additionally, a brief summary of SiC bipolar development will be offered, in particular GTO and IGBT type power transistors.

Biography
Dr. Casady is a Business Development and Program Manager for Cree, Inc. Power & RF. Dr. Casady has worked in SiC power devices and electronics since 1994. He received his PhD in Electrical Engineering in 1996, and has served a variety of roles in industry (Northrop Grumman, SemiSouth, and Cree), and academia (Auburn University, Mississippi State University). Prior roles included CEO, CTO, VP Business Development, and Senior Engineer. He has served with Cree since 2012, and has cumulatively over 80 technical publications, and three book chapters. He also co-authored numerous business articles, technical articles, book chapters, and patents.

ORGANIC ELECTRONIC AND PRINTED SMART SYSTEMS ON STEEL

Guaino, Philippe
Project Leader
CRM group - AC&CS

Abstract
Most of organic and smart devices are printed on plastic foils, papers, and more recently on thin glass "foils". Although such material are the most conventional substrates to fabricate smart system, difficulties can arise due to the shortcomings durability, moisture barrier properties (particularly for organic material) and heat dissipation. Metallic material as substrate foils appears to be a promising alternative for a possible future generation of printed electronic devices. This approach is new in both metallurgy and electronic world. Since several years, CRM group (previoulsy ArcelorMittal Research Laboratory) has developed a new advanced steel substrate dedicated to organic and more generally flexible or conformable electronic devices. Metal will be flexible, rigid, or even formable devices. Steel has very good oxygen and water barrier properties. It is an electrical and thermal conductor, which can greatly improve the lifetime of the device thanks to heat dissipation. Indeed, such substrates can be very helpful for integrated system in "extreme" environment (pressure, temperature conditions and so on). Moreover, smart steel systems can be manufactured in a roll to roll process, which is the key of a low cost, competitive process and compatible with flexible electronic manufacturing. During this presentation, advanced steel material manufacturing for smart system devices will be outlined, dedicated to large area device integration. Special focus will be treated on steel surface treatment to reach exigent physical properties (roughness, planarization, dielectric and conductive materials) and low cost manufacturing process. At last, we will show how back side steel surface can be exploited and dedicated to the integration of a "printed circuit board " and interconnected with front side coating devices

Biography
Philippe Guaino studied solid-state physics at the Faculty of Sciences and Techniques at Saint-Jérôme University, Marseille. In 2001, he obtained his PhD thesis. From 2001 to 2006, he was post-doc researcher in surface science at 'National Center for Sensor Research' in Dublin, Ireland, and other institutes in France. Since 2006, he has obtained a permanent position at ArcelorMittal research center, now CRM group, in Belgium. He is responsible of the smart coating activities and printing electronic process on steel.

Ultra low power microelectronics for wearable and implanted medical devices

Gray, Simon
Head of Marketing & Sales
CSEM

Abstract
Wearable sensors have been available for years, but have mostly been limited to heart-rate monitoring for athletes. The arrival of smart watches, as well as ubiquitous smart phones, has led to an explosion of wearable sensors and applications for healthcare and wellness. Nevertheless many products today remain bulky and need frequent re-charging, thus limiting more widespread application. This presentation will look at some recent advances in microelectronics for wearable sensors for medtech, from low power ASIC and SOC design, to choices about energy sources, antennas and processing and communication algorithms. It will be illustrated with some recent examples of miniaturised sensors for implantable and wearable sensors from both collaborative research projects as well as innovations for commercial products.

Biography
Simon Gray is responsible for marketing and business development in CSEM's Integrated and Wireless Systems Division. CSEM has been a pioneer in low power ASIC design and is today one of the leading design centers in Europe for ultra low power wireless sensing SOCs and systems. Prior to joining CSEM he held senior technical and marketing positions in the semiconductor industry for companies including Philips, Xemics and Semtech. He has a BSc in Physics from Nottingham University and an MBA from Open University.

Quantum Computing : The Engineering Challenges

Bertels, Koen
professor
Delft University of Technology

Abstract
The challenges to build a quantum computer are enormous and can be separated in physics and engineering challenges. The physics challenges focus on the coherence time of the superposition and entangled state of qubits and on defining ways to increase the fidelity of the qubit states and to compensate for the errors that occur during the quantum operations. The engineering challenge can be summarised by the word `scalability'. For instance, it has been stated that in order to apply the famous factorisation algorithm developed by Shor, it is expected that around 5 billion physical qubits are needed to factor a 2000 bit number in a reasonable time (expressed in number of hours). Knowing that the largest number of physical qubits one is capable today of creating and controlling is less than 10 it immediately becomes clear that several breakthroughs are needed to achieve the goal of building a quantum computer. The engineering challenges are thus focused on this scalability as the qubits need to be controlled, manipulated and corrected such that the exponential computing power is preserved. The quantum state and therefore the (entangled) qubit state is very fragile. Any small interaction with the environment causes a bit-flip or phase shift error and the superposed state to decohere. In addition, a quantum state cannot be measured directly without destroying the superposition. This destructive reading as well as the duration and fragility of the superposition (decoherence time) are the achilles heel of quantum computing and one of the main challenges of any quantum computer as this qubit behaviour interferes in its correct operation. In this talk, we will focus primarily on those aspects of building a quantum computer that are to a certain extent disconnected from the pure physics layer where one is focusing on building and improving the physical device. We focus on the system design challenges of a large-scale quantum computer.

Biography
Koen Bertels is professor and head of the CE Laboratory where 6 faculty members and around 30 PhD students perform research along 4 themes: the first is Liquid Architectures where we investigate how to make the processor architecture, interconnect and memory hierarchy responsive with respect to specific application requirements. The second focuses on the design of Big Data computing systems with an emphasis on genome sequencing. The third theme addresses issues such as reliability and fault tolerance and looks at non Von Neumann architectures based on novel devices such as memristors. The fourth theme is Quantum Computing where the CE lab is part of the larger QuTech research lab that aims to build a quantum computer based on quantum gates. Within QuTech, he is the principal investigator for architectural and system design of the quantum computer.

Fraunhofer Group for Microelectronics: The strategic core competence "RF and Communication Technologies"

Schneider, Peter
Director
Design Automation Division EAS of Fraunhofer Institute for Integrated Circuits IIS

Abstract
Information and communication technologies are changing our society significantly in many areas of life and work. As the largest innovation engine in Germany, key technologies of this kind form the basis for new products, processes, and services. Embedded systems comprising hardware and software components are, for example, decisive when it comes to the successes of the strong European sectors of automobile construction and mechanical engineering, energy technology, medical engineering, and safety and security technology. The networking of the member institutes of the Fraunhofer Group for Microelectronics covers both hardware and software aspects. With the cross-institute technology platform "RF and Communication Technologies" for wireless network solutions, the Group for Microelectronics is pursuing the aim of countering today's heavy, sometimes even extreme, dependency on external suppliers. The shared thematic focuses cover: - Algorithms for broadband communication (physical layer) - Broadband communication (upper protocol layers) - Localization and navigation - Digital broadcasting - Adaptive and cognitive transmission technologies - Radar systems - Microelectronically realized components (e.g. AD/DA, RF, power amps) - Broadband signal processing - Media technologies - Networking of embedded systems (fields of application: automotive, industry) At the same time, a range of development aims for highly specialized niche markets are being pursued: - Cross-layer real-time-capable test beds for LTE applications - Application-specific extension to the LTE standard (machine type comms) - Special telemetry (point-to-point/network, long-range, low-power, high data rate) - Special telemetry (long-range, low-power system solutions for communication in special application fields (Smart Grid, Car2X)) - Platforms for high-rate signal processing - Broadband networking of embedded systems (including automotive Ethernet/IP) - SDR-based cognitive radio demonstrators

Biography
1993 Diplom-Ingenieur in electrical engineering from Dresden University of Technology 1993 Research scientist at Design Automation Division EAS of Fraunhofer Institute for Integrated Circuits IIS 2000+ Group Manager "Heterogeneous Systems" 2006+ Head of the department "Heterogeneous Systems" at Design Automation Division EAS of Fraunhofer Institute for Integrated Circuits IIS 2010 Ph.D. in Electrical Engineering at TU Dresden 2011+ Director at Design Automation Division EAS of Fraunhofer Institute for Integrated Circuits IIS

Application of 3D integration technology to X-ray detector read-out chip

Sarajlic, Milija
Researcher
Deutsches Elektronen-Synchrotron (DESY)

Abstract
We report on application of the 3D integration technology to the specific type of the X-ray imaging detectors. Similar work was already performed by CEA LETI, France and CERN, Switzerland. The motivation is a significant reduction of the dead space between X-ray chip modules. Originally, this type of chip uses wire bonds as interconnection to ceramics substrate. We replace the wire bonds with TSV. The read-out chip was developed by CERN electronics department and fabricated in IBM foundry, USA. Read-out chip is premade with Through Silicon Via (TSV) landing pads in M1 metal layer. Together with Fraunhofer IZM institute, Germany, we are designing and fabricating TSVs in the read-out chip, Re-distribution layer (RDL), and PCB substrate. The end system will be a stack of X-ray sensor bump bonded to read-out chip which is on other side bump bonded to the substrate. Substrate is LTCC ceramics or PCB board designed in the course of this work. When designing the TSV structure, a challenge was to choose the ratio between thickness of the chip and diameter of the TSV. A thicker chip is more rigid but it would also require larger diameter of the vias. The RDL is designed on the back side of the read-out chip without using an interposer. RDL is designed in the single layer in order to reduce the complexity of fabrication. The challenge was to route all the signals in the single layer at the same time leaving enough space for bump pads. The RDL is the possible source of the digital signal leakage. This effect was modeled analytically and sources of leakage are identified. An additional challenge was to test the chips during fabrication. The plan is to use a probe station with the probe card accommodated to the bump pad structure and to test the chips in wafer at the technology step after RLD deposition. The presentation will give details of the challenges and solutions.

Biography
Milija Sarajlic graduated in Physics from Belgrade University, Serbia in 2001. He joined Institute for Microelectronics in Belgrade where he worked on the development of Silicon based pressure sensors, photodiodes, chemical sensors and photonic micro and nanostructures. In 2013 he joined DESY Detectors Group where is currently working on the application of 3D integration technology to the X-ray pixelated detectors. He has more than ten years of experience in Microelectronics technology and he is author or coauthor on over than 30 scientific papers in peer reviewed journals and conference proceedings. He is holding Master degree in Microelectronics and PhD in Applied Physics from Belgrade University

Ultra Sniffer - New atmospheric leak detection method

Brockmann, Robert
Dipl.-Ing. (FH)
Dipl.-Ing. (FH) Robert Brockmann

Abstract
The test sensitivity of classic sniffer test methods is limited by the helium noise in the air, but by reducing the atmospheric helium noise from 5 ppm to 10 ppt the test sensitivity of the classic sniffer test method can be significantly improved by the factor 500.000. The at the at the Max Planck Institute for Plasma Physics (IPP) developed Ultra Sniffer Testgas method (UST) has successfully been applied in the Nuclear Fusion domain. In particular it was used for tests during the construction of the Wendelstein 7-X fusion experiment at the Max Planck Institute for Plasma Physics (IPP) in Greifswald. It was shown that leaks at normal pressure (1013 mbar and 20°C) up to 10^-9 mbar*l/sec are easily detectable. This means that, with the UST-Method, leaks with a theoretical loss of gas of 5 cm³ in 30 years are well within the detectable range. The UST method is ready for use in the non-fusion domain. New application areas are for example in the area of material sciences and electronic devices. However, the application in all industry domains requiring leak detection and localization in pre-production seems promising, in particular for ad hoc testing.

Biography
Former employees at the Max Planck Institute of Plasma Physics in Munich and Greifswald and project manager of a start-up from the Max Planck Institute.

ENMOVER

Petersohn, Ronny
Member of Academic Staff
Dresden Institute of Automobile Engineering

Abstract
The Chair of Automotive Mechatronics at the Institute of Automotive Technology Dresden - IAD, at the Dresden University of Technology combines the interdisciplinary engineering expertise in the automotive sector. The chair is dedicated to research in the disciplines of energy and information management, energy storage technologies and battery systems, electrical / electronic architecture, diagnosis, driver assistance systems and vehicle networking and telemetry. The algorithms, concepts, methods developed at the department are modeled and simulated using standard simulation software as well as implemented in real hardware and deployed in vehicles and tested under road conditions. In this presentation, the content of the showcase project "ENMOVER - Energy and Mobility in Interaction" is presented. In addition to the development and testing of multiple usage scenarios, also their influence on the traction battery and therefore to the cost efficiency of the vehicle will be discussed. In addition data acquisition and the link to the public transport are discussed, which are processed in other showcase projects at the department.

Biography
Ronny Petersohn graduated in Mechatronics at Dresden University of Technology. In 2012 he joined the IAM GmbH (part of the TU Dresden AG) in Dresden as a member of the academic staff. His activity was the study of electrochemical storage for mobile use in vehicles. In this position he worked among other things with the modeling and simulation of electrochemical storage systems. Since 2014 he is member of the academic staff at the Institute of Automotive Technology Dresden. In his field of activity he continues the research of electrochemical storage systems with extension to electro mobility and the associated charging infrastructure.

How Semiconductor Technology can contribute to Innovative Biomedical Systems

Simkens, Peter
Managing Director
DSP Valley

Abstract
Thanks to Moore's law, the semiconductor industry has built up a lot of experience in how to produce large volumes of products in a very miniaturised form and at a very low cost, and with a highly increased computing performance. Modern biomedical systems are facing similar challenges: clinical tests on human fluids have to miniaturised in order to bring them closer to the patient, responding to the needs of personalised medecine. The analysis of the human genome, DNA sequencing and cell sorting (e.g. for early cancer detection) from their side require tremendously increased compute power. Just as in Moore's law, an exponential increase of the available compute power is required in order to make personalised medecine happen. By combining the experience of mass production from the semiconductor industry with the techniques from the biotech, new solutions for the above described challenges can be unlocked. This presentation will discuss the required cross-fertilisation between the two Key Enabling Technologies of micro/nano-electronics and biotech, and will illustrate the potential of this cross-KET approach with some emerging applications.

Biography
Dr. Peter Simkens holds a Master of Science degree in Mechanical Engineering (1984) and a PhD about "3D graphical simulation of sensor controlled robots" (1990), both obtained from KULeuven. During more than 10 years, Peter Simkens was involved in development projects for the European Space Agency, including the development of training and simulation facilities for European astronauts, and the development of real-time IT-systems for space applications. In 1998, Peter Simkens became managing director of DSP Valley, the cluster in Smart Electronic Systems, headquartered in Leuven (Belgium). He developed DSP Valley to an outstanding business and innovation cluster, where all participants are connected through strategic partnerships. He has been responsible for the internationalization of this cluster, by setting up an international network of clusters, enabling inter-cluster matchmaking opportunities. He has transformed the DSP Valley eco-system from a cluster of micro/nano electronics technology providers to a full value chain cluster in smart electronic systems, including applications in smart health systems. Currently, he is building new strategic alliances to exploit the potential of cross-KET innovation, e.g. between micro/nano electronics and biotech (in partnership with FlandersBio), for new health applications in the so-called Nano4Health domain.

CMOS imaging offers novel solutions to common application dilemmas

Prevost, Vincent
Technical Marketing Engineer
e2v

Abstract
The tides have turned on CCD based imaging solutions as CMOS pixels have come of age. Combined with higher electro-optical pixel performance the system-on-chip nature of CMOS enables novel application features and image processing to be performed with much lower cost. A number of innovative features that include extremely low-light scene capture, colour detection beyond human vision capability, and distance perception for 3D vision or range-gated active imaging are presented both from both technical and business aspects. This presentation will cover some of the ground-breaking application solutions with some projection on the market expanding impacts as the cost of ownership enables deployment in more mainstream markets such as industrial, automotive and security cameras.

Biography
Bringing life to technology, e2v partners with its customers to improve, save and protect people's lives. Delivering innovative technology for high performance systems and equipment, e2v leads developments in communications, automation, discovery, healthcare and the environment. e2v employs approximately 1700 people worldwide, has design and operational facilities across Europe, North America and Asia, and has a global network of sales and technical support offices.

Easy Smart Grid - opportunities in energy system transformation

Walter, Thomas
Managing Director
Easy Smart Grid GmbH

Abstract
Background Our energy system is based on fossils. Coal, oil and gas accounted for 68% of electricity and 81% of primary energy in 2012/13 (IEA 2014). Coal, oil and gas companies were valued at 5 Trillion $ in 2014. De-carbonization starts now (G7: 100% by 2100). Transformation Fossils provided energy and storage. Tomorrow energy will be supplied by solar, wind, hydro and biomass, and storage by pumped hydro, P2G, batteries and customer flexibility. A new (smart) grid operating system is needed. Positioning We focus on creating high added value in the first market segment to be transformed. Transformation of grid islands and island grids creates value as renewables are cheaper than oil, and our technology coordinates all grid actors. Future extension to cellular grids can be expected. Solution We create a real time market and price in a grid cell, the most efficient way to establish balance by influencing production and consumption. Our patented technology ensures real time performance and stability, data protection and resiliency, and minimum investment in ICT infrastructure. Most intelligence resides in the controllers of user devices ("Smart Grid on a chip"). Our solution is more efficient and cost effective than any other smart grid technology. Products We develop and sell the "Operating System" plus Smart Controllers for Automated Demand Response and ESG meters for billing. We plan to cover market by partnerships and licensing. In the long term, every flexible device (fridges, laptops) will include the function under our license for this energy IOT (Internet Of Things) technology. Status Easy Smart Grid was founded in 2014 and won 3rd prize as European Smart energy start-up from EIT ICT. Technology risk is low, IP has been filed in 2015, and pilot partners are being developed. We plan to implement the business plan in two phases: Development and pilot demonstration 2016/17, industrialization and rollout 2018/19. We look for partners for investment and business development.

Biography
Thomas Walter studied electrical engineering at the Universities of Karlsruhe and Essex (Diploma in 1982) and earned a PhD (Dr.-Ing.) for sensor technology research from RWTH Aachen in 1989. From 1983 to 1989 he worked for Cambridge Consultants Ltd. (An Arthur D. Little Company) on breakthrough technology and innovation consulting. 1989 to 1993 he was a product manager and assistant to the MD at German Philips subsitiary BTS. 1994 to 2000 he worked at a Dresdner Bank consulting subsidiary on banking, innovation financing and business transformation projects. 2000 to 2011 he was Associate Director at engineering consultancy Altran Group, where his responsibility included all work for the semiconductor subsidiary of Carl Zeiss. 2011 to 2013 he started and managed a subsidiary of Wirsol Solar AG with a focus on diesel substitution (first 650 kW of PV on the Maldives) and PV integration. He manages Easy Smart Grid GmbH since its foundation in April 2014

Richter, Reinhart
President
Ebara Precision Machinery GmbH

Biography
Reinhart Richter has recently been appointed President of EBARA Precision Machinery Europe GmbH. Previously he has worked for over 13 years at Multitest as Vice President sales and marketing and later President successfully promoting the company's transition to a leading edge solution supplier for advanced test handlers, test sockets and DUT boards. After the acquisition of Multitest by LTX-Credence he served the newly formed Xcerra Corp. as Chief Technology Officer. Prior to Multitest he held various positions at KLA-Tencor Corp., BBN Inc., and IABG. Reinhart Richter holds a M.Sc. and Ph.D. in Solid State Physics from McGill University, Montreal, Canada, and has authored over a dozen peer reviewed scientific papers.

Integrating critical sub-fab equipment into future adaptive maintenance methods.

Czerniak, Mike
Environmental Solutions Business Development Manager
Edwards Ltd

Abstract
As a substantive contributor to fab utility consumption, vacuum and abatement systems provide a focal point for cost reduction. The common themes of "green-mode" and reduction of the threshold barriers to implementation are developed. The pathway to a managed solution is vital and splits into two distinct areas. First formation of knowledge base for green mode actions based on process risk mitigation. Secondly, standardised approaches to distributing that knowledge throughout the broader fab. In EEM450PR models were constructed to simulate the impact of green modes, at various levels of wafer fab utilisation, initially for 300mm, and then extended for a hypothetical 450mm fab. It was also noted that additional savings would be possible in the facility. The model was then validated by looking at data from a representative high volume manufacturing 300mm fab, simulating the impact of green modes (without actually implementing them), and also live green mode implementation on pumps and abatement at a R+D lab in Europe. In G450C, Edwards' emphasis has been the risk mitigation elements and to capture sub-fab data analytics as a solid foundation for implementation of green modes in 450mm. / advanced node high volume manufacturing. Through incorporating vacuum as a key variable during the process qualification of the installed tools and then monitoring changes in this captured data, the basis for methodologies for risk mitigation are being designed for advanced vacuum systems.. Underpinning the data analytics is the requirement to ensure that data capture is robust & easily and precisely disseminated across the future fab wide information topologies. Central to this is the provision of standardised and agnostic interfaces and within this approach, a clear and strong focus on tool-centricity. The aim is to provide the material conditions for the progressive (fab and sub-fab synchronised) introduction of adaptive / condition-based maintenance modalities.

Biography
Following obtaining his doctorate in Electrical engineering from Manchester University in 1982, Mike started full-time work at Philips' UK R+D labs in Redhill, UK, working on the MOCVD growth of II-V materials, followed by 2 years in Holland transferring a III-V MOCVD process into the Nijmegen fab. Mike returned to the UK with Cambridge Instruments, a MOCVD OEM as a Product Specialist, before working at Courtaulds Advanced Materials in Business Development roles. He moved to UHV OEM VSW, then joined VG Semicon as Product Manager for MBE UHV systems. He joined Edwards 19 years ago, working through a number of roles before starting his current job this year as Environmental Solutions Business development Manager.

Management of hazardous process tool exhausts in high-volume device manufacturing

Chambers, Andrew
Senior Product Manager
Edwards Ltd.

Abstract
This paper reviews cost-effective methods for reducing risks associated with hazardous process tool exhausts. Typical risks fall into three categories - flammable process gases, condensed materials in exhausts, and toxic or corrosive gases. Although methods are available to mitigate these risks, their implementation is becoming increasingly inefficient and expensive. Dilution is widely used to reduce the risk of flammable process gas fires, but this is an intrinsically expensive method. Operational efficiency can be improved by reducing dilution rates, but personnel and equipment should not be exposed to increased risk as a result. To meet this need we propose that process exhaust designs incorporating fully-integrated safety features provide enhanced exhaust system integrity during high volume manufacturing with frequent service activities. Condensed materials block exhausts, and high pump exhaust pressure may cause seal damage or dry-pump shut-down. When blocked exhaust pipes are removed for cleaning, HF may be released from condensed materials on exposure to air. Furthermore, exhaust pipe fires may be caused by reaction of F2 gas with condensed silicon compounds during chamber cleaning. Exhaust pipe heating is used to avoid blockages and mitigate chemical hazards, and for efficient operation, the temperature management system may be integrated with other exhaust safety features. Gas leaks from damaged or poorly-maintained exhaust pipes cause equipment damage and harm to staff, and hazardous gas may contaminate the fab. Extracted equipment enclosures can mitigate the impact of gas leaks, but they take clean air continuously from the sub-fab which must be replaced with expensive clean make-up air. We propose that an integrated approach to process exhaust design, including continuous seal integrity checking, intelligent pipe temperature control and double-contained exhaust pipe joints improves fab safety and environmental stewardship while reducing total cost.

Biography
Andrew Chambers is a Senior Product Manager at Edwards Ltd. He is responsible for commercialisation and product management of new integrated sub-fab process solutions, which deliver industry leading operational efficiencies and low total cost of ownership. He has also served as Technical Manager for Edwards' Exhaust Gas Management Division, where he managed engineering and R&D activities for the semiconductor, flat panel and compound semiconductor business segments. With over 34 years working in the semiconductor industry Andrew has extensive applications experience, having held technical and managerial roles at several process tool and sub-fab equipment OEM companies, including Tokyo Electron Europe Ltd, Surface Technology Systems, Electrotech Group, Lasa Inc. and Oxford Instruments Plasma Technology.

A proposal for full test line automation at package level of SoC, under the very high test time paradigm

Moriconi, Luca
Test Application Division Manager
ELES Semiconductor Equipment Spa

Abstract
The present paper proposes an innovative automation solution that allows to overcome the high test time paradigm achieving a cost of test and complexity reduction with respect to the current approach based only low parallelism test architecture. This can be achieved by partitioning the test between a Massively parallel Low cost Tester and a standard ATE integrated with a low handling parallelism in a fully automated test line. In addition to that, the solution is able to perform adaptive test and embed reliability stress tests that can be analysed and used to guarantee maximum quality. Semiconductor products are becoming more and more complex and the expectations in terms of quality and reliability are growing especially in the automotive market, thus requiring the need for new test strategies: i.e. Application Specific tests, Re-configurability and Repair, Subtle defect screening. In this scenario the test time is going to increase from few seconds to probably minutes. The traditional approach - i.e. Pick&Place Handlers - that focuses on increasing the handling parallelism does not seem to be the most efficient answer. Complexity and cost would go dramatically up. ITRS Roadmap for Multisite Test at package level of MCU low power indicates that para 32 will be probably the limit for next years. As a consequence, new test arrangements need to be considered for a more cost effective solution. The aim of this paper is to propose an innovative Test Cell, fully automated, that bypasses the need of a high handling parallelism to manage the growing complexity. This solution is a fully integrated Test Cell in which N different Test stations are connected and different test insertions are managed within the same automated line; the device handling, loading/unloading for all the test insertions is fully automated as well.

Biography
Luca Moriconi holds a degree in Electronic Engineering from the University of Perugia, Italy. Luca joined ELES Semiconductor Equipment in 1999 and worked in the semiconductor reliability and testing industry as Senior application engineer and Test Application Division Manager. Luca in 2015 became Head of Technology and Solutions at Eles supporting the definition of the technical roadmap for the different solutions and the business development activities.

Industrial High Throughput Atomic Layer Deposition Equipment and Process for OLED Encapsulation

Kools, Jacques
CEO
Encapsulix

Abstract
Thin film encapsulation is a key enabling technology for OLED devices, in particular for applications such as automotive lighting and flexible displays. Ultrathin films deposited by low temperature Atomic Layer Deposition (ALD) have recently gained interest as an attractive approach. In order to enable a viable industrial solution, it is required to deliver low temperature processes (less than 100°C), exceptional barrier performance (WVTR better than 10-5 g/m2/day), high throughput processing (i.e. deposition on large glass substrates with takt times of a few minutes) and acceptable cost of ownership (single digit Euro per m2). Traditionally, ALD processes have been able to demonstrate barriers of excellent quality. However, the low throughput of these traditional processes has been a limiting factor for their adaptation in high volume manufacturing of OLED devices. The Parallel Precursor Wave (PPW) reactor architecture developed by Encapsulix allows overcoming this barrier, by a significant increase of the deposition rate (factor 20 or more) and reactor size (scaling to meter size). This innovative reactor technology has now been deployed for OLED manufacturing in the infinityTM series of equipment, which covers substrate sizes from 200x200mm (Infinity M200D) to Gen 2.5 (Infinity M500D) to Gen 4.5 ( Infinity M750D). In this presentation, we will review industrial solutions for OLED encapsulation for lighting and display application. Items which will be discussed include: *** The underlying gas injection and wave propagation technology allowing extremely fast pulsing and purging of precursors *** Process data, including optical , mechanical and barrier performance data *** Manufacturing data, including uniformity, repeatability, throughput, ..etc

Biography
Jacques Kools studied physics and materials science at Antwerp University (Belgium). From 1986 until 1997, he was a research scientist at Philips Research Labs in the Netherlands, working mostly on surface science and thin film materials. From 1997 through 2004, he worked in the semiconductor equipment industry in California, at CVC and Veeco. Since 2004, he is based in the South of France, on an entrepreneurial track. He founded Encapsulix in 2011.

Wine fermentation without worries

Blazinsek, Martin
CEO
Enolyse d.o.o.

Abstract
Winemakers lack time to constantly measure sugar during wine fermentation, because they have to focus on the harvest. Average winemaker in our segment spends 3h per day just for measuring sugar. They hardly ever analyze their data after the harvest, because they keep it in their mind, notebooks or on tanks, which is really unordered. If winemakers not keep track of sugar levels during wine fermentation this can affect wine quality. The solution is an IOT platform, which helps winemakers to track their work and measurements in the wine cellar quickly and easily. EnoMeter, smart sensor, helps them to track wine fermentation automatically and continuously by measuring sugar level and temperature every 2 hours. With EnoMeter they save time, improve wine quality and consequently increase wine price per bottle. We've developed a mobile app for Android and iOS, which helps winemakers to easily enter and track manual measurements, fining agents, racking, filtrations and track wine fermentation during their work in the wine cellar. We've also invented our own method for measuring sugar in liquids, which we've implemented into our smart sensor EnoMeter. EnoMeter measures electro-chemical properties of wine. Sensor sends all the data to the EnoApp via Bluetooth communication.

Biography
Martin Blazinsek has graduated at Faculty of electrical engineering, University of Ljubljana in 2010. After his study he has been working 3 years at the same faculty as a researcher in Laboratory of Modelling, simulation and Control and has developed algorithm for auto-tuning PID controllers. In 2013 he co-founded startup Enolyse, where he works as CEO and also works on marketing and sales.

The Green Contactless Horizontal Wafer Shipper Solution

Lundgren, Jorgen
Senior Applications Engineer
Entegris GmbH

Abstract
The traditional Horizontal Wafer Shipper with foam and interleaf was developed in early 2000. Since then many thousands have successfully been sold and used to ship hundreds of thousands of finished wafers around the globe. Recently semiconductor manufacturers started seeing issues and concerns with the Horizontal Wafer Shipper using advanced and or lensed/bumped wafers during storage and shipping applications. Customers started reporting flattened or shared lead bumps and also stain on their wafers. Investigations revealed that the ESD coating of the inserts is a salt comprised of potassium. In the presence of moisture, the potassium coating migrates to the wafer surface and can contaminate the finished product. The shared lead bumps are caused by the interleaf surface being in contact with the wafer surface. The request was to develop a Horizontal Wafer Shipper without the foam and interleafs. The new solution was completed in 2010 and the Contactless Horizontal Wafer Shipper (CL HWS)was developed. CL HWS consists of a base and top cover and 26 rings, the rings stack on top of each other and keep the wafers from contacting each other. The CL HWS is designed for standard, thin, 3D, MEMS and bumped wafers and eliminates the need to use inserts and foam cushions. The CL HWS significantly reduces the number of particles during shipments, has ESD properties is automation compatible and reusable. The CL HWS family includes products for 150mm, 200mm and 300mm wafers and can accommodate wafer thicknesses from 150um up to 950um for the 150mm and up to 1100um thick for the 200mm and the 300mm CL HWS product.

Biography
Senior Field Applications Engineer with electronic engineering degree from Sweden. Previously with a Swedish International company for 10 years in a world wide technical support function, 5 of those based in Germany. Worked for Entegris for the last 18 years supporting the Semiconductor Industry in many different technical roles with focus on wafer and reticle handling, transport and contamination control. Heading up key projects such as product qualification of a number of 300mm fabs in Europe, European fab conversions, as well as a large number of individual customer development projects. Active contributor to Entegris/CEA-Leti collaboration FOUP polymer contamination/decontamination research Project. Partner in the Catrene 3D European wafer handling Project. Active SEMI participant.

Large diameter GaN-on-Si epiwafers for Power Switching and RF Power electronics with enhanced efficiency

Germain, Marianne
CEO
EpiGaN nv

Abstract
GaN-on-Si technology is mandatory for extending the power electronics performance beyond Si material limitations. It is about reducing energy loss (power supplies, motor drives), enabling higher operating temperatures (servers, electric vehicle *** ) or reducing size and weight of power converters (computer power supply, automotive, space***). The decisive advantage of GaN-on-Si technology to break the Si boundaries for efficient power conversion resides in its excellent and unique combination of performance (breakdown voltage/reduced leakage/lower conducting and switching losses) and cost-efficiency. This mainly thanks to the use of low cost Si substrates, available in large diameters, fully compatible with existing Si manufacturing lines or foundries. Based on more than 15 years of experience in the field of MOCVD-growth of III-Nitrides structures, EpiGaN has established in its dedicated clean-rooms, a unique manufacturing platform supplying GaN epitaxial wafers to the semiconductor industry for power electronics, but also RF electronics for sensors applications. One of the key differentiators, the capping of the epiwafers with in-situ grown SiN, is offered as the optimal surface passivation layer; it enables more robust and more reliable devices, as well as provides the possibility for reducing transistor dimensions and thus increasing the number of chips per wafer. We'll review the key technical specifications of our GaN-on-Si epiwafers suited for industrial use, today developed on 150 mm as well as on 200 mm wafer diameter.

Biography
Marianne Germain is co-founder and CEO of EpiGaN nv. She received in 1999 her PhD degree in Electrical Engineering from the University of Liège (BE), where she conducted research in close collaboration with RWTH Aachen, and as invited scientist in Purdue University (US) and Wuerzburg University (D). In 2001, she joined imec, an international microelectronic research center (Belgium), where she led the development of Gallium Nitride technology for high power/high frequency applications. Since 2004, she became Program Manager of the "Efficient Power/GaN" program, then, group leader of the "III-V systems" group (2007/2010). She also pursued training management course in Vlerick Management School (Gent) in 2008/2009. In May 2010, with her colleagues, Dr Joff Derluyn and Dr Stefan Degroote, she co-founded "EpiGaN", a clean-tech spin-off, manufacturing GaN epiwafers for electronics applications, where she acts as CEO and member of the Board of directors. She has authored and co-authored more than 100 international communications. She co-holds several patents in the field of GaN material and devices.

Ultra-Low Power Computational Sensing: Challenges and Opportunities

Benini, Luca
Professor
ETH Zurich

Abstract
The "internet of everything" envisions trillions of connected objects loaded with high-bandwidth sensors requiring massive amounts of local signal processing, fusion, pattern extraction and classification. Higher level intelligence, requiring local storage and complex search and matching algorithms, will come next, ultimately leading to situational awareness and truly "intelligent things" harvesting energy from their environment. From the computational viewpoint, the challenge is formidable and can be addressed only by pushing computing fabrics toward massive parallelism and brain-like energy efficiency levels. We believe that CMOS technology can still take us a long way toward this vision. Our recent results with the PULP (parallel ultra-low power) open computing platform demonstrate that pj/OP (GOPS/mW) computational efficiency is within reach in today's 28nm CMOS FDSOI technology. In the longer term, looking toward the next 1000x of energy efficiency improvement, we will need to fully exploit the flexibility of heterogeneous 3D integration, stop being religious about analog vs. digital, Von Neumann vs. "new" computing paradigms, and seriously look into relaxing traditional "hardware-software contracts" such as numerical precision and error-free permanent storage.

Biography
Luca Benini is the chair of digital Circuits and systems at ETHZ and a Full Professor at the University of Bologna. He has served as Chief Architect for the Platform2012/STHORM project in STmicroelectronics, Grenoble. He has held visiting and consulting researcher positions at EPFL, IMEC, Hewlett-Packard Laboratories, Stanford University. Dr. Benini's research interests are in energy-efficient system design and Multi-Core SoC design. He is also active in the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications. He has published more than 700 papers in peer-reviewed international journals and conferences, four books and several book chapters. He is a Fellow of the IEEE and a member of the Academia Europaea.

REACH as an opportunity for Semiconductor Industry

Di Bastiano, Augusto
Senior Scientific Officer Risk Management
European Chemicals Agency (ECHA)

Abstract
The Regulation 1907/2006 of the European Union(referred as the REACH Regulation) on Registration, Evaluation, Authorisation and Restriction of Chemicals entered into force in 2007 in the EU. The Regulation has been adopted to improve the protection of human health and the environment from the risks that can be posed by chemicals, while enhancing the competitiveness of the EU chemicals industry. REACH applies to all chemical substances; not only those used in industrial processes but also in our day-to-day lives, for example in cleaning products, paints as well as in articles such as clothes, electronic devices, vehicles, equipment and machineries, furniture and electrical appliances. Therefore, the regulation has an impact on most companies across the EU but also on non EU companies with an EU business. This presentation aims to raise awareness on key REACH processes with potential impact for the semiconductor industry i.e. Supply Chain communication, Substances of Very High Concern, Authorisation, Restriction and Substances in Articles. It aims also to provide some practical information on how the Semiconductor Industry can support the Authorities' decision making process and to demonstrate that the burden for Industry can be significantly eased by early actions that anticipate regulatory decisions.

Biography
Augusto Di Bastiano joined the European Chemicals Agency (ECHA) on 2009. He currently held the position of Senior Scientific Officer in the Risk Management Implementation Unit. In his position at ECHA, Mr Di Bastiano has been involved in various projects related to the development and implementation of the Exposure Scenario Concept in the supply chain, assessment of Intermediates, identification and implementation of Regulatory Risk Management Options for substances of very high concern. Prior to joining the Agency Mr Di Bastiano worked for 13 years in the semiconductor industry in Europe and in the United States holding several technical and managerial positions in the field of Facilities Operation and EHSS at local and corporate level. In his corporate role he coordinated the identification, development and implementation of EHSS programs at local and global scale. He has also worked in the Chemical Industry as process engineer, and in the Mechanical Industry as head of quality control. Mr Di Bastiano holds a degree in Chemical Engineering from University of Rome and is a licenced professional engineer. Mr Di Bastiano is Italian.

EU Industrial Electronic Strategy - Where do we stand?

Van Puymbroeck, Willy
Head of Unit A4 Components
European Commission

Abstract
In progress.

Biography
Willy Van Puymbroeck holds a PhD in Physics (1981) and an MBA (1986). Before joining the European Commission in 1988, he worked as a software researcher in Alcatel Bell from 1982 to 1988. In the Commission Willy Van Puymbroeck worked in various areas going from Computer Integrated Manufacturing, International Cooperation to Budget Implementation. He is currently Head of Unit in DG CONNECT 'Components' covering strategy and R&D&I in micro- and nanoelectronics and smart integrated systems.

Trends in Device Encapsulation and Wafer Bonding

Uhrmann, Thomas
Director of Business Development
EV Group

Abstract
Future needs for MEMS devices is the need of high vacuum encapsulation, where future indoor and outdoor motion sensing are up and coming applications, that demand new wafer bonding technology. However, vacuum encapsulation needs for future MEMS devices are changing. With increased sensing accuracy for more reliable motion sensing, control of vacuum levels, gas compositions and hermetic sealing are getting at center stage. One attempted solution today is the use of getter materials that are chemically binding oxygen the cavity of the MEMS after bonding. The biggest issue, however, is the special process requirements and also the need for a high temperature activation step, which is both sacrificing device performance and restricting the process latitude. With the introduction of a new wafer bonding process, the wafers are preprocessed in vacuum, which means bake out and joining is all done in vacuum. In this presentation we will focus on metal, fusion and covalent bonding technology for vacuum encapsulation with respect to future device requirements.

Biography
Dr. Thomas Uhrmann is director of business development at EV Group (EVG) where he is responsible for overseeing all aspects of EVG's worldwide business development. Specifically, he is focused on 3D integration, MEMS, LEDs and a number of emerging markets. Prior to this role, Uhrmann was business development manager for 3D and Advanced Packaging as well as Compound Semiconductors and Si-based Power Devices at EV Group. He holds an engineering degree in mechatronics from the University of Applied Sciences in Regensburg and a PhD in semiconductor physics from Vienna University of Technology.

200 mm G-FET GaN On Silicon power switch technology : a robust path to manufacturing

Letertre, Fabrice
COO
EXAGAN

Abstract
GaN on Silicon power devices are recognized as a key technology to sustain future power systems integration roadmaps in the field of IT electronics, renewable solar and emission free automotive applications. Despite significant efforts to develop cost effective, high performing and reliable devices, GaN on silicon devices still need R&D efforts to fulfill application requirements. Besides these remaining technical challenges, such new emerging disruptive technology (compared to established silicon power devices) need to prove its economic model to bring end users new levels of performance at an affordable price, out of a robust supply chain as close as possible to silicon proven one. Exagan as a new startup company is pushing the limits of its proprietary 200 mm GaN on Silicon G-FETTM technology to propose the advantage of its unique expertise in GaN on silicon material fabrication while leveraging on its attractive fab lite business model to meet future market performance, reliability and cost targets. This paper will present the latest developments achieved.

Biography
Fabrice Letertre received engineering degree from INPG- ENSPG with specialization in semiconductor materials, technology and devices, Grenoble, France in 1995. He joined CEA-LETI in 1995 in the Silicon On Insulator (SOI) material department and Soitec in 1998 where he held various R&D management and project leader positions. From 2009 to 2003, he was responsible, as Soitec group VP R&D, of managing Soitec's strategic projects portfolio including GaN, III-V and advanced SOI activities. In 2014, he co-founded Exagan with the aim to develop a leading European source of GaN power switches based on Exagan proprietary 200 mm GaN on Silicon technology, for power conversion applications. He holds more than 60 patents and has co-authored more than 40 technical papers.

Adaptive PolCarr^#CHR:reg# carriers for novel applications in live science

Schmidt, Heidemarie
Group Leader
Faculty of Electrical Engineering and Information Technology

Abstract
The selective attachment of molecular or cellular biological elements on flat substrates plays a critical role towards advancements in the field of adherent cell growth in biotechnology. As majority of the available market for live science products is based on the functionalization of substrates, new approaches offering carriers with superior performance i.e. with easy-to-control immobilization and detection of the target bio-elements are of considerable interest. Following this trend, herein we propose a promising concept for new carrier design - PolCarrWell. PolCarrWell stands for the customized PolCarr^® carrier (a doped Si-wafer with an ultra-thin insulating film and a characteristic pattern of surface near electrostatic forces, SNEF [1,2]), which is design-compatible with standard bottomless microwell plates. Though, a myriad of microplate types have been devised and successfully commercialized over the past decades, the controlled entrapment of analytes remains a challenging matter. To alleviate this challenge, manifold coatings, e.g. functionalized polyelectrolytes [3], are being applied. Unfortunately, the immobilization via functional coatings on such surface-functionalized microwell plates is very sensitive to the environmental conditions. Variable temperature, pH, pressure and humidity may strongly injury the overall binding effect. In stark contrast, the newly developed bulk-functionalized PolCarrWell (PolCarr^® carrier coupled with a standard bottomless well microtiter plate) offers a highly controlled, environmentally inert immobilization of the adherent and electrically polarizable bio-element. The entrapment is purely driven by the SNEF, which can comfortably be modulated. [1] C. Baumgart, M. Helm, H. Schmidt, Phys. Rev. B. 80 (2009) 085305 [2] H. Schmidt, S. Habicht, S. Feste, Anne-Dorothea Müller, O. G. Schmidt, Appl. Surf. Sci. 281 (2013) 24-29 [3] Advances in Polymer Science 255 & 256 (Ed.: Martin Müller), Springer, 2014

Biography
H. Schmidt from Technical University Chemnitz has completed her Ph.D in semiconductor physics at the University Leipzig in 1999. Since 2003 she heads the "Nano-Spintronics" group and develops artificial synapses for cognitive computing and smart carriers for live science applications. H. Schmidt has published more than 160 papers in peer-reviewed journals and served as an advisory program committee member for the international workshops subtherm-2011, WSE-2014, and WSE-2015. She received the Nano-Future prize from the Bundesministerium für Bildung und Forschung (2002) and a Heisenberg Fellowship from the German Science foundation (2011).

Neyer, Thomas
VP R&D
Fairchild Semiconductor

Biography
Dr. Thomas Neyer has received his PhD from University of Technology in Vienna and Cambridge University in 1995. He joined Siemens HL to work on mixed signal Product design and Test. Over the years Dr. Neyer worked on HV and BCD Technologies at Siemens and Infineon Technologies and in 2003 he was entrusted to setup Technology Centers of Competence in Malaysia and China. During the PowerFab start and ramp-up in Kulim, Malaysia in 2005, Dr Neyer was building and leading the Fab engineering and manufacturing teams. Subsequently he was appointed as EVP for R&D and Fab Operation of Grace Semiconductors in Shanghai, China - an advanced Foundry for differentiated, analog Technologies. In 2011, Fairchild Semiconductor founded a R&D center for High Voltage Technologies in Munich and assigned Dr Neyer to spearhead the effort and coordinate all related Silicon and SiC HV development activities covering device design, modeling and High Power package development.

Solar Storage: New approaches for Bidirectional Chargers

Haaf, Peter
Senior Field Application Engineer
Fairchild Semiconductor

Abstract
For multiple reasons storage systems become more important: grid stability, storage units for UPS and Solar Island grids, and for increased self consumption of residential solar plants. In this work, the most common isolated and non isolated topologies for storage systems are summarized. A clear trend to 48V batteries for the residential applications is identified. A special focus of this paper is the optimization of the secondary side by reducing all parasitics significantly with the introduction of a new packaging technology.

Biography
Peter Haaf is a Field Application engineer at Fairchild Semiconductor. He studied electrical engineering at the technical University in Karlsruhe, Germany. Prior to Fairchild, Peter worked for 8 years in the R&D department at Vossloh-Schwabe GmbH developing standard and dimmable electronic ballasts for fluorescent lamps. Peter has been with Fairchild Semiconductor for 14 years as an expert for the industrial segment focusing on lighting and high power systems like UPS, Welding, Inductive heating and Solar Inverters.

Single-Photon detectors for real-time 3D-ToF imaging

Carrara, Lucio
CTO
Fastree3D SA

Abstract
The availability of Single-Photon Avalanche Diodes (SPADs) in standard high-voltage CMOS and CIS processes offers great flexibility in the conception and design of real-time direct Time-of-Flight (dToF) imagers. The scalability of CMOS, paired with the digital nature of SPADs and their outstanding timing performance, lends itself to the conception of innovative, all-digital solutions to the problem of real-time depth sensing. Among existing techniques, Time-Correlated Single-Photon Counting (TCSPC) in particular benefits from the massive parallelism, high speed, and low power consumption of digital CMOS solutions. In this talk we focus on the core architecture of a TCSPC system and on the impact that highly integrated CMOS technologies have on speed, power consumption, and costs of the overall 3D ToF solution. We will introduce the concept of digital d-ToF pixel, and analyse two possible architectures: a pure ASIC and a mixed ASIC-FPGA.

Biography
Co-Founder & CTO, Fastree3D Senior development engineer for electronics and integrated circuit design. Expert in CMOS singlephoton avalanche diodes (SPAD) for 3D time-of-flight imaging. Over 7 years' experience in IC design, test, and fabrication, 5 of which were spent in industrial design of 3D cameras (ESPROS Photonics Corp). Education: Master Degree in Micro and Nanotechnologies for Integrates Systems (Politecnico di Torino, IT; Institut National Polytechnique de Grenoble, FR; École Polytechnique Fédérale de Lausanne, CH); Bachelor in Electrical Engineering, Politecnico di Torino (IT)

INVEST - Investment Grant For Venture Capital

Isken, Hardy
Officer (416)
Federal Office for Economic Affairs and Export Control (BAFA)

Abstract
The Federal Ministry for Economic Affairs and Energy started the INVEST - Investment grant for venture capital in 2013. Aim of this program is to help young and innovative companies to find early stage investors. Business Angels play an important role in early stage financing. The aim of INVEST is that these companies can acquire more and larger investments from business angels. The grant pays an investor 20% of his investment into a young innovative company.

Biography
Hardy Isken has administrated the investment grant INVEST - Zuschuss für Wagniskapital" for the Federal Office of Economics and Export Control (BAFA) since it started in 2013. He oversees the application process and audits all relevant contracts on the investor´s side. After working as a Key Account Manager for Apple in Ireland and as a Business Development Manager for the polish IT company Comarch AG he had co-founded a finance start-up.

UVphotonics - Design, development and marketing of UV LED-Chips & packaged LEDs

Lobo-Ploch, Neysha
Wissenschaftliche Mitarbeiterin
Ferdinand-Braun-Institut Leibniz-Institut für Höchstfrequenztechnik

Abstract
The focus of UVphotonics is the design, development, and marketing of highly efficient and reliable UV-B and UV-C LEDs for applications in disinfection, medicine, sensing and industrial production. The product portfolio comprises standardized products as well as UV LEDs tailored to customer-specific demands. The profound technological expertise of the UVphotonics team ensures that customers are provided with the most suitable and efficient LEDs for their applications. UVphotonics is in the process of being founded as a spin-off from the Ferdinand-Braun-Institut, Leibniz-Institut fuer Hoechstfrequenztechnik and the Technische Universitaet Berlin, and is supported by the German Federal Ministry for Economic Affairs and Energy.

Biography
Neysha Lobo-Ploch has been working on the development of UV LEDs since 2008. Initially as a scientist in the work group of Prof. Dr. Michael Kneissl at the Technische Universitaet Berlin, her work focused on the development of new chip-designs to increase the light extraction efficiency of UV LEDs and to improve the thermal management of the devices. Since April 2014, she has been working at the Ferdinand-Braun-Institut, Leibniz-Institut fuer Hoechstfrequenztechnik on the chip design and packaging of UV LEDs and is also responsible for customer inquiries. Her technological expertise in the field of LEDs enables her to design customer specific solutions. In the spin-off UVphotonics, Neysha Lobo-Ploch will be the Chief Executive Officer and will be responsible for the marketing and sales of UV LEDs.

Individualized sensor production for industrial applications: expectations and options

Krause, Peter
VP Business Unit Industrial
First Sensor AG

Abstract
The sensor market is divided into two main streams of production: Low and medium market of the specialists for customized solutions and the market of high volume standard products of mass production manufacturer. Drivers of the industrial sensor market are high flexibility combined with high reliability, by continuous cost reduction and demand for a short time to market. The relationship and successful combination of these drivers will be discussed within different projects along the value chain (from wafer production incl. MEMS technology up to packaging and system production). Co-Author: Franz Leibl, Site Manager First Sensor Wafer Fab

Biography
Peter Krause studied Physics at Humboldt-Universität zu Berlin with an emphasis on ion and electron physics. After working as a development engineer in the field of ion implantation, he acquired extensive knowledge of MEMS sensors as a research assistant at Technische Universität Berlin, where he was responsible for development work on microsensors and actuators at the "Institute for Microperipheric Technologies." Since 1999, Peter Krause has headed the piezoresistive pressure sensor chips area at First Sensor as Managing Director. In 2013, he assumed joint management of the Business Unit Industrial with Olaf Hug. Both are reorienting the unit strategically and stand for its success. Peter Krause is also responsible for the areas of development and quality management.

Novel Health Solutions for patients and consumers

Joos, Henk
Managing Director
FlandersBio vzw

Abstract
The Health Management space where pharmaceutical and biotech companies traditionally were the sole actors is being disrupted dramatically due to the entrance of new players traditionally active in the food or consumergood space. The presentation is going to explain what are the key causes for this perfect storm, but will also elaborate on the challenges of collaboration in this new space. The presentaion will also explain the activities that are specifically undertaken in the region of Flanders (Belgium) in order to manage this storm.

Biography
Dr. Henk Joos had a career in different farmer oriented biotech projects in Plant Genetic Systems, AgrEvo, Aventis and Bayer CropScience before he became involved in the development of novel feedstock species for the production of energy. Dr. Joos became managing director of FlandersBio in December 2013.

Low cost flexible displays and ubiquitous sensors for Wearables, Everywhere-ables and IoT

Milligan, Chuck
CEO
FlexEnable Ltd.

Abstract
Rigid large area displays and sensors today have provided a constraint in design and implementation for so many years that we almost forget until it's pointed out - for example the only flat surface in most cars today is the LCD display. Large area flexible electronics is the key to activating surfaces in our daily lives - from wearables to car dashboards and windscreens, the ability to conform as well as curve display and sensor surfaces opens up almost limitless applications. Such technology is perfectly complementary to silicon - where cost per unit area (rather than cost per function) is the key economic metric, flexible electronics can broaden silicon's reach into bringing surfaces to life everywhere with displays and sensing. Building supply chains and enabling end user companies to trial such new technology is key to kick-starting new markets for this technology. We have developed a flexible electronics platform that is highly compatible with existing FPD infrastructure, to produce highly flexible, light-weight and unbreakable displays and sensor arrays. We will discuss the economic breakthrough of this approach, and the business opportunities that this creates for a new generation of electronics.

Biography
Chuck Milligan is CEO of FlexEnable, the leader in flexible electronics technology for wearables and sensors. Chuck has over 20 years' commercial and general management experience across the globe in the semiconductor, consumer electronics, communications, industrial and aerospace markets. Most recently, Chuck served as CEO of EM Test, the leading conducted EMC test equipment company, successfully completing its sale to AMETEK in 2011. Prior to this, Chuck was CEO of Finnish/Swiss firm Heptagon micro-optics, which he grew from a 16-employee, pre-revenue company, to an industry-leading business, with 300 employees and a Singapore-based volume production facility - working with leading mobile handset companies such as Nokia and Apple. Raising $70m from venture capital and strategic investors, Chuck was able to achieve this growth over a six-year period. Chuck also served as Vice President of Industrial & Defense Solutions for Bookham Inc., a leading international optical components manufacturer. Chuck was Commercial Director at JDS Uniphase/Nortel Networks GaAs semiconductor fab in Zurich, Switzerland prior to Bookham's acquisition of the company. American-born, Chuck moved to Switzerland 20 years ago to establish a Europe/Africa sales office for Harris RF Communications. He speaks English, French and German.

Ciesinski, Mike
President and CEO
FlexTech Alliance

Biography
Michael Ciesinski is president and chief executive officer of the FlexTech Alliance (www.flextech.org). FlexTech is a R&D consortium and trade association chartered with building the infrastructure for flexible electronics manufacturing. FlexTech sponsors and conducts a multi-million dollar technology development program, as well as providing the industry with technical, financial and market information. Ciesinski's prior executive positions include vice-president and director of North American Operations for Semiconductor Equipment and Materials International (SEMI), an international trade association in San Jose, CA. Prior to joining SEMI, Ciesinski was appointed as Director, New York State Labor-Management Committee. Under Ciesinski's direction, FlexTech has completed 150+ R&D projects and coordinated more than $170M in federal R&D directed to the flat panel display (FPD) and flexible electronics supply chain. Industry cost-share funds have contributed an additional $200M of the total FlexTech R&D program. In February 2012, FlexTech created and now manages the Nano-Bio Manufacturing Consortium (www.nbmc.org). In August 2015, FlexTech was awarded a $75M U.S. Government grant to form and manage a Flexible Hybrid Electronics Manufacturing Innovation Institute (www.fhemii.com). In addition to directing an aggressive R&D program, FlexTech sponsors capital investment forums with participation from small and mid-cap companies and start-up firms. FlexTech's industry workshops and conferences set the standard for information and technology exchanges within the flexible electronics community. Michael Ciesinski is a graduate of the State University of New York at Albany. He is a member of the Board of Directors of FlexTech Alliance and a member of the Dean's Advisory Council (Engineering) at the California Polytechnic State University at San Luis Obispo.

Key Technology Trends and Emerging Applications for Compact Thermal Imagers

Walters, Michael
Vice President of Micro Camera Product Management
FLIR

Abstract
The FLIR Lepton LWIR camera module, which was introduced in January 2014, has demonstrated that compact, cost-effective thermal imaging modules are achievable for consumer electronics applications. The FLIR ONE which turns a mobile phone into a complete thermal camera solution has further started the process of putting thermal imaging in the hands of many consumers. The open question is, "What is the killer application for consumer thermal imaging?" This paper presents an overview of some key technologies and technology trends that will enable consumer thermal imaging applications. This paper also discusses the range of potential future applications for thermal imaging and how the market and use cases might evolve over the next 3-5 years.

Biography
BA Physics and BS Electrical Engineering, University of Southern California 1984 MS Electrical Engineering, Stanford University, 1988 31 years of professional optoelectronic experience at Hewlett Packard's components group, Flextronics/Vista Point and FLIR. Co-founded Hewlett Packard's CMOS camera module business for mobile phones in 2001. Related areas of interest: Integrated circuit design, sensors, semiconductor processing, mobile phones and Internet of things I joined FLIR in May of 2012 where I am Vice President of Micro Camera Product Management. I am responsible for the Lepton LWIR camera module family and the FLIR ONE smart phone thermal attachment camera family at FLIR.

Alternative Hardware Architectures for Digital Imaging

Zaharia, Corneliu
VP, VLSI
FotoNation Ltd.

Abstract
Computer vision and smart imaging are becoming part of many advacned electronic systems. The latest digital cameras and smartphones incorporate a range of face tracking, analysis and even dynamic 'beautification' of facial regions. The same technologies can be extended to high performance scene analysis, pedestrian detection, video stabilization and dynamic distortion correction. GPU based chipsets can provide some of these capabilities, but they are not energy efficient. The technology was developed for high-quality gaming applications and when adapted into handheld devices retains high power requirements of the order of a watt per GPU core. Energy is currently the limiting factor of performance in handheld devices and is becoming increasingly important in the automotive sector where the latest stop/start and hybrid technologies need to carefully conserve and manage battery power. There is a need for solutions to dramatically increase the energy efficiency of advanced computer vision systems. In this presentation several alternative hardware architectures are presented to solve several fundamental image processing challenges 'at the edge'. This is the optimal place to processing image data - in the main pipeline as it is clocked off the image sensor and before compression for storage or transmission over a network. Solutions are provided for (i) a template matching engine for multi-object detection; (ii) a programmable distortion correction engine; (iii) a hierarchical registration engine for inter and intra-frame motion analysis that can distinguish device from object motion; (iv) a system-on-chip design that can integrate the above and other support hardware on a platform that is 10% of the size of a typical GPU core and with power requirements of 10s of milliwats, rather than a watt per GPU core. Some practical evaluation tests will be presented to demonstrate the scalability of these architectures beyond full-HD to 4k and even 8k video streams.

Biography
BS in Applied Electronics (2000) and Industrial Electronics (1996) and MSc in Electronic Design Automation (2002), Transilvania University in Brasov, Romania. 15+ years of VLSI design experience in the imaging industry. Currently managers FotoNation's VLSI team with over 20 ASICs (mobile and/or DSC) containing one or more FotoNation IP cores. Teaching digital electronics and computer architecture in Transilvania Univerisity, Brasov. Areas of interest include digital electronics, hardware description languages, computing architectures, machine learning and Network on Chip.

Innovative and environmental friendly Fluorine F2 based cleaning process to replace C2F6, CF4 and NF3 as cleaning gas

Wieland, Robert
Nano Materials, Devices & Si Technologies
Fraunhofer EMFT

Abstract
Since the beginning of the 1980's per fluorinated carbons (PFC's) such as C2F6 and CF4 have been used as cleaning gases in thin film technology and since the 1990's NF3 has been used in the same way. PFC's and NF3 have long atmospheric lifetimes and therefore high global warming potentials. The main applications of these gases are to remove residual films left behind after a chemical vapor deposition process (CVD). The most important materials to be removed are dielectric layers like silicon oxides (SiO2), silicon nitrides (Si3N4) and, to a certain extent, conducting films like doped poly-silicon and silicide layers. According to the World Semiconductor Council the semiconductor industry in 2013 used 7512 t NF3, 1133 t CF4 and 708 t C2F6 on a global basis. Approximately 72% of all semiconductor industry emissions are based on these three gases (C2F6, CF4 and NF3). Fraunhofer EMFT and Solvay Special Chem have developed an alternative cleaning process, which can be a "drop in" replacement for the PFC's and NF3 used in semi. tools. The target of this work was to find viable alternative gas mixtures for the semiconductor industry which could be used as a "drop in" to avoid additional high investment costs from equipment modification. Crucially our study has demonstrated that these more environment friendly gas mixtures also provide a more efficient and faster cleaning behavior. A shorter cleaning time can lead directly into a higher equipment throughput and more cost effective usage of these expensive thin film tools. Higher throughput of the existing equipment will lead to an immediate decrease in the cost per wafer and an increase in the profitability of a FAB. A first "mini marathon" test run has been performed to generate data on particle and tool attrition. The test reactor, a 200mm wafer size CVD tool, was equipped with a mass spectrometer, to verify the end point of the chamber cleaning and to gain an overview of the waste gases going into the abatement system.

Biography
CV Robert Wieland: Robert Wieland received his degree in physical engineering, TH Ravensburg-Weingarten, and is responsible for plasma deposition and plasma etch processes at Fraunhofer EMFT, Hansastraße 27d, 80686 Munich, Germany. Phone: +49 89 54759 373 mail: robert.wieland@emft.fraunhofer.de CV Dr. Jamila Boudaden: Jamila Boudaden received her PhD degree in physical from the University of Basel. Since 2011, I am responsible of CVD processes at Fraunhofer EMFT, Hansastraße 27d, 80686 Munich, Germany. Phone: +49 89 54759 161 mail: jamila.boudaden@emft.fraunhofer.de CV Michael Pittroff Michael Pittroff is Global Marketing Manager for electronic gases and worked for Solvay in several functions like research& innovation, technical service in several countries (Belgium, Korea and Germany). Phone +49 511 857 3448 mail : michael.pittroff@solvay.com

Cost efficient miniaturised silicon micropumps for medical applications

Richter, Martin
Head of Department
Fraunhofer EMFT

Abstract
Drug delivery components like micropumps to be in contact with medicals have to be disposable and for that very cost efficient. Beside functional challenges like back pressure, particle tolerance, free flow protection, flow control and dosing accuracy, these cost requirements are hurdles for successful industrialization of micropumps. The smallest state of the arte micropumps are made of Silicon (e.g. chip sizes: Fraunhofer micropump 7x7 mm2, Debiotech micropump: 6x10 mm2). That chip size makes it very difficult to meet manufacturing costs below 1 $/chip, even at mass production. It is evident that manufacturing cost scale down with the chip size of the silicon micropump. With that, to address high volume medical applications like therapy of diabetes or other medical patch pump applications it is essential to shrink the micropump chip furthermore. On the other side, from physical reasons it is just difficult to meet micropump performance parameters like stroke volume, flow rate, compression ratio or back pressure ability, if the lateral dimensions of the actuation diaphragm will be reduced. Next, not only the silicon front end technology, also the back end manufacturing steps like piezo mounting has to be cost efficient. Finally, also the fluidic test cost of the micropump chip. In this presentation an overall strategy will be presented for a Technology platform for Silicon micropumps with small chip sizes down to 3x3 mm2. Results of this strategy regarding piezo mounting on wafer level, fluidic micropump test on wafer level are explained. Finally, first performance results of a 5x5mm2 micropump chip will be presented

Biography
Martin Richter´s mission is to enable microdosing systems for industrial applications. He studied Technical Physics at the Technical University Munich. His PhD about Simulation and experimental characterisation of microfluidic systems was finished 1998. Since 2000 he is head of department Micromechanics, Actuators and Fluidics of Fraunhofer EMFT in Munich.

New processing scheme for embedding and interconnection of ultra-thin IC devices in flexible chip foil packages

Landesberger, Christof
Dipl.-Phys.
Fraunhofer EMFT

Abstract
The paper will present the concept and the successful technological demonstration of a new processing scheme for the manufacture of flexible chip foil packages and experimental data on the mechanical behavior of thin silicon embedded in polymer laminates. Technological Concept: By a first processing step thin or ultra-thin microelectronic devices are bonded onto a film substrate in face-up orientation. Then devices are embedded in a planar polymer layer, which can be structured by a photolithographic process. After opening the vias above the IC contact pads a thin film redistribution process is carried out, which results in a fan-out routing for the I/O contact pads. Finally the top wiring layer can be covered by a polymer film layer. Such concept results in a chip-foil-package where fragile ICs are embedded in the center of a three layer plan-parallel polymer laminate of an overall thickness below 150 µm. Technical Results We prepared 25µm thin microcontroller IC (Microchip, PIC16LF1519). For the first demonstrators we used sheets of polyimide films with a thickness of 50 µm and a diameter of 150 mm, which were temporarily attached onto silicon carrier wafer. This allows photolithographic patterning for a large number of chip packages in parallel. We used sputter deposited copper films for interconnects and top wiring layer. Finally the polyimide films were released from the carrier and cut into separated chip-film-packages. It was verified that a high yield has been reached for the electrical interconnects. Detailed results will be presented in the paper. Furthermore, it was experimentally confirmed that embedding of 30 µm thin silicon samples in polymer laminates nearly triples the fracture strength of the fragile silicon components. This result is in very good agreement with FEM calculations of the deformation of thin silicon embedded in polymer films.

Biography
Christof Landesberger received the diploma degree in physics from Ludwig Maximilians University in Munich. He joined Fraunhofer Institute in Munich in 1990. Since 2000 he is heading the research group "substrate preparation and handling" at Fraunhofer EMFT. He has been working in the field of ultra-thin silicon since more than 15 years and prepared more than 20 patent applications in the field of processing techniques for ultra-thin semiconductors. His current research topics are focusing on new packaging technologies for ultra-thin semiconductor devices and handling techniques for fragile substrates by means of electrostatic forces. Christof is chairman of the international workshop "Thin Semiconductor Devices" (www.be-flexible.de) since year 2000.

Tailoring Printed Primary Batteries for Various Kinds of Applications

Willert, Andreas
Senior Scientist
Fraunhofer ENAS

Abstract
Printed batteries are almost known for two decades although only a very small number of applications made it to the market that are powered by this type of energy storage devices. The approach of this implementation of electrochemical energy is reasonable: employment of printing technology to deposit the demanded amounts of battery materials delivering exactly that amount of energy for the application that is required during its lifetime. Additionally this type of battery has unique features like bendability or a very thin encapsulation. In this presentation an overview is given about approaches to customize electrical power according to applications' requirements. Achievements are presented as well as implications deducted. E.g. our approach is to design the battery consequently according to the boundary conditions of the application. I.e. to arrange areas for different components of the application rather than to design the application around any type of standardized battery. Following this approach applications like LED demonstrators or the power supply of a sensor device are presented.

Biography
Dr. Andreas Willert is deputy head of the department Printed Functionalities at the Fraunhofer Institute for Electronics Nano Systems ENAS in Chemnitz, Germany, since 2007. Since 2003 he has studied various processes related to printing processes. Since 12 years he is giving lectures about printing technologies and their applications. He graduated from the Kiel University in Physics and holds a PhD in Physics from the Technische Universität Chemnitz. He is involved in R&D aiming in manufacturing of functionalities employing printing technologies. Further topics are printed large area electronics, the digital manufacturing of smart objects and the industrialization of these activities.

Coating, encapsulation, and packaging technologies for smart integrated systems

Baum, Mario
Researcher
Fraunhofer ENAS

Abstract
Highly integrated and autonomous sensors and electronics fabricated using semiconductor technologies conquer our modern society in all possible fields. Smaller footprints, integrated communications and power supply should work together with high precision MEMS and electronics. Smart miniaturized systems enable novel applications but demand at the same time new materials, coatings, and packaging concepts to address functionality, biocompatibility, reliability, and live time as well as cost issues. Fraunhofer ENAS is facing these challenges in certain fields. Using nanoimprint technologies novel surface properties due to nano patterns could be achieved. Ionic liquids enable electro chemical deposition of special metals like Ti, Pd, Al and others or even for functional coatings or active sensor structures. Room temperature parylene deposition is used for homogenous biocompatible thin film coatings, for moisture barriers or intermediate layers. Different types of Parylene could be deposited including special pre-treatment processes at room temperature. Adpating well known screen and ink-jet printing processes together with 3D suitable aerosol-jet technologies nanoparticle based inks or pastes could be deposited on different substrates like flexible organics, polymers, PCB's, wafers, etc. Additionally the combination and process integration of these techniques with established micro system technologies will lead to better performances of micro and nano systems in future.

Biography
Mario Baum was born in 1975 in Burgstaedt near Chemnitz, East Germany. After taking a combined MBE (Master of Business and Engineering) degree at Chemnitz University of Technology he started working as an application engineer for a company called GEMAC mbH Chemnitz in the field of micromechanical sensor systems. In 2002 he joined the team of Prof. Gessner at Fraunhofer ENAS (formerly Fraunhofer IZM) as a scientist with both research and marketing tasks. In 2015 he finished his Phd thesis on packaging topics. Currently his research work is focused on MEMS packaging and microsystems as well as medical applications.

WIRAplant WIReless Active imPLANTs

Büker, Maik-Julian
Researcher
Fraunhofer ENAS

Abstract
Implants with actuators and telemetry functionalities require a lot of energy. Therefore wireless charging of the implants is useful: Inductive wireless charging of the Implants through the skin with ranges from 5cm (5W) to 15cm (0,5W). By using smart antenna structures we can deliver an optimized lateral freedom for displacement. Also a impedance matching method is introduced to improve efficiency. The presentation will be rounded off to telemetry through the transition and actuators.

Biography
Maik-Julian Bueker was born in Germany in 1982. He received the diploma degree in electrical engineering from the University of Paderborn, Germany in 2008. His current research interests focuses on wireless energy transmission and nearfield coupling.

OLED lighting using ultra-thin flexible glass

Mogck, Stefan
Department Manager
Fraunhofer FEP

Abstract
Ultra-thin flexible glass appears as a highly attractive substrate and encapsulation material for OLED lighting. Properties like high moisture barrier, high temperature resistance and high surface quality are the main reasons for that. Fraunhofer FEP is working on ultra-thin flexible glass using sheet-to-sheet and roll-to-roll processes as well, Ultra-thin glass with thickness of 50 µm and 100 µm is suitable to wind through the roll-to-roll OLED line at Fraunhofer FEP which consists of a vacuum coater for small molecule depositions, a roll-to-roll encapsulation under inert atmosphere and an optical inspection system for defect characterization. For the minimization of glass breakage the ultra-thin glass is laminated on a host PET film to increase the robustness during the roll-to-roll process. In general, this glass PET laminates supports the tool enhancement to find proper web tensions and critical bending radii for winding pure ultra-thin glass in the future. At present, a challenge is to minimize the residual water in films for OLED substrates on roll materials. Especially, a lot of efforts have been started to dry in Roll-to-Roll polymer based barrier films. Low water content in ultra-thin glass will be expected that an extensive roll-to-roll drying process can be avoided. Additionally, high process temperature above 200 °C can be applied on ultra-thin glass to remove residual water from the surface or coating of highly conductive ITO for homogenous large area OLED light illuminations. In this paper the OLED manufacturing on flexible ultra-thin glass will be outlined of efficient OLED devices with bottom emitting or transparent designs. A challenge of the roll-to-roll process and electrical connectivity on ultra-thin glass will be discussed in correlation with obtained OLED lifetime. Finally, the Roll-to-Roll processed OLED devices will be compared with sheet based OLED devices on ultra-thin glass regarding lifetime and power efficacy.

Biography
Dr. Stefan Mogck, studied physics at the University of Tübingen, Germany in 2000. In 2004 he received his PhD at the Institute of Applied Physics (Materials science and engineering) of the University of Groningen (NL). Afterwards, he joined to Advanced Micro Devices in Dresden as a defect engineer. In 2007 he was engaged at MicroEmissive Displays (MED) in Dresden as process engineer for the sputtering and the PLED spin coat process. Since 2008 he moved to Fraunhofer Institute for Photonic Microsystems. He is now leading the department "Roll-to-Roll Organic Technology".

Fraunhofer Group for Microelectronics Session in TechARENA 2 Technology - Application - Society: Bridging the Gap - Introduction

Pelka, Joachim
Managing Director
Fraunhofer Group for Microelectronics

Abstract
The Fraunhofer Group for Microelectronics is a leading international research and development service provider for microelectronics and smart systems integration. As part of Fraunhofer-Gesellschaft, Europe's largest organization for application-oriented research, we are able to combine the years of experience and the expertise of more than 3,000 scientists in our member institutes. Our expertise in the areas of microelectronics and smart systems integration allows us to bridge the gap between application-oriented fundamental research and product development along the entire added-value chain within our business units: - Ambient Assisted Living, Health and Well-being - electronic assistance for the user's individual needs - Energy Efficient Systems - taking us towards the "all-electric society" - Mobility and Urbanization - quality of life in urban areas - Smart Living - living and working in a knowledge-based society Since the beginning of 2014, our strategy has been based on cross-institute core competences that can provide the technologies needed to make the guiding product ideas in our application-oriented business units a reality: - Design for Smart Systems - Semiconductor based Technologies - Power Electronics and System Technologies for Energy Supply - Sensors and Sensor Systems - System Integration Technologies - Quality and Reliability - RF and Communication Technologies The bundling of the core competences of our current 16 institutes allows sector-specific, holistic, and tailor-made system developments based on both "More-Moore" and "More-than-Moore" technologies. The basis for our work is the market-oriented balance between short-term, development-oriented research-to-order for small and medium-sized enterprises and heavy industry on the one hand, and our own long-term strategic preliminary research.

Biography
Dr. Joachim Pelka is the Managing Director of the business office for the Fraunhofer Group for Microelectronics. He studied electrical engineering, with an emphasis on semiconductor technology, at Berlin's Technical University and was awarded a doctorate there for his work on semiconductor components. He has been with the Fraunhofer-Gesellschaft since 1983. Today, following many years in the organization, Dr. Pelka is the Managing Director of the Fraunhofer Group for Microelectronics. His previous position was as the Fraunhofer ISIT's department head responsible for the simulation of semiconductor patterning processes. He also spent two years in the JESSI coordination office (also located at the ISIT). As managing director he is responsible for strategic planning and for the coordination of work in the microelectronic institutes of the Fraunhofer-Gesellschaft. Under his directorship, the business office carries out studies on current areas of research that form the basis for the Group's strategic planning. In the past, this included for example the "MST fireside chats", a series of workshops conducted on behalf of the project sponsor, Mikrosystemtechnik VDI/VDE IT and a study concerning road mapping activities of microelectronics on behalf of the CATRENE Scientific Committee. In keeping with deepening European integration, Dr. Pelka today functions more and more as a contact person for other European research facilities such as CEA-Leti, CSEM, IMEC and VTT. He represents the Group, complementing the Chairman of the Group, in the Heterogeneous Technology Alliance HTA. Dr. Pelka is a member of the ENI2 Steering Committee and the organizational committee of the INC Conference Series. The International Nanotechnology Conference on Communications and Cooperation INC9 held in Berlin in 2012 was organized under his supervision. Currently, he has been focusing on a study named "smart cities" commissioned by the CATRENE Scientific Committee.

Gender aspects in innovation practices: status and opportunities

Schraudner, Martina
Head of Fraunhofer Center for Responsible Research and Innovation
Fraunhofer IAO

Abstract
Dynamic markets require quick solutions and creative ideas. Seeking to holistically tap innovation and market potential, both the perspectives of women and men must be accommodated. Our recent research results show: The underrepresentation of women in STEM subjects explains the small number of high-tech founders only partially. Women involved in ideation and creation processes often take a "place in the second row ".

Biography
Prof. Dr. Martina Schraudner is the Head of Fraunhofer Center for Responsible Research and Innovation. Her research focuses on methods, instruments and processes to make diversity accessible and manageable for organizations and companies. Prof. Dr. Martina Schraudner is a member of several national and international selection committees.

Integrated Voltage Converters in Energy Harvesting Applications

Spies, Peter
Groupmanager
Fraunhofer IIS

Abstract
Energy Harvesting uses ambient energy like light, thermal gradients or vibrations to generate electrical energy for powering electronic devices. In that way, power cords or batteries can become redundant and real self-powered systems are possible. Typical energy transducers to convert ambient energy into electrical energy are solar cells, thermoelectric generators, inductive generators or piezo-electric materials. Most promising devices to be powered with energy harvesting are wireless sensors and sensor networks, but also displays or actuators in various application fields like the home automation business sector and the area of condition monitoring. The power management composed by voltage converters is a key element in energy harvesting systems. Highly optimized semiconductor circuits adapt the voltage and current profile of energy harvesting transducer to meet the requirements of typical applications or storage elements. In the presentation, the generic architecture of an energy harvesting system will be introduced and typical performance values of state-of-the-art transducers will be given. Several integrated voltage converters and charge circuits will be explained and performance data presented. Finally, a couple of practical applications of energy harvesting systems are presented. In self-powered tracking systems, vibration transducers are employed to use the mechanical excitation from the vehicle to power a GPS-GSM-module. In a wireless window monitoring system, energy from light and thermal gradients powers sensors and a wireless transceiver. In a Bluetooth wristband, the heat of the human body is used to supply sensors and a Bluetooth module. An oval-wheel counter uses the energy of the fluids to power signal processing electronics and a GSM module.

Biography
Dr. Peter Spies studied Electrical Engineering at the University of Erlangen / Germany and graduated with a Dipl.-Ing. degree in 1997. In 2010, he finished his PhD thesis on the topic of power saving in mobile communication devices. Since 1998, he is with the Fraunhofer IIS, power efficient systems department. He was working on the field of multi-standard front-ends and system simulations for communication applications. Since 2001 he is group manager of the "Integrated Energy Supplies" group where he is doing research and design on the field of power and battery management, energy transmission and energy harvesting. Focus of his group is integrated circuit and system design as well as software development. Most important applications are wireless sensor networks or hybrid and electrical vehicles.

Pfeffer, Markus
Group Manager
Fraunhofer IISB

Biography
Dr. Markus Pfeffer- Group Manager Fraunhofer IISB Dr. Markus Pfeffer holds a diploma in Electrical Engineering and a PhD (Dr.-Ing.) with specialization in manufacturing optimization both from the University of Erlangen- Nuremberg. Since 2002 he is with Fraunhofer IISB in the department Semiconductor Manufacturing Equipment and Methods. He leads the group Manufacturing Control and is responsible for the analysis laboratory for micro and nano technology at the IISB. He has been engaged in the fields of equipment control, advanced process control, manufacturing optimization, analytical methods, equipment assessment and especially discrete event simulation. He was/is involved in several national and international cooperative R&D projects, e. g. FLYING WAFER, IMPROVE, EEMI450, EEM450PR, SEA-NET, SEAL and SEA4KET in different functions also as coordinator. He is member of the Steering Committee of the 450mm Equipment & Materials Initiative EEMI450 and since 2012 a member of the Factory Integration Group and Yield Enhancement Group of the ITRS.

SEEDs - intelligent use of energy in small and medium-sized companies

Oechsner, Richard
Head Section Energy Technology
Fraunhofer IISB

Abstract
The basic idea of the project SEEDs is to restructure and optimize local energy systems for small and medium-sized companies (industrial level) by utilizing and further developing existing approaches and techniques. The goal is the research, development and implementation of sustainable energy production, energy storage, energy supply and efficient use of energy at industrial local level. The specific areas covered in SEEDs are microgrids, energy storage, gas-to-power coupling, grid connection, load shift, sustainable creation and use of energy as well as energy efficiency. The whole chain of energy technology will therefore be investigated. Specific attention will be paid to an efficient interlinking of the different components of the local energy system by power electronics and interfaces. These interfaces are a core competence of Fraunhofer IISB. Also the Fraunhofer institutes IIS and ISC are participating in the project. IIS will cover communication-related topics and ISC material aspects for electrical battery development. The overall institute building of the Fraunhofer IISB serves as a research and demonstration plat-form. The requirements for different energies (heat, cold, and electricity) as well as the range, infrastructure and energy consumption of the IISB are comparable to those of small and medium-sized companies.

Biography
Richard Öchsner received the M.S. (Dipl.-Ing.) degree in Electrical Engineering and the Dr.-Ing. degree from the University of Erlangen. Since 1991 he is with Fraunhofer IISB and working in the department Semiconductor Manufacturing Equipment and Methods as deputy head of department and leads the group Manufacturing Control and Productivity. He was engaged in the fields of semiconductor equipment assessment, contamination control in equip-ment, equipment control, integrated metrology, advanced process control, manufacturing methods, optimization, productivity and energy efficiency. Since 2012 he is head of section energy technology and working on energy concepts covering creation, storage, distribution and efficient use of energy. Richard Öchsner was/is involved in several European and national co-operative R&D projects also as coordinator. He was active in SEMI standardization and a member of the Factory Integration TWG within ITRS (International Technology Roadmap for Semiconductors).

Energy Harvesting for Sensor-Near Electronics - Challenges and Solutions

Hentschel, Dieter
Head of Department
Fraunhofer IKTS

Abstract
Structural Health Monitoring (SHM) applications in many industrial fields have gained significant attention. One of the most important physical method to achieve SHM is the detection of (material- inherent or stimulated) acoustical lamb waves. To detect lamb waves in (mostly larger) technical structures, it is necessary to implement a sensor network inside the structure. These sensor networks are often "in the field", that means far away from any power supply. Furthermore, the usage of cabling is not desirable in many applications. Examples are the aircraft industry (each cable produces more weight) and rotor blades of wind energy plants (to avoid lightning flash damages). Completely in carbon fibre reinforced plastics (CFRP) embedded sensor nodes should also be wireless, because any additional cable could weak the stiffness of the structure. For this reason, there is a need for completely wireless, self-sufficient sensor nodes. Along the leading edge technology project »CoolSensornet« initiated and led by my Fraunhofer group and based within the leading edge technology cluster named »Cool Silicon« Fraunhofer IZFP and IKTS jointly develop energy autonomous and wireless sensor systems together with IMA GmbH Dresden, Technische Universität Dresden, ZMDi AG and RHe Microsystems GmbH. Those sensor systems are due to be used for monitoring large sized aircraft structures and wind power rotor blades long term. First results of the project revealed that with wireless acoustical lamb wave based sensors it is possible to detect damages after impact in CFRP materials.

Biography
Dr. Dieter Hentschel Dr. Dieter Hentschel was from 2004 until 2013 business unit leader aerospace in the Fraunhofer Institute for Nondestructive Testing (IZFP) in Dresden. He is now working on the fields Structural Health Monitoring and Quality Assurance in the Fraunhofer-Institute for Ceramic Technologies and Systems IKTS in Dresden. Dr. Hentschel is member of the CoolSilicon Cluster Management since its founding.

Fraunhofer Group for Microelectronics: The strategic core competence "Sensors and Sensor Systems"

Ambacher, Oliver
Executive Director
Fraunhofer Institute for Applied Solid State Physics IAF

Abstract
It's impossible to imagine life today without sensors to determine measured data. Sensors are often directly linked to increasingly sophisticated data processing systems as well as wireless data transmission. These types of sensor systems form the backbone of modern concepts such as home automation, medical engineering, and industrial process monitoring. The demands being placed on them, however, are becoming ever more varied. The normal development path - prototype construction, troubleshooting, and optimization - is often not sufficient to deal with this level of complexity. The member institutes of the Fraunhofer Group for Microelectronics bundle all the technologies needed for the development of reliable, robust, energy-efficient, yet cost-effective sensor systems in the "Sensors and Sensor Systems" core competence: - Micro- and nano-sensors, CMOS-compatible sensor processes - MEMS and NEMS technologies, add-on technologies, system integration (including 3D - Transmission systems, RF technologies - System and application design - Systems, signal processing, sensor data fusion This basis allows us to offer our customers tailor-made sensor solutions from a single provider - from design to the finished system, reliability monitoring, and accompanying services. The presentation will be focused on microelectronics sensory systems dedicated to increase the safety and security critical infrastructures and production lines.

Biography
Dipl.-phys. - 1989 (LMU-Munich); Dr. rer. nat. - 1993 (Technical University Munich); Habilitation - 2000 (Technical University Munich); Professor of Nanotechnology - 2002; Head of the Institute of Solid State Electronics - 2002, Head of the Center of Micro- and Nanotechnologies - 2004 (Technical University Ilmenau); Chair of Compound Microsystems - 2007 (University Freiburg); Head of the Fraunhofer Institute of Applied Solid State Physics - 2007 Oliver Ambacher received his Dipl.-Phys. and Dr. Degrees with honors from the Ludwig-Maximilians and Technical University Munich, in 1989 and 1993, respectively, where he was involved in the deposition and characterization of amorphous silicon for solar cells. In 1992 he received a German Science Foundation Graduate Research Fellowship. In 1993, he joined the Walter Schottky Institute of the TU-Munich to investigate the epitaxial growth of group-III nitrides based heterostructures. Since 1995 the research of his group is focused on fabrication of GaN based devices like UV detectors, surface acoustic wave devices or microwave amplifiers as well as on the understanding of polarization induced effects in group-III nitride heterostructures and quantum wells. 1998/99, he spent one year at Cornell University, Ithaca, NY, as an Alexander von Humboldt fellow, where he was involved in the optimization of polarization induced AlGaN/GaN HEMTs for high frequency and high power applications. He became a Professor of Nanotechnology and head of the Institute for Solid State Electronics located at the Technical University of Ilmenau in 2002. In 2004 he was elected as head of the new Center of Micro- and Nanotechnologies. Since 2007 he is the head of the Fraunhofer Institute for Applied Solid State Physics and Professor for Compound Microsystems in Freiburg, Germany.

Physical Failure Analysis at 3D Structure

Zschech, Ehrenfried
Director of Materials and Nanoanalysis Division
Fraunhofer Institute for Ceramic Technologies and Systems IKTS

Abstract
- TBA -

Biography
Ehrenfried Zschech is Director of Materials and Nanoanalysis Division at Fraunhofer Institute for Ceramic Technologies and Systems IKTS in Dresden, which he joined in 2009. He received his diploma degree in solid-state physics and his Dr. rer. nat. degree from Dresden University of Technology. After having spent four years as a project leader in the field of metal physics and reliability of microelectronics interconnects at Research Institute of Nonferrous Metals in Freiberg, he was appointed as a university teacher for ceramic materials at Freiberg University of Technology. In 1992, he joined the development department at Airbus in Bremen. There he managed the metal physics group and worked on laser-joining metallurgy of light metals. From 1997 to 2009, Ehrenfried Zschech managed the Materials Analysis Department and the Center for Complex Analysis at AMD in Dresden. In this position, he was responsible for the analytical support for process control and technology development, as well as physical failure analysis. His current research interests are in the areas nanomaterials and nanoanalysis, with the focus on thin film technology and nanotechnology. He has published three books and more than 170 papers in scientific journals in the areas of solid-state physics, materials science and reliability engineering. He holds honorary professorships for Nanomaterials at the Brandenburg University of Technology in Cottbus-Senftenberg and for Nanoanalysis at the Dresden University of Technology. Ehrenfried Zschech is acting as Past President of the Federation of European Materials Societies (FEMS).

A Cu based TSV technology for MEMS accelerometers

Schulz, Stefan E.
Deputy Director / Dept. Head
Fraunhofer Institute for Electronic Nano Systems

Abstract
3D integration represents a decisive technology for realizing miniaturized, heterogeneous smart systems. In contrast to microelectronic devices, specific constraints have to be considered for MEMS with fragile structures. Hereby, the wafer thickness is usually higher (~200-400 µm) due to the MEMS fragility and for reasons of avoiding thin wafer technologies. This requires through-silicon vias (TSVs) with large dimensions and high aspect ratios. In this presentation a Cu-TSV technology and its application to MEMS accelerometers based on high aspect ratio microstructures will be described. In the presented TSV technology approach the TSVs are fabricated after the device fabrication as so called Via Last technology. One distinctive feature hereby is an incomplete TSV Cu-filling, which avoids long processing and complex process control, while minimizing the thermomechanical stress between Cu and Si and related adverse effects in the device. However, the incomplete filling also includes various challenges regarding process integration. A method based on pattern plating using spin-on negative resist will be described where the TSVs are metalized at the same time as the redistribution layer. This eliminates the need for additional planarization and patterning steps. As demonstrator a 2-axis MEMS accelerometer based on the so called AIM (air gap insulated microstructures) technology has been built up with TSVs. Cross sectional analysis as well as functional tests will be shown in order to validate the feasibility of the presented Cu based TSV technology.

Biography
Stefan E. Schulz is head of the Department Back-end of Line and Deputy Director at the Fraunhofer Institute for Electronic Nano Systems (Fraunhofer ENAS), Chemnitz, Germany. His main research fields are on-chip interconnects, 3D integration, and Carbon Nanotube (CNT) based devices. S. E. Schulz received his doctoral degree in electrical engineering from Technische Universität Chemnitz in 1996. Before entering the newly founded Fraunhofer ENAS in 2008 as head of Dept. BEOL, he held several positions as researcher and research group leader at Technische Universität Chemnitz, Center for Microtechnologies and Fraunhofer IZM. S. E. Schulz was appointed as Honorary Professor for "Nanoelectronics Technologies" at the Technische Universität Chemnitz in 2008. In 2013 he became Spokesman of the Fraunhofer Cluster 3D Integration. S. E. Schulz authored and co-authored more than 150 publications in journals, books and conference proceedings, held 11 invited speeches at international congresses and symposia, and is inventor of 3 granted patents and 4 published patent applications.

High-efficient modeling for very fast and precision analyses

Hedayat, Christian
Head of Department
Fraunhofer Institute for Electronic Nano Systems ENAS

Abstract
Wireless and mobile applications are becoming more important since the last few years. These fields of operation are characterized by power efficient and highly integrated circuits. Therefore, mostly mixed-signal systems like DC-DC converters and phase-locked loops (PLL) are used. These systems exhibit a nonlinear pulse-width modulated switching behavior. Due to these properties it is challenging to analyze and to design such components utilizing general theories of control systems. Thus, simulation models at transistor-level (TL) or behavioral models are often used. The former are very accurate, whereas the latter allow an easier handling of parasitic effects. The main bottlenecks of these approaches are the high time and computer resource consumption which in turn restrict the designer to efficiently characterize the nonlinear and non-ideal system behavior and thus to achieve a robust system design. To get a quick overview of the system properties, linear models can be used. Because of the early linearization, nonlinear and non-ideal effects are not considered. However, it is crucial to take them into account when a reliable and robust system design is desired. Additionally, this modelling approach is only valid near the operation point and thus the pull-in region cannot be represented. Based on the example of a PLL this talk shows an event-triggered approach which accurately represents the mixed-signal system behavior. This event-driven model combines the accuracy of a TL simulation and the time and computer resource efficiency of the linear model. It evaluates only the triggering edges of the reference and feedback signals and thus highly reduces the simulation time and the amount of data. Speed-up factors up to 100k are achieved, whereas the rel. RMS errors are in the range of a few tenth of a per cent. This efficiency enables an exhaustive analysis and characterization of parasitic effects which enriches the mixed-signal system design.

Biography
Christian Hedayat studied Physics at the University of Nice Sophia-Antipolis, France. In 1993 he obtained his Masters of Electrical Engineering, with focus on Telecommunication and Antenna Design. In 1998 he obtained his Ph.D. degree in the area of modeling of mixed-signal PLL systems in collaboration with Texas Instruments France. He worked then with Atmel France as an analog IC designer before joining in 2004 the Fraunhofer Institute for Reliability and Micro-integration (IZM) in order to work on fast simulation models of mixed-signal devices for EMR purposes. Dr. Hedayat is leading since July 2008 the Dpt. Of Advanced System Engineering within the Fraunhofer Institute for Electronic Nano-Systems, managing several European industrial projects related to automotive and communication applications.

GMR based 2D magnetic field sensors

Matthes, Patrick
Head of magnetic sensor technology group
Fraunhofer Institute for Electronic Nano Systems ENAS

Abstract
Magnetic field sensors have been utilized for various applications such as, for instance, switches, positioning and velocity sensors, ampere meters or can even be used as a weighing device. Most commercially available sensors are based on the anisotropic magnetoresistance (AMR) effect or the Hall effect, both being robust and allowing, e.g., angular as well as very high field sensitivities. Even higher field sensitivities are expected for giant magnetoresistance (GMR) or tunneling magnetoresistance (TMR) effect based sensors, which, furthermore, can be less power consumable and scaled to smaller dimension. We have designed and studied 2D GMR spin valve sensors (IrMn/CoFe/Cu/CoFe/NiFe) in monolithic integration for high sensitivity applications. For a maximum signal-to-noise ratio we realized a focused double Wheatstone bridge layout, featuring an antiparallel exchange bias pinning for neighboring meanders and an orthogonal pinning for different bridges. This precise alignment is achieved with microscopic precision by local ns-laser heating and subsequent in-field cooling. Striving for maximum signal sensitivity and minimum hysteresis, we studied the impact of single meander geometries (e.g. stripe width, stripe length) and different alignments of the locally defined reference magnetization with respect to the meander stripes on the electronic transport properties. Using a set of optimum parameters, we demonstrate that our sensor may readily be employed to measure small magnetic fields, such as the ambient (geomagnetic) field, in terms of a 2D vector with high spatial (~200 µm) and temporal (~1 ms) resolution.

Biography
Patrick Matthes started to study physics at the Chemnitz University of Technology in 2005. In his diploma thesis he investigated the magnetic properties of FePt thin films deposited on previously optimized MgO and Cr seed layers. After his diploma in 2010 he continued as a PhD student in the group of Prof. Albrecht and since July 2015 he is head of the magnetic sensor technology group at Fraunhofer ENAS. His research activities concentrate on coupling phenomena and magnetic as well as magneto-transport properties of magnetic thin films and nanopatterns.

Mechatronic Powerstage design of the COSIVU Drivetrain with parallelized SiC BJT Half-Bridge Modules and Drivers

Hilpert, Florian
Scientific Engineer
Fraunhofer Institute for Integrated Systems and Device Technology IISB

Abstract
The project 'COSIVU' aims at new system architectures for electric drive-trains by developing a smart, compact, modular and durable in-wheel drive unit with full SiC power electronics and a novel control, sensing and health monitoring system. The main goals for the mechatronic integration concept of the COSIVU Inverter are to provide easy servicing of the complete Powerstage and a good manufacturability and flexibility due to the modular approach. This helps increasing the availability of hybrid/electric vehicles, which are even more demanding for commercial vehicles than for other types of vehicles. To show the flexibility of the system, the new architecture will also be adapted to other vehicle platforms such as passenger cars. Main component of the modular integration approach is a newly designed Inverter Building Block (IBB). The IBB is a mechanically self-supporting structure with all necessary components to drive one Half Bridge of the Inverter. It consists of a Cooling Plate, three parallel Half-Bridge 1200V SiC BJT Power Modules each with its own Base Driver Module, an AC-Current-Sensor and a DC-link-Capacitor. This approach offers a low parasitic inductance design which supports a reduction of switching losses and allows higher switching frequencies of the SiC devices. The Base drivers can be extended with a thermal impedance board for health diagnostics on the power modules. The current driven silicon carbide bipolar transistors exhibit the lowest on-state losses in comparison to IGBTs or SiC-MOSFETs. Extra driving losses due to a necessary dc-on-state base current are around 3% of the rated current. The drive unit features fast and parallel signaling, desaturation protection, high power flow-rate with compact design and an attachable PCB for monitoring the power semiconductors. The COSIVU project brings SiC BJTs into real application and includes innovative diagnostic features that can be used and extended to any kind of electrical drive application.

Biography
2006-2011 University of Erlangen-Nuremberg, studies of Mechatronic with focus on Power electronics and Electric Drivetrains 2012 1st price winner "Drive-E Studienpreis 2012" 2012-today Scientific Engineer at Fraunhofer Institute for Integrated Systems and Device Technology IISB, Group Drives and Mechatronics Presentation-Related: COSIVU Workpackage Leader System Integration

Fraunhofer Group for Microelectronics: The strategic core competence "Power Electronics and System Technologies for Energy Supply"

Frey, Lothar
Executive Director
Fraunhofer Institute for Integrated Systems and Device Technology IISB

Abstract
Demand-actuated supply of electrical energy is a globally important issue. In the smart power grid of the future, a large number of energy sources, storage options, and grid levels will be linked together in complex infrastructures. The energy will be used in a very wide range of areas of application and power classes: Largely regenerative, decentralized energy production, high-efficiency sub-grids, and the coupling of electrical energy with other types of energy (chemical, mechanical, thermal) are becoming more and more important. At the same time, electrical and secondary storage options are being more heavily integrated into the grid and load shifting effects are exploited. Large overall systems with a high degree of independence (industry, large building complexes, towns, etc.) need new types of energy concepts. The Fraunhofer Group for Microelectronics develops high-efficiency systems and components to provide the technology needed for sustainably efficient yet cost-effective energy supply. The strategic core competence "Power Electronics and System Technologies for Energy Supply" bundles the specialist knowledge of the member institutes in the areas of power electronics and information technology for the smart grid as well as energy harvesting, energy storage, and energy management. In addition to minimizing energy losses and lowering costs, the focus is placed particularly on issues of reliability and robustness as well as increased grid quality and stability. Application-specific optimization of installation space, weight, and material consumption is another aim of the research and development.

Biography
Lothar Frey received the Diploma degree of physics and the Dr. rer. nat. degree in 1983 and 1987, respectively, from the University of Würzburg, Germany. In 1987, he joined Rice University, Houston, for a post-doc position working on new laser sources. In 1989, he returned to Germany to the new Fraunhofer AIS, Erlangen, to build up a group on semiconductor characterization. In 1993, he joined the University of Erlangen-Nuremberg being responsible for the clean room facility of the university and also heading the department of silicon technology of Fraunhofer IIS-B in Erlangen. In 2004 he completed his habilitation (venia legendi) at the University of Erlangen-Nuremberg. During this period, research focused on micro technology for electron devices with special emphasis on ion-beam-based technologies and the introduction of new materials to silicon technology. In 2005, these activities brought him in to Infineon Technology (Qimonda) Dresden. Two years later, he became full professor for applied physics at the Technical University of Freiberg. Since 2008, Lothar Frey is holder of the Chair of Electron Devices (LEB) at the University of Erlangen-Nuremberg and director of the Fraunhofer Institute of Integrated Systems and Device Technology IISB, Erlangen. Current activities cover semiconductor technology and power electronic systems for application in energy supply and mobility.

Bearing with integrated Energy and Data Transmission

Heckel, Thomas
Research Fellow
Fraunhofer Institute for Integrated Systems and Device Technology IISB

Abstract
The ability to transfer power in fast rotating systems is required for a wide range of applications, such as wind power systems with electronics integrated in the rotor blades or highly-automated Industry 4.0 production platforms. In this talk, a technology for the contactless transfer of power and data in fast rotating objects using the example of a standardized ball bearing is presented. This alternative to failure-prone cable-based solutions like slip rings offers further advantages such as improved safety for manufacturing systems, the chemical industry, and medical technologies. The bidirectional data transfer offers both system safety functions as well as an interface for sensors and machine controls. This contribution is supported by the Bavarian Ministry of Economic Affairs and Media, Energy and Technology as a part of the Bavarian project "Leistungszentrum Elektroniksysteme (LZE)".

Biography
Thomas Heckel studied Mechatronics focussing on power electronics, control theory, and drive technologies. He received the Diploma degree from the Friedrich-Alexander-University Erlangen-Nuremberg, Germany, in 2011. Since then, he has been working at Fraunhofer IISB and the Chair of Electron Devices, Erlangen, on his Ph.D. thesis. His research interests include the characterization and application of Wide-bandgap semiconductors in high efficiency power electronics as well as inductive power transfer systems. Furthermore, he is currently project manager of one of the pilot projects of the "Leistungszentrum Elektroniksysteme" in Erlangen.

High Temperature 0.35µm SOI CMOS Process (250°C and beyond)

Dreiner, Stefan
Group Manager/Deputy Head of Department
Fraunhofer Institute for Microelectronic Circuits and Systems IMS

Abstract
The application temperature of microelectronic circuits has been steadily increasing over the years (125°C-> 150°C-> 175°C) and will be even higher in the next future. This is due to new challenges regarding energy efficiency, reduction of emissions and reduction of system size, for example in the automotive and aviation markets. The exploration of natural energy resources (gas, oil, geothermal) is a high tech operation with sophisticated sensor and data acquisition systems that are among the core technologies to enable deep hole drilling (T>200°C). The recent availability of power devices based on GaN and SiC in combination with a high temperature capable CMOS (for control electronics) offer the potential for making significant progress since driver and power device can operate at temperatures beyond 200°C, increasing overall system efficiency and drastically reducing cooling effort and package size. Published work on high temperature CMOS circuits typically refers to technologies with a minimum feature size of 0.8 to 1.0 micron even though for complex digital circuits this results in large die size. Technologies with smaller feature size are available but typically not suitable for reliable high temperature (>175°C) operation due to high leakage, decreasing threshold voltages over temperature or reliability issues with the standard aluminum metallization. Fraunhofer IMS has developed a high temperature 0.35 micron thin film SOI CMOS technology. The mixed signal technology provides numerous devices, e.g. specific transistors for analog and digital domain, diodes, resistors and voltage independent capacitors. Also non-volatile memory cells (EEPROM) are available. In addition the technology is equipped with a tungsten metallization for highly reliable operation even at high temperatures. An overview on the new technology including characterization results of devices and test circuits is given in the presentation.

Biography
Dr. Stefan Dreiner studied Physics at the University of Essen/Germany and graduated with Diploma degree in 1996. He received the Ph.D. degree in physics from the University of Münster/Germany in 2002. Afterward, he was a Postdoctoral Fellow with the Technical University of Dortmund/Germany. Since 2005, he is with Fraunhofer Institute for Microelectronic Circuits and Systems, Duisburg, where he is currently Manager of the Semiconductor Processes and Devices Group. Focus of his group is the CMOS technology and devices development for special purposes like high temperature (high voltage) and the integration of optical and other sensors in CMOS.

Metering Encapsulation and Barriers: A Key Challenge for Market and Technology Development

Fahlteich, John
Senior Scientist / Project Manager
Fraunhofer Institute for Organic Electronics, Electron Beam and Plasma Technology

Abstract
Encapsulation and ultra-high permeation barrier films are one critical component for the market entry of flexible organic and printed electronic devices. First high performing barrier film products entered the marked within the last years. However, the difficulties in comparing the performance of different barrier films and translating device's requirements into measurable quantities for permeation barriers have been identified as key challenges for a broader market penetration of these products in large area organic electronic encapsulation. The first step is to compare the barrier performance (mostly represented by the water vapor transmission rate) of different barrier films. While several highly sensitive WVTR-measurement techniques are described in the literature, their accuracy and comparability has only been tested recently in a systematic way. With a growing body of literature referring to different coating and barrier technologies, it is challenging to gather a coherent picture both of the performance of the materials studied and the permeation measurement methods used. We report on independent WVTR measurements of the same batch of a high performance barrier film under two sets of conditions in several laboratories with different state-of the-art methods. These methods also include several calcium test set-ups. The results showed that, while some differences are present, there is a remarkable level of agreement between the measurement methods. In the second step, we report on key properties of permeation barrier and encapsulation systems in relationship to the requirements of the organic electronic devices as well as their application cases and application conditions discussing ideas for translating device requirements into measurable quantities of the encapsulation product.

Biography
John Fahlteich was born in 1981 in Lutherstadt Wittenberg, Germany. He graduated from the University of Leipzig with a diploma in physics in 2005. After that he worked as PhD student and scientist at the Fraunhofer Institute for Electron Beam and Plasma Technology, Dresden. In 2010, John earned a PhD from the Technical University of Chemnitz with a thesis about a detailed characterization of vacuum deposited permeation barrier layers. In total, he has now over 10 years of experience in the field of thin film technology, vacuum deposition techniques, permeation barriers and encapsulation of flexible electronics. Since 2010, John has been working as project manager and expert for permeation barriers at Fraunhofer Institute for Organic Electronics, Electron Beam and Plasma Technology FEP. Up to today he published over 35 papers, conference contributions and patents as well as one book chapter in the field. Since 2012, he represents the Fraunhofer FEP as leading member in several organizations dealing with flexible electronics encapsulation such as the Organic-Electronics Association (OE-A) and the Flexible Electronics Encapsulation Technologies (FLEET) Cluster in Dresden, Germany.

Integration of polymer organic photodiodes on complementary metal-oxide-semiconductor (CMOS) backplanes for bio and medical applications

Jahnel, Matthias
Researcher
Fraunhofer Institute for Organic Electronics, Electron Beam and Plasma technology FEP

Abstract
Solution processed organic photodiodes (OPD) are promising candidates to offer a high potential in optical sensor applications [1][2]. They can be used as photo detectors for industrial process monitoring, health care, as well as for sensors in bio and life science. Organic semiconductors offer general advantages such as simple fabrication and the integration on flexible substrates which enables ultra-thin and low weight devices, especially for large area OPDs. On the other hand, the combination of organic materials deposited on top of CMOS circuit enable a fill factor of up to 100% while minimizing the process complexity and cost [3]. We present different polymer bulk heterojunction OPDs on CMOS compatible electrode materials for sensor and lab-on-a-chip applications. These devices are either based on the polymer-fullerene blends P3HT:PC60BM and P3HT:ICBA to detect light in the visible or on the blends PTB7:PC70BM and PCPDTBT:PC70BM to detect light in the visible and the near infrared range. Every device is built in top absorption geometry where the light passes through a semi-transparent cathode towards the absorption layer. The fraction of absorbed photons in the semi-transparent Ca/Ag cathode, in the TiN/Al anode as well as in the absorption layer P3HT:PC60BM is calculated and compared to experimental data. In conclusion, the spectral sensitivity of the devices mainly depends on the absorption blend layer itself. It is shown that OPD on CMOS enable a fast method to combine various absorber materials with a CMOS backplane and their optimization towards optical requirements for customer specific applications. [1] M. Burkhard, W. Liu, C. G. Shuttle, et. al., Appl. Phys. Lett. 101, (2012) 033302 [2] F. Arca, E. Kohlstädt, S. F. Tedde, et. al., IEEE (2013) 60, 5 (2013), 1633-1667 [3] D. Baierl, M. Schmidt, G. Scarpa, et. al., IEEE, Ph.D. Research in Microelectronics and Electronics (PRIME), 7th Conference on, (2011) 89-92

Biography
Matthias Jahnel is a Ph.D. candidate in physics in the department of Microdisplays and Sensorics at Fraunhofer FEP combined with TU-Dresden, Germany. He received his Dipl. Ing. (FH) in electrical engineering in 2008 at FH Lausitz (Germany) and worked at the Fraunhofer IPMS, division (COMEDD) from 2008 to 2012 in field of organic semiconductors. During this time he received the M.Sc. in physics at BTU-Cottbus in 2012 and worked as scientific research assistant at Fraunhofer COMEDD from 2012 to 2013. He worked as Ph.D. candidate associate with Prof. Chan Im from 2013 to 2014 in the department KFnSC at Konkuk University (Republic of Korea). Jahnel has expertise in metal semiconductors and organic and printed electronics, especially OPD, OPVs, and OLEDs. He is currently interested in printed electronics, roll-to-roll processes and a combination of organic with metal semiconductors for organic optoelectronics and sensorics.

Fraunhofer Group for Microelectronics: The strategic core competence "Semiconductor-based technologies"

Lakner, Hubert
Executive Director
Fraunhofer Institute for Photonic Microsystems IPMS

Abstract
There is scarcely a technology sector where global competition is as challenging as in electronic systems. Invisible to the naked eye as they usually are, hidden under the surface of the product, electronic systems with a high degree of complexity must be designed, manufactured, and brought to market in an extremely short period of time and they must work absolutely reliably and energy efficiently. Basic technological research, customer-specific process development, and reliable production are the key to the development of innovative system solutions. In order to be able to offer a stable process platform as the basis for innovative continued development, the employees of the Fraunhofer Group for Microelectronics work on a shared technology platform. This cooperation takes place under the auspices of the Fraunhofer Institute for Photonic Microsystems IPMS. The strategic core competence "Semiconductor-based technologies" bundles the specialist knowledge of the member institutes in this technology platform - particularly within the area of More-than-Moore technologies, as they are known. The basics are the technologies available at the institutes, such as: - Si process technology for wafer diameters of 150 and 200 mm - Individual processes on 300 mm wafer - Special aspects of 450 mm technology - MEMS specific add-on technologies - Development of SiC materials and technology for power electronics - GaN process technology for power and ultra-high frequency applications

Biography
Hubert Lakner (born in 1958) received his diploma-degree in physics at the Eberhard-Karls-Universität in Tübingen in 1986. After one year in the industry he joined the Gerhard-Mercator-University in Duisburg where he worked in the field of nanocharacterization of mesoscopic semiconductor structures. He received his PhD (Dr.-Ing.) in Electrical Engineering in 1993. From 1994 until September 1998 he was appointed Lead Engineer (»Oberingenieur«) at Gerhard-Mercator-University. His work was focussed on high frequency and high speed circuits based on compound semiconductor heterostructures. From October 1998 until December 2001 he was head of the Department of Micromechanical Sensors and Actuators (a group of 25 employees) at the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS, now IPMS) in Dresden. There, his research fields were Spatial Light Modulators (SLM) like micromirror arrays and scanning micromirrors. From January to December 2002 he was Acting Director of the Fraunhofer Institute for Microelectronic Circuits and Systems IMS in Dresden. Since January 2003 he has been the director of the new Fraunhofer Institute for Photonic Microsystems IPMS which emerged from the former IMS Dresden. At the same time, Dr. Lakner was appointed Professor for »Optoelectronic Devices and Systems« in the Department of Electrical Engineering and Information Technology at the Technical University Dresden. Prof. Dr. Lakner is cochairing the annual international SPIE conference on »Micro Opto Electro Mechanical Systems (MOEMS) and Miniaturized Systems« which is part of Micromaching and Microfabrication at Photonics West. Since January 1st 2011 he has been Chair of the Fraunhofer Group for Microelectronics.

Ultra-thin capacitors for enabling miniaturized IoT applications

Seidel, Konrad
High-key Devices
Fraunhofer Institute for Photonic Microsystems IPMS

Abstract
The growing demand on small system solutions for internet of things applications is driving the compression of many functions into small package outline. This also requires sophisticated solutions for the integration of passive components in order to avoid external circuitry. In many cases it is required to suppress cross-coupling between different power planes. That can be achieved by placing decoupling capacitors as close as possible to the circuits. The demonstrator that was developed in joint collaboration between Fraunhofer IPMS-CNT and Fraunhofer IZM-ASSID presents a very compact and thin capacitor for direct integration into chip-package. The capacitor concept can be easily adjusted regarding design and electrical properties to the requirements of customers. A wide range of capacitance values from pF to µF in a small footprint is achieved by means of high-k material integration and special patterning processes, thus supporting a broad application range from RF-filtering to decoupling and energy buffering. Based on characterization results of voltage and temperature characteristics it is shown that this concept offers good electrical properties and linearity compared to conventional ceramic capacitors, like MLCC. Besides the integration in chip package (System in Package) this capacitor solution is suitable for embedding in high-end PCB as well. Furthermore this modular capacitor fabrication concept can be applied within chip-interconnect metallization levels or on interposers.

Biography
Konrad Seidel received the Diploma degree in electrical engineering from the Dresden University of Technology, Germany, in 2003. From 2004 to 2008, he was with the Reliability and Qualification team of Flash Product Engineering, Infineon Technologies AG, Dresden, Germany, later Qimonda. Since 2008, has been working as research associate with Fraunhofer Center Nanoelectronic Technologies, Dresden, which is now a business unit of Fraunhofer Institute for Photonic Microsystems, Fraunhofer IPMS. His research focus areas are electrical characterization and reliability of integrated circuits as well as the integration and design of integrated high density capacitors.

Advanced Sensor Technologies

Amelung, Jörg
MEMS Business Manager
Fraunhofer Institute for Photonic Microsystems IPMS

Abstract
Mobile applications are the main driver for the next generation of sensor technologies. The Internet-of-Things will additionally generate a huge demand for new sensor devices. Beside the high production volume in this market segment the sensors have to fulfill additional aspects. Extreme miniaturization, low power consumption and new functionalities are only three important aspects. Micro-Electromechanical-Systems (MEMS) were the base for new sensor developments in the last decades. Based on the huge demand in the mobile application field there is strong trend to higher integrated systems. Inside the talk an overview about some Fraunhofer IPMS developments in this field and future plans will be given. Miniaturized MEMS based spectrometers allow new possibilities in mobile analytics. Applications can be found in the fields of food processing, biotechnology, industrial automation and recycling. A main application scenario is the mobile quality inspection of food for improved customer satisfaction, higher feedback for selection, better wellbeing and health. The miniaturized grating spectrometer developed at Fraunhofer IPMS based on a MEMS scanning device exhibits a volume of only 2.1 cm³ what is about 30% less than an ordinary sugar cube. Due to the small physical dimensions and a power consumption of only a few milliwatts, it is perfectly suited for the integration in mobile devices. Ultrasonic transducers as second example are present in everyday life in the form of level sensors, speed sensors, medical imaging systems and distance sensors. Capacitive Micromachined Ultrasonic Transducers (CMUTs) are MEMS based structures that can be used to generate and sense acoustic signals in the ultrasonic. The CMUT technology developed in the Fraunhofer IPMS allows the reliable fabrication of such devices which could be integrated on top of a CMOS process to generate highly functional systems.

Biography
Jörg Amelung received his diploma in physics from the University of Duisburg, Germany, in 1993. In the same year, he joined the Fraunhofer Society in the field microsystem sensor technology. Since 1999 he was responsible for the OLED activities and the COMEDD (Center for Organic Materials and Electronic Devices Dresden) inside the Fraunhofer Institute for Photonic Microsystems IPMS in Dresden, Germany. In 2009 he founded LEDON OLED Lighting, a joint venture of Zumtobel and the Fraunhofer Society, and was the General Manager of the company. Since end of 2014 he is MEMS business manager inside the Fraunhofer Institute for Photonic Microsystems, Dresden.

Fraunhofer Group for Microelectronics: The strategic core competence "System Integration Technologies"

Lang, Klaus-Dieter
Executive Director
Fraunhofer Institute for Reliability and Microintegration IZM

Abstract
The wide-ranging demands placed on the packaging of electronic systems can be summarized in three main trends: - Customer-specific solutions in increasingly large batch sizes - Greater functionality - Fusing product and electronics In order to maintain existing strengths and to take advantage of new opportunities, close internal cooperation and a merging of technological possibilities are required. - 3D system integration of digital and analog components on the wafer (use of Si interposers), package (SiP, PoP), and panel (SoF, embedding) levels - Comprehensive range of technology for system-in-package on the following levels: wafer, package, panel (incl. flex) - Integration of MEMS components, sensor-actuator components and electronics - Integration of photonic device and electronics - Compact power electronics - System integration in atypical materials for electronics (textiles, stretchable substrates) - Draft analysis of software-based embedded systems - Networking of embedded systems - Tool prototypes for integration of embedded systems with multicore processors. The strategic aim of Fraunhofer Group for Microelectronics is to establish a cross-institute technology platform that will create a critical mass and will focus on Germany's industrial strengths to ensure that a significant part of the value creation can be returned to Germany. The platform concentrates on the following aims: - Comprehensive range of technology for system-in-package on the following levels: wafer, package, panel with system solutions from a single provider - 3D system integration of digital and analog components with TSV in active wafers - Integration of MEMS components and electronics including package with derogations - Compact power electronics with integrated driver electronics - Integration of photonic device and electronics - Online networking of embedded systems with cyber physical systems - Tool chains for comprehensive integration of embedded multicore systems

Biography
Prof. Lang studied Electrical Engineering from 1976 to 1981 at Humboldt University in Berlin. He received his M.S. Equivalent Diploma (Metallization Layers on GaAs) in 1981. During his employment at Humboldt University from 1981 to 1991 he worked in the research fields of microelectronic assembly, packaging and quality assurance. In 1985 and 1989 he got his two Doctor Degrees (Wire Bonding of Multilayers and Quality Assurance in Assembly Processes). In 1991 he joined the company SLV Hannover to build up a department for microelectronic and optic components manufacturing. In 1993 he became Section Manager for Chip Interconnections at Fraunhofer IZM (Institute for Reliability and Microintegration Berlin). From 1995 to 2000 he was the Director's personal assistant at Fraunhofer IZM, also responsible for Marketing and Public Relations. From 2001 to 2005 he coordinated the Branch Lab "Microsystem Engineering" in Berlin-Adlershof and from 2003 to 2005 he headed the Department "Photonic and Power System Assembly". From 2006 to 2010 he was Deputy Director of Fraunhofer IZM. Since 2011 he is Director of the institute and responsible for the chair "Nano Interconnect Technologies" at Technical University Berlin. Prof. Lang is a member of numerous scientific boards and conference committees. Examples are the SEMI Award Committee, the Scientific Advisory Board of EURIPIDES, the Executive Board of VDE-GMM and the scientific chair of the Conference "Technologies of Printed Circuit Boards" and "SMT/HYBRID/PACKAGING". He is a member of DVS, IEEE, IMAPS and he plays an active role in the international packaging community (e.g. German Chapter Chair IEEE-CPMT) as well as in the field of conference organization (e.g. Committee member SSI). Prof. Lang has authored and co-authored 3 books and more than 130 publications in the field of wire bonding, microelectronic packaging, microsystems technologies, chip on board and others.

Integrated Micro Camera Devices

Töpper, Michael
Business Unit Developer
Fraunhofer Institute for Reliability and Microintegration IZM

Abstract
This live presentation will focus on the packaging and system integration aspect of image sensors. Two different approaches will be presented and discussed in detail: One approach is a wafer level packaging concept using TSV (Through Silicon Vias) technology and the other is an image sensor on a small PCB with embedded image processor. Both technologies are a versatile step for new and advanced systems. The enabling key technology for wafer level packaging of camera systems based on top-side illuminated imagers are TSV because they allow a redistribution on the backside of the wafer wherefore the active side remains unaffected and can be completely used for the optic assembly. The wafer level camera having a size of about 1mm x 1mm will be presented in a live-demo. Another packaging process was made possible by an embedding technology. At a size of only 16x16x12 cubic millimeters, including, the microcamera module is an extremely small system. A total of 72 passive and 13 active components (such as oscillators, DC-to-DC converters, memory chip and image processor) have been embedded inside the module and the image sensor is mounted on top. The main system advantage is the fact that the image material is directly inside the camera, since it is equipped with an integrated processor for image processing. In addition it is fully encapsulated. After the image sensor has recorded the image, the integrated processor evaluates the frame. The video itself no longer has to be sorted and analyzed by an interposing system. Instead, only the relevant signals are transmitted. This camera will be also demonstrated. An outlook on a crowd-funding project will be given leading to the next step of integration. Based on an universal and flexible programmable image sensor SoC developed by Fraunhofer IIS/EAS a new "SmartHighProCAM" will be developed in cooperation with Fraunhofer IZM.

Biography
Michael Töpper has a M.S. degree in Chemistry and a PhD in Material Science. Since 1994 he is with the Packaging Research Team at TU Berlin and Fraunhofer IZM. In 1997 he became head of a research group. In 2006 he was also a Research Associate Professor of Electrical and Computer Engineering at the University of Utah, Salt Lake City. The focus of his work was Wafer Level Packaging applications with a focus on materials. Since 2015 he is part of the business development team at Fraunhofer IZM. Michael Töpper is Senior Member of IEEE-CPMT and has received the European Semi-Award in 2007 for WLP. He has published several book chapters and is author and co-author of over 200 publications.

3D Wafer Level System Integration

Wolf, M. Jürgen
Head of Department
Fraunhofer Institute for Reliability and Microintegration IZM

Abstract
3D integration is considered to be the key technology in microelectronic packaging to meet the requirements of future electronic systems especially with respect to the integration of even more functions, miniaturization, performance, energy efficiency. According to these increasing application driven demands System in Packages (SiP) using 3D integration are key elements for advanced microelectronic packaging. The heterogeneous integration of different devices by using 3D architectures allows the realization of applications especially optimized for SiP in a high efficient and cost effective way. Key elements for 3D wafer level SiPs are the formation of Through Silicon Vias (TSVs) and their process integration into active devices as well as silicon interposer as a key enabler for 3D Systems which are very attractive to deal with system performance improvement and to achieve cost effective packaging solutions. To meet the complexity of this technological approach, five Fraunhofer Institutes cluster their competencies in a network to cover a broad spectrum of topics related to 3D integration. The presentation will show the complex correlation of the different aspects of 3D integration covering the fields of technology, design and reliability.

Biography
M. Juergen Wolf received a M.S. degree in Electrical Engineering. In 1994, M. Juergen joined Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin and has worked e.g. as group & project manager in the field of wafer level packaging and system in package (SiP). Since 2011 he is head of department Wafer Level System Integration, responsible for the coordination and management of ASSID - "All Silicon System Integration Dresden-ASSID" with its 300 mm Wafer Level Integration. He manages as well as participates in a number of research projects on European and international level. M. Juergen Wolf is a European representative in the technical working group Assembly & Packaging of ITRS, JEC, JIC and a board member of EURIPIDES as well as member of IEEE and SMTA. He is also chair of Fraunhofer Cluster 3D Integration. He has authored and co-authored numerous scientific papers and reports in the field of microelectronic packaging and holds a number of patents.

Energy-independent asset tracking system for logistic applications

Milosiu, Heinrich
Senior Engineer RF- and Microwave IC-Design
Fraunhofer Instiute for Integrated Circuits IIS

Abstract
Energy-independent extremely efficient sensor nodes are one of the key technologies for the "Green Internet of Things" and "Smart Objects". Thereby, a sub-10-µA UHF WakeUp receiver plays a central role. Pursueing a high-performance logistics solution, this project involves the implementation of an asset tracking system, including the development of the electronics for the gateways and location beacons, as well as a miniaturized wireless tag integrated into the tracked asset. An energy-saving wireless solution is especially important for this application. The tag electronics consist of a three-band wake-up receiver with a current consumption below 10 µA, plus an efficient UHF two-band transmitter. The tag will be completely powered with energy harvesting technology for permanent autonomous operation. The energy-saving electronics solutions developed in this project will be suitable for a wide range of applications such as logistics, building automation, intelligent lighting, electronic labels, remote maintenance and control and wireless sensor networks.

Biography
Heinrich Milosiu was born in Regensburg, Germany, in 1976. He received the Masters degree in electrical engineering from the Friedrich-Alexander-University of Erlangen-Nürnberg, Germany, in 2002, and the doctoral degree (Dr.-Ing.) in 2012. He has been with Fraunhofer Institute for Integrated Circuits (IIS) in Erlangen since 2002. His research interests are RF CMOS synthesizer design and UHF receiver design in the sub-10 microwatts area. Since 2008, Dr. Milosiu has been project manager for UHF Wake-Up Receiver Design. Dr. Milosiu has been lecturer at the Friedrich-Alexander-University of Erlangen-Nürnberg since 2014.

Technical Visions of Industry 4.0

Seidelmann, Joachim
Head of Competence Center "DigITools"
Fraunhofer IPA

Abstract
With the introduction of IoT (Internet of Things) technologies and CPS (Cyber-Physical Systems) to the manufacturing domain, the integration of real and virtual worlds along the whole value chain will reach the next level. In order to seamlessly support and integrate innovative business processes on the shopfloor, as well as to enable new, possibly disruptive business models, highly agile manufacturing infrastructures have to be developed and implemented. This will affect all involved stakeholders such as equipment manufacturers, software vendors, and manufacturers. Several generic use cases are already implemented in the context of Industrie 4.0, but it has to be discussed how the semiconductor industry can benefit from the Industrie 4.0 initiative, and how it can maintain its role as innovation driver in the area of manufacturing technologies.

Biography
Joachim Seidelmann obtained his diploma degree in mechanical engineering at the University of Stuttgart in 1996. Subsequently he worked as research assistant in the area of IT-Systems for High-Tech manufacturing industry at the Fraunhofer IPA. Since 2000 he was in charge of the research team "Logistics and Production-IT for the semiconductor industry". In 2012 he started additionally building up the Competence Center "Digital Tools in production" with a strong focus on Industry 4.0 concepts and solutions. He is co-author of the "Recommendations for implementing the strategic initiative INDUSTRY 4.0 - Final report of the Industry 4.0 Working Group" and responsible for several large Industry 4.0- projects.

Ferroelectric Hafnium Oxide: Material Innovation for Ferroelectric Memories

Müller, Johannes
Group Manager NVM
Fraunhofer IPMS

Abstract
The first research and development efforts focusing on ferroelectric random access memory (FRAM) were started more than 60 years ago. Even though new and promising nonvolatile device concepts have emerged since then, the right to exist for FRAM is still provided by its excellent energy efficiency, fast rewrite speed and low voltage operation capability. Compared to the heat induced switching in PCRAM, spin transfer in STTRAM, ion conduction in RRAM or hot electron injection in NOR-FLASH, the electron efficiency of the polarization induced displacement current in FRAM remains unchallenged. Nevertheless, besides some temporary upturns and the launch of a few niche products, the focus of attention has notably shifted away from FRAM. This is mainly due to the challenging integration and limited scalability of capacitor-based (1T-1C) as well as transistor-based (1T) ferroelectric memory cells. These issues are decisive upon the future of FRAM and can be traced back to the choice of the ferroelectric itself. The commonly utilized perovskites, e.g. PZT or SBT, do not provide the thickness scalability and CMOS-compatibility required for cost efficient, high density 1T-1C or 1T memory solutions. However, utilizing ferroelectric hafnium oxide based memory devices, this scaling and integration dilemma can be overcome. Highly scaled 1T memory cells at the 2X nm node, as well as the possibility of a DRAM-like 3D-integration of 1T-1C FRAM has been demonstrated. In this contribution the current status of this disruptive technology will be critically reviewed and its future potential assessed.

Biography
Dr. Johannes Müller is heading the group for Non-Volatile Memories at the Fraunhofer Institute for Photonic Microsystems (IPMS) in Dresden, Germany. He received the diploma degree in Applied Natural Science from the Technical University Freiberg, Germany, in 2007 and later joined the Fraunhofer Center for Nanoelctronic Technology (CNT), Dresden, Germany, which since 2013 operates as business unit of IPMS. In 2014 Dr. Müller received his Ph.D. in electrical engineering from the Technical University Dresden for his research on next generation high-k dielectrics and the investigation of ferroelectricity in hafnium and zirconium oxide. To date Dr. Müller has authored/co-authored 29 peer-reviewed journal papers, 32 contributions to international conferences, including invited presentations at IEDM, ECS, NMTS and SSDM, and several patents. He was awarded the "Georgius-Agricola-Medal" from the Technical University Freiberg in 2008, the "Scientific Paper Award" from Fraunhofer in 2012 and the "Cool Award" from the leading edge Cluster Cool Silicon in 2014. Dr. Müller is an active member of IEEE and serves as an expert for ferroelectric memories and devices in the Emerging Research Devices Working Group of the ITRS.

Excimer Laser patterning for high density interposer and substrate fabrication

Boettcher, Mathias
Scientist
Fraunhofer IZM

Abstract
Mathias Böttcher, Michael Töpper, Karin Hauck, Martin Wilke, Juliane Krause, Klaus-Dieter Lang Within "More than Moore" concepts interposer based packaging technologies, known as 2.5D/3D system integration, open up a wide range for miniaturized multi-functional system solutions mostly known as System in Package (SiP). Pending on the final application dedicated interposer concepts are available for grabbing multiple active components, fabricated by using different technologies and materials, e.g. sensors, logic, RF and memory-ICs, as well as passive devices, including antennas. In many cases the application of high density multi-layer wiring and µ-pillar interconnects are needed. In order to support further system miniaturization and extension of system performance on one hand and to meet costs and time to market challenges on the other hand the development of organic interposer applications as well as the use of Excimer laser patterning technics for high density substrates is at high interest for R&D, prototyping and volume production. A short outline of high density substrate technologies developed and available at IZM will be presented. Starting with a brief discussion of basic elements of interposers, several technology concepts developed and validated for high density interposer applications will be shown. The pro and con of different process approaches will be discussed. Focus will be on the application of laser technology compared to photo- and etching-processes. Especially the strong influence of the polymeric material to the system functionality and reliability will be given. Challenges related to µ-pillar applications and high density wiring will be addressed and generic results will be presented. Using the variety of interposer technologies investigated at IZM a high level comparison of challenges and opportunities will be shown and discussed. A brief outlook of future development work for system applications will be given.

Biography
Mathias Boettcher started his carrier in 1982 at the Dresden University of Technology where he got his PhD in electrical engineering. In 1997 when Mathias joined the young AMD Team in Dresden and was deeply involved into the selection, transfer and start-up of a new C4 bumping technology for microprocessors at AMD's FAB30. In 2002, he got a new opportunity at Infineon and was the technical leader of the R&D team for memory module development at the Dresden site and later on in a similar position at the production site at Qimonda Malaysia. Since 2009 Mathias is leading the development team at Fraunhofer IZM-ASSID focusing on wafer processing for 3D-System integration, covering TSV, RDL and Bumping.

Integration Technologies for Image Sensors

Toepper, Michael
Business Development Manager
Fraunhofer IZM

Abstract
Packaging is a dominant part for the integration of image sensors into electronic systems for ultra-small and/or high performance applications. This presentation will focus on the packaging and system integration aspect of image sensors. Two different approaches will be presented and discussed in detail: One approach is a wafer level packaging concept using TSV (Through Silicon Vias) technology and the other is an image sensor on a small PCB with embedded image processor. Both technologies are a versatile step for new and advanced systems. The enabling key technology for wafer level packaging of camera systems based on top-side illuminated imagers are TSV because they allow a redistribution on the backside of the wafer wherefore the active side remains unaffected and can be completely used for the optic assembly. The wafer level camera having a size of about 1mm x 1mm will be presented. Another packaging process was made possible by an embedding technology. At a size of only 16x16x12 cubic millimeters, including, the microcamera module is an extremely small system. A total of 72 passive and 13 active components (such as oscillators, DC-to-DC converters, memory chip and image processor) have been embedded inside the module and the image sensor is mounted on top. The main system advantage is the fact that the image material is directly inside the camera, since it is equipped with an integrated processor for image processing. In addition it is fully encapsulated. After the image sensor has recorded the image, the integrated processor evaluates the frame. The video itself no longer has to be sorted and analyzed by an interposing system. Instead, only the relevant signals are transmitted.

Biography
Michael Töpper has a M.S. degree in Chemistry and a PhD in Material Science. Since 1994 he is with the Packaging Research Team at TU Berlin and Fraunhofer IZM. In 1997 he became head of a research group. In 2006 he was also a Research Associate Professor of Electrical and Computer Engineering at the University of Utah, Salt Lake City. The focus of his work was Wafer Level Packaging applications with a focus on materials. Since 2015 he is part of the business development team at Fraunhofer IZM. Michael Töpper is Senior Member of IEEE-CPMT and has received the European Semi-Award in 2007 for WLP. He has published several book chapters and is author and co-author of over 200 publications.

Cost efficient miniaturised silicon micropumps

Richter, Martin
Head of Department Micromechanics, Actuators and Fluidics
Fraunhofer Research Institution for Microsystems and Solid State Technologies EMFT

Abstract
Silicon MEMS components require high number of pieces for efficient manufacturing. On the other side, the manufacturing costs of high volume applications for MEMS components in automotive, consumer (like smart phone industry), and disposable drug delivery applications has to be very low, most of it in the region below 1$ / component and below. Due to physical reasons, MEMS actuators like silicon micropumps require a certain chip size to meet functional challenges like back pressure, compression ratio, and flow rate. The smallest state of the arte micropumps are made of Silicon (e.g. chip sizes: Fraunhofer micropump 7x7 mm2, Debiotech micropump: 6x10 mm2). That chip size makes it very difficult to meet manufacturing costs mentioned above. It is evident that manufacturing cost scale down with the chip size of the silicon micropump. With that, to address high volume applications it is essential to shrink the micropump chip furthermore. On the other side, it is just difficult to meet micropump performance parameters like stroke volume, flow rate, compression ratio or back pressure ability, if just the lateral dimensions of the actuation diaphragm will be reduced. Next, not only the silicon front end technology, also the back end manufacturing steps like piezo mounting has to be cost efficient. Finally, also the fluidic test cost of the micropump chip. In this presentation an overall strategy will be presented for a Technology platform for Silicon micropumps with small chip sizes down to 3x3 mm2. Results of this strategy regarding piezo mounting on wafer level, fluidic micropump test on wafer level are explained. Finally, first performance results of a 5x5mm2 micropump chip will be presented.

Biography
Martin Richter´s mission is to enable microdosing systems for industrial applications. He completed his studies in technical physics at the Technical University of Munich, and gained his PhD at the University of Armed Forces in the area of microfluidics. Since 2000 he has been heading the department Micromechanics, Actuators and Fluidics at Fraunhofer. His scientific focus is on microfluidic actuators such as micro pumps, micro valves, open jet dispensers or micro blenders, and integrating these in microfluidic systems. Such microfluidic actuators are deployed in varied applications, e.g. in medical technology (such as drug dosage, glaucoma therapy), laboratory technology or dosage of lubricants.

Massively Parallel 3D Inspection thru Metrology of µFeatures in 3D Packaging

Aiyer, Arun
CTO
Frontier Semiconductor

Abstract
All commercially viable chip stacking and die stacking methods require that conductors such as Cu nail or Cu pillar or solder bumps be placed on the chip or die I/Os to act as the interconnection. So in the realm of 3D packaging involving TSV/Cu nails, RDL µBumps or solder bumps, 3D co-planarity inspection of these interconnect features are critical for enhancing yield. Miniaturization in 3D packaging is challenging inspection and metrology approaches to higher measurement capability and throughput. Therefore, a high throughput, production ready metrology tool that can measure C4 bumps to Cu reveal height and capable of 100% height inspection, will be very valuable in terms of yield improvement, cost of ownership reduction and tool utilization. Frontier Semiconductor will introduce and present data on a new sensor platform that has the ability to measure in one exposure, individual heights of several hundreds of bumps or as many bumps as are there in one field of view. With this parallel measurement capability, the sensor can be configured to measure 100% of µBumps & Cu pillars/posts used in 2.5D, Flip Chip, e-WLB packaging and Cu-Nails in 2.5D/3D stacking at industry acceptable throughput levels. This patent pending technology is based on imaging technique using tailored optics in the imaging path. From captured images, metrology/inspection data are extracted using proprietary image processing algorithm. With this approach we have measured a few microns tall Cu nails from Cu reveal process to tens of microns tall µBumps used in 3D chip packaging such as Flip Chip, e-WLB etc. The theoretical resolution is <1% of the nominal height. Initial dynamic repeatability tests show that measurement is reproducible to ~1% of the nominal height. Correlating data from White Light Interferometer and FSM's patent pending Virtual Interface Technology will also be presented. Extension of this technique to measure RST will also be discussed.

Biography
Dr. Arun A. Aiyer is chief technology officer (CTO) for Frontier Semiconductor (FSM). He has extensive hands-on experience in technology innovation, IP protection, product innovation & development, and program management. At FSM he is leading the development of new products. Dr. Aiyer has experience and expertise in the areas of solid state lasers, Raman Spectroscopy, Interferometry, wafer metrology and inspection. Before coming to FSM, Dr. Aiyer was Chief Scientist at Verity Instruments. Prior to that he held positions as Director of Optical Engineering at KLA-Tencor and Senior Optical Physicist at Nikon Research Corporation of America. Dr. Aiyer has published 30 papers and holds over 20 patents with a few applications still pending. He has been the recipient of several patent awards and has delivered many talks at major international conferences. Dr. Aiyer received his Ph.D. from the University of Hull (England) in the areas of lasers and laser plasma interaction and was a Commonwealth scholar during his tenure at the university.

3D IC? 3D Metrology!

Marheineke, Bastian
President
FRT GmbH

Abstract
to be published soon

Biography
Bastian Marheineke graduated in Physics at RWTH Aachen and received his PhD from University of Ulm, working on MOCVD and PVD technologies for deposition of compound semiconductors. In 1998 he joined AIXTRON AG, Aachen Germany. Until end of 2013 he filled various management positions in Sales and Business Development for deposition tools for compound and organic semiconductors. In 2006 Bastian was appointed Vice President Sales, being in charge of global sales and service organisation. Beginning 2014 Bastian joined FRT GmbH, Bergisch Gladbach, Germany. He also appoints FRT as co-president.

EHS Challenges, Opportunities and Implementation Strategies

Vloeberghs, Hans
Business Director Europe
Fujifilm Electronics Materials

Abstract
Electronic devices play a key role in our daily life, and will continue to take a major role in the coming years. This will fuel a continued drive for increased functionality in semiconductor devices with improved energy efficiency. Historical these device evolutions have been driven by Moore's law and in addition, more recently, by More than Moore's law. In order to continue to drive these laws, it becomes increasingly important to introduce new innovative materials in IC manufacturing processes to stay in line with the device functionality requirements. With this comes the challenges of lower cost, higher performance expectations, increasing quality standards and equally important the more stringent Environment, Health and Safety (EHS) requirements. Compliance to the EHS regulatory, like REACH, is a major challenge for chemical suppliers to the semiconductor industry in order to continue the supply of current chemicals to the semiconductor industry and to maintain the supply at competitive price. For new innovative chemicals, the cost is even higher due to additional testing required by new EHS legislation in order to bring them on the market. In addition, some of the EHS regulatory requirements, like ROHS, require extensive chemical analyzes and control of the supply chain which comes not for free. This presentation will discuss the key EHS challenges which the chemical suppliers to the semiconductor industry faces and will introduce some ideas on how to effectively deal with these challenges.

Biography
Hans Vloeberghs is Business Director Europe at Fujifilm Electronic Materials Europe which is the European headquarters of Fujifilm Electronic Materials, a division of Fujifilm, and a worldwide manufacturer and supplier of photoresists, polyimides, thin film systems, CMP and other high purity chemicals to the semiconductor industry. In addition to his role as Business Director for Europe, he is the Global Business Director of Fujifilm Electronic Materials Polyimide product line. He joined Fujifilm Electronic Materials Europe at that time OCG (Olin-Ciba-Geigy) Microelectronic Materials Europe in 1993 as an Application Engineer and as a Collaborator of OCG R&D programs. At OCG which changed name to Arch Chemicals and finally acquired by Fujifilm, he held several positions from Product Manager photoresist to Business Manager Europe for all electronic materials. He received his Ph. D. in Physics from the University of Leuven (Belgium) in 1992. At that time, he was a research assistant of the Belgian National Fund for Scientific Research in the Laboratory of Solid State-Physics and Magnetism.

The Quest for Quality and Yield Improvement for High Speed Serial Interfaces in Vehicles

Leblond, Nicolas
Senior Application Engineer
Galaxy Semiconductor

Abstract
Inova Semiconductors GmbH is a fabless semiconductor manufacturer headquartered in Munich, Germany, which specializes in the development of products for Gigabit/s serial data communication. As vehicle manufacturers deploy intelligent driver assistance systems and eventually even self-driving cars, the need for high speed serial interfaces between cameras, displays and video units is skyrocketing. Because of the mission -critical nature of these automotive applications, Inova has demonstrated a strong focus on quality and reliability, while also keeping costs under control. In this paper we will describe the advanced test techniques that we have put in place, including Part Average Test (PAT) and Statistical Yield Analysis (SYA) to eliminate outliers and maverick lots. We will also describe our analysis of field returns using a die traceability capability that helps us recreate the wafer map from which the failing die originate and looking for systematic process problems. We will provide specific examples that illustrate how the combination of advanced test techniques and detailed failure analysis has helped us improve the manufacturing process to achieve better quality and yield at the same time. This paper is coauthored with Lothar Doni Director Quality Assurance at Inova Semiconductors GmbH and Nicolas Leblond Senior Application Engineer at Galaxy

Biography
Nicolas Leblond holds an Engineering degree from INP Grenoble and specialized in Microelectronics. He has been working for more than 10 years in the software and semiconductor industries, in startups as well as in larger companies like Xilinx. He is now Senior Application Engineer at Galaxy Semiconductor and provides technical support for customers in Europe, Asia and USA. Lothar Doni is currently Head of quality assurance at Inova Semiconductors. He worked as unit process engineer and team leader at Infineon in Villach and in development alliance for 45/65nm in Fishkill, as process engineer at Steag Microtec and studied micro system technology at university of applied science in Regensburg

Organization and Goals of the Industry 4.0 Platform

Schulz, Thomas
Channel Manager Central and Eastern Europe
GE Intelligent Platforms GmbH

Abstract
The term 'Industry 4.0' was introduced the first time in Germany at the Hanover fair in 2011 and is a central focus of the Federal Government's Digital Agenda. It is supporting and promoting the digitization of industry and has the potential to bring about profound transformation to efficient factory manufacturing. The implementation strategy forms the basis for all future work. It not only records the research agenda that has been pursued to date, but also lays out core components of 'Industry 4.0'. Given the complex and broad starting point of the platform work nowadays, a framework is to be established that allows for 'Industry 4.0' reference architecture to developed - a set of parameters that can be used in order to press ahead with digitization and comprehensive networking in production. The substantive work of the platform is initially being undertaken in five working groups (reference architecture, standardisation / research and innovation / security of networked systems / legal framework / labour, training). The platform's governing body includes Economic Affairs Minister and Research Minister as well as representatives from business, science, and trade unions. This presentation is intended to provide an introduction to the platform 'Industry 4.0', its potential, on opportunity and restrictions.

Biography
Thomas Schulz has a Master of Science degree in engineering technology. He has many years' experience in manufacturing organization and process automation with a number of printed publications and presentations. He is currently employed by GE (General Electric) Intelligent Platforms division and is responsible for GE Partner business covering Central and Eastern Europe. Since 2013 he has been a member of the Working Group covering reference architecture and standardization of the platform 'Industry 4.0' - the strategic initiative and high-tech strategy of the Federal Republic of Germany. He has been actively participating, as part of a team of authors, working on Chapter 6: Reference architecture, standardization and standardization of the implementation of the strategy for the 'Industry 4.0' results report.

28/22nm RF Technology status and future roadmap

Harame, David
CTO RF Technology and Enablement
Global Foundries

Abstract
The IoT with billions of connected devices will require wireless connectivity, faster processing, faster data rates, longer battery life and lower cost. For the wireless connectivity, especially IOT, low power, cost, and RF performance are the most important considerations. FDSOI offers a unique combination of low cost, low power, and RF performance which nicely meets these targets. This presentation will focus on the RF performance. All RF designs require RF passives including RF capacitors (MOMs), Inductors, Varactors, and Resistors, supported with models tuned to S-parameter data. An RF custom PDK with RF models for all RF devices is provided. 22FDX transistors have excellent electrostatics compared to bulk. The HiK Metal Gate stack and short gate length (Lg) provide high transconductance (gM > 2mS/um) with low gDS. The high gM, and low gDS gives a high self gain, important for all RF/Analog applications. The FDSOI transistor is architected for effective body biasing. The Back Gate Bias (VBG) enables reducing the threshold voltage (FBB) for increased current drive or increasing the threshold voltage (RBB) for decreased leakage. The RF performance of 28nm FDSOI has been published by Lucci as fT= 380 GHz and fMAX= 390 GHz (2015 IMS Symposium). This combination of high fT and fMAX is amongst the highest achieved for any RFCMOS technology and clearly demonstrates the performance potential of FDSOI technologies. Simulations show 22FDX has better AC gain than bulk 28nm SLP technology. Using the back gate to lower Vt expands the voltage range over which a high gM is found. This expanded dynamic range is also true for fT and fMAX. In Summary, FDSOI makes an excellent RF technology.

Biography
David Harame joined GLOBALFOUNDRIES in 2014. David is a Global Fellow and the Chief Technical Officer for RF Development and Enablement. Prior to GLOBALFOUNDRIES worked for IBM where he was an IBM Fellow and was also the CTO for RF Development and Enablement. David has worked in the area of RF technology for over 30 years. In 2005 David was awarded the IEEE Daniel E Noble Award "For the development of manufacturable Silicon Germanium, HBT Bipolar and BiCMOS technologies." He also received the IEEE BCTM Award for his work in SiGe BiCMOS. David is an IEEE Fellow.

Investing in Europe

Wijburg, Rutger
Senior VP and General Manager Fab Management
GLOBALFOUNDRIES

Abstract
T B A

Biography
Dr. Rutger Wijburg is Senior Vice President and General Manager of GLOBALFOUNDRIES Fab 1 in Dresden, Germany. He is responsible for GLOBALFOUNDRIES' highend 300mm manufacturing operations in Europe. Prior to joining GLOBALFOUNDRIES in 2011, Rutger Wijburg was Senior Vice President and Operations Manager Front End at NXP Semiconductors (formerly Philips Semiconductors) in the Netherlands. In this role, he was responsible for the company's seven wafer fabs, led outsourcing and building strategic partnerships, and was in charge of real estate and facilities management. Rutger Wijburg has also held leadership positions with Mesa Research Institute in the Netherlands and CSEM SA in Switzerland. He holds both a Master of Science degree and Ph.D. in Electrical Engineering from the University of Twente, the Netherlands.

InterfaceA: Candidate for Industry 4.0? Adoption and Challenges in Semiconductor Industry

Kuehn, Ingo
MTS Design Engineer
GLOBALFOUNDRIES

Abstract
Interface A: Candidate for Industry 4.0? Adoption and Challenges in Semiconductor Industry. Smart communications between production equipment and factory IT solutions is a key element of Industry 4.0. Starting in the 1980's, the semiconductor industry developed SECS (SEMI Equipment Communications Standards) and related E-Standards which are widely implemented in semiconductor front end production factories and in the solar industry. A subset of the standards categorized as Interface A (IFA) is a relatively new SEMI Equipment Data Acquisition (EDA) set of standards built on non-proprietary Web technologies. It provides a more flexible interface between production equipment and factory IT solutions and improves some data collection limitations of the existing SECS/GEM (Generic Model for Equipment & Control of Manufacturing Equipment) interface. This presentation introduces IFA featuring a comprehensive self-descriptive capability. Major differences compared to SECS/GEM communication will be highlighted. As with many other new technologies, IFA has not been spared from its own challenges which last even until today. At GLOBALFOUNDRIES selected IFA Vendor deliverables lag behind expectations for meeting factories full production ramp capability, to include IFA reliability. In part, this may be due to the fact that a comprehensive and widely accepted IFA test suite has not been available - at least not in a comparable scope as to what was available when SECS/GEM and 300mm automation standards was ramping in the Semiconductor Industry. Consequently we will touch on GLOBALFOUNDRIES' IFA test methodology and associated test software with examples of common problems found. A discussion of current data collection and equipment control challenges in semiconductor industry and an outlook on a broader application will summarize the presentation.

Biography
Authors: Ingo Kühn Olaf Zimmerhackl Mr. Ingo Kuehn studied Technical Cybernetics and Automation at TU Chemnitz, receiving a Master degree in 1991. He continued his studies at Tampere Technical University, Finland in the Digital Signal Processing Lab at Prof. Yrjö Neuvo. He worked in the Telecommunication area, developing DSP software for the first UMTS mobile network at NOKIA Telecommunication, Oulu. From 2000, he works for AMD Dresden, later Globalfoundries Inc. first in the field of Digital Design Verification. From 2010 he started working in the Automation department. Currently, he is responsible for development of Equipment Interfaces and supports the ACM team. Mr. Kuehn holds three patents in the Digital design and verification area. Olaf Zimmerhackl received his Diplom-Ingenieur in electrical engineering from Dresden University of Technology in 1997. He is member of the Technical Staff Factory Automation Engineer and is Program Lead for Automation Capabilities Management (ACM) at GLOBALFOUNDRIES Fab 1 in Dresden.

22nm FDSOI Technology & Devices for Energy-Efficient Applications

Wiatr, Maciej
Senior Manager Device Integration
Globalfoundries

Abstract
Current estimates forecast 26-30 Billion devices will be connected wirelessly to each other and to the Internet by 2020 forming the so called Internet Of Things (IoT). The ability of IoT devices to network and perform complex tasks with limited CPU, memory and power resources introduces special requirements to the IoT systems and the underlying semiconductor technologies. Globalfoundries develops new semiconductor technologies supporting the long-term vision of Billions and Billions IoT devices constrained by resources and power. 22 FDSOI technology from Globalfoundries offers unique characteristics suitable to serve IoT systems with the required balance between ultra-low power operation at adequate performance.

Biography
Maciej Wiatr graduated in the field of Solid State Electonics in 1997. During his PhD study at University of Kiel, Germany he focused on compact modeling of partially and fully-deplested SOI devices. After his PhD (2003) he joined the Design Enablement (modeling) group at Philips Semiconductors in Hamburg. In 2005 he joind AMD Dresden and worked on technology & transistor integration in 65, 45, 32 and 28nm technologies. He acompanied the transistion of GlobalFoundries from IDM (AMD) to Foundry business and has been assigned Senior Manager Device Integration in Dresden in 2014. His responsibilities include integration concepts of transistors, NONFETs and most recently also "More-Than-More" technology extensions like RF and NVM for 28/22nm technologies. Electrical parameter monitoring as well as definition of electrical monitoring structures and methodologies complete the field of his duties.

Silicon, Interconnect, Packaging and Test Challenges from a Foundry Viewpoint

Bonkass, Matthias
Director Bump Test Facility
GLOBALFOUNDRIES Dresden

Abstract
Beyond the complex wafer fabrication processes starts a very challenging world of silicon interconnect, packaging and test. Many aspects of leading edge fab processes drive for smaller and dense die-to-die interconnects as well as next technology stage packing and test challenges. The cost of silicon scaling effects rapidly increases. New packaging solutions have to balance the performance, power and cost. Chip-Package-Interaction (CPI) at leading edge technology nodes become a very complex system containing different types of material which require new ways of controlling mechanical and electrical stress. While new bump technologies allow reducing cost with the introduction of new materials the overall test cost trend increases. The key note speech will highlight the industry trends, technical challenges and potential solutions addressing those areas. The foundry point of view offers a summary for the various trends seen in the industry.

Biography
Matthias was a member of the Dresden startup teams for AMD Fab30 (200mm) in 1997 and AMD Fab36 (300mm) in 2004. He started his career as a CMP/Plating process engineering back in 1997 with long term assignments in AMD Sunnyvale/California. After holding several operation management positions in the 200mm and 300mm lines he became a Module Manager in CMP/Plating in Fab1 in 2007. In 2012 he became the Module Manager for GLOBALFOUNDRIES Fab1 Thin Films. Since 2013 he has been the Director of the Bump Test Facility (BTF) in GLOBALFOUNDRIES Fab1. Matthias holds a degree of electrical engineering of University of Applied Science Lausitz.

Fully Automated Vendor Lot Start

Puelm, Stephan
MTS Program Management
GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KG

Abstract
Following the Industry 4.0 approach, GLOBALFOUNDRIES has implemented a fully automated vendor lot start process, covering the entire wafer material supply chain. In the new process, each raw wafer that is delivered to GLOBALFOUNDRIES has its certification automatically checked, is registered in all manufacturing IT systems and is transferred to sorters and FOUPs (Front-Opening Unified Pod), which are the containers in which wafers are transported through the manufacturing process. This automated handling replaces five manual steps, and integrates several former lot start processes. This solution is an important step for fully automated FAB logistics and wafer start. It covers: * Automation of wafer material registration at Lot start * Automated synchronization of supplier data with incoming physical wafers * Certificate release procedure * Automated transfer from FOSB to FOUP * Automated vendor lot start in MES The presentation will show the implanted (consider grafted?) business process, and will highlight implementation details, such as Supplier involvement and standardized COA data transfer, as well as the FOSB recognition hardware preconditions.

Biography
Stephan Puelm: After studying physics with areas of concentration in fields surface science and semiconductor physics, Stephan Puelm worked as a software engineer at Sympatec GmbH (particle size analysis system vendor). In 1999, he transferred over to GSM GmbH as branch lead (software and project management consultant). Since 2006, he has worked in the semiconductor industry. He worked at Qimonda from 2006 to 2010, then transferred over to GLOBALFOUNDRIES as a project lead for automation projects. Tony Genenncher: Mr. Genenncher is currently working as project lead and application engineer for Logistics at GLOBALFOUNDRIES. In 2000, he started an apprenticeship in micro-technology in cooperation with AMD and the Bildungszentrum für Hochtechnologie GmbH. As a member of the Production Control Department, he was involved in the ramp-up of AMD's then new Fab36 in 2005. After he completed his studies in mechatronics in 2011, he began work for Fab Logistics Support at GLOBALFOUNDRIES, where he continues to make significant contributions.

An Integrated Electroluminescence, Photoluminescence and Thermography Inspection Tool for Wafer and Semiconductor Characterisation

Regehly, Martin
CEO
greateyes GmbH

Abstract
Luminescence imaging has become a powerful tool for quality control of wafers, processed solar cells and thinfilm substrates. Electroluminescence (EL), Photoluminescence (PL) and Dark Lock-In Thermography (DLIT) are the most common imaging methods,delivering spatially resolved informations about material parameters and allowing to detect cracks, hot spots, impurities and shunts fastly and in a non invasive fashion. Typically EL and PL measurement capability are integrated in the same instrument, a powerful laser source serves for optical excitation of the sample in case of PL characterization. DLIT requires an alternating current, an thermal infrared sensitive camera and a precise synchronization between image acquisition and driving current. For the reason of complexity and different requirements of the individual methods, a unified tool has not been proposed. On the other side, the gathered information from EL, PL and DLIT are complementary and can provide a more comprehensive understanding of the device under study. The presented system integrates EL, PL and DLIT measurement capability with a low number of components. It employs a HighPower LED based light source instead of a laser for excitation, making the system more flexible, safe in its usage and cost-effective. We report about the design of the system and example characterisation of preprocessed wafers and finished solar cells.

Biography
Mr. Regehly studied Physics at University of Ilmenau and at Humboldt-University Berlin. He wrote his diploma thesis about the HDAC instrument onboard the Cassini spacecraft. For this purpose he had worked at German Aerospace Center (DLR) in Berlin und at Laboratory of Atmospheric and Space Physics (LASP) in Boulder, Colorado. In the following he did a doctoral degree in physics at Humboldt-University Berlin about photodynamic cancer therapy. In 2007 he founded greateyes, a company developing and manufacturing scientific cameras and optical inspection systems. In his current position as CEO, Mr. Regehly directs the activities of the innovative, growth-oriented high tec company.

Efficient low power architectures design for wireless Security systems - Intrusion Alarms

VIVANCOS, Philippe
Security System Hardware Manager
Hager Security

Abstract
Hager Group is an independent Franco-German family-owned company operating worldwide. Hager is a leading supplier of complete solutions and services for electrical installations in residential, commercial and industrial buildings. Product's offer ranges from Energy distribution through Cable management and wiring accessories to Building automation and Security systems including alarm systems, smoke detectors and access control devices. Based on a full wireless architecture for both the power and the communication, most of the Intrusion Alarm devices are designed and developed under strong and challenging constraints in terms of low power consumption, long lasting battery life, radio performances as well as efficient sensor signal conditioning. The content of the presentation will explain how low power consumption is addressed during the design and the development phases of wireless products in the Security domain. Topics will cover both the hardware and the firmware design aspects.

Biography
- 1992, I received my engineering degree from Polytech'Grenoble in Industrial Computer Science, Instrumentation and Electronics. - 1994, I started my professional life working for a System Integrator in Montpellier specialized in industrial automation and process control systems design. During two years, in addition to oversee the department of Automation & Electrical engineering, I participated to the design and the development of multiple projects in relation with the food industry, water treatment, quarries ... - 1996, I joined Adaptive Micro Systems Europe in Grenoble, a brand new European subsidiary of an international U.S. company doing business in indoor & outdoor electronic LED displays signs (Billboards & Message Centers). During 18 years, I had the chance to fulfill different complementary positions such as Principal Architect for Hardware & Software designs, Project & Product Manager and finally Engineering Manager. This work experience gave to me a great opportunity to acquire and develop strong competences both in hardware, firmware and software in the following technological & technical fields: Embedded PC controllers, µC & FPGA based system architectures, High speed PCI-x video boards, Industrial communication & data acquisition gateways ... - 2012, I joined Hager Group at the R&D Center located in Crolles where I hold the position of Hardware Manager for the entire Security systems product range.

Zimmermann, André
Executive Board Member
Hahn-Schickard

Biography
André Zimmermann studied chemistry and crystallography at Julius-Maximilians-Universität Würzburg as well as materials science at the Technical University Darmstadt. After several research stays in the USA at NIST (National Institute of Standards and Technology, Gaithersburg, Maryland) and University of Washington (Seattle, Washington) he received his PhD in materials science from the Technical University Darmstadt. In 1999, he became a group manager at the Max-Planck-Institute for Metals Research in Stuttgart where his research focused on the reliability of materials and on the assembly and interconnection technology of actuators for adaptronics. Between 2002 and 2014 he was holding various positions within the corporate research and development of Robert Bosch GmbH in Waiblingen in the area of electronic assembly and interconnection technology, computer aided engineering, strategy and innovation management. A focus of his tasks at Robert Bosch GmbH was the position as senior manager for electronic packaging. Since January 2015 he is professor for microtechnology at the IFM (Institut für Mikrointegration) at the University of Stuttgart. Simultaneously, he became an executive board member of Hahn-Schickard, a non-profit organisation for applied research on microsystems technology. The current work of André Zimmermann concentrates on the following fields: electronic assembly and interconnection technology, reliability of microsystems.

HERO unchained - Modular AGV for multiple handling applications

Stegemann, Burkhard
Sales Director
HAP GmbH Dresden

Abstract
The big majority of European chip fabs still uses wafer sizes of 200mm and smaller. Most of these fabs are older and grew over many years. Hence, the infrastructure in the cleanrooms is very different from fab to fab. This is related to the available space and the positioning of equipment inside the cleanroom, but also to the carriers that are used during the transport and production. While some fabs already use open cassettes fab wide, most use different kinds of transport boxes that additionally require the un-locking and the opening of the covers. As these tasks are challenges for automation systems, most of these fabs still manually load the wafer carriers onto the systems by operators. The HAP-HERO FAB system family addresses these diverse requirements. These fully free (no rail, cable or chain attached) navigating AGVs are able to handle different kinds of transport boxes, to un-lock and open them and to take out and load the cassettes onto the equipment loadports. SMIF pods, RSPs and FOUPs can be loaded as well.

Biography
Born in 1969, Burkhard Stegemann studied Physical Technics at the FH Aachen and completed his final year at Coventry University. In 1996 he joined Carl Zeiss in Jena in the department of microscopic wafer inspection. After two years in R&D/ application, he changed to product and project management. As part of the acquisition of the Zeiss business field "optical wafer inspection" by HSEB Dresden GmbH in 2004, Burkhard Stegemann joined HSEB in 2007. His responsibilities were sales and service. Since May 2014 Burkhard Stegemann is sales director of HAP GmbH Dresden.

Highlights of the International Image Sensor Workshop 2015

Theuwissen, Albert
CEO
Harvest Imaging

Abstract
This presentation will give an overview of the highlights of the IISW2015, recently held in Vaals, the Netherlands. The IISW2015 is being known at the world's top conference/workshop in the field of solid-state imagers. Many excellent papers are presented and published on a wide variety of topics related to solid-state imaging. During the presentation, the main focus will be on small-pixel devices and how their performance is further improved.

Biography
Albert J.P. Theuwissen was born in Maaseik (Belgium) on December 20, 1954. He received the degree in electrical engineering from the Catholic University of Leuven (Belgium) in 1977. His thesis work was based on the development of supporting hardware around a linear CCD image sensor. From 1977 to 1983, his work at the ESAT laboratory of the Catholic University of Leuven focused on semiconductor technology for linear CCD image sensors. He received the Ph.D. degree in electrical engineering in 1983. His dissertation was on the implementation of transparent conductive layers as gate material in the CCD technology. In 1983, he joined the Micro Circuits Division of the Philips Research Laboratories in Eindhoven (the Netherlands), as a member of the scientific staff. Since that time he was involved in research in the field of solid state image sensing, which resulted in the project leadership of respectively SDTV- and HDTV imagers. In 1991 he became Department Head of the division Imaging Devices, including CCD as well as CMOS solid state imaging activities. He is author or coauthor of over 160 technical papers in the solid state imaging field and issued several patents. In 1988, 1989, 1995 and 1996 he was a member of the International Electron Devices Meeting paper selection committee. He is co editor of the IEEE Transactions on Electron Devices special issues on Solid State Image Sensors, May 1991, October 1997, January 2003 and November 2009, and of IEEE Micro special issue on Digital Imaging, Nov./Dec. 1998. In 1995, he authored a textbook "Solid State Imaging with Charge Coupled Devices" and in 2011 he co-edited the book "Single-Photon Imaging". In 1998 and 2007 he became an IEEE ED and SSCS distinguished lecturer. He acted as general chairman of the International Image Sensor Workshop (formerly IEEE International Workshop on Charge-Coupled Devices and Advanced Image Sensors) in 1997, 2003, and 2009. He is member of the Steering Committee of the aforementioned workshop and founder of the Walter Kosonocky Award, which highlights the best paper in the field of solid-state image sensors. During several years he was a member of the technical committee of the European Solid-State Device Research Conference and of the European Solid-State Circuits Conference. From 1999 till 2010 he was a member of the technical committee of the International Solid-State Circuits Conference. For the same conference he acted as secretary, vice-chair and chair in the European ISSCC Regional Committee and since 2002 he was a member of the overall ISSCC Executive Committee. He has been elected to be International Technical Program Chair vice-chair and chair for respectively the ISSCC 2009 and ISSCC 2010. In March 2001, he was appointed as part-time professor at the Delft University of Technology, the Netherlands. At this University he teaches courses in solid-state imaging; coaches MSc and PhD students in their research on CMOS image sensors. In April 2002, he joined DALSA Corp. to act as the company's Chief Technology Officer. In September 2004 he retired as CTO and became Chief Scientist of DALSA Semiconductors. After he left DALSA in September 2007, he started his own company "Harvest Imaging", focusing on consulting, training, teaching and coaching in the field of solid-state imaging technology (www.harvestimaging.com). In 2006 he co-founded (together with his peers Eric Fossum and Nobukazu Teranishi) ImageSensors, Inc. (a California non-profit public benefit company) to address the needs of the image sensor community (www.imagesensors.org). In 2008, he received the SMPTE's Fuji Gold medal for his contributions to the research, development and education of others in the field of solid-state image capturing. He is member of editorial board of the magazine "Photonics Spectra", an IEEE Fellow and member of SPIE. In 2011 he was elected as "Electronic Imaging Scientist of the Year", in 2013 he received the Exceptional Service Award of the International Image Sensor Society and in 2014 he was awarded with the SEMI Award.

Organic solar films - a novel and truly urban-fit source of energy

Bickl, Thomas
VP Sales & Product Development
Heliatek GmbH

Abstract
Nowadays standard solar technology has reached a cost level, which allows competitive power generation. Amongst other reasons one way to reach that cost level has been the standardization into similar module sizes and optical appearances with little flexibility for adaptation. The speech will present a novel flexible approach based on a organic solar film. The solar film invented by Heliatek is based on nano-sized carbon molecules which are deposited in a unique roll-to-roll process onto a flexible PET film substrate. This film weighs only 500 grams/m², and can be tailored in many different ways for length and color. Special versions of the film will also feature a transparency level of up to 50%. That special combination of material properties is further complemented by the fact that the organic solar film harvests about 25% more energy from the solar spectrum than standard crystalline solar cells. The reason for that lies in the unique material properties of carbon absorber molecules which perform extremely well under hot temperatures or overcast sky conditions, which e.g. are very prevalent in tropical regions. This additional energy harvesting factor comes on top of the world record efficiency for organic solar cells of 12%, which Heliatek has demonstrated. It will be further shown that the production conditions for Heliafilm® are such that the energy payback time is at record low of less than 3 months and does not contain any hazardous or rare elements - a fact, which is important for the future mass scalability and life cycle analysis. In conclusion we will present the various ways in which this solar film can be integrated into buildings materials like glass, concrete, steel or polycarbonate on a variety of locations in Europe and Asia.

Biography
Dr. Thomas Bickl Dr. Thomas Bickl studied physics in Munich, Austin (TX, USA) and Hamburg. In 1994, he obtained the PhD degree from the University of Würzburg for a thesis on "Nanostructuring of III/V semiconductors". He brings about twenty years experience in sales, business and product development of international high-technology companies in the markets of semiconductor equipment, industrial digital printing and solar technology. In the solar sector he gained professional expertise in the area of building integrated photovoltaic (BIPV) and developing of international markets and applications. He joined Heliatek in May 2014, and is responsible for Sales, Marketing and Product Development.

Spin-based nanoelectronic devices for mobile Informaion-Communication Technology

Deac, Alina
Group Leader
Helmholtz-Zentrum Dresden - Rossendorf

Abstract
Perhaps the best known (or most successfully implemented) spin-based device is the hard-disk read-head. Indeed, the discovery of giant magnetoresistance enabled a paradigm shift in the miniaturization of magnetic storage technology, which was disruptive enough to earn its discoverers a Nobel price [1]. More recently, it has been demonstrated that non-volatile, ultra-fast spin-based memory bit devices can be designed so that they can scale down to more than one fifth of all other available technologies, including SRAM [2]. Other spin-based nanoelectronics devices currently under consideration - which will be discussed here - range from tuneable radio-frequency oscillators to magnetic field sensors, negative resistors, amplifiers, write heads and random number generators. [1] http://www.nobelprize.org/nobel_prizes/physics/laureates/2007/index.html [2] http://www.avalanche-technology.com/technology/ram

Biography
Alina Deac is currently the leader of the Spintronics Group at the Helmholtz-Zentrum Dresden - Rossendorf in Dresden, Germany. During the last 15 years, her research has been focused on spin-torque induced phenomena and their potential applications for mobile ICT devices. After obtaining her PhD in Physics at the Universite Joseph Fourier Grenoble, France in 2005, she pursued her career by working with top-notch institutions in Japan, US and Switzerland. She is a Senior Member of the IEEE Magnetics Society and an expert in the field of spintronics for the EU.

Micro-technologies for 3-D depth sensing systems

Rossi, Markus
Chief Innovation Officer
Heptagon Advanced MicroOptics

Abstract
Optical depth sensing technologies in consumer electronics, in particular mobile devices, are driven by an increasing number of applications, such as enhanced imaging, gesture control, user interfaces, augmented reality, vital sign measurements, etc. The depth sensing technologies range from passive and active stereo-vision over triangulation technologies to time-of-flight concepts. This talk will focus on the micro-systems technologies of the different depth sensing concepts, in particular the miniaturization aspect, as well as some selected used cases.

Biography
Formerly head of CSEM Zurich Replicated Micro-Optical Elements, Markus became CTO of Heptagon after CSEM's microoptics division was acquired by Heptagon in 2000. He is an expert on design and fabrication of diffractive and refractive micro-optic components and subsystems for industrial applications in the European and US markets. Markus holds a Ph.D. in Micro-Optics from the University of Neuchatel, Switzerland and a master's degree in physics from ETH Zurich.

Intermetallic Coverage (IMC) in Cu and Ag Ball Bond

Senthil Kumar, Balasubramanian
Project Manager
Heraeus Deutschland GmbH & Co. KG

Abstract
Gold,Cu,Pd coated Cu(CuPd and alloyed Ag bonding wires are commonly used for inter-connection in integrated circuits. Though Au wire is still considered to be good in reliability, corrosion resistance and high productivity, rising cost of it leads to the trend in using other types of wires. Due to inherent stiffness and hardness Cu and CuPd wires induce high stress on the bond pad and underlying structure. This pave ways to investigate on Ag based bonding wires. Where Ag wires have issues on free air ball (FAB) morphology. In addition, when bonded to Al bond pad, both Cu and Ag ball bond reliability is not as good as Au bond. Among the factors that contribute for better reliability, as intermetallic coverage (IMC) was well established in Au ball bonding in the packaging industry by wet chemical etching method, it is vital. The rule of thumb for a reliable bond in Au ball bonding is to attain greater than 80% IMC (gold aluminide) and 5.5 g/mil2 ball shear at time zero. There is no clear method adopted to measure the IMC in Cu and Ag ball bonds, either with alloyed or coated wires, particularly when bonded to Al bond pad. The paper enumerates a cost effective and quick procedure to observe the IMC in Cu and Ag ball bonds when bonded to Al pad metallization. In Au ball bonding at time zero, gold aluminide nucleates in a fraction of micron. Whereas, Cu and Ag ball bonding nucleate with copper aluminide and silver aluminide in nano-meter scale. Therefore, to observe the aluminides clearly, a pre-thermal treatment is needed. The pre-treatment ranges from 150C to 250C for 30minutes up to 5hours. Similar to IMC study of Au ball bond, Al bond pad is dissolved using 10 to 20 vol% KOH or NaOH solution. Later, topsy-turvy the Ag ball bond to observe the silver aluminide. time zero and hence, ball shear between 8 and 11 g/mil2 is recommended for good reliability and bondability.

Biography
B.Senthil Kumar received the B.E. in Mechanical engineering from University of Madras, Chennai, India and the M.S. degree in Precision engineering from the Nanyang Technology University (NTU), Singapore. He is a Staff Engineer for Heraeus in the bonding wire R&D Department, Hanau, Germany. He was the senior engineer for Infineon Technology Singapore to develop a Copper wire bonding process development for Automotive packages. His current efforts include developing fine copper and silver alloyed wire for various application related packages. He had published and presented six technical papers at advanced package conferences. He has a total of 15 years of semiconductor industry experience.

Photonic processes in printed electronics

Giesbers, Merijn P.
Research Engineer
Holst Centre / TNO

Abstract
In this presentation photonic-based patterning and sintering processes for printed electronics will be introduced and their advantages and challenges compared to conventional techniques will be discussed. Firstly, Laser Induced Forward Transfer (LIFT) will be considered. LIFT is a technique which uses a laser pulse to transfer material from a donor layer to an acceptor substrate. It is a promising technology providing flexible, high resolution and fast printing, capable of handling a wide range of materials, and enabling printing on a wide range of substrates, including conformal surfaces. An overview of our results regarding the printing of silver inks, conductive adhesives and dielectric materials will be given. In particular, fine (15 µm) silver lines, printed dots of highly viscous adhesives and bridging using dielectric materials. Secondly, photonic flash sintering will be discussed. By exposing printed metal ink structures to intense short light pulses, drying and sintering of metal particle inks can be achieved yielding highly conductive structures. Since the heating by light is localized in time and space, sintering of the metal at high temperatures can be achieved much faster while keeping the supporting (often heat sensitive) foils cool. The given talk will provide an overview of our progress on developing a Roll-to-Roll system capable of patterning and sintering multilayer stacks, consisting of electroluminescent materials, insulators and metallic conductors, thereby covering a wide range of applications, such as printed sensor platforms, RFID tags and electroluminescent devices. Functional materials are deposited and patterned on flexible substrates by rotary screen and inkjet printing at web speeds of up to 20 m/min. Post-deposition treatment of the deposited materials (drying, curing and sintering) is carried out by a combination of near-infrared and photonic flash treatment, allowing much higher manufacturing speeds compared to traditional approaches.

Biography
Merijn Giesbers is a Research Engineer at Holst Centre, an open innovation centre in the Netherlands. He studied physics at the Radboud University in Nijmegen. He has worked on research into Laser Induced Forward Transfer for the past 4 years, in close collaboration with industrial partners.

Hybrid printed electronics: 2D manufacturing for freeform 3D application

Koetse, Marc
Senior Researcher
Holst Centre / TNO

Abstract
Electronics today are becoming more and more ubiquitous. This leads to ever greater challenges in design, engineering and manufacturing of the electronic modules. For instance electronic devices may be worn on the body in health patches, be integrated in textiles or be used in car interiors. In generic term: the electronics needs to be applied in a 3D environment, must be stretchable or at least conformable. At the same time modern electronics manufacturing lines are completely equipped for 2D fabrication on boards, sheets or rolls. Hybrid printed electronics (HPE), the combination of printed conductive tracks on cheap foils and classic microelectronics, seems very well suited to overcome the gap between 2D manufacturing and 3D application. In recent years, our research and developments have mainly focused on the improvement of existing technologies in order to improve the TRL level but also the complexity of the demonstrators. For instance, In the field of printing, mayor improvements were made that allow for the realization of a circuit with 5 conductive layers. Another important improvement was realized in the reliability of placed components for application in wearable devices again the technology could be transferred to an external party. This, together with much improved design rules have allowed us to make highly demanding yet appealing demonstrators. In our contribution we will discuss these topics and will show how the improved technologies helped to solve the specific demands and requirements of our customers. At the same time many of the developed solutions proved to be highly generic and are applicable in wide variety op applications where freeform electronics are desired.

Biography
Dr. Marc Koetse received his PhD in polymer chemistry and material science from the Université Catholique de Louvain (B) in 2001. After a few years at TNO, where worked on organic PV, he joined the Holst Centre in 2005 to start a group on "Interconnect Technologies". In 2007 he moved to the Sensor Tags and Systems program where he is responsible for the integration of organic electronics and Si-based devices and technologies in sensor platforms. Currently he is senior researcher in the integration technologies for flexible systems group.

FD-SOI film thickness metrology tool

Srocka, Bernd
Manager R&D
HSEB Dresden GmbH

Abstract
The newly evolving technology of building transistors superior in speed and/or power consumption on fully depleted silicon on insulator wafers (FD-SOI) is well known to be critical dependent on film thickness homogeneity of the silicon and BOX layers used. For certain products these transistors compete with the early FINFET or if combined with it makes its production easier while boosting FINFET performance to even higher parameters at the same time. The threshold voltage of a FD-SOI transistor is reported to depend with 25 mV/nm on a nominal 8.5 nm thick silicon SOI film thickness (Khafikirooz et al, 2010). Hence, in order to gain the full benefit of the FD-SOI technique the silicon film thickness and its homogeneity needs to be tightly controlled during wafer and chip manufacturing. Any thickness variation makes the low voltage operation worse by dictating to run the chip at the voltage level of the worst transistor. We present a new metrology tool dedicated to this purpose. The system combines the extreme thickness resolution and accuracy of sub-Angström range with the needed high spatial resolution and a high volume wafer throughput, as it is inevitable for a production control system. The lateral resolution can be adjusted by recipe parameters to the user needs from full wafer overview to sub-micron resolution. We use an all optical method with special emphasis on high reliability and reproducibility. Results of the tool performance checks like reproducibility and accuracy are reported. Measurement results are presented for a range of production wafers. The tool is a new part of HSEB's field proven modular tool platform for fully automated inspection and metrology applications. Thus, it can run fully automatic as well as in a manual mode and incorporates all automation requirements in a SEMI conform manner.

Biography
Dr. Bernd Srocka studied physics and obtained his PhD in semiconductor physics at the Technical University Berlin in 1993. Starting with his diploma and thesis he was all the years dedicated to semiconductor metrology and processing physics as well as to equipment development for the semiconductor industry. Since 2004 he has been working for HSEB in several positions. Today he is the director of the HSEB R&D department.

China Opportunities and Challenges

Jones, Handel
FOUNDER AND CEO
IBS, Inc.

Abstract
The semiconductor industry is entering a new age. China is committed to supply up to 40% of the total consumption in China by 2025, which means revenues of Chinese semiconductor companies will be $134B compared to $17B in 2015. To achieve this goal, there is the need for access to a wide range of IP, the ability to develop complex semiconductor products, and building up the full supply chain (includes wafer fabrication, packaging, and testing). It is likely that there will be acquisitions of U.S. and European semiconductor companies, and joint ventures will be established. Governments, financial institutions, and major cities in China are active in stimulating the growth of the electronics industry in China. There has been some success to date, but the growth rate of the semiconductor supply chain in China has been slower than expected. New approaches are expected to accelerate growth. Europe has to be prepared for the changes that are being implemented in China, which is the evolution from Brawn to Brain (China Daily article by Handel Jones.) There are major competitive threats to Europe along with large market opportunities. While GDP growth in China is slowing, there is also an acceleration into the high technology phase in China. - 5G: China is attempting global leadership. Investments currently above $2B per year. - IoT: Increased investments in China. Building of full supply chains including MEMS sensors. - Automotive electronics: Large investments for building supply chain, including ADAS. - Other areas: Full supply chain for LED lighting, UHD flat-panel displays, super computers, optical communications (gives access to advanced technologies and manufacturing-intensive industries). The China of 2020 to 2025 will be very different from the China of 2010 to 2015, and it is important to have good understanding of the key factors for growth in China. Europe can obtain many opportunities from having creative strategies to actively participate in the emerging China.

Biography
Has been in business for over 26 years Previous experience in managing 1.5K+ engineers at Rockwell International, which included avionics, communications, and semiconductors. Strong emphasis on communications Interface with most global leaders in electronics industry, with customers in U.S., Europe, South Korea, Japan, Taiwan, China, India, etc Interface and support for major global corporations such as Intel, Qualcomm, Broadcom, Microsoft, Seagate, Samsung, SK Hynix, Sony, Toshiba, Apple, Cisco, Huawei, IBM, Fujitsu, Canon, Hitachi, Renesas, TSMC, Globalfoundries, SMIC, STMicroelectronics, NXP, TI, ARM, and others Participated with French Government on their advanced technology initiatives Interface and support for financial institutions such as Goldman Sachs, Carlyle, Blackstone, CitiGroup, Warburg Pincus, Walden, KKR, Morgan Stanley, Credit Suisse, BNP Paribas, Bain Capital, Bank of America, TPG, and others Involved with advanced technology concepts, including smartphone, IoT, and other high volume devices. Active in supporting companies in high performance infrastructure applications Strong expertise in China. Latest book is called China's Globalization (How China Becomes No. 1). Published business book entitled Chinamerica (McGraw Hill) Forbes blog contributor, China Daily articles, Global Times editorials, Wall Street Journal, and others Involved in number of due diligence projects on number of IPOs Support for strategic initiatives for number of global technology leaders

Quantum random number generator using a mobile phone's CMOS camera

Sanguinetti, Bruno
Product Manager
ID Quantique

Abstract
Random number generators (RNGs) play an essential role in the generation of cryptographic keys. Purely mathematical (software) RNGs do not guarantee the uniqueness, and therefore the security, of the keys, so that in cryptographic applications it is essential to use RGNs based of physical principles. The randomness of certain quantum mechanical effects can be demonstrated from first principles, and the entropy generated by these effects can be precisely quantified, making quantum random number generators an attractive solution. These however have typically relied on specialized, power hungry, and "large" hardware devices, such as single photon detectors. Here we show that it is possible to generate random numbers of a quantum origin using a standard mobile-phone camera. Besides its economical and practical advantages in mobile applications, this method allows for a more precise estimation of the entropy than previous methods, and is resilient to a larger class of attacks.

Biography
Bruno Sanguinetti has studied for his PhD in cavity quantum electrodynamics at the Universities of Sussex and Leeds (UK), and at the Max Planck institute for quantum optics (Germany). After his PhD, Bruno joined the group of applied physics of the university of Geneva. Now Bruno works at the company ID Quantique where he is product manager. His interests are in applied quantum photonics, sensors and detectors.

Development of ultra high speed on-chip Optical Interconnects by state of the art Si etching process and Nano Imprint Lithography

Charania, Sujay
M.Sc. Student
IHM, TU Dresden

Abstract
The computing power of the chips is progressively increasing, which makes the speed of the conventional interconnections lag behind. Experts are adding more and more active devices by incorporating various 3D chip integration techniques (e.g. C2C, C2W, TSVs inclusion, etc.). So, to get maximum advantage of the speed of active devices, the interconnects must catch up with the speed and optical interconnection link could be the best choice for this. Within the project of '3D Chip Stack Intraconnects' at TU Dresden, the possibility of fabricating an optical connection link between two (or more) active layers of the chip is explored. Depending upon the TSV sizes and connection link possibilities, a desired shape of the connection is carved on the Si. A state of the art etching process, yielding positive profiled structures, is developed in order to achieve variable angles depending on the requirement of the connection shapes of respective TSVs. The etching process is the combination of various types of dry plasma etching processes. It was optimized for desirable angles and low surface roughness to improve the efficiency of the final optical interconnection link. This Si imprint master is then used to develop polymer stamps. Using these stamps, pre-fabricated air TSVs can be filled to provide ultra high speed data, of the order of a couple of hundreds of Gbps, interconnection link. The final optical link is prepared under vacuum using Nano Imprint Lithography and transparent polymer SU-8. A set of simple SU-8 filled TSVs were examined for their optical signal carrying capacities and the primary results have shown excellent connectivity (loss of less than 2 dB). Inclusion of photonic devices and polymers for the interconnects and waveguide last process, gives a novel approach to the conventional (C2C, C2W, etc.) fabrication techniques. This More-than-Moore approach is driving advanced packaging towards improved efficiency, high yield, low parasitic and inexpensive solution.

Biography
The author's full name is Sujay Ashok Charania, was born on 27th July, 1990 in Ahmedabad, India. He achieved his Bachelor of Engineering in Electronics and Communication in 2011 with distinction from Gujarat University, India. After that the author moved to Germany to work on his area of interest and joined M.Sc. in Nano Electronics System at TU Dresden. He has worked on a project titled "Design of a compression system using ADV212 in raw pixel mode" at SAC-ISRO, India. At TU Dresden he has worked on '3D Chip Stack Intraconnects' project as a student research assistant. At present he is working on the development of Laser diode drivers, which will be used with the structures discussed in the paper to prepare very high speed on-chip optical interconnects.

Monolayer controlled deposition of 2D transition metal dichalcogenides on large area substrates

Delabie, Annelies
Professor
Imec

Abstract
Two-dimensional (2D) transition metal dichalcogenides (MX2, with M a transition metal of group 4 - 7 and X a chalcogen) have versatile properties that complement those of graphene. Depending on the metal and chalcogen, these 2D materials exhibit insulating, metallic, semi-metallic or semiconducting properties. The anisotropy in their electrical, chemical, mechanical and thermal properties is of interest for applications ranging from nano-electronics to sensing and photonics. MoS2, MoSe2, WS2, and WSe2 are 2D semiconductors that attract significant interest for ultra-scaled nano-electronic devices because of their large band gap values, low dielectric constants, lack of dangling bonds and structural stability. In contrast to graphene, the presence of a band gap in MX2 allows fabrication of transistors with high Ion/Ioff ratio. Further exploiting the potential of MX2 and enabling integration in nano-electronic devices requires the development of deposition techniques for MX2 that provide monolayer growth control on large area substrates. Next to Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD) is a promising technique because its deposition principle ensures growth control at the atomic level on large area substrates. We will discuss the CVD and ALD of WS2 from the WF6 and H2S precursors. The deposition of WS2 on Al2O3 substrates is enabled at low temperature (300-450ºC) by either Si layers or H2 plasma as reducing agents. The 2D structure of thin WS2 layers (2-3 monolayers) is obtained at low deposition temperature without using a template or anneal, as indicated by Raman Spectroscopy and Transmission Electron Microscopy. Nevertheless, the layers are polycrystalline with a rather small grain size. The orientation of the WS2 basal planes is parallel to the substrate at 300ºC and depends on temperature. We will discuss the need for a better understanding of the nucleation and growth mechanisms, as this will enable improvement of the crystallinity.

Biography
Annelies Delabie obtained a master degree in chemistry in 1997 and a PhD degree in science in 2001 from the University of Leuven (KULeuven) in Belgium. In 2001, she joined imec, research institute for nano-electronics and nanotechnology in Belgium. As a senior scientist, she investigates the fundamentals and applications of thin films and their deposition techniques, with a focus on Atomic Layer Deposition (ALD). Since 2012, she is also appointed associate professor at the chemistry department of the KU Leuven, where she started the research group "Nano-engineered Thin Films". She is a member of the American Vacuum Society (AVS) ALD conference committee and the ALD applications symposium of the Electrochemical Society. She is (co-) author of 9 patents and more than 160 scientific publications in peer reviewed journals, with an h-factor of 30.

Beyne, Eric
imec fellow & 3D System Integration Program Director
Imec

Biography
Eric Beyne obtained a degree in electrical engineering in 1983 and the Ph.D. in Applied Sciences in 1990, both from the Katholieke Universiteit Leuven, Belgium. Since 1986 he has been with IMEC in Leuven, Belgium where he has worked on advanced packaging and interconnect technologies. Currently, he is imec fellow and program director of imec's 3D System Integration program. Since the early 90's he has been involved in multi chip modules and integrated passive device technologies for miniaturizing electronic systems and realising SiP solutions. Around 2000 these developments were focussed on ambient intelligence, a predecessor for what is currently known as IoT devices. In the meantime 3D integration technologies (TSVs, Die and wafer stacking) have been developed, enabling even denser 3D and SiP integration for IoT devices.

IOT driven innovation and 'smart' R&D flows in imec's nanoelectronics platform

Lauwers, Lode
Vice President
IMEC

Abstract
The next new big thing is the 'internet of everything'. Market studies predict that by 2020 50 billion devices will be connected. The internet of everything can drive innovation in every industry: agriculture, logistics, food, industrial monitoring, healthcare, automotive, energy... It has the potential to stimulate economic growth in Europe as we have many assets to connect the unconnected. To realize this internet of everything, business models will need to shift from the traditional paradigm putting more pressure on building the right eco-systems and adopting open innovation models. Clearly a value-add eco system will have different players from the electronics industry, which will manufacture the sensing devices, up to the communication and cloud data storage industry, which will handle data transmission, storage and processing, to the service companies, which will valorize the data either through processing or by selling to a third party. In Europe we do have many valuable assets driving this industry: we are strong in system development, materials and equipment and we stimulate innovation with our world-leading research centers. These research centers act as a catalyst and provide a neutral ground for collaboration opportunities, having an impact on the different segments of the revolutionizing internet of everything industry. There is an opportunity for new collaborations in a combination of new enabling devices, new architectures, and new memory technologies, all guided by Ultra low power consumption and lowest cost considerations. How will this affect our roadmaps? Furthermore, all R&D will be driven by an increased manufacturing efficiency focus. Examples will be given on how to set up 'smart' and 'distributed' R&D flows which benefit from enabling process steps and demonstrate new capabilities at system level.

Biography
Lode Lauwers was born in St.-Joost-Ten-Node, Brussels, on November 14, 1962. He has a degree as Master in Electro-technical and Electronics Engineering (1985) and Ph. Doctor in the Applied Sciences (1993). He is Vice President Business Development & Sales in IMEC, the nanoelectronics R&D Center in Leuven, Belgium. He oversees Corporate Business Development of IMEC Business Lines, CMOS scaling, Smart Systems and Energy, with a shared responsibility over sales with VP world wide Account Management. In the area of CMOS technology, he is responsible for IMEC business offerings, covering collaborations with leading IC manufacturers and equipment and material suppliers worldwide. Since he joined IMEC in January 2005, he had various roles in IMEC's technology business and sales field, a.o. as Director Strategic Program Partnerships, with main focus on IMEC's core CMOS program, and having Regional Sales responsibility for IMEC business in Japan. From 2000 to 2004, he was general manager of ASIC design house Easics NV, a wholly-owned subsidiary of TranSwitch Corporation, a provider of Application-Specific Standard Products for the telecom industry. From 1992 to 2000, he was sr. scientific advisor in IWT, institute for the promotion of Science and Technology in Flanders, where he coordinated and advised for government funding in local and European cooperative networks in micro-electronics and telecommunications. From 1985 until 1992, he was also with IMEC, as researcher in the area of MOS device modelling and simulation, which was also the subject of his PhD in 1993.

Comparison of EUV single exposure vs 193i multiple pattering for N10 BEOL

Wilson, Christopher
BEOL R&D Integration Team Leader
imec

Abstract
Advanced scaling requires innovative pattering solutions to meet half pitch requirements. In this work we compare the pattering integrity results of N10 product like structures using EUV- and 193i-Lithography. Traditional 193i based lithography requires multiple litho etch (LE) or pitch doubling techniques to reach sub resolution pitch. These however add additional films and steps in the pattering process, and introduces CD and overly variability. EUV offers the possibility of single print for advanced nodes with a simplified process. However EUV introduces pattering selectivity and uniformity challenges. The process flows, complexity and results will be presented for EUV single exposure, 193i multiple Litho Etch (LE3), and 193i Spacer Assisted Double Pattering (SADP+Keep).

Biography
Christopher J. Wilson is the BEOL R&D Integration Team Leader and Technical Lead in the Logic Technologies Department, at imec, Belgium. His team is responsible for projects covering advanced node integration, patterning exploration, EUV insertion, advanced and alternative metallization, novel low-k investigation, alternative integration, CPI vehicles, and incite road mapping. He received the PhD degree from Newcastle University, United Kingdom, and MBA degree from the Vlerick Business School, Belgium. Christopher's previous roles at imec include Project Manager and Senior Scientist, where he led a broad range of projects, including: 28nm/22nm/10nm/7nm node low-k dual damascene integration, low-k spin-on polymer evaluation, and synchrotron material analysis. He led imec's first EUV BEOL demonstrator on the alpha-demo tool and has been subsequently involved in imec EUV activates. He is active in the work of imec's Advanced Litho Program, Nano-Interconnect Program and the Beyond CMOS Program.

A big data analysis of IoT trends in Europe

Christie, Phillip
Principal Scientist
imec

Abstract
As both an international research institute and a provider of silicon foundry access to Small and Medium Enterprises (SMEs), imec has a unique perspective on the European high tech landscape. In addition to providing foundry access and support, the research culture at the core of our organization leads us to quantify and analyze both business and technology trends in new emerging markets that we serve. Our role as a silicon broker gives us access to a fully indexed business database of over 300 companies going back ten years and a technology database containing over 3 TBytes of information, covering 10 foundry technology generations from 500nm to 16nm. Perhaps more importantly, the high degree of segmentation and fragmentation we observe in our high growth SME application domains, means that the business and technology trends we observe may be used as leading indicators. In this presentation we will report the results from a new imec data-mining initiative to combine business intelligence with technology analysis to quantify leading trends in SME IoT markets.

Biography
After seventeen years as a professor of Electrical and Computer Engineering at the University of Delaware, USA, Phillip Christie joined Philips research in 2002, leading teams integrating low power chip design and fabrication processes. In 2009 he joined imec and currently leads a team responsible for business and technology strategy for the IC-link division, which provides SMEs and universities with access and design support for advanced electronic and optical semiconductor technologies.

Semiconductors as a key enabler for the transition of the automotive industry

Ploss, Reinhart
CEO
Infineon

Abstract
The automotive industry has great opportunities which require tackling significant challenges. Our society is constantly growing and so too is industrialization, leading to an increased demand for mobility. At the same time, we need to find ways to provide this mobility in a clean and energy-efficient way. New technologies like the electrification of the drive train and (semi-)autonomous driving are key enablers to solve these challenges. Electronics has been the driver for innovation in cars in the last years. On the way to the highly efficient and autonomous car it will play an even more important role. Systems and components have to be extremely reliable at affordable cost. This will drive new ways of development, but will also have an impact on manufacturing. Connectivity will enable further options. Overall traffic management can help increase fuel efficiency with a smoother traffic flow. There are high expectations on emerging services and business models. However, IT security will become a major challenge. Automotive is one of Europe's key industrial strengths. To maintain this position a significant increase in competency is needed - both in the traditional areas and also in completely new fields.

Biography
Reinhard Ploss joined Siemens/Infineon in 1986, working in Munich as a process engineer with focus on chip manufacturing. In 1992 he moved on to Villach, Austria, where he started in chip manufacturing and took over the position as Head of Technology in 1993. He returned to Munich in 1996 and took charge of the Power Semiconductor Business Unit, focusing on development and manufacturing. In 1999, Reinhard Ploss was appointed Head of the Industrial Power Business Unit as well as President of eupec GmbH Co. KG, a subsidiary of Infineon. In 2000, Reinhard Ploss took over as President of the Automotive & Industrial Business Group of Infineon. From 2005 on, he held responsibility for manufacturing, development and operational management in the Automotive, Industrial & Multimarket Business Group. In June 2007, Reinhard Ploss was appointed to the Management Board of Infineon, with responsibilities for manufacturing activities. In addition, he became Labor Director and Head of Research & Development. He remains responsible for these three areas to the present day. Since October 1, 2012, Dr. Reinhard Ploss is Chief Executive Officer of Infineon Technologies AG.

Fab performance increase by using solver solutions

Werner, Sebastian
Senior Manager Industrial Engineering
Infineon Dresden Technologies GmbH

Abstract
Who does not know the complexity of WIP flow management in a semiconductor fab? There are many problems to be solved: Primary resource allocation is subject to different tool speeds, dedication, secondary resource availability, setup and batching constraints, inappropriate recipe sequences, process capability, time limits, due dates, lot transport, priority classes and others. Where state-of-the-art dispatching is getting to its limits, math can help. Solvers are becoming more powerful and nowadays able to solve complex problems as described before. The advantage is obvious. Instead of making dispatching rules, fitting to a certain operating point, mathematical approaches can calculate an optimal schedule regarding a target function under different conditions. Infineon applies solver solutions to different machine groups, where optimized schedules have a valuable impact on performance. Of course, this is where complexity is high in areas like litho, batch tool groups, test, and implant. By classifying the above mentioned constraints, one can state: The constraint classes are recurring in each single problem, but in different combinations. This helps us to create a flexible framework holding a model kit applicable to all kind of problems. Each application uses the same model and the constraint classes are enabled in combinations as needed. The results are convincing, efficiency increase by two-digit percentage points is visible. The presentation will give an overview of solutions to point out different aspects like performance gains and levers, generic model setup, data quality, shop floor execution, automation, and system reliability.

Biography
Sebastian Werner is Site Head of Industrial Engineering at Infineon's Dresden fab, where he is mainly responsible for equipment asset productivity. He is holding a degree in electrical engineering from several universities in Germany and abroad. After product design in medical engineering he changed to manufacturing simulation and optimization with a wide experience in research and industry in numerous manufacturing branches before he moved to Infineon. Contact him via sebastian.werner@infineon.com

Efficient Energy Conversion using Power Electronics

Schulz, Martin
Principal, Application Engineering
Infineon Technologies

Abstract
Growing energy consumption is a challenge for all nations around the world and there are two options to cope with this challenge. Increasing the amount of available energy by setting up more power plants is the most obvious one. Though typically plants using fossil fuel or nuclear power have the higher power output, plants based on renewable energies have to be favored to reduce the impact to the environment. Power electronic systems to convert the energy harvested into grid-compatible form have to be used, directly influencing the plant's efficiency. Complementary, an increase of efficiency in energy conversion, transmission & distribution and consumption can contribute a similar share. On its way from generation to consumption, energy passes semiconductors for a multitude of times making this technology a true gateway to efficiency improvements. The presentation will give an insight on what efficiency improvements mean in terms of saving energy and reducing greenhouse gases on a national and global scale along with the current developments in power electronic device technology.

Biography
Martin Schulz is with Infineon Technologies since 2005. In 2011 he joined the application engineering group. His responsibilities are in the area of industrial battery chargers and electrified commercial and agricultural vehicles (CAV). Furthermore, thermal management is his field of expertise. Martin Schulz holds a Dr.-degree in electrical engineering, gained at the University of Siegen at the Department of Power Electronics and Electrical Drives. He is a Senior IEEE-Member.

The Right Security for the Internet of Things

Spaenkuch, Juergen
Division Vice President Chip Card & Security (CCS), Infineon Technologies AG
Infineon Technologies AG

Abstract
Data Security and system integrity are prerequisite for successful implementation of Industry 4.0, the application of "Internet of Things" (IoT) concepts and technologies in industrial settings. Especially, as with smart factories and connected industrial production, economical assets such as machinery, Intellectual Property as well as product and service quality are at stake and hence the overall competitive ability of the business itself. For example, advanced factory automation uses networking to integrate the entire supply chain from supplier to customer to enabling Lot-Size-1 or customized production. In such a connected environment, identity of machines and personnel must be verified and communications must be protected end-to-end to make sure that system integrity is maintained. Therefore, all elements of the system from customer to supplier must be identified and secured adequately to protect systems and components from unauthorized access, attacks, fraud and sabotage. Several attempts have been made in the past to apply purely software-based security solutions. Unfortunately, software - due to its nature - bears several significant weaknesses. Software is written code, and code can be read and analyzed. And once it is analyzed, it can be modified to the requirements of an attacker and system integrity can be broken. However, software can be protected by hardware: hardware protects the processing and storage of code by using encryption, fault and manipulation detection, and by providing secure data storage. This has been proven by extensive experience from the areas of trusted computing and the use of secure elements in mobile phones. Following the same principles, hardware-based security tailored to industry-specific requirements provides a trust anchor for digitized and connected industrial production and helps to secure physical as well as intellectual property.

Biography
Juergen Spaenkuch Division Vice President Chip Card & Security (CCS) Infineon Technologies AG - born on April 22, 1969 - in Rastatt, Germany - married, 2 children Juergen Spaenkuch studied at the University of Applied Sciences in Karlsruhe from 1991 to 1997 and holds a Master degree in informatics. He started his professional career at Siemens AG in the Memory Products division of the semiconductors business unit, which later became Infineon Technologies AG. In the years thereafter, Mr. Spaenkuch held various positions in logistics, technical marketing and product management and also had managerial responsibilities for the Automotive and Chip Card Divisions of Infineon. In 2008, Juergen Spaenkuch became the head of the Embedded Security product segment of the Chip Card Division. Since July 1, 2011, he is the Vice President and General Manager of the business line Platform Security within the Chip Card & Security (CCS) Division.

Automotive multi-core architectures in the tension field of autonomy and hybridization

Steurich, Bjoern
Sr. Automotive System Manager
Infineon Technologies AG

Abstract
Automotive industry is today mainly driven by three mega trends that can be described by the buzzwords electrification, automated driving and connectivity. The 1st includes all forms of electrification of belt driven mechanics, from auxiliary pumps till fully electrical vehicles, which is mainly driven by the ever increasing emission and fuel consumption regulations. The progress towards the 2nd thereby involves in several steps (starting with basic capabilities as e.g. traffic jam assistance). Even if the fully self-driving vehicle might need some decades till market maturity, the possible customer benefits are compelling (less traffic victims, additional fuel savings, reduced traffic congestion and a potentially increased productivity of the occupants). The latter is certainly the main motivation factor for the engagement of companies like Google and Apple and closely related to the last megatrend - connectivity. Connectivity includes the integration of consumer devices (tablets & smartphones), the connection of the car to the cloud (e.g. for remote diagnostics and potential software updates) as well as the car to car and car to infrastructure communication. As a result, we see an evolution of the entire board net architecture away from distributed control (incl. almost one electronic control unit per mechanical function) to distributed computing with functions clustered in domains and connected by high-performance networks. Besides a considerable increase of the required computing performance, solutions are required to keep the autonomous car operational in the case of an error. Apart of the advantages of opening the car to the cloud, it also increases the attack surface so that a combined safety and security risk analysis will be required (incl. a potential extension of the ISO26262). Based on all these considerations an automotive multi-core architecture will be presented taking those requirements into account through innovative system on chip solutions.

Biography
Dipl.-Ing. Bjoern Steurich studied General Electrical Engineering at Saarland University. He started his career in 1995 at Siemens AG as a CMOS-ASICS designer. Changing in 1997 to system engineering, he worked as microcontroller expert on a couple of customer projects (beyond others on an airbag ECU with Siemens Automotive). After his change to product marketing, he was responsible for three generations of TriCore 32bit Microcontroller and from 2006 to 2009 for Infineon's regional automotive Microcontroller business in the US. Since his return from US, he is working in Infineon's Automotive System Group focusing on powertrain, security and connectivity.

Vock, Stefan
Principal Test Engineering
Infineon Technologies AG

Biography
Stefan Vock is with Infineon Technologies. Dr. Vock has been in the Automated Test Equipment (ATE) industry for more than 20 years. He worked in different positions for ATE vendors, for design houses and integrated device manufactures. Further, one of his major areas of research and focus is on semiconductor product and test engineering, defect screening concepts, test for reliability methodologies and innovation targeting quality and efficiency. Stefan Vock was awarded the degree Doctor of Philosophy May 2015 for his thesis about "An Approach for Addressing Challenges and Quality Robustness in Test Engineering for Semiconductor Manufacture".

Future requirements on semiconductors as enablers for automotive innovation

Gutheit, Tim
Sen. Dir. Technology Innovation
Infineon Technologies AG

Abstract
Infineon Technologies AG is a world leader in semiconductors. Infineon offers products and system solutions addressing three central challenges to modern society: energy efficiency, mobility, and security. Microelectronics is the key enabling technology for major breakthrough innovations in the automotive arena which we will see on the road in the next 3..10 years. With its broad portfolio of automotive semiconductors ranging from sensors, MOSFET switches, protected switches, ICs and modules for conventional and electrical drivetrain and microcontrollers Infineon is well prepared to shape the future of automotive electronics together with our customers and partners. The complexity on system level is driven up in several dimensions at the same time as data capture and processing, highly reliable power electronic, high levels of security and functional safety. The presentation will selectively cover some of the emerging applications in automotive as autonomous driving, advanced driver assistance systems and networked cars. We will provide an insight into new requirements which the semiconductor industry is facing here and into the approaches Infineon is taking to tackle these challenges.

Biography
Dr. Tim Gutheit is Senior Director of Technology & Innovation of Infineon's Automotive Division. In this function he is responsible for the innovation and predevelopment strategy of that division , which includes roadmaps for technology and development methodologies, the global development center footprint and competence development of the R&D staff. From 2008 to 2011 he was leading the development group for Automotive Power Semiconductor Platforms in which wafer and package technologies and design kits for automotive power ICs were set up. From 2005 to 2008 Tim Gutheit headed Infineon's productline for high integration IC for use in automotive powertrain and safety applications. Tim Gutheit started his career 1992 at Daimler Benz central research lab, working on materials for high temperature electronics before moving on to Siemens Semiconductor (later Infineon Technologies) where he held numerous positions in R&D and Operations. He holds a diploma and Ph.D in physics of the Technical University in Munich, Germany, and is inventor of 12 patents.

Enhanced Equipment and New Processes as Enabler for Power Technologies on 300mm Substrates

Engelhardt, Manfred
Senior Principal Plasma Etch
Infineon Technologies Austria AG

Abstract
Transferring power technologies from 200mm silicon substrates to 300mm provides challenges with regard to substrate materials, process equipment, and unit processes in addition to a similar transfer of standard CMOS. Tight furnace temperature uniformities across the wafers within large wafer batches required severe simulation support. Wafers with polysilicon films on the backside for impurity gettering are so far only available on 200mm. Such films were deposited and analytically assessed. Extremely high doped wafer substrates for manufacturing power devices were not available yet in both sufficient quality and quantity to start 300mm power semiconductor activities and had to be manufactured by epitaxial growth. In addition to severe modifications of the reactors and the provision of the complete infrastructure unit process development is very challenging. Simultaneous achievements of both supreme uniformity of thick epitaxial layers and of the dopant distribution therein is key to allow perfect pattern generation and transfer and hence identical electrical device performance across the wafer until the very wafer edge to take full advantage of the productivity plus. For IGBTs a 5-wafer epi batch tool was used on 200mm to transfer all the tool and process learning for building a 300mm tool. Hereby the main focus was on the reduction of sliplines resulting from non-uniform thermal substrate-susceptor coupling. While critical CDs in high end products differ by almost an order of magnitude between power semiconductors and standard CD driven CMOS technologies, the tolerated CD uniformities are rather comparable. This finally requires plasma etch equipment with all the "knobs" to address wafer center and wafer periphery individually regarding etch rate, profile shape, and CD to achieve lowest center-edge non-uniformities. The work has been performed in the project EPT300, co-funded by grants from Austria, Germany, Italy, The Netherlands and the ENIAC Joint Undertaking.

Biography
Manfred holds a PhD in Solid State Physics from 1984 from the University of Regensburg, Germany. He is a 30-year semiconductor industry veteran. In processing of electronic materials he held several positions at Siemens Semiconductors, Infineon Corporate Research, Infineon Memory Products, and Qimonda on the various frontend sites. In his current position with Infineon Austria he is owner of both the equipment and process roadmaps for plasma etch processes for Infineon worldwide. He has pioneered plasma etching of high-aspect-ratio structures and plasma damage assessment methodologies. He has authored and co-authored more than 150 peer-reviewed papers and 90 invention disclosures with more than 50 patents and delivered about 100 presentations on international conferences. Manfred is member-at-large and Fellow of the Electrochemical Society Inc. (ECS) and co-organizer of the bi-annual Plasma Processing Symposium of the Society.

ECSEL-project PowerBase

Pairitsch, Herbert
Senior Manager Technology & Innovation
Infineon Technologies Austria AG

Abstract
PowerBase stands for "Enhanced substrates and GaN pilot lines enabling compact power applications". After years of research and first products on the market GaN on silicon devices still need R&D efforts to address application requirements in a broader range. Especially when high power density is a value, the performance of GaN-devices will generate a steadily growing market. Nevertheless the price performance ratio will determine the growth rate of this market. Therefore the ECSEL Pilot line project PowerBase targets to lay the foundation for a stable and achievable high volume production of GaN-devices. The bullet-points below give an impression on the holistic approach along the entire value chain ranging from base-materials to high performance applications. * GaN on carrier (Si and other advanced materials) technologies will provide major enhancements and cost competitiveness for novel power semiconductors focused on e-mode (= normally off) devices * Expanding the limits of silicon based power technologies in leading 300mm wafer diameter will improve the current limitations in on-resistance of Trench-Power-MOSFET and IGBT devices and extend the capabilities of already installed 300mm pilot lines * Pushing GaN power device technology and its superior performance towards the absolute GaN limit compared to current approaches taken * Setup pilot production line for fully processed GaN on carrier power semiconductors in leading 200mm wafer diameter coexisting and compatible with high volume CMOS power manufacturing facilities * Setup pilot production line for chip embedding (packaging) for advanced GaN based power products * Prove target achievements in key demonstrators applications in the "smart energy" domain addressing compact power advancements together with leading European systems suppliers * Reliability and quality as key enabler to gain market acceptance for these new technologies.

Biography
DI Herbert Pairitsch holds a degree in electrical engineering from the Graz University of Technology, from where he graduated in the year 1985. In 1986 he started his career at Infineon Technologies Austria AG (former Siemens HL) and held leading positions at various manufacturing and development departments. Since 2014 he serves as divisional Head of R&D Funding PMM (Power Management & Multimarket). His responsibilities include the coordination of national and international research projects in the context of energy efficient electronics like PowerBase (ECSEL Pilot line project).

3D Structuring Techniques as Enablers for New MEMS-based Devices

Kautzsch, Thoralf
Sensor&MEMS Development
Infineon Technologies Dresden

Abstract
This year, we celebrated the 50th anniversary of Moore's Law. Over the past decades, the development of the semiconductor industry has been driven by miniaturization of standard devices. In parallel, the demand for sensor devices undergoes a dramatic change - not only in terms of volume and average selling price, but also with respect to requirements of further miniaturization. As an example, in a few years, a package height for pressure sensors in the order of one millimeter will not be accepted anymore by most of mobile device providers. The discussion on the choice "system in package" or "system on chip" is not only driven by production costs anymore. Furthermore - in some cases, the miniaturization of micro mechanic devices is the door opener for CMOS integration by also reducing production cost of the system: New versions of MEMS resonators in the 10MHz to 100MHz range are smaller than a single bond pad - an integration might save chip area. On the other hand, new sensors for ambient radiation and chemical analyses will capture new markets. In this contribution, a discussion on the link of structuring techniques to system design is provided. Taking three practical examples, the consequences of technological concepts and the choice of sensing techniques are presented. It underlines the need of continuous concept reviews even of mature device and product groups such as pressure sensors, acceleration sensors or ambient light sensor systems.

Biography
Thoralf Kautzsch coordinates pre-development and innovation activities in the field of sensor and MEMS solutions at Infineon Technologies Dresden. In 2003 he received his PhD from the Technical University of Berlin. Since 2003 he has been with Infineon Technologies Dresden, his activities covered embedded flash integration, development of power devices and investigation of new sensor concepts. His current interests include MEMS-based sensors, optoelectronic devices and sensing systems based on infrared spectral analysis.

Pyper, Oliver
Senior Manager Innovation Projects
Infineon Technologies Dresden GmbH

Biography
Dr. Oliver Pyper holds a Diploma in chemistry and a PhD in natural science. After his studies at the Technical University of Berlin, he joined Infineon Technologies Dresden in 2000. Until 2005 he was responsible for a module of the DRAM-technology and managing several projects for optimising current technologies and fast ramp of new technologies. In 2005 he changed to production, managing several projects to improve the manufacturing landscape. Since 2007 he is also responsible for managing innovation projects within R&D- and pilotline-projects.

Innovative Interconnects in System in Package Drive Application

Roemer, Bernd
Senior Principal
Infineon Technology AG

Abstract
Infineon Regensburg is one of the leading locations worldwide for innovations of assembly and packaging. The investigation of innovative interconnects is one of the core competencies. We will provide an overview of recent developments plus an outlook to the future. In 2004 Infineon introduced the TSLP package into the market. This was not only a thin package, but also a package that allowed 4 times smaller pads compared to a VQFN package. The small contact pads of the TSLP allowed improved heat dissipation and improved signal integrity. IFX Regensburg was the location where chip embedding technologies were investigated and introduced in the market. The first example is the eWLB technology, where chips were embedded into a mold compound. The eWLB fan-out assembly and packaging technology was introduced into market for mass production in 08/09. This was the first time that a redistribution layer was applied to a molded chip to get a fan-out routing. Meanwhile we extended this eWLB technology further towards 3D system integration. Work included introducing integrated antennas TEV (Through Encapsulant Vias) and the EZL (embedded Z-line) interconnect technologies. A novel package technology with innovative interconnects was investigated and developed also for power devices e.g. for DrBladeTM. This package technology was a package without wirebonds and flipchip bonds. With DrBladeTM, which includes the innovative packaging technology, Infineon is among the 4 finalists of the innovation award of the German Economy 2015 In future low parasitic interconnects are required for optimum signal integrity as well as for unnecessary heating. A coherent development taking into account chip, package, and board is needed. We present examples that summarize the outstanding capabilities of various packages and corresponding interconnect types, e.g. the chip embedding Technologies to demonstrate that assembly and packaging is becoming of ever more importance as product differentiator.

Biography
Bernd Römer received his diploma in mechanical engineering and precision engineering from the University of Applied Sciences Giessen/Germany in 1983. He joined Infineeon Technologies former Siemens Semiconductors in 1983. Bernd had various engineering and management positions in the area of semiconductor package / product development, technology & innovation, research & development and production. As Senior Principal Packaging and System Integration he is the leading a Trends & Integration conpepts team within the Infineon Packaging Innovation group. Bernd Römer is an active member in different organizations like ITRS TG Assembly & Packaging, IEC, JEDEC, and JISSO International Council (JIC).

Vacuum-deposited fluoropolymer films for organic electronics

Grytsenko, Kostyantyn
Researcher
Institute for Semiconductor Physics

Abstract
First researches concerned thin polymer film production by decomposition of bulk polymer in vacuum and condensation of chemically active fragments of macromolecule on substrate were made in mid-20th century. Polytetrafluoroethylene (PTFE) was among the first tested polymers. The perflouoropolymer (PFP) films were deposited using various gas phase methods: thermal decomposition, magnetron sputtering, laser ablation, plasma polymerisation and hot-wire chemical vapor deposition. Partially fluorinated polymer (FP) films were deposited by gas phase methods and wet methods as well. Recently the thin FP films found several industrial applications. They include film applications both in traditional domains like antifriction and protective coatings and in high-technology devices: barrier, dielectric, aligning and protective layers in organic light emitting diodes, organic field effect transistors, sensors, optical waveguide layers, etc. For example, the vacuum deposited PTFE thin (20 nm) buffer layer was used in organic light emitting diode, developed in South Korea. The quantum efficiency of devices was improved about twice. The PFP films were used in organic field-effect transistors as aligning, dielectic and protective layers. For advanced applications the PFP films, filled with metal nanoparticles or/and organic compounds are designing and studying. PFP, filled with silver and gold nanoparticles, were tested for biocide coatings and plasmonic sensors. We developed the special method of deposition of PTFE films in vacuum, which allows co-deposition with organic dyes. Produced dye-filled PTFE films revealed extreme stability of the optical properties under environment actions. Dye-filled PTFE films were used as laser recording media for super-high density archive storage and optical reversible media. PTFE films, filled with both dye- and metal nanoparticles, are using as optical sensors for aggressive compounds.

Biography
Dr. K. Grytsenko was born, got education and started research in Ukraine. He was among the persons, who pioneered research in the field of formation of soft condensed matter in vacuum and its application in optoelectronics since eighties of the 20th century. He employed all gas phase deposition methods: physical vapour deposition, chemical vapour deposition including the plasma enhanced, laser evaporation, ionisation- assisted deposition of chalcogenide glasses. Various thin films were produced: polymers, dyes, metal-polymer nano-composites before the term "nano-technology" appeared. He worked at: Institute for Problems of Information Recording and Institute of Semiconductor Physics, both of National Academy of Sciences of Ukraine, Metal-Polymer Research Institute of Belarus Academy of Sciences, Technische Hochschule Wildau. His experience includes: - Strategic planning of the design of organic functional films for optoelectronics; - Organization of collaboration between Ukrainian and EU, Ca, USA institutions; - Design of combined deposition methods for molecules with complex chemical structure and nano-composites. Matching organic molecule structure with deposition technology. Organic molecules for self-assembled nano-structures and in multilayered systems. - Technology of PTFE and nano-composite films production were transferred to TH Wildau. Dr. K. Grytsenko published 60 Papers in journals, 110 Conference Reports and 9 Patents.

Internet of Things - the next 50 years of Moore's Law

O'Shea, Rod
EMEA Regional Director IoT Group
Intel

Abstract
Will come soon

Biography
Rod is responsible for extending the reach, benefits, and value of Intel technology into new business areas. This includes solutions embracing the Internet of Things, Network Infrastructure, Smart Manufacturing, Embedded Retail, Consumer Electronics, Transportation, and Energy. Joining Intel 20 years ago, Rod has held a variety of international positions within both Intel's Sales and Marketing Group and Product Divisions, including Chief of Staff for our Mobility Group and Regional Director for our Middle East Turkey Africa Region. Rod holds a First Class Honours Degree in Operational Research and Computing.

Wearable electronics

Moynagh, Philip
VP of Internet of Things Group (IOTG) and General Manager of Intel's Quark Solutions Division
Intel Corporation

Abstract
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Biography
Philip is VP of Internet of Things Group (IOTG) and General Manager of Intel's Quark Solutions Division. Designed in Ireland, the Quark System on Chip and its Software Stack enables us to move past an Internet comprised primarily of connected Computers, Tablets and Phones to an Internet that connects Everything in the physical world (including everyday objects). Widely referred to as the "Internet of Things", this technology is transforming high technology businesses today. Brussels, Beijing and Washington predict that Billions of Things will have built-in Connected-Compute by the close of this decade, and that they will create Trillions of Euro in economic value. Philip's organisation identifies transformation opportunities, translates them into silicon and software architectures and builds real world solutions. Prior to this role, Philip managed multi-Billion-Euro silicon chip fabrication factories in Ireland and the US. He is married to Claire, has three children (Niamh, Ciara and Cian), and lives in Dublin.

Opportunities and challenges for the using big data analytics in factories of the future

MacGearailt, Niall
Process Control Researcher
Intel Ireland

Abstract
The push for productivity improvements in semiconductor manufacturing and the continued technology node shrinking is driving more emphasis on what big data analytics can deliver to the manufacturing operations. Current factories do generate vast amounts of data that is used in the operations of the factories. However over the last decade there has been a huge rise in the amount of data generated and stored. Much of this data is stored out of fear of "missing out" and never analysed and value extracted from it. There have been great advances in new sensing, database storage solutions and statistical and machine learning analytics that have shown what valuable information can be extracted and how that can drive decisions. Bringing a once off analysis project into a mission critical operations environment, and delivering 24x7 analytics that can be relied on to make business decisions, is a whole new challenge. This talk looks at the practical implementation of introducing this kind of technology into semiconductor fabs and gives some use cases of how powerful the results can be.

Biography
Niall Mac Gearailt joined Intel in 2001 as a process engineer in Intel Ireland. In this role he developed and implemented fault detection and process diagnostics solutions using high-resolution sensors. In 2005 Niall moved to a research group developing next-generation process control solutions for Intel. He leads the development and implementation of virtual metrology and plasma diagnostics for Intel worldwide. Previous to working at Intel, Niall worked for Lam Research Ireland as a process technologist and Lam Research US in the R&D department. Previous to this he spent a number of years working for semiconductor fabs, Analog Devices and integrated devices technologies in San Jose California. Niall has over 19 years of experience working in the semiconductor industry. He holds a bachelor's degree in mechanical engineering from University College Dublin and a Ph.D. in electrical engineering from Dublin city University.

Driving Sustainability in a Global Semiconductor Manufacturing Operations

Capraro, Bernie
Research Manager, Silicon Technology
Intel Ireland Ltd

Abstract
Intel Corporation is committed to being a leader in environmental responsibility, from resource conservation to addressing long-term sustainability challenges. Intel's approach to green manufacturing includes, but is not limited to the following - Intel incorporates green design standards and building concepts into the construction of new facilities with a number of Intel's manufacturing facilities being LEED certified. - Intel maintains a multi-site, 3rd party verified ISO14001 registration which evaluates the effectiveness of its environmental management system at its manufacturing sites. - Since 2008, Intel Corporation invested more than $118 million to drive energy efficiency in its operations. - According to U.S. EPA, since 2008, Intel Corporation has been the largest voluntary purchaser of ''green'' power in the U.S.. In addition, Intel has worked with partners to complete solar electric arrays and has installed solar hot water at a number of its manufacturing sites. - Over the past two decades, Intel set aggressive GHG reduction goals and worked with others to drive industry-wide improvements. - Intel works to minimize emissions of volatile organic compounds (VOCs), hazardous air pollutants (HAPs), nitrogen oxide (NOx), and carbon monoxide (CO) emissions. - Since 2008, Intel has recycled more than 75% of the total waste generated in its operations, while also taking action to reduce the amount of waste generated. - Intel set and made good progress towards achieving ambitious 2020 environmental goals. - Intel continues to explore opportunities to design and deliver new technologies to address environmental challenges. This presentation will outline a number of Intel's achievements in the areas of energy efficiency in our operations, Green Building and LEED Certification, responsible water management, and waste reduction.

Biography
Bernie received a Masters Degree in Engineering (MEng) from Newcastle upon Tyne Polytechnic (with Distinction) and has been working at Intel for the past 18 years holding various Engineering and Management roles across the wafer fabrication facilities. Bernie is currently responsible for all silicon nanotechnology research involving Intel Ireland, helping to deliver potential solutions to Intel Components Research for materials, devices, equipment and processing techniques required for the future technology nodes and the continuation of Moore's Law, in collaboration with Research Centres, Academia and Industry across Ireland and Europe. Bernie's semiconductor career spans 28 years, with other Process and Equipment Engineering positions held at Telefunken GmbH (Ge), Nortel/Bell Northern Research (UK/Canada), Applied Materials (UK) and Newport Wafer Fab (UK).

InVisage, the camera in a whole new light

Lacombe, Remi
VP Sales & Marketing
InVisage Technologies Inc.

Abstract
QuantumFilm is a light-sensitive layer of quantum dots that takes the place of silicon, the conventional material used in digital camera sensors. It has 80% quantum efficiency in the visible range and absorbs 8 times more light than silicon in an equivalent thickness. In fact, it's so sensitive that 0.5um of QuantumFilm can detect colors more accurately than a 3um layer of silicon, enabling lower lens height and much thinner cameras. In addition, by changing the size of the quantum dots, we can tailor their sensitivity to specific wavelengths. This means QuantumFilm can be dynamically optimized for a variety of applications, from visible to infrared. Not only that, but the dots' sensitivity can also be turned on and off electronically, resulting in our proprietary global shutter and dynamic zoom mechanisms. The design of the QuantumFilm camera sensor maximizes the film's higher sensitivity by incorporating it in a continuous layer closer to the top surface of the sensor. Thus, the entire area of the pixel is sensitive to light (100% fill factor), and more light can be absorbed faster. Thanks to added room in the silicon circuitry underneath, a significantly higher full well capacity allows more of that light to be stored, which in turn produces images with enhanced details in both dark and bright areas-also known as higher dynamic range. QuantumFilm is a truly remarkable breakthrough, freeing digital cameras from the technical limitations of silicon. You'll see the camera in a whole new light.

Biography
At InVisage, Remi leads the sales & marketing team. He joined InVisage in 2013 bringing 20+ years of international business development and marketing experience with a focus on multimedia and imaging hardware and software technologies. Before InVisage, he was the Vice President of Business Development at DxO Labs where, as an early employee, he created the mobile imaging business, won imaging technology design wins at all major device manufacturers and helped grow the 120+ staff company to sustainability and multi-year profitability. Previously, Remi led several entrepreneurial ventures including CEO of Zandan and co-founder of PAS International. Remi's previous companies also include C-Cube Microsystems, Chorus Systems, and Sun Microsystems. Remi received his MS degree in Engineering Management from Stanford University as well as applied science and engineering degrees from Ecole Polytechnique and Ecole Nationale Supérieure des Télécommunications both in Paris, France.

Embedded passives on low profile Silicon substrate technology for Medical implants, Wearables and Connected Objects

Murray, Franck
CEO
IPDIA

Abstract
Innovation is a "Must" in medical implants, wearables and other connected objects. IPDiA, as a center of excellence, is already deeply involved with the key players of Medical devices. These most recent innovative devices, based upon new implantable electrical stimulation technologies, are adopting these Silicon based technologies, to enhance the "performiniaturization" (a word invented by IPDiA). On the performance side, design flexibility, low leakage current, extended life time and the suppression of burn in tests are making the differences. As a reminder this technology is also selected by the downhole players for its capability to withstand temperature of 250°C fduring 12 000hrs as well as by aerospace companies. On the miniaturization side, differences consist in the ability to be delivered with a very low thickness as well as innovative form factors for wearables and implants. This presentation will concentrate on the technology and will be illustrated by several examples of solutions with innovative shapes, heterogeneous stacks with different form factors.

Biography
Franck Murray is presently the CEO of IPDIA. IPDIA is developing, manufacturing and selling Integrated Passive Devices. IPDIA has 120 employees. Since its start in 2009, IPDIA has a worldwide commercial presence and sells 90% outside Europe. Franck got his Engineer Degree from Ecole Centrale de Paris in 1984 and an MBA at ESSEC (Paris) in 2003. He has also a PhD in Physics. After his PhD, his first experience was with Philips in the development of LEDs. This first experience led him to create a start up in Material Analysis and then move to a position of CTO of a start up in the field of optical disk. He came back to Philips in 1996 (becoming NXP in 2006) to occupy various positions in Operations in Semiconductors Wafer Fab. He moved to Corporate Innovation and R&D in 2000 with the assignment to develop new technologies and design tools and find new ways to miniaturize electronic devices. He also occupied several technology related corporate positions. All this work has constituted the roots of today's IPDiA technologies.

New perspectives for CMOS image sensors in harsh radiative environments

MAGNAN, Pierre
HEAD OF IMAGE SENSOR GROUP
ISAE

Abstract
There is a fast growing interest in a strong enhancement of image capture capabilities in very harsh radiative environments. The Fukushima Nuclear Power Plant accident in Japan has strongly exacerbated the civil society sensitivity to Nuclear Facilities potential weaknesses and dangers highlighting especially the lack of vision capabilities in very harsh radiative environments, e.g. required for rescue robots actions. Consecutively, ability to capture images from radiation-resistant cameras in such environments has been identified as a critical issue for monitoring and remote handling in highly radioactive areas of nuclear facilities including power plants and nuclear waste repository sites but also in next generation particle physics research facilities such as the ITER. Imaging system withstanding dose above 1 MGy (100 Mrad) of Total Ionizing Dose are required for such applications. Available Rad-Hard cameras have been using imaging tubes technology limiting the miniaturization and functions integration capability that full solid-state solutions would allow. In the past, the radiation hardness of Radiation-Hardened CMOS Image Sensors has been demonstrated up to several hundreds of kGy (several tens of Mrad). Recent developments performed at ISAE using CMOS technology have demonstrated spectacular improvements in radiation tolerance of sensors and image capture capability over 1 MGy, paving the way to integrated compact Radiation-Hardened camera suited to the MGy range applications. In this presentation, we will present the key technical challenges to be faced related to radiation-hard photodiodes and circuits to achieve imaging capability in the MGy dose range. Additionally, we will also describe how CMOS image sensors have proven to be a key solution in experiments ("diagnostics") of Inertial Confinement Fusion (FCI) facilities (e.g. Mega Joule Laser class) where neutrons flash is a killer issue. Based on the obtained results, new perspectives will be drawn.

Biography
Pierre Magnan graduated in E.E. from ENS Cachan and University of Paris in 1982 After being a research scientist involved in analog and digital CMOS design up to 1993 in LAAS-CNRS, he moved to image sensors research in SUPAERO, now called ISAE-SUPAERO, in Toulouse, France. Since 2002, he is Full Professor there and Head of Image Sensor Research Group involved in CMOS Image Sensor basic and applied research. He has supervised 15 PhDs and co-authored more than 70 scientific papers. He has served in IEEE IEDM Display Sensors and MEMS subcommittee in 2011, 2012, and in the International Image Sensor Worshop (IISW) TPC in 2007, 2009, 2011, being the General Technical Chair of 2015 IISW.

Mai, Joe
Managing Director
JEM Europe

Biography
Joe Mai is founder and managing director of the European subsidiary of Japan Electronic Materials (JEM), a leader in wafer-probing technologies, for whom he's worked for over 20 years, playing both technical and business-development roles in the US, Europe and Asia. His technical experience includes product R&D, PCB design, automation, and applications engineering. During these past two decades, he has worked closely with many customers to improve their test capabilities and develop JEM's technologies.

JenaBatteries - Novel Metal Free Aqueous Redox Flow Batteries

Schneider, Steffen
Managing Director
JenaBatteries GmbH

Abstract
Issue to be solved Low-cost sustainable and long-lasting energy storage systems are the major bottleneck in the renewable electricity generation industry. Key Investment Highlights The deployment of novel, metal-free substrates developed by JenaBatteries becomes the desired catalyst to reduce the cost of REDOX FLOW battery systems substantially. Fully industrialized the costs per kWh storage capacity will be EUR <500, significantly lower than all other stationary battery technologies. Unique Selling Proposition 1 Cost leader by newly patented electrolyte in commercially available and long-established redox-flow- battery concept, 2 Simple, water-based electrolyte. 3 No heavy metals or rare elements. 4 Unlimited capacity by mature redox-flow-system design, 5 Low material cost. 6 No self-discharge. 7 No explosives, 8 Easy to scale-up. Company JenaBatteries' technology is based on several years of national and international battery research of one of the leading polymer research groups. The company employs industry professionals of chemists, hardware, software and material. JenaBatteries is profiting from the progress in lithium batteries, fuel cells and redox-flow developments in the last decades by employing experts of all of these segments. The company focuses on hardware, software and system design. The in-house development of the electrolyte is enhanced by an intensive collaboration with the University of Jena/Schubert group. With the first kW/kWh scale demonstrator unit the team demonstrated the commercialization potential of the system. Commercialization Strategy The key advantage of JenaBatteries' patented technology is the low-cost, mass-manufacturing potential. Based on huge economies of scale in modern mass manufacturing of organic substrates, JenaBatteries will be able to establish cost leadership in the stationary battery business. Market launch is expected in 2017. Structured product roadmap, partner list and targeted bill of materials per product are available.

Biography
Steffen Schneider Executive Summary 1) Entrepreneur and Managing Director 2) Business Development and M&A within 2004 - 2013 to support sales growth from US$ 500 mill to US$ 800 mill to support EBIT increase from US$ 25 mill to US$ 75 mill 3) Total of US$ >500 mill in 8 major M&A disposals 4) Total of US$ >400 mill in 4 crucial corporate finance transactions 5) Total of US$ 100 mill in 11 main M&A investments 6) Total of transactions 1999-2013: >30 7) Content focus: a) Raise of capital (several IPO's, bonds, convertible bonds, capital increases) b) Investments in privately hold and quoted companies c) Support & integration of newly acquired companies d) International business development of in the tech industry e) Founding start-ups in the high-tech industry & energy markets Since 2013 Start-up Investor, Managing Director & Shareholder of JenaBatteries GmbH Responsibility for (a) Financing, (b) Financial and business planning and (c) Project management and (d) Strategic partnerships 2013 - 2010 Vice President Strategy, Business Development, Innovation Management, Internal Audit of JENOPTIK AG (quoted, German TecDAX, US$ 780m sales) Responsibility for (a) Group's strategy, (b) Key growth projects, including M&A activities, (c) Key account management, partnerships with leading investors combined with product roadmap design of the group and (d) Internal audit 2010 - 2004 Vice President Corporate Development, M&A, Investor Relations of JENOPTIK AG Defining major catalysts for growth. Focus on (a) Strategies to open up international markets, (b) Economies of scale, (c) Value chain, (d) Round-up of product portfolio 2004 - 1999 Manager IPO-Management & Capital Markets and Head of Investor Relations of DEWB AG & JENOPTIK AG 1999 - 1997 Consultant Change Management with Accenture in Frankfurt & Chicago Restructuring projects and Customer Relationship Management projects Mr. Schneider holds a diploma in Business Administration at Friedrich-Schiller-University in Jena, Germany; Focus: Marketing, Taxes and Intercultural Business Communication

Analysis and In-Line Monitoring of Non-Visual Crystalline Defects (cNVDs) in Silicon Wafers to Identify Wafers at Risk from breakage

Atrash, Fouad
Senior Physicist
Jordan Valley Semiconductor

Abstract
Silicon wafers break during different processing within a Si manufacturing fab. Beside the yield-losses, due to lost material and tool availability during cleaning and requalification, each wafer breakage event is accompanied by conventional failure analysis methods that consume much effort, cost and time. In this presentation, we report on recent advance in our research aiming at developing a methodology to identify wafers with an increased risk of breakage during processing. We used X-ray diffraction imagining (XRDI) technology to map the strain fields in silicon wafers after applying defined impact forces at the wafer bevel, similar to those applied in fab environment by mechanical handlers. We show that slight misalignments in the handers might cause unexpected crystalline damage to the wafer bevel and thus to significantly decrease the wafer's residual strength. To understand the nature of the crystalline damage we used optical microscopy, AFM and SEM and performed finite element analysis. We show that the crystalline damage is dictated by the magnitude of the impact force, indenter (material and geometry) and damage location at the wafer bevel. Controlling these parameters has allowed to generate specific defect shapes and sizes and to generate sub-surface crystalline damage, which might affect the fracture toughness but are not detected by conventional optical surface inspection tools or by SEM. We refer to these defects as crystalline non-visual defects (cNVD). Recent developments in XRDI allow automatic, fast, precise and accurate inspection of the crystalline damage in silicon wafers within the fab and not just limited to the FA labs. XRDI defects maps are analyzed to identify and classify crystalline defects. We suggest that monitoring the crystalline defects at the wafer edge by XRDI accompanied with actions that keep the tools within specific envelope of mechanical force may reduce wafer breakage ratio.

Biography
Dr. Fouad Atrash received his PhD degree in materials engineering from the Technion in 2010 in the field of fracture dynamics of brittle crystals. He then served as a researcher and lecturer at the Technion, his main research interest was solving fundamental inquiries in fracture dynamics of brittle single crystals using multi-scale computational methods. Dr. Fouad joined Jordan Valley semiconductors in 2012 as a Senior physicist. He is leading the development of XRF technology algorithms and projects linking wafer breakage and XRDI technology.

Computer vision on manycore processor

Kalemkarian, Yann
Field Application Engineer
Kalray

Abstract
Kalray, Supercomputing on a chip technology, brings one of the most efficient processor that fits perfectly with the constraints of the future computer vision used in the future semi or fully autonomous vehicle industry. Kalray with its MPPA manycore processor proposes a disruptive processing solution to address the huge demand of computer vision application. Innovative architecture of the MPPA processor allows multiple applications with mixed criticality level to run on the same IC without any perturbation between the different kernels. Such feature provides to our customer the capability to save cost and merge many different functions on a single chip instead having it spread over the vehicles with communication and data streaming capability issues. MPPA Manycore is a C/C++ fully programmable processor capable to evolve with the sensor technologies and the algorithm research. Software engineers will modify their application on purpose with minimum time proposing with the same hardware different level of options/functions saving development time and cost.

Biography
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MOFs as Low-k Candidates for Future Technology Nodes

Wöll, Christof
Director
KIT

Abstract
Materials with good mechanical properties and low k dielectric constants are of paramount interest for the next generation of electronics, since for the needed increases in clock frequency low-k materials are a crucial ingredient. It is very difficult to achieve dielectric constants below k = 2 with conventional polymers. Here, we focus on a novel, highly tunable class of materials, metal-organic frameworks (MOFs). MOFs are highly porous hybrid materials consisting of organic linkers connected to inorganic metal (or metal/oxo) clusters. Due to their crystalline, highly ordered, and porous structures, MOFs exhibits a number of highly interesting properties. The Young's modulus of a particular MOF, HKUST-1, amounts to 9.3 GPa[1] Because of the very low mass density of MOFs, the static dielectric constants k is very small and can drop to values far below 2.[3] We have introduced a novel method to grow SURMOFs, thin films of this exciting new class of porous solids, by liquid phase epitaxy (LPE) [2]. The solid state elastic and mechanical properties of SURMOFs, as well as their optical, electrical and electrochemical [4] properties have been investigated.[5] In addition, they are suited for photolithography [6]. References [1] S. Bundschuh, O. Kraft, H.K. Arslan, H. Gliemann, P.G. Weidler, C. Wöll, Appl. Phys. Lett. 101, 101910 (2012) [2] O. Shekhah, H. Wang, S. Kowarik, F. Schreiber, M. Paulus, M. Tolan, C. Sternemann, F. Evers, D. Zacher, R. A. Fischer, Ch. Wöll, J. Am. Chem. Soc. 129, 15118 (2007). [3] E.Redel, Z. Wang, S.Walheim, J.Liu, H.Gliemann, Ch.Wöll, Appl. Phys. Lett., 103, 091903 (2013) [4] V. Mugnaini, M. Tsotsalas, F. Bebensee, S. Grosjean, A. Shahnas, S. Bräse, J. Lahann, M. Buck, C. Wöll, Chem. Comm., 50, 11129 (2014) [5] H. Gliemann, Ch. Wöll, Materials Today, 15, 110 (2012) [6] S. Grosjean, D. Wagner, W. Guo, Z.-G. Gu, L. Heinke, H. Gliemann, S. Bräse, Ch. Wöll, Chem.Nano.Mat., DOI: 10.1002/cnma.201500031

Biography
Hochschulstudium und Stipendien 1979-1984 Physik-Studium (Dipl.) an der Universität Göttingen 1984-1987 Promotion am Max-Planck-Institut (MPI) für Strömungsforschung, Göttingen unter Anleitung von J. Peter Toennies Stipendien während des Studiums und der Promotion: 1982-1987 Stipendium Studienstiftung des Deutschen Volkes Berufliche Laufbahn 1988-1989 Postdoktorat, IBM-Forschungslaboratorien in San José, USA 1989-1992 wissenschaftlicher Mitarbeiter am Lehrstuhl für Angewandte Physikalische Chemie in Heidelberg 1992 Habilitation an der Fakultät für Physik und Astronomie der Universität Heidelberg 1992-1993 Hochschuldozent (C2) am Lehrstuhl für Angewandte Physikalische Chemie der Universität Heidelberg 1994 Umhabilitation von Heidelberg an die Fakultät für Physik der Georg-August-Universität Göttingen 1997-2009 Hochschulprofessor (C4), Lehrstuhl für Physikalische Chemie I der Ruhr-Universität Bochum 2001 Visiting Professor am Materials Research Laboratory der University of Illinois at Urbana-Champaign, USA 2006-2007 Visiting Professor am Materials Science Laboratory an der Nagoya University, Japan 2009- Direktor des Instituts für Funktionelle Grenzflächen (IFG) am Karlsruher Institut für Technologie (KIT, Campus Nord) Funktionen 2000-2009 Sprecher des DFG-Sonderforschungsbereichs (SFB) 558 ***Metall-Substrat-Wechselwirkungen in der Heterogenen Katalyse" 2001-2007 Koordinator des DFG-Schwerpunktprogramms 1121 ***Organische Feldeffekttransistoren" (OFET) 2004-2007 Sprecher des Transferbereichs des SFB 558 ***CVD-Präparation von Cu/Zn/Al-Trägerkatalysatoren für die Methanolsynthese" 2006-2009 Koordinator des EU-STREP-Projektes ***Anchoring of metal-organic Frameworks, MOFs, to surfaces" (SURMOF, FP6) 2009- Mitglied des Senats des KIT 2011- Sprecher des Helmholtz-Programms BioInterfaces Stipendien/Auszeichnungen 1988 Otto-Hahn-Medaille der Max-Planck-Gesellschaft für die im Rahmen der Promotion erfolgten Arbeiten ***zur Demonstration der Anwendungsmöglichkeiten der Helium-Atomstrahlmethode auf Oberflächenuntersuchungen" 1994-1996 Heisenbergstipendiat der Deutschen Forschungsgemeinschaft (DFG), Tätigkeit in Heidelberg und Göttingen (MPI für Strömungsforschung) 2013- Mitglied der Deutschen Akademie der Naturforscher Leopoldina Mitgliedschaften Herausgebergremien wissenschaftlicher Zeitschriften und Monographienserien - Editorial Board Surface Review and Letters - Editorial Board Progress in Surface Science Wissenschaftliche Gesellschaften - Gesellschaft Deutscher Chemiker - Deutsche Physikalische Gesellschaft - Deutsche Bunsengesellschaft für physikalische Chemie Gutachtertätigkeiten - Gutachter der DFG, Studienstiftung des dt. Volkes, u.a. - der NSF, des DOE (USA) - Gutachter für den FWF (Österreich), den EPSRC (GB), die Israel Science Foundation, u.a. - Gutachter im Zusammenhang mit Beförderungen und Berufungen an deutschen, europäischen und nordamerikanischen Universitäten Forschungsaktivitäten Photoelektronenspektroskopie (XPS, UPS) sowie Absorptionsspektroskopie im weichen Röntgenbereich (NEXAFS) an dünnen organischen Filmen und Adsorbatschichten auf Metallen, Halbleitern und Isolatoren, Messungen am Synchrotron BESSY in Berlin; Herstellung, strukturelle und chemische Charakterisierung von ultradünnen organischen Filmen (Langmuir-Blodgett, selbstorganisierende Filme aus Alkanthiolen und Alkylsilanen) auf metallischen (Au,Cu) und oxidischen (Si) Substraten, Infrarotspektroskopie an organischen Dünnstschichten auf metallischen und oxidischen Substraten, Flüssigphasenepitaxie von metallorganischen Gerüstverbindungen (MOFs bzw. SURMOFs) auf organischen Oberflächen, Beladen der epitaktischen Schichten mit Gastmolekülen Publikationsaktivitäten Ca. 400 Veröffentlichungen, 2 Patente, 1 Buch (Herausgeber)

In-line Spectroscopic Ellipsometry and Raman Spectroscopy as powerful quality control tools for roll-to-roll manufacturing of Organic Electronics

Laskarakis, Argiris
Head of Organic Electronics Group
Lab for Thin Films, Nanosystems & Nanometrology (LTFN), Department of Physics, Aristotle University of Thessaloniki

Abstract
Roll-to-roll (r2r) manufacturing processes offer clear advantages for the low-cost and large area production of several Organic Electronic devices on flexible substrates, such as Organic Photovoltaics (OPVs). One of the main factors that contribute to the achievement of high efficiency of OPVs is the optimization of the blend morphology of the photoactive layer, which consists of a polymer electron donor and a fullerene-based electron acceptor. Also, the optimization of the quality of the OPV printed nanomaterials (organic semiconductors, transparent electrodes, barrier nano-layers etc.) is a prerequisite for the achievement of the required performance, efficiency and lifetime of OPVs that will enable their wide market exploitation. In this work, we present an innovative methodology for the in-line quality control of r2r print-ed OPV nanomaterials by the adaptation of robust optical methods such as in-line Spectroscopic Ellipsometry and Raman Spectroscopy on a r2r printing pilot line for the manufacturing of Organic Electronic devices. These optical techniques are combined with sophisticated mod-elling procedures and methodologies in order to obtain significant information on the optical properties of bulk heterojunction (BHJ) photoactive layers for OPVs that consist of state-of-the-art electron donors (e.g. polythiophenes) and acceptors (e.g. fullerene derivatives, PC60BM, PC70BM, ICBA, etc.). This innovative methodology establishes the importance and applicability of optical tools to be used as standard tools for the in-line robust determination of the thickness, optical and structural properties and the quality of other thin films and nanolayers for many Organic and Printed Electronics applications.

Biography
Dr. Argiris Laskarakis is the Head of the Organic Electronics Group of the Aristotle University of Thessaloniki, Greece. He is specialist in the fabrication and characterization of Organic Electronics nanomaterials. He has many years xperience on the optical characterization and modelling of the optical properties of inorganic, organic and hybrid nanostructured materials by Spectroscopic Ellipsometry in an extended spectral region from the IR to Vis-fUV, and Raman Spectroscopy. He is specialist in thin film deposition with various PVD (e.g. e-beam evaporation and magnetron sputtering), CVD techniques, and plasma treatment of bulk materials and thin films. He is experienced in the modelling of the optical properties of bulk materials and nanostructured thin films, and in theoretical investigations & modelling of optical properties of anisotropic materials by Mueller Matrix methodologies.

Ultra-fast laser patterning for roll-to-roll manufacturing of organic photovoltaics onto flexible substrates

Logothetidis, Stergios
Professor of Physics
Lab for Thin Films, Nanosystems & Nanometrology (LTFN), Department of Physics, Aristotle University of Thessaloniki

Abstract
Ultra-fast laser processes are attractive as alternative patterning techniques to photolithographic methods that have the advantage for implementation to roll-to-roll (r2r) manufacturing processes for the low-cost and large area production of numerous flexible Organic Electronic devices, such as Organic Photovoltaics (OPVs). Laser processes offer greater resolution than printing methods, whereas the incorporation of laser scribing allows closer spacing of the P1, P2 P3 laser scribes, increasing the active area of the printed OPV device, which contribute to the increase of the OPV efficiency. In this work, we present the latest results on the implementation of in-line laser scribing meth-od on a r2r pilot line for the ultra-fast laser scribing of inorganic and organic nanomaterials for flexible OPVs. These include state-of-the-art inorganic nanomaterials (e.g. Indium Tin Oxide), as well as transparent polymers (e.g. PEDOT:PSS) and photoactive polymers as electron donors (e.g. polythiophenes) and acceptors (e.g. fullerene derivatives, PCBM, etc.) in single and multilayer structures. This innovative methodology demonstrates the potentiality of ultra-fast laser processes to be used as a standard process step for r2r manufacturing processes for Organic and Printed Electronics devices.

Biography
Prof. Stergios Logothetidis is the Founder and Director of the Lab of Thin Films - Nanosystems & Nanometrology (LTFN, www.ltfn.gr) and the Center of Organic & Printed Electronics, at Aristotle University of Thessaloniki, Greece (AUTh). His research activity is complemented by over 880 papers and review articles in international journals & conferences. He has given more than 150 invited talks. He is a referee in more than 25 scientific journals and on the board of several journals. He is the editor of several books with topics ranging from Nanotechnologies, Nanomedicine to Organic Electronics. He has been the coordinator and principal investigator in more than 70 R&D projects funded by European Commission in the fields of Nanotechnologies, Materials Science, Organic Electronics and Nanomedicine. He is the director and founder of the Post-Graduate Program "Nanosciences & Nanotechnologies" of Aristotle University, with the participation of Depts. of Physics, Chemistry, Medicine and Polytechnic School in 2002, and other Depts and Institutes from Greece and abroad. He is the founder and Coordinator of the Thematic Research Network on Nanotechnologies and Nanobiotechnologies "NANONET" with more than 370 members (of Laboratories, Research Centers and companies) from all over the world, established in 2003. Finally, he annually organizes a platform of events since 2004 with two International Conferences, three International Summer Schools and one Exhibition) on Nanotechnologies, Nanomedicine & Organic Electronics under the umbrella of NANOTEXNOLOGY (www.nanotexnology.com). He is founder and responsible of the Hellenic Organic and Printed Electronic Association (HOPE-A) (www.hope-a.com) that consists of more than 20 companies and 3 research institutes for the formation of the Organic Electronics Industry in Greece.

Pain, Laurent
Patterning Programs Manager
Leti

Biography
Laurent Pain is graduated from the Ecole Nationale Supérieure de Physique de Grenoble in 1992. He received his Ph D after his work on DUV resists study. He joined CEA-LETI in 1996 to work on infra-red technology, and then came back to microelectronics in 1999 working on 193nm and e-beam lithography technologies. From 2008 to 2014, Laurent Pain leaded the lithography laboratory of the silicon technology division of CEA-LETI. He was also managing in parallel the industrial consortium IMAGINE dedicated to the development of multibeam lithography with MAPPER lithography BV. Since July 2014, he took new responsibilities inside the LETI Silicon Technology Division. He is now the Patterning Programs Manager and ensures the associated Business developments.

Martorelli, Riccardo
COO
LFoundry

Biography
Riccardo completed his degree in Chemical Engineering at the "La Sapienza" University of Rome and started his career in semiconductor industry on 1995 as Process and Equipment Engineer at Texas Instrument in the Avezzano Plant. He gained several technical and managerial positions, first in Texas Instruments and later in Micron Technology, main focus being on planning, organizing and directing the manufacturing and maintenance operations. He effectively assures attainment of business objectives and productions schedules, improving the production methods, quality and safety attitude, controlling and reducing cost in a high tech environment, requiring frequent and high cost technology's evolution. In 2008 he took over the responsibility of Fab Manager in the Italian Fab and since 2011 he took the role of Site Manager. Since May 2013 he is appointed as Chief Operating Officer of LFoundry.

Advanced Semiconductor Manufacturing Fabs: A View from a Gas and Material Supplier

Cigal, Jean-Charles
Programme Manager
Linde AG

Abstract
With the implementation of advanced technology nodes below 20nm, semiconductor companies are facing a dramatic increase of manufacturing costs. Furthermore, the consolidation of the industry into few leading edge manufacturers is inevitably leading to the emergence of larger fabs. Gas companies are preparing themselves for this rapid metamorphosis of the industry landscape. Whether or not the transition to 450nm happens, economies of scale need to be addressed, as the demand for gases is drastically increasing. The consequences for bulk gases delivery (nitrogen, argon, and hydrogen) need to be assessed and delivery strategies must be developed and implemented. In many cases, the standard truck delivery scheme is to be replaced by on-site production. The logistics of cylinders needs to be revamped as well. The materials supply chain has become truly globalized and material companies are facing new challenges to avoid any interruption of product delivery. At the same time, material quality requirements are reaching levels never observed in the industry before. New and innovative material quality controls are required all along the supply chain. New analytic methods also need to be developed to challenge the current detection limits. Finally, limited natural resources need to be addressed. Innovative solutions like materials recycling can be a useful tool in reducing environmental impact.

Biography
Jean-Charles Cigal is currently Programme Manager at Linde Electronics. In his role, Jean-Charles helps customers and equipment manufacturers with technical support to achieve their roadmap with the introduction of new processes and materials. He joined Linde as principal technologist in 2009, where he was technology consultant for the semiconductor and the photovoltaic industry. Prior joining the Linde Group, Jean-Charles worked several years as senior process engineer in the semiconductor industry. He owns a M.Sc. in Applied Physics from Pierre et Marie Curie University, Paris, France, and a PhD in Applied Physics from Eindhoven University of Technology, the Netherlands.

Speech and Gesture -- Futuristic Human Machine Interfaces

Petrick, Rico
CEO
Linguwerk GmbH

Abstract
Technical devices are logical and functional units by nature. Their actual purpose is often very straight-forward, but also often very technical or highly complex. They measure temperatures, wash dishes, control industrial equipment, provide information, entertain, save lives, or provide support. They are operated using buttons or touch. They "speak" to us via display, LEDs, vibration, speech, sounds, shapes, colours, and sometimes not at all. In some situations user interaction without touching the device is useful. In those cases speech recognition or gesture recognition can be a solution. Linguwerk GmbH develops such technologies with a very low footprint as such, that they fit on a low price microcontroller (e. g. 1 USD). The very low hardware price is precondition to implement such future HMI technologies into customer products such as house hold devices or home automation equipment.

Biography
Rico Petrick is initiator, founder and CEO of the Linguwerk GmbH, a company that is specialized in signal processing and speech technology. He has graduated in electrical engineering at the Dresden University of Applied Sciences and received a PhD degree in electrical engineering with a specialisation in speech processing from the Dresden University of Technology. His scientific major is the robustness of speech recognition systems in real and adverse acoustic environments. He has worked in algorithmic design of digital signal processing systems and embedded speech processing since 1998 in various positions in science and industry. Selected academic positions included the University of Technology, Sydney (UTS), Australia; the Japan Advanced Institute of Science and Technology (JAIST), Kanazawa, Japan; the St. Petersburg Institute for Informatics and Automation of the Russian Academy of Sciences (SPIIRAS), St. Petersburg, Russia; and the Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. As a scientist, Rico Petrick has published about 30 national and international scientific papers, and he is further reviewer for the scientific journal Speech Communication (SPECOM), run by the world's leading speech technology organisation ISCA.

3D printed optics

Tierie, Eric
CEO
Luxexcel

Abstract
Luxexcel is the only company in the world able to 3D print optics. Directly from a cad-file to proprietary printers, without the need for any post-processing. High transparency, high accuracy, high speed. Based upon ink jetting of acrylics and soon also silicones. Serving a wide range of industries including photonics, lighting, automotive, medical, aerospace & defence. Not just for prototypes but also for small/medium volume series, within just days instead of weeks or months.

Biography
Eric Tierie has a MSc degree in process engineering from Technical University Delft and a secondary degree in business economics. With international management experience in polymers, metals, energy, aerospace & defence, chemicals and packaging he worked for multinationals such as Unilever, Exxon and Arcelor Mittal. Since 2014 he joined Luxexcel as CEO in the Netherlands.

Atomistic Simulations for the Design, Fabrication, and Reliability of Semiconductor Devices

Eyert, Volker
Senior Scientist
Materials Design s.a.r.l.

Abstract
With feature sizes of semiconductor devices reaching the nano-scale, the design, fabrication, and reliability face unprecedented challenges. Atomic-scale phenomena play an increasingly critical role and can have a major impact on materials properties. In this context, atomistic simulations offer unique capabilities for predicting key materials properties needed in the design of novel devices, to optimize the various processing steps in fabrication, and to control the reliability of the devices by anticipating possible failure mechanisms. With the recent advances in computational methods and computing power, atomistic simulations have evolved as an integral part of materials research and engineering. The MedeA® computational environment of Materials Design is geared towards the high demands of the semiconductor industry and is already adopted by an increasing number of leading industrial players worldwide. The capabilities of MedeA® will be illustrated by selected examples regarding interfacing with TCAD simulations, critical design parameters such as Schottky barriers and effective work functions, and transport properties including thermal conductivity. Demonstrating the benefits of atomistic simulations our presentation will address a broad audience with various technological and business perspectives of the value chain.

Biography
Volker Eyert is senior scientist at Materials Design, a company providing software, support, consulting, and contract research for materials research. He received a physics degree (Dipl.-Phys.) in 1986 from the University of Münster and a doctoral degree (Dr. rer. nat.) in physics in 1991 from the Technical University of Darmstadt. After taking a postdoctoral position in the group of Prof. O. K. Andersen at the Max-Planck-Institute for Solid State Research in Stuttgart he got an offer from the Helmholtz-Center Berlin to form a new group on atomistic simulations for photovoltaic applications in 1995. In 1998, Dr. Eyert finished his habilitation in theoretical physics at Augsburg University (Priv. Doz.), where he joined the faculty of the Institute of Physics as well as the Center for Electronic Correlations and Magnetism as an assistant professor, prior to becoming a member of the Materials Design team in 2011. During his time at Augsburg University, Dr. Eyert played an essential role in initiating and leading multi-institutional and interdisciplinary advanced research projects (SFBs) as funded by the German Science Foundation. In addition to having given numerous lectures worldwide, Dr. Eyert is author and co-author of over 130 scientific publications and book chapters as well as a monograph.

Multi-site Probing of Magnetic Sensors at 175 deg C

Gouwy, Geert
Process Owner Probing
Melexis

Abstract
The rapidly-growing sensor market for automotive and other industries is driving innovations in semiconductor wafer test. Stringent safety and reliability standards requires extreme tests, including tests at high/low temperatures, which is notoriously difficult to achieve at the wafer level, due to uncontrolled movements of the various parts of the test-cell (probe card, prober components and probe-card interface, etc..), which affect yields, pad damage, bonding reliability, and test through-put. In addition, sensors require stimuli (pressure, magnetic fields, light, etc.) in addition to electrical tests. As such stimuli are difficult or impossible to apply during wafer test, sensors are often tested in special handlers, individually, and after device packaging. The cost of this method is very high because more test systems are required, and bad devices are packaged along with good ones. So, unless device volumes are very low, wafer-level test of multiple devices in parallel is usually desirable. However, achieving this is not easy. The stimulus requires equipment that often interferes with the tester/prober interface. Often the probe card is a physical barrier, preventing access to the device. This presentation will describe how Melexis successfully implemented multi-site (x8) testing of magnetic devices at temperatures up to 175 deg. C, while applying a uniform magnetic field to all devices. The key elements included in the presentation will be: - The challenges and requirements of probing of magnetic sensors in parallel and over a wide temperature range - The development of the probing hardware (magnetic source, prober interface, probe card) - The test results which validated the probing hardware - Best practices for probing at high/low temperatures

Biography
Melexis - Geert Gouwy, - Olivier Dubrulle - Lindsey Ameele - Frederic Plancke - Filip Beyens - Peter Schops Melexis Internship - Ruth Verheyen JEM - Joe Mai - Christopher Mackanic - Sebastien Perino

Connock, Peter
Chairman
memsstar Limited

Biography
I have been working in the semiconductor industry for over 35 years with positions in development, customer service, marketing and management at Edwards, Applied Materials and memsstar at locations around the world. My current role, Board Chairman at memsstar, has involved both operational and strategic activities in the global MEMS market and European secondary equipment industry. memsstar (http://www.memsstar.com) is Europe's premier semiconductor equipment remanufacturer and services provider and also serves the global MEMS marketplace, offering etch and deposition expertise, experience, proprietary and remanufactured systems and know-how to deliver innovative products and services for research, commercial R&D and production. This year, I have been appointed Strategic Programme Director of AENEAS (AENEAS.eu), responsible for the introduction of the new EUREKA "PENTA" funding cluster. This is a five-year programme supporting the development micro- and nano-electronics systems and applications in Europe. I have augmented my operational activities by establishing a long-term relationship with industry representative bodies such as SEMI (http://www.semi.org) serving on SEMICON, ISS and now the Secondary Equipment committees in Europe for many years. These activities have now been complemented by my appointment to the nmi Board in the UK - representing the UK microelectronics industry (http://nmi.org.uk). As well as working with memsstar I am closely involved in the ENIAC & ECSEL European Union funding programme for technology with special responsibility, as part of the AENEAS industrial association, for encouraging SME involvement in EU funded projects. I now specialise in working with SME's at Board level in strategic marketing and business development. I am currently on the Board of several SME's and industrial organisations.

Supporting the Secondary Market - Matching Products & Services to Changing Customer Needs

McKie, Tony
CEO
memsstar Ltd

Abstract
The Internet of Things is truly upon us. Exploding at an exponential rate it is expected to grow at a CAGR of 31.72% for the five years to 2019. The potential is limitless as market sectors of all types embrace the opportunities of integrated electronic devices in a huge range of products and services which will inform, measure, control, record and report. This has resulted in a massive outflow of new systems & applications to be delivered faster, smaller and at very low cost. To meet these demands, there is pressure on industry suppliers to increase capacity & throughput on new processes, whilst working with lower technology equipment, in many cases at 200mm. To be competitive costs are key and the successful adaptation of secondary equipment is paramount. A supply chain which can quickly fulfil the need for re-purposed equipment, support and services is critical. We need to understand developing customer needs and identify how we can cost-effectively meet them in a way that will allow new applications to be built competitively. In the last 15 years we have seen customer requirements for secondary equipment change dramatically. From days of simply refurbishing or making small modifications to older equipment, we now have to provide bespoke solutions for a wide variety of applications, extending the life span and evolving the functionality of older equipment. This isn't without its challenges - the availability of donor tools, where to source legacy components, the provision and knowledge transfer of engineering and process expertise in older technologies, and ensuring standards and quality to satisfy a demanding industrial environment. This presentation will address the evolution of the secondary equipment market and how the secondary industry can support that market, providing a supply chain with solutions to satisfy customer demands. It will also look at future challenges that will need to be faced, exploring the potential to transform them to new opportunities.

Biography
Tony McKie is CEO of memsstar. As one of the company's founders, McKie was responsible for developing the ORBIS, XERIC and AURIX product lines and managing business development activities for the single wafer release etch platforms. He has an extensive background in semiconductor equipment manufacturing through prior management roles at Electrotech, Lam Research and Applied Materials. He has a BSc in Physics.

High Performance Organic Semiconductor Manufacturing Using Printing and Photolithographic Processes

James, Mark
R&D Director
Merck Chemicals Ltd

Abstract
Merck has been actively researching Organic Electronic materials since 2000 with the objectives to develop products that enable mass production of plastic electronic devices. We demonstrate how the co-development of organic semiconductors, passive materials and formulations with process optimisation enable the manufacture of high performance OTFT arrays suitable for mass production of display backplanes and other circuit applications using polymeric organic semiconductor systems. These materials can be either printed or patterned using photolithographic process to fabricate OTFT's with commercially viable device sizes and mobilities greater than amorphous silicon.

Biography
Mark James has a PhD in organic synthesis. After postdoctoral research he joined ICI and remained there for 18 years seeing the transformation through Zeneca to Avecia. He managed projects ranging from biocide design to developing inkjet processes to manufacture PCB's. In 2005 he moved to the CPI and managed their flexible electronics operation. Mark joined Merck in 2006, leading the company's functional material patterning activities and in 2010 took over responsible for Merck's Organic Electronics Business covering the development of and commercialisation of organic semiconductor materials for display backplanes, circuits, OPV and OPD applications. From 2014 he became Merck's global head of R&D for Electronic Materials.

Shoval, Menachem
chairman
Metro450

Biography
Menachem Shoval is holding an Electronic Engineering degree since 1973 specializing on Industrial Control Systems. After 10 years of working in different companies and research organizations in Israel Menachem joint Intel to start the first Fab in Israel in 1984. Menachem spent 28 years in Intel, working in F8, PTD, F18 and TME, fulfilling different engineering tasks, technological tasks and managerial positions. In his last position Menachem was in-charge of introducing Intel with new/ relevant technologies available in Israel and the region, focusing mainly on Lithography and Metrology. In 2012 Menachem left Intel to start leading the Israeli 'Metro450' consortium as the Chairman of Board.

Depth imaging the engine of the renaissance of Virtual Reality

Yahav, Giora
General Manager of AIT (Advanced Imaging Technology) group
Microsoft

Abstract
When scientist and futurist Jaron Lanier cooked up the term "virtual reality" in the 1980s, it was little more than a marketing device. It explained the new virtualization and simulation system he and his team at VPL Research built to help them develop a new programming language. It was the first VR boom. Consumer VR, however, never quite achieved liftoff. So what will it take for mainstream consumers to embrace the traditionally cumbersome technology? As with any emerging technology, consumers are only interested in VR as so far as it measurably improves their lives (or enjoyment of their lives) and is easy and affordable. Microsoft's 3D-imaging system, Kinect, which was introduced in 2010, has done more than any other product to introduce virtual reality experiences to the masses. The motion and depth detection device, which was developed at Microsoft is a "virtual reality breakthrough." Kinect performed better than anything similar at any price, the depth camera measuring human motion in real time was a breathtaking experience. Kinect's ability to measure a room and everything in it is transforming gaming and VR experiences alike, was the drive for more immersive experiences like Oculus Rift and Hololens.

Biography
Dr. Giora Yahav was appointed in June 2009 as the General Manager of AIT (Advanced Imaging Technology) group at Microsoft R&D Israel, as part of the acquisition of 3DV Systems. Dr. Yahav previously served as Senior VP R&D and CTO of 3DV Systems. Dr. Yahav is a one of 3DV's founder and Inventor of the basic technology. He is a leading expert in imaging technologies and is regarded as an opinion leader in advance imaging technologies especially in novel CMOS based imagers. He is an active member of IEEE and SPIE, lecturing on various international conferences and academic conventions. He published over 22 papers and contributed to several fundamental researches in the field of imaging with an emphasis on active 3D imaging. He has over 16 years experience in Research and Development project management at Rafael, the Israeli Armament Development Authority, as the Head of active Electro-Optical Systems department. He has extensive experience in Electro-Optical projects and holds over 20 patents. Previously, he spent eight years in academic research at the Hebrew University in Jerusalem, the Technion in Haifa and the Max-Plank Institute in Germany. Dr. Yahav holds a Ph.D. in Physical Chemistry, an M.Sc. in Inorganic Chemistry and a B.Sc. in Chemistry & Physics.

Mind-Objects - Visual Requirements Engineering

Brade, Marius
Founder
Mind-Objects

Abstract
Mind-Objects offers a software running on tablet-PCs for consultants and requirements engineers making their meetings with customers more productive. Using the software is as easy as using pen and paper with the advantage of an automated documentation of meetings.

Biography
After finishing his Ph.D. in Media-Computer-Science at Technische Universität Dresden in Germany, Marius Brade is currently starting a company together with Hannes Leitner and Martin Gregor on top of the results. His Ph.D. research project named "Visualization Methods for Interactive Gathering and Structuring of Information in the Context of Knowledge Modeling" was a cooperation between industry and academia. The partner from industry for this research was the User Experience Lab at SAP Research.

Deposition of hermetic glass thin films for Opto and MEMS

Hansen, Ulli
CEO
MSG Lithoglas GmbH

Abstract
Hermeticity permitting elevated lifetimes is an essential characteristic of higher quality devices, esp. in sensors and actuators. In many cases the desired reliability of a device can only be achieved by complex packaging solutions, which are designed to keep moisture and aggressive media away from the silicon circuitry while not impairing its interaction with the outside world. Lithoglas offers an unique solution to apply thin borosilicate glass films directly onto semiconductor surfaces to create a hermetic sealing right on the active or sensitive circuitry, allowing for simplified packaging solutions and smaller overall device sizes. The deposition is conducted at very low temperatures (<80°C) allowing for a wide variety of materials to be processed. The glass films can be precisely structured by lift-of-lithography. Opto-electronics widely uses glass components to create optical windows within the package. These can be replaced by directly coating glass onto the device or by creating glass cavity caps, which can be integrated into the package. MEMS devices widely rely on the hermeticity of anodic bonding, employing borosilicate glass wafers in conjunction with the silicon devices. There are drawbacks to these solutions, as the glass is a much more rigid material, which can influence the silicon transducer when thermal or mechanical stress is applied. Replacing glass wafers by glass coated silicon wafers in anodic bonding significantly reduces this disadvantage. In MEMS capping cavity structures are joined with silicon devices e.g. by glass frit or eutectic bonding to create hermetic sealing. Using deposited borosilicate glass films such structures can be anodically bonded with high precision at reasonable cost. Especially favorable is the possibility to bond deposited glass to deposited aluminum structures, allowing for a higher freedom of design without the need of bare silicon in the bond interface.

Biography
Ulli Hansen is co-founder and CEO of Dresden-based MSG Lithoglas. He received his Ph.D. in 2004 from the Techn. University of Braunschweig in the field of TCAD for MEMS prior to engaging in the development and commerzialization of the proprietary Lithoglas glass deposition technology in 2006.

GaN Transistors for Power Electronics

Wachowiak, Andre
Senior Scientist
NaMLab gGmbH

Abstract
Power semiconductor transistors are at the core of power electronics systems and, therefore, determine their potential efficiency by the device related performance. Next to SiC-devices, GaN based transistors are becoming a more serious competitor for the presently dominating Silicon power devices. The superior intrinsic material parameters of GaN (wide band gap, high breakdown field strength,...) compared to Silicon in combination with the ability to use heterojunction interfaces as transistor channels of very high mobility predict an out-performance of current Si-technologies and an extended operation regime at higher temperatures. However, GaN related technology hurdles have to be overcome in order to meet the requirements for a mature product. Main challenges start at the growth of high-quality substrate material, over specific characteristics of GaN devices up to final reliability in harsh environment. Solutions of some issues and different approaches to tackle the remaining tasks will be described and discussed. The activities of NaMLab within this context of technology development are presented.

Biography
Andre Wachowiak received his diploma degree in physics in 1998 from the University of Heidelberg, Heidelberg, Germany in and the P.h.D. degree in 2003 from University of Hamburg, Hamburg, Germany. After being a post-doctoral research fellow at the physics department of UC Berkley and Lawrence Berkeley National Laboratory, Berkeley, CA, USA for two years, he joined the DRAM division of Infineon Technologies Dresden (later Qimonda), Germany, in 2006. As device engineer, he was responsible for pre-development of CMOS periphery devices in up-coming technology nodes of DRAM chips until 2009. He has been a Senior Scientist with NaMLab gGmbH, Dresden, since 2010, where he is responsible for concept evaluation and device development in different areas of Silicon to GaN technology.

Next Generation Ferroelectric Field Effect Transistors enabled by Ferroelectric Hafnium Oxide

Mikolajick, Thomas
scientific director
NaMLab Gmbh / TU Dresden

Abstract
Ferroelectrics are very interesting for nonvolatile memories. The progress is limited by the low compatibility of ferroelectrics like PZT with CMOS processing. Therefore 1T/1C ferroelectric memories are not scaling below 130 nm and 1T ferroelectric FETs are still struggling with low retention and very thick memory stacks. Hafnium oxide, a standard material in sub 45nm CMOS, can show ferroelectric hysteresis with promising characteristics. By adding a few percent of silicon and annealing the films in a mechanically confined manner Boescke et al. demonstrated ferroelectric hysteresis in hafnium oxide for the first time. Recently a large number of dopants including Y, Al, Gd and Sr have been used to induce ferroelectricity in HfO2. In the first part of this talk the different doping elements that have been shown to enable ferroelectricity will be compared and general trends will be established. The second part will focus on the memory relevant characterization data. Finally the application in 1T FETs will be demonstrated and the potential to solve principal issues of ferroelectric FETs will be illustrated.

Biography
Thomas Mikolajick received the Diploma (Dipl.-Ing.) in electrical engineering from the University Erlangen-Nuremberg in 1990 and his phD in electrical engineering in 1996. From 1996 till 2006 he was in the semiconductor industry developing CMOS processes,ferroelectric memories, emerging non-volatile memories and Flash memories first at Siemens Semiconcuctor and later at Infineon. In late 2006 he moved back to academia taking over a professorship for material science of electron devices and sensors at the University of Technology Freiberg, and in October 2009 he started at Technische Universität Dresden were he now holds a professorship for nanoelectronic materials in combination with the position of scientific director at NaMLab GmbH. Since April 2010 he is the coordinator of the "Cool Silicon" Cluster in Dresden. Prof. Mikolajick is author or co-author of about 220 Publications in scientific journals or at scientific conferences and inventor or co-inventor of about 50 patents.

Testing solder ball alloy materials for reliability improvement in eWLB technology

Miguel Amorim Barbosa, Hugo
R&D Materials Development Engineer
NANIUM S.A

Abstract
Depending upon the end user application a specific focus in terms of Drop Test, Thermal Cycling on Board is required and the chosen alloy has often been tailored for this use. Furthermore, alloys with similar composition but from different suppliers do not necessarily have equivalent performance and behavior. This raises other questions such as supply chain, second sourcing and IP considerations. The present work aims to evaluate and compare the processability and reliability of solderballs with a standard SAC305 and a similar alloy with dopants designed to enhance drop shock performance. Two nominally identical alloys of the reliability enhanced solderball from different suppliers are employed to respond to the question of second sourcing. Test vehicle #1 was utilized in a complimentary study using an additional 2 solderball alloys expected to improve drop shock performance -Ni doped SAC (2.0Ag,0.75Cu,0.07Ni) and SAC (1.0Ag, 1.0Cu). Alloys with a reduced silver component and increased level of copper are well known to improve drop shock performance however a balance must be achieved with Thermal Cycling on Board, since this type of alloy usually displays poorer TCoB performance. Regarding the SAC 305 alloys, it was noted that the presence of dopants slightly postpones the first fail appearing in terms of drop shock and a slight performance impact in terms of TCoB. With respect to the comparison between two suppliers (for sourcing purposes), although it seems there is a better performance in terms of drop shock resistance from one of them, more pronounced in TV #2, the same cannot be state about TCoB results.As for complementary evaluation over Ni doped SAC (TV #1), it achieved the higher value of drops until first fail occurs as well as the failure rate along the time. By other side, this alloy reached the worst performance on thermal fatigue which indicates the combination of Ni addition and a medium Ag percentage cannot overcome a SAC305 (doped or not) alloy.

Biography
Hugo Barbosa have been working at NANIUM for approximately two years as R&D Materials Development Engineer. He received a MSc. degree in chemical engineering from Aveiro University in 2013.

Kroehnert, Steffen
Director of Technology
NANIUM S.A. - Niederlassung Dresden

Biography
Dipl.-Ing. Steffen Kröhnert received his master degree in Electrical Engineering and Microsystem Technology at Technical University of Chemnitz, Germany, in 1997. In the same year he started his professional career as Development Engineer in the Corporate Package Assembly, Interconnect and Test Development Center for Semiconductors of Siemens AG in Regensburg, Germany. After carve out of the Semiconductors Business Unit to Infineon Technologies AG in 1999, he worked as Project Manager and moved to Infineon Dresden GmbH & Co. OHG in 2002 to support local setup of Package Development Department for Memory Products. He became R&D Area Manager Component Development and took over Technology Platform ownership for FBGA products. From 2006 he was working as Senior Manager in Qimonda Dresden GmbH & Co. OHG, the carve out of the Memory Products Business Unit of Infineon Technologies. Begin of 2007 he was assigned to Qimonda Portugal S.A., the largest Packaging, Assembly and Test facility of Qimonda, in order to setup and lead the Package Development team at this volume production site. Since 2009 he is Director of Technology at NANIUM S.A. in Vila do Conde, Portugal, the largest independent Semiconductor Packaging, Assembly and Test Foundry (OSAT) in Europe. Steffen is author and co-author of 23 patent filings in the area of Semiconductor Packaging Technology. He is member of IEEE CPMT, IMAPS, MEPTEC, SMTA, VDI, VDE and GPM. He actively contributes as Co-Chair to SEMI Europe's Advanced Packaging Conference (APC), as Technical Committee member to IEEE Electronic Components and Technology Conference (ECTC), IEEE Electronics System-Integration Technology Conference (ESTC) and IMAPS European Microelectronics Packaging Conference (EMPC), and as Assistant Technical Co-Chair (Europe) to IMAPS Device Packaging Conference and International Symposium on Microelectronics.

Nano-Join

Röhrich, Tobias
Founder
Nano-Join

Abstract
Nano-Join produces and sells newly designed and patented sinter pastes, which will mainly be used in the connection technology. After five years of development at the Chair of Joining and Coating of the TU Berlin, the materials are now ready to be commercialized and be produced on an industrial scale. The startup just received an EXIST entrepreneurship grant from the Federal Ministry of Economics and Energy. The developments in electronics and micro-technology are characterized by increasing miniaturization and a growing complexity of components. The results are higher power density and thus an increase of the operating temperature of electrical components. Occurring local overheating can lead to failure of the solder joints. Since electronic modules include temperature-sensitive elements it is usually not possible to use higher melting and therefore more reliable soldering materials. The silver sinter pastes developed by Nano-Join have been designed for applications in power electronics and allow for connections with highest thermal/electrical conductivity at simultaneously low process temperatures and thus creates more reliable and durable connections. Due to nano effects, dense and massive silver layers can be created pressureless below 250° C on various surfaces, e.g. directly on copper. Nano-Join is currently setting up development projects with large industrial companies that consider the technology state-of-the art and very promising. According to current market studies, the overall market volume for interconnection technologies in power electronics was around $10bn in 2012 worldwide at an annual growth rate of 10%. As established methods like wire bonding or conventional soldering are expected to remain predominant processes, experts estimate the substitution potential at around 10%, leading to an overall market volume up to $1.3bn in 2020 for sintering processes. As a team, Nano-Join has more than 10 years of relevant industrial and entrepreneurial experience.

Biography
2009: Graduation as Dipl.-Ing. in Material Science/ TU Berlin 2009 - 2015: Research Assistant at Chair of Joining and Coating Technology/ TU Berlin 2012 - 2015: Head of Group Microjoining & Laserprocessing at Chair of Joining and Coating Technology/ TU Berlin Since May 2015: EXIST scholarship holder at TU Berlin/ Start-up project: Nano-Join

Non-destructive high-resolution 3D imaging for next generation packaging

Capria, Ennio
Business development manager
Nanoelec Advanced Characterisation Platform

Abstract
With a density of integration continuously increasing, driven by a need of an always growing power efficiency and performance, 3D integration represent today the most promising strategy to adopt for next generation packaging. Although, various designs are considered, whatever the proposed technology, all of them share the same need to find critical defects (to be correlated with failure events) or to verify the compliance of structural elements in the bulk. X-rays are a powerful tool for this kind of analysis, in particular because they allow a non-destructive approach. 3D characterisation of the device can be obtained, whilst keeping the device functionality, enabling multimodal characterisation and in-situ/in-operando analysis. However, today, the instruments delivering 3D X-ray imaging ("computed tomography") available for conventional laboratory purposes, offer a too poor resolution, compared to the needs of nano-electronics. Thanks to the power of synchrotron radiation, this limit can be now overcome. This talk will illustrate the opportunities offered by synchrotron X-ray 3D imaging operated at the European Synchrotron in Grenoble (France) in collaboration with CEA-LETI. We will describe the unmatched characterisation opportunity offered by the new generation nano-tomography instruments on some standard 3DIC components. This presentation will demonstrate the power of this novel investigation tool, and their importance to boost the packaging innovation. Moreover, we will describe the complementarity between synchrotron X-ray 3D imaging and other traditional nano-characterisation techniques, to offer a multi-modal/multi-scale/multi-technique approach to the future challenges of characterisation in micro and nano-electronics. Finally, we will introduce the Nanoelec Advanced Characterisation Platform, which has been recently established in Grenoble, in order to offer these characterisations on a service based approach.

Biography
Dr.Ennio Capria gained his PhD in Applied Physics at Cranfield University (UK). He then undertook a series of academic and industrial positions in different sectors of nanotechnology. In his research career he has worked on the development of nanobiosensors and on nanocomposites for various applications. In 2011 Ennio joined Elettra where he worked on manufacturing of optoelectronic devices and particularly their characterisation with synchrotron light. Finally, from September 2013 Ennio joined ESRF as the IRT NanoElec Industrial Liaison Engineer, dedicated to the domain of micro-electronics. Ennio has a strong background in the application of a wide range of synchrotron techniques to industrial and applied R&D problems.

Wafer Handling Challenges

Karasikov, Nir
Senior Vice President & Vice President of Research & Development
NANOMOTION

Abstract
The MAGNET Metro450 consortium WP1 is addressing the wafer handling challenges of the evolving Semicon market., including increased throughput, accuracy and cleanliness. The challenge is further manifested by the increase in wafer dimension to 450 mm. Inherently the stage mass increases according to diameter squared or cubed and can reach a moving mass of 100 kg or more. Achieving a high natural frequency, typically required for a precision motion system is becoming practically impossible and advanced solutions of perturbation suppression are being developed. Flatness and Cleanliness are also key factors and the requirements are setting sub-micron flatness and 1 particle contamination for 1000 wafers. The consortium is addressing these challenges by a set of innovative multi disciplinary motion solution developments for ambient and vacuum environment,. Advanced solutions are described for contact less acoustic levitation chuck, super flat stage and chuck, XYZT fast stage, fast tracking focus mechanism and Z stage, advanced nonlinear control algorithms to facilitate fast convergence to nanometer accuracy, vibration modeling, passive damping and suppression, piezo-based vibration suppression and advanced composite material structures to yield high stiffness in lower mass. Actual designs, prototypes and results are presented and discussed. The consortium is now in its 4th year out of 5. Basic technologies are being developed. Novel building blocks were already demonstrated and the ultimate objective is to integrate the innovative development into a combined demonstrator that will be the base for the next generation motion platform for the 300 and 450 mm wafers, compatible with 10nm nodes.

Biography
Dr. Nir Karasikov - Nanomotion Senior Vice President & Vice President of Research & Development Dr. Nir Karasikov is Nanomotion's senior Vice President, and Vice President of Research and Development. Dr. Karasikov joined Nanomotion in 1997. Prior to joining Nanomotion, Dr. Karasikov was involved for many years in various hi tech industries, leading the development of infrared systems, electro-optic systems, laser based metrology systems, security systems, image analysis systems and precision mechanical systems for microscopy. Dr. Karasikov has vast experience in developing and introducing new pioneering technologies into the market and in collaboration with major worldwide corporations. Since achieving his Doctorate in Material Science and Solid State Physics from the Technion, Dr. Karasikov has authored over 20 articles in his field, and has invented and patented applications in electro-optics, inspection and piezoelectric related fields. In the Metro450 consortium Dr. Karasikov manages WP1 and is a member of the consortium Scientific Committee

Sub-wavelength Holographic Lithography

Rakhovskiy, Vadim
CTO
Nanotech SWHL Gmbh

Abstract
Nanotech SWHL offers investment opportunity in revolutionary photolithography - Sub-Wavelength Holographic Lithography for production of IC, MEMS, Sensors. The technology is based on unique mathematical apparatus. It allows to generate images not possible with traditional projection lithography and provides much lower cost of ownership for anybody who is or wants to engage in the production of MEMS, Sensors, IC's. Physical concept of the technology has been proven theoretically and experimentally. Test topology was produced on photo resist. 4 RF Patents and 1 US Patent received for the technology; 3 US Patents approved; 2 US patent applications pending Partnerships established with several leading European semiconductor companies who have expressed interest in the project.

Biography
Professor Rakhovskiy graduated from Physical Chemistry Department of the Moscow Institute for Steel and Alloys. Ph.D. degree in physical electronics from the All-Union Electrotechnical Institute and the Doctor of Science Degree in Plasma Physics from the Leningrad State University. Full Professor in plasma physics and chemistry Holds more than 90 patents in the field of high-voltage technology, physical electronics, surface analysis, microelectronics and nanotechnology Professor V. Rakhovsky founded Project SWHL in 2002.

Dimensional & Material metrology to meet industry growing needs

Wolfling, Shay
CTO
Nova Measuring Instruments

Abstract
Dimensional & Material metrology to meet industry growing needs

Biography
Dr. Shay Wolfling is Nova's Chief Technology Officer, since 2011. Prior to joining Nova, Dr. Wolfling was an R&D manager at KLA-Tencor-Belgium (formerly ICOS Vision Systems), and a founder and VP R&D of Nano-Or-Technologies (a start-up company for 3D optical measurements). Shay holds a B.Sc. in physics and mathematics from the Hebrew University of Jerusalem, a M.Sc. in physics from Tel-Aviv University, and a PhD in physics from the Hebrew University of Jerusalem.

How More-Than-Moore technologies impact every day applications

Wetzel, Jeff
Distinguished Member of Technical Staff
Novati Technologies

Abstract
Many of today's systems are beginning to hit their performance limits based on conventional packaging. Platforms in medical electronics, exa-scale computing, telecommunications, night vision and wearable electronics are all key platforms that will be significantly impacted by the implementation of 2.5 and 3D packaging. As sensors are integrated into more applications, the need for a higher level of integration becomes even more important. Novati's emerging packaging capabilities are a national asset that promises to become key in addressing many of these current and future needs. Novati has developed world leading expertise in 2.5 and 3D packaging. This includes integrated circuits and platforms requiring mixed technologies & heterogeneous materials such as III-V on silicon, etc. Further, by leveraging its advanced copper backend, Novati is able to take incoming wafers before interconnect, complete the metal routing interconnection and perform the wafer-scale packaging. This direct from foundry to packaging capability is an exceptional advantage within the U.S. allowing more advanced packaging solutions to be utilized while maintaining quality, yield and security. In addition to copper backend process, Novati has three, unique, first-in-country packaging technology elements that are enabling for 2.5D/3D packaging: 1. FaStack® stacking technology 2. Direct Bond Interconnect (DBI®) technology 3. ZiBond® Direct Wafer Bonding Using these elements, Novati is able to integrate with vertical interconnects and pitch far in excess of the rest of the industry having assembled devices with more than 10 million vertical interconnects per layer and up to 9 device layers within a 3D architecture. This presentation is designed to summarize each of these enabling technologies, and the value they provide for advanced 2.5/3D packaging, today.

Biography
Author's name: Jeff Wetzel, Ph.D. Title: Distinguished Member of Technical Staff Contact info: (512) 356-2320 jeff.wetzel@novati-tech.com Dr. Jeff Wetzel is the Senior Staff Technologist responsible for technical inputs for business development and identification of new process technology to enhance Novati's capability. He performed Technical/Project mentoring of Advanced Memory, BioMEMS and 3D TSV programs at SVTC. Technical Management of advanced transistor programs in ATDF/SeMaTech including MUGFET, mobility enhancement, 3D TSV, Dual Work Function/Metal Gate and Phase Change memories. Experienced in introducing new materials/processes in CMOS fabs from Proof of Concept Phase through Manufacturing Transfer. Experienced with Design of Experiments methodology for process integration/development and yield enhancement. With more than 25 years experience in leading and managing advanced CMOS process technology development at IBM, Motorola, Tokyo Electron and SeMaTech. Dr. Wetzel completed his Post Doctoral Research at IBM T.J. Watson Research Laboratories, Yorktown Heights, NY. His Ph.D. in Metallurgical Engineering, M.S. in Metallurgical Engineering, and B.S. in Chemical Engineering, all from Columbia University, NY, NY.

New method for reticle lay out, enabling singulation quality improvement and minimum saw lane

Kamphuis, Tonny
Manager Assembly Industrialization
NXP

Abstract
For production of integrated circuits, optical and process control modules, (OCM and PCM) are usually applied to control the placement of reticle fields (RF) on the wafer and check the wafer fabrication process. Once the wafer is finished, the OCM/PCM is no longer needed and actually are making the process of final die singulation more complicated. Increasing quality requirements on sidewall cracks and chipping, require new methods to do die singulation. These methods, plasma etching for instance, require OCM/PCM to be placed in such a way that at least a lane of 10 micron free of PCM/OCM is available. For conventional wafer technology nodes, commonly used by OEM suppliers, alternative methods have been developed to enable this. For low K nodes, typically the PCM and OCM are placed in the saw lane, consuming unnecessary large area of silicon and making the die singulation difficult, due to saw lane has to first be freed up from metal content using additional processes, such as laser grooving, which may have their own merits next to costs. A new method for the PCM/OCM placement will be proposed, suitable for low K technology nodes as well as conventional nodes. This method allows the use of the existing PCM/OCM, without impacting the low K wafer manufacturing other than the need for a new reticle, while at the same time enable saw lane width reduction and non-mechanical die singulation processes.

Biography
Tonny Kamphuis Mechanical Engineering, Twente University Philips/NXP since March 1986 Assembly Industrialization Manager Package Innovation & Subcon Operations NXP Netherlands

PISTON: a production platform for high-end imagers

Van den Branden, Gerd
System Development Manager
ON Semiconductor

Abstract
This paper presents the PISTON test head. PISTON stands for Pretty Image Sensor Tester from ON Semiconductor. It has been designed to support production test for the full CMOS image sensor product portfolio with a unique focus on high-speed and high-performance CMOS imagers. For these high-end imagers no existing tester solution was found to be available on the market. The PISTON test head can be used for both device as for wafer sort test. Device test is done in dead-bug mode, such that the optical area of the imager faces the light source system that is integrated in the test head. A single loadboard PCB design can accommodate both sort and device test. This reduces the development effort and cost for new DUT boards. The loadboard requirements have been minimized to contain only passive components. The tester resource modules consist of commercial PXI(e) modules in combination with proprietary PXIe frame grabbing, synchronization, timing engine, and light source modules. All tester modules are calibrated to a golden standard. Calibration term violations are managed and monitored by the proprietary 64-bit SW framework. An overview of the tester module configuration will be presented. One of the benefits of the PISTON test head is the ability to support custom interface protocols. It does this for interfaces up to 500 MHz while maintaining per pin pintest on all digital IO and reference voltages. PISTON makes use of a single PCIe (x16) communication link to the host machine controller providing a high-BW data link for image and result data transfer to the host pc. The PISTON supports DMA link setup from frame grabber to machine controller, GPU, and between frame grabbers to optimize data transfer times and test time performance. In the paper a comparison on key performance parameters with commercially available testers will be presented. The key differentiators that justified ON Semiconductor to invest in this custom PISTON development will be highlighted.

Biography
Gerd Van den Branden received the Master's degree in Electronics from the KULeuven (campus De Nayer), Belgium, in 2003. He started his career at the Erasmushogeschool Brussel as a scientific researcher on a project on dynamic reconfiguration with FPGA technology. In 2004 he became assistant professor at Erasmushogeschool and joined the ETRO research group of the VUB. In 2007 he joined the CMOS image sensor group of Cypress Semiconductor as a test engineer, working on the completion, release and deployment of an image sensor test platform and responsible for transferring production test to South-East Asia. Since 2011 he is leading the System Development group of the Industrial image Sensor Division of ON Semiconductor where he is responsible for providing all HW, SW, firmware and infrastructural tools and equipment to characterize and test high-end CMOS imagers.

Small is Beautiful - Time-to-Market Estimates with 'Smart' Data Analyses

Karner, Gunther
Director
optimiSE

Abstract
Statistical Data Analysis is recognised as a method for extracting knowledge from large data sets. The latest example is 'Big Data', which claims to explain 'everything'. In semiconductor production, however, the application of this doctrine runs into a serious obstacle: (i) The crucial phase in the semiconductor life-cycle is the ramp-up period, characterised by the quest for maximal quality in minimal time-to-market. Naturally, during this span the amount of analysable test data is (rather) limited. (ii) Once the roll-out is achieved, the data volume grows rapidly. Yet, the coercion for test optimisation declines proportionally to the number of STDF logs and data graveyards sprawl while the engineer's mind is already set onto the next product. Thus, when the talk is about New Product Introduction (NPI) in the semicon industry, the order of the day is 'Smart' rather than 'Big' Data! The present note introduces a new approach to the analysis of test data collected during the NPI phase. The backbone of that algorithm is Trend Estimation, a statistical technique allowing the construction of a model independent of 'anything' known about the underlying process. Trend Estimation employs the Ordinary Least Square Estimator as the best linear unbiased estimator, if the requirements of the Gauss-Markov Theorem are met. Therefore, the first part of the analysis demonstrates that the specific Trend Model indeed represents the NPI test set-up. Thereafter, the NPI tests are qualified with respect to their temporal and spatial coherence into stationary and non-stationary entities by means of a Time Series analysis. To accelerate improvement of non-stationary tests, a drill-down feature relates jumps in sublot autocorrelations to local quality issues on the wafer. It acts as a precursor to root-cause analyses done by specialists. At last, based on the analysis of current data, a prediction on the time remaining to reach stationarity is presented for each test.

Biography
Born 1959, Austrian Nationality, married PhD in Mathematical Physics from the University of Graz, Austria Research and Teaching in Germany, France and the US Founder of optimiSE GmbH in 2001 (as spin-off from the University of Karlsruhe, Germany) Executive Director of optimiSE ever since Knowledge in mathematical modelling and evaluation of non-linear processes (such as testing of semiconductors)

Status and Prospects of OLED Lighting Technology

Fleißner, Arne
Development Engineer
OSRAM OLED GmbH

Abstract
OLED lighting technology offers many interesting features for various applications. From a design perspective, OLEDs enable high-quality glare-free illumination from very thin light sources with a superb off-state appearance. Furthermore, OLED is an efficient light source with the potential to complement LEDs in the SSL revolution. The increasing number of OLED-based luminaires introduced by luminaire makers highlights that OLEDs are the key emerging technology for general lighting. In addition, the automotive sector has become highly aware of OLED technology, as testified by the host of recent automotive design studies. Considerable challenges still remain, but we anticipate that once OLED reaches a certain base performance in efficiency, lifetime, robustness and cost, it will enter the lighting and automotive market. We will review recent R&D highlights that have clearly demonstrated the potential of OLED technology for efficiency and operational lifetime. In our view, automotive will be the first volume application. Market entry will be driven by differentiators against other technologies, like free-form large-area homogeneous emission of rigid OLED panels, and afterwards flexible OLEDs will provide the next major advancement in lighting technology. We will discuss recent progress in the area of flexible OLEDs that provides an encouraging view on the prospects of OLED lighting with a thin and flexible form factor. Special attention will be paid to the results of the BMBF-funded R2D2 research project, in which partners along the complete value chain from materials research to end users have been working on production capable processes and technologies for flexible OLEDs. Within this project, OSRAM OLED has scaled up the sheet-to-sheet manufacturing of metal-foil based OLEDs which have then been evaluated by automotive end-users in modulisation tests.

Biography
Dr. Arne Fleißner was awarded his PhD in Material Science in 2008 at the Darmstadt University of Technology, Germany. Until 2013 he was working at Cambridge Display Technology, UK, where he developed flexible low-cost low-information-content displays based on all-printed organic light-emitting electrochemical cells (OLECs). Dr. Fleißner joined OSRAM OLED in 2013 to take up one of the key roles in OSRAM's flexible OLED lighting R&D team.

Chip Interconnect in LED Packages - Methods and Materials

Galesic, Ivan
R&D Engineer
Osram Opto Semiconductors

Abstract
A wide variety of interconnect methods are applied in packaging of light emitting diodes (LED). The technologies mostly coming from IC industry and using LED specific materials for optimized and stable optical performance. Development activities have to consider that the LED market segments automotive lighting, general lighting and consumer electronics have different requirements in terms of performance and cost. Important aspects for the selection of appropriate substrate and interconnect materials are power class and thermal management as well as reliability and life time requirements. In terms of quality the understanding of degradation mechanisms in LED packaging is a crucial factor. The challenge of materials development for mass production of high brightness LEDs is to use inexpensive materials with stable optical properties (no discoloration) under operating and aging conditions (heat, current, light, humidity and reactive gases). In order to contribute to the continuous increase of luminous efficacy of LEDs the reflectivity of packaging materials (metals and polymers) have to increase. Adhesive bonding and soldering are established techniques for LED die attach, whereas sintering is less common. Adhesive bonding is carried out with electrically conductive or insulating adhesive materials based on polymer matrix. For chip soldering pastes and thin film techniques are applied. Adhesion of the LED die to substrate plays a key role for product performance and lifetime. In particular when forces caused by expansion or shrinking of polymer materials during temperature change "pull" at LED chip. The LED chip technology can be split into top emitting and side emitting type. For top emitting chips usually a metal based joint is formed, whereby for side emitting chips transparent or high reflective adhesive materials are needed. Additionally, the side emitting type requires a high reflective substrate surface like Ag platings, which has a limited corrosion stability.

Biography
Ivan Galesic is key expert for backend technology and materials innovation at Osram in Regensburg, Germany. He received a Ph.D. in 2000 from the Institute of Inorganic and Analytical Chemistry at University of Frankfurt am Main. In the same year he joint Infineon Technologies in Villach (Austria) and was responsible for wafer back-side metallisation and thermal processes (CVD, annealing and alloying). From 2003 to 2007 he joined Infineon in Regensburg and he developed thin-film chip soldering for power packages. In 2007 Ivan Galesic started working at Osram as R&D engineer for plasma processes. He is currently responsible for development and implementation of LED package substrate materials and platings (galvanic and electroless).

450mm plasma etch module

Cooke, Mike
CTO - OIPT
Oxford Instruments

Abstract
Plasma etching is one technique that offers direct productivity increase by scaling to a larger wafer size. We describe the development of a plasma etch module for 450mm wafers, within the ENIAC project EEM450PR. The requirement for uniform processing over a larger area triggered two significant changes in approach. At 300mm, a static table was used, with a wafer loading slot above the table. This chamber asymmetry was noticeable at 300mm, but acceptable. At 450mm, it could no longer be tolerated and forced a change to a vertically movable table, so that the wafer loading chamber opening was below the table during processing. Secondly, a tubular ICP plasma source was used at 300mm. The skin depth for power coupling into this plasma is of order 50 - 100mm, so that power is principally coupled into an annulus around the chamber edge. At 450 mm, this tended to starve the centre of the wafer of active species to drive etching, so the induction coupling geometry was changed to a planar form. A mechanical change for improved chamber access was also necessary, because the previous tilted lid method was not practical at the larger scale. Plasma simulation has advanced to the point that it was possible to examine alternative geometries, and even to perform sensitivity analysis, at least to the point of identifying the most critical dimensions, before design the first prototype hardware. We outline briefly an approach to simulation, and its usefulness to the design process. We present characterisation of the chamber and an etch process, together with an estimation of the cost of ownership compared to the equivalent 300mm tool. This is offered as a short presentation, intended to be joined to other partner contributions from the project EEM450PR M Cooke, G Hassall

Biography
Mike Cooke is CTO at Oxford Instruments Plasma Technology (OIPT), responsible for technical developments which have included plasma sources for etching and deposition, plasma-enhanced atomic layer deposition, and ion beam processing tools Geoff Hassall is Principal Development Scientist at OIPT, and developed the 450mm plasma etch module, with a novel large area plasma source.

Review of digital laser microfabrication for flexible electronics manufacturing

Karnakis, Dimitris
Technical Manager - R&D Projects
Oxford Lasers Ltd

Abstract
Diode-pumped solid state (DPSS) laser technology facilitates digital fabrication and can become a simple, low cost alternative to printing for flexible electronics. It offers high resolution, maskless direct-write additive or subtractive processing that can be easily reconfigured and scaled up as needed, paving the way for affordable mass customisation without the usual limitations of other production setups. Laser techniques such as (i) laser-induced forward transfer (LIFT) printing, (ii) selective laser sintering of conductive inks on top of functional layers, (iii) selective thin-film patterning of multi-layered stacks (P1, P2, P3) or (iv) laser surface functionalisation could be widely adopted for a range of materials on rigid or flexible substrates for prototyping or production. Laser technologies have been investigated for more than a decade on flexible electronics for manufacturing of OLEDs, OPV cells, logic circuits, RFID, biosensors etc. Despite the extensive studies practical problems remain, such as the degradation of processed film edge quality (delamination) or introduction of undesirable non-uniform spatial temperature gradients in sintering affecting process resolution and repeatability, etc and solutions to those will be discussed. Here, we review the state-of-art of both laser and beam delivery technologies (including ultrafast DPSS, laser beam shaping) for selective thin film patterning, surface functionalisation for controlled wetting, laser-induced forward transfer printing (LIFT) for liquid ink or solid donor targets, conductive ink sintering, via drilling, wafer cutting/dicing to make components such as displays, solar cells, organic transistors, sensors, etc. The advantages and limitations of each laser technology will be discussed. The presented work has been supported by projects FP7-PEOPLE-IAPP project Lasermicrofab, No. 324459 and OLAE+ Digiprint

Biography
Dimitris Karnakis (PhD, Hull University) is Technical Manager for R&D Projects at Oxford Lasers Ltd (UK) having spent time as Applications Engineer and Project Leader for laser micromachining systems since 2003. He is responsible for collaborative research and technology development for advanced laser micro/nanofabrication applications. Dimitris has 25 years' experience in laser technology having previously held various research and management positions at Exitech Ltd (Oxford), Japan Atomic Energy Research Institute (Osaka) and Hull University (Hull). He presents frequently at international conferences (> 80 papers) in the field of laser applications and referees regularly for optical engineering journals. He is currently interested in advanced laser beam shaping, ultrathin layer patterning, laser transfer LIFT, conductive material sintering and ultrafast laser processing of dielectrics

Oppert, Thomas
Vice President Global Sales & Marketing
PacTech

Biography
Biography Thomas Oppert Mr. Oppert is "Vice President Global Sales & Marketing" at PacTech in Nauen, Germany, a manufacturer of advanced packaging equipment for the microelectronics industry and a leading provider of subcontracting services for wafer level packaging & bumping. Earlier he held positions as Product Manager, Manager Sales & Marketing and Business Unit Manager in the advanced packaging industry. He earned a master's degree in Electrical Engineering from the Technical University of Berlin in 1995. Thomas Oppert is a senior member of IEEE-CPMT and IMAPS and author and co-author of more than 60 technical papers & publications related to advanced packaging, especially bumping and bonding processes as well as flip chip & laser soldering technology. He is an active member of the Organizing Committee of the SEMI Advanced Packaging Conference yearly held during Semicon Europa.

Plasma Cleaning Application

Windemuth, Reinhard
Sales Director Microelectronics Europe
Panasonic Automotive & Industrial Sales Europe GmbH

Abstract
Packaging is getting more and more important for MEMS and Sensor packages. Flipchip Process is more and more getting important to replace conventional COB technologies such as Dieattach and Wirebonding. Main target is to shrink the Sensor package size and increase the package reliability. Plasma Cleaning process can be used for improving any package reliability when different material are connected to each other. Such applies for Molding, Flipchipbonding, Underfill Wirbonding, Diebonding and other compound or interconnection processes. Panasonic provides manufacturing solutions for any Plasma Cleaning application. Basic applications will be described accordingly. Some Flipchip approaches will be mentioned and described. Some equipment requirements and features that are suitable for MEMS packages will be highlightes so far.

Biography
Degree of Diplom-Ingenieur in Process Engineering on Technical University in Munich / Germany in 1988. Since then Project Management & Sales for different kinds of Industy, mainly in chemical Industry. Since 1998 Sales & Project management in Microelectronics & Semiconductor Industry for F&K Delvotec, Wirebonding and Diebonding Technology. Profund experience in handling packaging projects in both Semiconductor and Device-Manufacturing Industry. Since 2006 Sales Director for Microelectronics Equipment at Panasonic Factory Solutions Europe (PFSE). Main target is to establish new PFSE business fields in the Backend and Frontend Industry in Europe: Dieattach, Flipchip, Plasma Cleaning and Plasma Etch Technolgies.

Longford, Andy
Consultant
PandA Europe

Biography
Andy Longford (C.Eng FIET)is Managing Partner (CEO) and Senior Consultant at PandA Europe, a technical & market Consultancy Company involved in Semiconductor chip Packaging and Electronics Interconnection. He has worked on chip package designs for a number of years and is currently involved with emerging chip package design analysis and technical support work. He is a member of a number of technical committees, including SEMI Europe (APC), and also provides Secretariat Services for IMAPS-UK. For further information contact: Andy Longford PandA Europe Oakbury House Mill Lane LAMBOURN Berkshire RG17 8YP Tel: + 44 1488 73512 Mob: +44 7710 209640 Email: andy@pandaeurope.com

Panono Panoramic Ball Camera

Pfeil, Jonas
President
Panono GmbH

Abstract
The Panono is a grapefruit-sized, ball-shaped camera with 36 camera modules embedded around it that fire simultaneously to capture fully spherical, 108-megapixel panoramic images. Viewing Panono panoramas on a mobile device with the free Panono App offers a unique immersive experience in which the viewer moves through images simply by tilting their device up and down, left and right, and all around as if inside the image.

Biography
Jonas Pfeil is a co-founder and the president of Panono GmbH, the company that builds the Panono Panoramic Ball Camera. He graduated with a Diplom (M.Sc.) from the TU Berlin, worked as a visiting researcher in Japan and participated several times in the German contest for young scientists "Jugend forscht" while still at school. There his team won the second place at the national level in 2002. He loves problems and climbing.

Embedded cameras on consumer and professional drones

Pochon, Benoit
Image, Video and Control Group Leader
Parrot

Abstract
Images from drones that are capable of flying a few metres above the ground fill a gap between expensive images provided by satellites and phone or action-camera based images limited to human-level perspectives. The field of applications of quadcopters or fixed wing drones is huge, and lead to a need for embedding various imaging systems, from high resolution camera, stabilizing system, multispectral camera or stereo and other depth sensors. As the regulation evolves, light weight drones (below 500g) becomes an important target, leading to new challenges in the integration of such imaging systems. Parrot, as a strong player in the field of consumer and professional drones, has gained experience in the integration of innovative camera systems, addressing the problem of weight, stabilisation, vibration, while optimizing image quality. The presentation will cover topics such as: - the design of high-end camera systems for drones - computer vision applications to assist piloting and gives autonomy to drones - other types of camera integration

Biography
Benoit Pochon has joined Parrot is 2002. During 7 years he worked in the audio field developing new technologies in voice processing and active noise cancelling. When Parrot pioneered the drone consumer market, he redirects in the field of image processing and specialized in the integration of cameras on drones. He is now leading a team of research engineers in the area of computer vision, image quality and control. He and his team are responsible for the definition and design of the whole image pipe, with a focus on the tight integration of multi-cameras with inertial sensors.

Arnold, Michael
Managing Director
PEER Group GmbH

Biography
Dr. Michael Arnold, Managing Director PEER Group GmbH, has over 25 years industrial experiences in high-technology areas. From 1981 - 1986 he studied Physics at the Friedrich-Schiller-University in Jena, Germany, where he obtained his PhD in 1994. Based on his history in different industrial sectors, Michael gained broad experiences in system simulations, software design and development, optical inspection systems, and device development for aerospace technology. Michael has been involved with factory automation software solutions for the semiconductor and solar industry since 2001 when he became Operations Manager of TRW and later in 2003 Managing Director of PEER Group GmbH in Dresden.

Wafer-scale CMOS image sensors for fast, low dose X-ray imaging

Bullard, Edward
VP of Business Development, Marketing and Sales
PerkinElmer Medical Imaging

Abstract
X-ray detectors are used in medical imaging for static, dynamic and 3D imaging. The most common technology in use today for digital X-ray imaging is indirect detection in which an image sensor is combined with a CsI scintillator. The scintillator converts X-ray photons into green light, which can be detected by an image sensor. A-Si photodiode arrays are the dominant technology in use today and are well suited to static X-ray applications, where their read noise is not a major problem. However, in dynamic applications their read noise is a problem, because the X-ray dose per frame is far lower. CMOS sensors offer an alternative with much lower read noise of ~1/10 of a-Si. This reduction in read noise results in a significant reduction in radiation dose in low dose fluoroscopy. CMOS sensors also permit higher frame rates, smaller pixel sizes and exhibit almost no image lag. This makes them well suited to orthopaedic and vascular surgery and other applications where fast, low dose imaging is required. The latest wafer-scale CMOS sensors for use in surgery have a pixel pitch of 100 µm and incorporate on-chip 14 bit column parallel ADCs. These sensors must provide multiple gain modes to support various different X-ray protocols and have a frame time of 15 ms. Although the fibre optic plate and scintillator block most of the X-ray radiation, the image sensor should be tolerant of X-ray radiation. The major challenge in producing an X-ray detector using CMOS sensors is producing a large active area without large gaps between modules. The largest die from 20 cm wafers is about 13 cm2. However, an active area of 30 cm2 is required for vascular surgery. To achieve this, Dexela developed a method of butting wafer-scale dies closely together and permanently attaching them to a fibre optic plate. To make a detector for vascular surgery a 2 X 3 array of 15 X 10cm2 sensors is used. Needless to say, this must all be achieved with a very high yield!

Biography
I am responsible for global business development, marketing and sales for PerkinElmer Medical Imaging, a leader in flat panel X-ray detectors using both a-Si and CMOS image sensor technologies. I was a founder and CEO of Dexela from 2005 until its acquisition by PerkinElmer in July 2011. Dexela developed X-ray detectors using wafer-scale CMOS image sensors for applications including mammography and breast tomosynthesis, orthopaedic surgery, angiography, dental CBCT, scientific imaging, electronics inspection and industrial NDT. Dexela also developed acquisition methods and reconstruction and visualisation software for breast tomosynthesis. ISDI is an innovative semiconductor design business specializing in wafer-scale image sensors and other ASICs for medical, industrial and scientific imaging including the design of devices for X-ray, electron, proton, optical luminescence and optical fluorescence imaging. I am a founder and director of ISDI.

Next step in electrical power consumption reduction.

Colin, Patrick
Global Product Manager
Pfeiffer Vacuum

Abstract
Several reports or benchmarks have already shown the significant overall power consumption impact of pumps and abatements in Semiconductor fabs. Many accomplishments and evolutions were achieved for pumps and abatements dedicated to clean and light processes. However the harsh process segment (CVD, Diffusion...) has not seen major improvements from sub-fab components. The next step for pump and abatement power consumption reduction is in these departments. These harsh application targets create challenges for power reductions as the process trend is to have increased gas flows and higher pumping speeds requiring larger pumps. Another challenge is the use of new gases and chemistries requiring more powerful pumps. Our study has demonstrated with an accurate dedicated harsh product design, the real pump and abatement power consumption impact can be drastically reduced without risk for the process.

Biography
Patrick Colin obtained a master degree in mechanical and electrical engineering (Dipl.-Ing.) at Ecole Nationale Supérieur d'Electricité et de Mécanique of Nancy, France in 1994 - since 1995 he has held several positions in adixen Vacuum Products (Pfeiffer Group). He first worked in R&D to develop high efficiency monitoring for vacuum pumps. After 5 years as Dry pumps Product Manager, he took the head of R&D development for dry pumps. Current position is now Global Product Manager for all dry pumps at Pfeiffer Vacuum.

Solutions for the Semiconductor Market

Sälzer, Daniel
Market Manager Semiconductor
Pfeiffer Vacuum

Abstract
Today, billions of transistors are inserted into a single microprocessor for computers. Incredibly large numbers of these semiconductor components are also incorporated in smartphones, flat screens, LED TVs, and digital cameras, to make them meet the ever increasing performance demands. Without the use of vacuum technology today's method of chip production would be unthinkable. With its broad product portfolio, Pfeiffer Vacuum offers comprehensive solutions for chemical and physical manufacturing processes that are commonly used in semiconductor manufacturing.

Biography
Daniel Sälzer has been working for Pfeiffer Vacuum at different positions since 15 years. He managed the Pfeiffer Vacuum operation in China for about four years and was responsible for the operation and development of Pfeiffer Vacuum Singapore for more than 2 years. Since a few years he is back in Germany and responsible for key customers in the semiconductor market. He holds a degree in Electrical Automation from the University of Applied Sciences Giessen-Friedberg.

From Chips in Organs to Organs-on-Chip

Dekker, Ronald
Professor
Philips Research

Abstract
Micro-fabricated devices are finding their way to the frontend of medical equipment, where they are the interface between body, or in general living tissue, and machine. They enable better and cheaper diagnostic equipment, they add "eyes and ears" to minimally invasive instruments such as laparoscopic instruments and catheters, they allow for un-obtrusive monitoring of body functions, they add functionality to implants, and they enable the development of better and personalized medicines. Despite their great promise it has been proven difficult to bring these devices out of the laboratory phase into production. One of the reasons is the lack of a suitable fabrication infrastructure. Much more than standard CMOS or MEMS devices, these medical devices rely on the processing of novel materials, especially polymers, in combination with advanced molding, micro-fluidics, and assembly technologies. At the same time these devices have to be fabricated under strict quality control conditions in a certified production environment. In the recently granted ECSEL project "InForMed" a supply chain for the pilot fabrication of these medical devices is organized, which brings together key European technology partners in an integrated infrastructure linking research to pilot and high volume production. The pilot line is hosted by Philips Innovation Services, and open to third party users.

Biography
Ronald Dekker received his MSc in Electrical Engineering from the Technical University of Eindhoven and his PhD from the Technical University of Delft. He joined Philips Research in 1988 where he worked on the development of RF technologies for mobile communication. Since 2000 his focus shifted to the integration of complex electronic sensor functionality on the tip of the smallest minimal invasive instruments such as catheters and guide-wires. In 2007 he was appointed part time professor at the Technical University of Delft with a focus on Organ-on-Chip devices. He published in leading Journals and conferences and holds in excess of 50 patents.

Key challenges of DRIE Technology for MEMS devices

Pilloux, Yannick
Business Development Manager for MEMS Market
PlasmaTherm

Abstract
MEMS devices become more and more tiny to be integrated in smartphone, tablets, as well as automotive industry. In addition, quality needs to be improved to keep reliable devices and to increase the yield per wafer. As for mature MEMS devices, production cost has to be reduced in order to be prepared for the large volume manufacturing for the Internet of Things ( IoT ) "Smart Home" and "Smart City". Complex MEMS devices can be very challenging to manufacture. Gyroscopes, accelerometers, and microphones are established devices in automotive and consumers products. Emergent new complex devices include pico-projectors and energy-harvesting systems. For many years Plasma-Therm has delivered the most advanced DRIE solutions for R&D, focusing on feature quality control (smooth sidewalls, notching control, and nanoscale etch). Now, Plasma-Therm is expanding into large production solutions, augmenting the Versaline® product platform with the introduction of DSE IV technology. This recent addition offers a competitive solution reducing the Cost of Ownership (CoO) for manufacturing MEMS devices. DSE IV innovations extend the extreme selectivity of silicon etching to oxides, polyimide, PBO and metals, resulting in the ability to etch silicon without damaging sensitive materials like aluminum, gold and copper without needing to protect these layers, making this technology ideal for MEMS devices containing shiny mirrors. The time-multiplexed anisotropic etching, also known as Bosch process, has greatly improved the MEMS manufacturing capability especially for deep etch requirement and is now extended to Thru Silicon Via (TSV) for 2.5D and 3D packaging. This presentation will focus on the trends and evolution of the Deep Silicon Etch technology for the MEMS Market and particularly on the most recent process needs. Challenges of DRIE technology to manufacture MEMS devices will be addressed in this presentation, from mature to emerging sensor.

Biography
Yannick Pilloux is Business Development Manager at Plasma-Therm, where he is responsible for the MEMS Market. Prior to Plasma-Therm, he was Product Manager at Tegal and Alcatel Micro Machining System for about 13 years, leading the DRIE technology for MEMS Industry as well as TSV applications. Yannick holds a Master degree from CESI Lyon France.

Challenges and Opportunities in the Manufacturing of Large-Area Organic Robust Imager for X-Ray Sensing (LORIX)

Trovarelli, Octavio
Director of Strategic Projects
Plastic Logic Germany

Abstract
Despite a regular growth in terms of volume and key features for the global market of X-Ray image sensors, such as analog-to-digital conversion, low operational cost, higher performance and throughput, the market penetration of flat panel digital detectors (FPD) for diagnosis still remains behind that of computed radiography (CR) & film. This is partially linked to the relative long time-to-market of a new modality in medical imaging, but also to some other factors like high costs of system ownership and a lower mechanical reliability of FPD detectors compared to CR & film for some diagnosis applications (e.g. portable). In this talk we will describe how the LORIX1 consortium, formed by leading European technology companies, is addressing the task of speeding up the FPD market penetration in the global X-Ray image sensors market using disruptive technologies. Following an introductory description of the partners and project objectives, we will describe the consortium competences and know-how covering the entire value creation chain - from organic materials manufacturers and technology providers to end-users - for innovative LORIX X-Ray image sensors. We will explain how the use of a cross-KET (key enabling technology), multi-disciplinary approach, combining advanced organic materials and manufacturing printing technologies with microelectronics and photonics is enabling our planned prototype development and demonstrators. Initial project findings and results will be presented. Furthermore, we will focus on the challenges and opportunities of using TOLAE technologies in the manufacturing of the innovative LORIX sensing plates by combining printed organic photodiodes either with active matrices of thin film transistor arrays on glass or on flexible, organic TFT-based plastic foils, depending on the targeted medical, NDT and security applications. (1)LORIX has received funding from the European Union's H2020 research and innovation program under grant agreement N°644103

Biography
Octavio joined Plastic Logic in 2010 as lead process integrator and subsequently took over the group of process engineering responsible for process development, process integration, technology transfer and innovation projects. Currently he is in charge of Plastic Logic Germany's strategic projects. Octavio has more than 15 years' experience in research and technology development in the semiconductor industry. Before joining Plastic Logic, Octavio was technology platform manager for wafer-level package technologies at Infineon Technologies and Qimonda. Octavio holds a diploma and PhD in solid state physics, an MBA and is a former Alexander von Humboldt Fellow.

Mierau, Wolfgang
Director Quality & Operations
pmdtechnologies gmbh

Biography
- born in 1950 - 1969 - 1980 studies (information technology), PhD and work at Technical University of Dresden/Faculty Electrical Engineering) - since 1981 in microelectronics, years of experience in engineering management, longterm at Zentrum Mikroelektronik Dresden AG, but also at International Electronics & Engineering S.A. Luxembourg (IEE) and since 2011 at pmdtechnologies gmbh - intermediate (5 years) Professor (information technology) at the Technical University of Dresden/Faculty Electrical Engineering - since 2001 working in the field of development of optical sensors (ASIC-development), especially 3D-sensors (time-of-flight sensors)

3D Time-of-Flight Image Sensor Solutions for Mobile Devices

Buxbaum, Bernd
CEO
pmdtechnologies gmbh

Abstract
Since William Gibson's visions* of VR and AR finally get omnipresent in mobile devices, sensing technologies are confronted with new requirements to solve the problems of Human-Machine-Interfaces. Neither VR nor AR can rely on classical input media like mouse or keyboard - special controllers are barely accepted while natural interface methods are the key. Proximity information has to be provided to augment real or virtual scenes or to assist the user for security and guidance reasons (environmental awareness). Moreover mobile systems have strong limitations in terms of form factor and power consumption. pmd's ToF (Time-of-Flight) based 3D-sensor camera systems will push this trend further due to their scalability, tiny form factor and low power capabilities. They enable touchless interaction in the near-field as well as 3D environmental awareness - already today even on mobile devices. No need for a baseline, robust and reliable calibration, operation from pitch black to bright sunlight are valuable criteria for pmd depth sensors to be a key component of an emerging mobile ecosystem. * ( Neuromancer, Virtual Light)

Biography
EDUCATION - Technical University of Darmstadt, University of Siegen - Master of Engineering, PhD in Micro-/Optoelectronics, MBA CAREER - Founding CEO/CTO of pmd in 2002 - pmd today is world's leading 3D ToF chip technology provider - 1st products launched 2005, more than 1 Million devices shipped up to date - More than 100 employees - Revenue with pmd-based products over 30 Million USD expected 2015 - Besides other design wins, pmd is partner in Project Tango as the 3D technology provider - Lecturer at the University of Siegen - Member of Advisory Boards

Multi Beam Sputtering: the vulgarization of ion beam deposition of thin films

Sortais, Pascal
Ingeneer
Polygon Physics

Abstract
Polygon Physics introduces a new approach to Physical Vapor Deposition to tackle the growing demand for more complex thin films (multicomponent, magnetic, very smooth & dense, on fragile substrates, etc). Key to bringing the production of such layers from the lab to industrial production are versatile, robust and high throughput systems. Existing technologies are mature and therefore struggle to adapt. With a new technology based on Ion Beam Deposition (IBD) we can offer an extremely versatile system that in addition is up to ten times smaller and cheaper than conventional IBD systems. Key to our technical solution is a miniaturized low-power ion source (patented). This reliable and maintenance-free source type enables the use of source arrays to create spatially separated and individually controlled sputtering points, instead of a single large one. Each point can thus be a different target material, and in combination with a smart geometry this enables full control of the deposition profile, in thickness and in composition. The use of a multitude of small sources instead of a single large one also generates an enormous flexibility in terms of the size and geometry of the samples that can be coated with this technology (from wafers to roll-to-roll, from wires to tube interiors).

Biography
Pascal Sortais is an internationally recognized ion source expert and co-author of ten patents. His approach illustrates his passion for creating bridges between basic research and industry. In parallel to a career in accelerator physics at CNRS (France), Pascal Sortais has been consultant for various companies, is before becoming an entrepreneur. Polygon Physics, founded in 2014, is his second company.

Flexible integrated circuits: Moving beyond Silicon

Cobb, Brian
Product Manager
PragmatIC

Abstract
Flexible integrated circuits are a novel approach to providing intelligence to electronic systems without the need for rigid, bulky and expensive silicon chips. Silicon ICs provide the core intelligence in every modern electronic device. Moore's Law has hastened this process, guiding a continual reduction in the key feature size of silicon transistors, allowing more complicated circuits to be fabricated at progressively lower costs. As costs have fallen, intelligence is able to be integrated into more objects, driving the growth of the Internet of Things. However, the absolute cost of a silicon IC can only be reduced so much - at some point, the very small size of the chip limits the ability to handle and integrate it into a complete product. This is in conflict with an increasing desire to add electronic intelligence to everyday objects, including low cost disposable objects, which require a far lower cost point. Flexible integrated circuits offer the potential to overcome both cost and form factor limitations of silicon, enabling ultra-thin and mechanically flexible ICs at significantly lower cost. Several key innovations make this possible, including: - Functional electronic materials that are much cheaper than silicon, and able to be formed in extremely thin films - less than 100nm thick, about 1000 times thinner than a human hair. - Patterning processes that are able to accurately define features in these thin film materials, also at very fine scale (less than 100nm), but are dramatically simpler and faster than the processes used in an expensive silicon fabrication plant. - Flexible plastic substrates enabling novel integration processes that can further simplify the production chain needed for many applications and allow seamless integration into fundamentally flexible objects such as paper and textile.

Biography
Dr. Brian Cobb received his BS in Electrical Engineering from the University of Virginia in 2004, and then went on to attend the University of Texas at Austin where he received his MS and PhD in Solid State Electronics 2005 and 2010 respectively. From 2011 to 2015, he worked as a Senior Researcher at the Holst Centre in the Netherlands, where he was a project lead for oxide TFT development and flexible display and circuitry applications in collaboration with both academia and industrial partners. Since September of 2015, he has been employed as the Product Manager for PragmatIC, focused on bringing flexible logic applications into production.

Production of Carbon NanoTubes with defined electronic properties for innovative applications in microelectronics

Bezugly, Viktor
CRO
ProNT

Abstract
For the development of the semiconductor industry and novel applications there is an urgent need for new materials which allow further miniaturization of active elements and enable increased energy efficiency and reliability of devices operation. Carbon nanotubes (CNTs) are nanometer-size objects and have extraordinary electronic and thermal conductivities. They are very attractive class of materials for the use in innovative electronic devices like CNT-based computer chips, sensors, displays and other. However, conventional processes to produce CNTs are not optimal, they yield mixtures of metallic and semiconducting CNTs, having also admixture of other substances like catalyst. This causes failures and dysfunctions of the CNT-based applications. Start-up project ProNT is engaged in the Production of carbon NanoTubes with defined electronic properties. Our products are "ready-to-use" materials, which have a high potential in the application in innovative electronic devices. Our know-how is a new method of catalyst-free production of CNTs with defined electronic properties, either semiconducting or metallic. Our production procedure yields high quality CNTs allowing the direct application by customers without a pre-treatment. We aim to provide optimally designed CNTs for the individual needs of customers from R&D and industry. The use of CNTs in microelectronic products of next generation will make these products more competitive in the fast changing field of electronic devices. They will allow our customers to keep the leading position on the market and to fulfil the needs of their end-customers.

Biography
Start-up ProNT is the spin-off project of the University of Technology Dresden, chair of Materials Science and Nanotechnology. We are an early stage project and we are looking for partners and potential customers from the microelectronic branch.

Digital integration: a path to lower system cost in imaging systems

Dupont, Benoit
Business Development
Pyxalis

Abstract
In many fields of imaging applications, the image is not at the destination of a human being. Instead, imaging data is used by machines to interpret a data, for instance: shape, thickness, color, intensity, etc. As a consequence, imagers are usually coupled to a rather complex digital system that configures the image sensor to acquire the correct data (window size, frame rate, sequence, gains,...) and perform post processing and image treatment on the acquired data. With nowadays technologies, it is possible to lower the total camera cost by integrating more on the sensor itself or on a dedicated digital chip. In this paper, and after considering various possible options, we describe a general approach using integrated microprocessors, sometimes dual core, to achieve more compact, more affordable cameras. We also present how this integration can also lead to a significant gain in camera development time and cost as the flexible digital sensors become easier to integrate. In particular, we will discuss how digital processing can be used to reconstruct High dynamic range directly at the sensor output. Finally, we will demonstrate that digital integration does not come at the expense of performance with measurements of a 2e- noise sensor using dual-CPU architecture on-chip.

Biography
Benoit Dupont received his PhD in physics from the University of Paris-Sud in 2008 and an IC design engineering degree from ISIM, Montpellier in 2002. He worked as digital system engineer and cmos image sensor designer at FillFactory from 2002 and 2005. He made his PhD research in partnership with the LETI and ULIS, Grenoble, in the field of infrared image sensors from 2005 to 2008. He worked as chief designer at Caeleste until 2015 where he joined Pyxalis Image Sensors, as business development manager.

3D Light Field Cameras for Machine Vision

Perwass, Christian
CEO
Raytrix GmbH

Abstract
Light Field cameras are a new type of 3D-cameras that capture a standard image together with the depth information of a scene. Metric 3D information can be captured with a single light field camera through a single lens in a single shot using just the available light. Raytrix has specialized on developing light field cameras for industrial applications. A patented micro lens array design allows for an optimal compromise between high effective resolution and large depth of field. Raytrix cameras are already in use in applications like volumetric velocimetry, plant phenotyping, automated optical inspection and microscopy, to name a few. The talk will introduce the technology, show a number of applications and discuss the redundant and important aspects of a light field image for applications.

Biography
Christian Perwass received his Ph.D. in engineering from Cambridge University, UK and his habilitation in Computer Science from Kiel University, Germany. He then worked in R&D at Robert Bosch GmbH developing automated optical inspection systems before founding the company Raytrix GmbH to develop and market 3D light field cameras for research and industrial applications. He developed the award winning multi-focus plenoptic camera, which became a unique enabling technology for a number of applications in research and industry.

450mm module readiness and direct benefit for 300mm yield improvements

JARRE, ALAIN
CEO
RECIF Technologies

Abstract
"450mm module readiness and direct benefit for 300mm yield improvements" A challenge of the 450 mm introduction is to demonstrate (after prototyping stage) the rationale which allows productivity increase for an IC manufacturer, with economics making business sense also for the Supplier. Notchless has been standardized taking the opportunity of the 450mm transition to enhance productivity. Recif, as leader in automation, had the opportunity to be involved from the standardization stage up to field trial using "Sorter/EFEM 450mm" installed at imec. Productivity enhancement is also possible at the R&D stage, through the cross-collaborative concept, the Recif tool installed at imec is evaluated using the "Demonstration Test Methodology" (DTM) in place at G450C and therefore considered as an offsite tool for G450C. Beyond this 450mm achievement, RECIF will also demonstrate how it was possible to retrofit some of the learning to their latest 300mm wafer handling prototype. It was recently installed at imec within a new collaborative work to demonstrate how it can benefit to the N7 pilot/production lines.

Biography
Alain has over 25 years of international experience in high tech industry (Semi-conductor, Telecom & Smartcard). Alain started his career with Schlumberger, where he held several technical positions. He then moved to STMicroelectronics for 10 years including 3 years in Japan. Prior to join Recif Technologies in July 2008, he was Deputy General Manager of the Mobile Product Line at Oberthur Card Systems. Alain holds a Master of Science in Electronic and Computer Sciences Degree and a MBA.

Jaffard, Jean-Luc
Consultant & Advisor
Red Belt SA

Biography
Jean-Luc Jaffard was born in Alès (France) in 1956 He studied Electronic and Microelectronic and has been graduated from Ecole Supérieure d'Electricité of Paris in 1979. He started his career 1980 joining Thomson- Semiconductor Bipolar Integrated Circuits Division as Analogue and Mixed Designer dedicated to Consumer applications. In 1987 after the creation of SGS Thomson Microelectronics he became TV Design Manager coordinating the development of the entire product family dedicated to Analog TV and VCR. From 1996 to 1999 Jean-Luc Jaffard paved the way of Imaging activity at STMicroelectronics managing the first internal projects and being at the forefront of the acquisition and integration of VLSI Vision Limited. He was then appointed Imaging Division Research Development and Innovation Director managing a large multidisciplinary and multicultural team spreaded around the world with responsabilities covering imager technology coordination, image sensors, image processing controllers and camera module development and industrialisation and the coordination of cooperative programs with partners and research institutes In 2007 Jean-Luc Jaffard was promoted Imaging Division Deputy General Manager and Advanced Technology Director in charge of identifying, selecting, sourcing or developing the breakthrough Imaging Technologies and Applications to transform them into innovative and profitable products In 2010 he moved to STMicroelectronics Headquarter to develop a new business line exploiting the wide range of Intellectual Assets. Multiple Licensing agreements have been concluded demonstrating the benefits of such business model Jean-Luc Jaffard owns multiple patents in semiconductor and Imaging domains and has been invited speaker in many conferences worldwide. In January 2014 he created the Technology and Innovation branch of Red Belt Conseil, to support High Tech actors like SME, Research Institutes, Start-ups, Analyst, Investors and public authorities

Segers, Rene
chairman
ReSeCo

Biography
After getting his degree from the University in Eindhoven, Rene Segers started his professional career at Philips. Rene held technical and managerial positions in various divisions from Philips, including Research, Consumer Electronics, the Centre for Manufacturing Technology and Philips Semiconductors which later became NXP. Technically, over the years the focus has broadened from just DfT in the first couple of years, towards Test and Product Engineering, Diagnosis, DfX and supply chain management. The last couple of years of his career at NXP, Rene was responsible for the Test and DfX strategy as well as for its implementation in the global NXP. Rene left NXP in 2009 and is since then active as an independent consultant, supporting mainly start-ups and smaller companies in developing their business. Rene maintains many contacts in the industry in Europe, Asia and the USA. Rene plays a key role in 2 European conferences, the EMTC and the ETS2. Between 1988 and 2004, Rene was also as a (part-time) professor at the University of Eindhoven, teaching DfT and Testing of electronic circuitry.

Koyuncu, Metin
Senior Project Manager
Robert Bosch GmbH

Biography
Dr. Metin Koyuncu is a senior project manager at the corporate research division of Robert Bosch GmbH, Germany. He is active in the field of electronic packaging for over 10 years. After his responsibility for development projects leading to mass production for the automotive industry, he switched to research on conformable and high density electronic packaging. He was the project coordinator of the EU funded project "Interflex" that focused on the development of heterogeneous integration technologies for a hybrid System-in-Foil. Together with his team Mr. Koyuncu is active in the field of flexible electronic systems, additive manufacturing for electronic packaging and molded interconnect devices. He is the author and co-author of a number of publications and patents in these fields.

Opportunities for additive manufacturing and printed electronic within Robert Bosch

Schaller, Andreas
Senior Expert
Robert Bosch GmbH

Abstract
Additive manufacturing has already a large share in the production processes of automotive engine control units. Due to the increasing requirements in power dissipation and devices tightness more and more, non-heat curing, paste dispensing and ink printing processes are implemented on the factory floor. Additionally for realizing new electronic functionalities processes like screen-printing and ink-jetting are, historically, in use for component and substrate manufacturing. Nowadays, driven by IOT AIT trends, such as flexible electronics, harsh environment and wireless sensors, new technological approaches are needed to integrate the customer required electronic functionality. On the way to a connected car new interaction concepts push the market for innovative user interfaces, e.g. "printed" gesture recognition. In the fields of consumer packaging heterogeneous integration technologies on flexible substrates are necessary. With a product portfolio of processing and packaging technology for the food, pharmaceutical, and confectionery industry, this could one relevant trend for Bosch Packaging Technology. The IOT targets the development of innovative electronic packaging technologies for individualization of mass products, especially sensor nodes in the key application fields like Smart Production and Smart Society. Combining flexible electronics and additive manufacturing enables the development of in principle - generic, highly reliable, complex systems but with the possibility of individualization by 3D-printing of the housings. Leverage additive manufacturing and printing technology will allow to increase the number and types of sensors as well as increasing the number of devices the sensor nodes can be easily integrated.

Biography
Dr. Andreas Schaller joined Robert Bosch's Automotive Electronics Division in 2011, currently acting as Senior Expert at the Robert Bosch Center of Competence "Connectivity". In 2009 he founded ASC - Technology Consulting to support the European businesses on the Internet of Things and joined OE-A. He previously worked for Motorola Labs, Germany, managing the Motorola Labs research area 'Short Range RF Communications' in Europe

Electrical Overstress (EOS) of Semiconductors (SC) in Automotive Applications, Root Causes, and Conclusions

Thienel, Christoph
Head of Department
Robert Bosch GmbH

Abstract
In automotive business customers urgently want to get solutions in case of damaged parts. Thus a short, simple, consistent description of EOS is mandatory. Today there are many diversifications of EOS. We try to describe the EOS phenomenon from customers` point of view by a simple and universal, but consistent approach. So, we are striving for congruence of real electrical stress levels in applications and the amount of stress the device is able to withstand, the resilience. Our sole reference is the SC device specification. It is the exclusive interface between customer and supplier and it contains the entire information we need to know for judging about EOS. Electrical Overstress is every electrical stress situation for a SC beyond Absolute Maximum Rating (AMR). There are two kinds of destroyed SC devices: Weak parts (defect inside) are failing being operated under specified conditions and on the other hand parts being damaged by out of specification operation mode. In the first case supplier needs to improve his process (reduction of defect density) and in second case customers` processes must be investigated for EOS root causes. Electrostatic Discharge (ESD) is a normal electrical stress and is one part of our EOS definition. According to specification there is also a limit for ESD operation, which is not allowed to be exceeded. This understanding of EOS and ESD is very successful for our business. We will show several clusters of root causes we found and will conclude for all involved levels of automotive industry from supplier to final customer. We want to contribute to a better understanding and global avoidance of EOS.

Biography
1956 born in Bamberg, Bavaria 1984 diploma in physics from Friedrich-Alexander-University in Erlangen, Bavaria since 1984 with Robert Bosch GmbH in Reutlingen Experience in design, test, qualification, release, and analysis of SC for more than 25 years in SC area of Robert Bosch GmbH, Reutlingen. Therefrom 10 years intensive work in global EOS area. 100 linewalks worldwide in assembly lines of car manufacturers. Chairman of working group "first-mate-last-break" of German Electric and Electronic Manufacturers` Association, ZVEI, and edition of a whitepaper "Introduction of FMLB contacts in automotive industry", www.zvei.org/first-mate-last-break.

Connecting things and services. How Industrie4.0 increases the benefit of automation at the Bosch 200mm-Waferfab

Schuler, Thomas
project manager
Robert Bosch GmbH

Abstract
After a brief overview over the Bosch-RtP1-Plant in Reutlingen the presentation will show how highly automated production areas benefit from Industrie4.0 methods. An example will be shown how connection of things and services enables highest throughput of production tools as well as an extended usage of a transport system. A second example will highlight a modular automation concept that has been developed by using local intelligence instead of global logistics-management. Modularity ensures a simple rollout of high-automation in an existing fab-environment.

Biography
Dr.Thomas Schuler started his industrial career in 1998 at Robert Bosch GmbH after he recieved a doctorate degree in Physics from University of Stuttgart. Several years later after working on different positions in wafer production he entered the field of high automation in the 200mm Wafer Fab, where he is in charge of many automation solutions implemented at the Bosch-Wafer-Manufacturing site.

Automotive MEMS Sensors - Overview & future Trends

Kramer, Torsten
Teamleader - Senior Expert
Robert Bosch GmbH

Abstract
Bosch Automotive Electronics (AE) - headquartered in Reutlingen, Germany - is the largest manufacturer of micromechanical products and one of the largest automotive semiconductor manufacturers in Europe. Bosch has been at the forefront of MEMS (microelectromechanical systems) technology since the very beginning. Since the start of production in 1995, the company has manufactured well in excess of five billion MEMS sensors. Bosch supplies sensors for applications in the consumer electronics and automotive industries. The presentation will show this wide range of MEMS Sensors for automotive applications focusing on the necessary technologies developed within the last 20 years. These sensors measure pressure, acceleration, rotary motion and mass flow. With consumer electronics entering the vehicle the automotive demand for faster development processes, advanced designs and technologies is rising. However, automotive quality and reliability still need to be assured to fulfill consumer's expectations on vehicle safety and lifetime. In the second part of the presentation this topic will be covered, showing applications arising from consumer applications like combo inertial sensors or air quality measurements. Finally an outlook on further potential applications will be given.

Biography
Dr. Torsten Kramer graduated in Physics at University of Heidelberg and received his PhD in microsystem technology from University of Freiburg. In 2003 he joined the Robert Bosch GmbH in Reutlingen as a development engineer of Si-based sensor chips for mass flow- and pressure sensors. Between 2009 and 2011 he worked at Bosch Sensortec as a senior project manager for triaxial accelerometers for consumer applications. Rejoining Robert Bosch GmbH in Reutlingen in 2011 as a teamleader he is responsible for wafer process development of membrane sensors for automotive and consumer applications. Since 2014 he is appointed senior expert 'technology membrane sensors'.

Managing Variability in Complex Production Systems

Moll, Reiner
Director for Manufacturing Excellence and Production Planning
Robert Bosch GmbH

Abstract
In complex production systems, as the semiconductor industry, variability is one of the main contributors to high cycle times, high inventory and limited throughput. To extend existing market share and gain organizational growth, short cycle times, low inventory and high service levels are vital. The most effective way to reach these goals, without investing in capacity, is to consistently reduce variability in all processes and therefore to optimize the fab-wide operating curve. Robert Bosch Reutlingen introduced a new approach of variability measurement and variability reduction in its Wafer- and Sensorfab, which will be presented in this keynote. This systematic and proactive approach enables the organization to reveal equipments, which are responsible for high variability, that have not been on focus yet. By applying the systematic approach on regular basis in operations, sustainable throughput improvements and cycle time reductions can be achieved. Co-author: Tobias Weissgaerber, Senior Manager for Industrial Engineering, Dispatching and Line Control, Bosch

Biography
Reiner Moll Academic education in Electronics at the technical university of Munich Since 1988 working for Robert Bosch GmbH in several Business Units and Countries Professional Experience in -Production Planning & Logistics -Design & application of Production Systems -Industrial Engineering Tobias Weissgaerber is the Senior Manager for Industrial Engineering, Line Control and Real Time Dispatching of the Robert Bosch Wafer- and Sensorfab in Reutlingen. Prior to joining Robert Bosch GmbH, Tobias Weissgaerber has been the Group Leader for Production and Lean Management at a SME. He holds a Master of Business Administration from the ESB Business School at Reutlingen University and a Diploma Degree of industrial engineering from the Cooperative State University in Stuttgart.

Opportunities and Challenges Using Self-Navigating Systems in Semiconductor Fabs

Hantzschmann, Karli
Division Manager Automation
Roth & Rau - Ortner GmbH

Abstract
Self-Navigating Systems (SNS) with and without handling functionality are considered as one option to go beyond commercial and technical limits of traditional Automated Material Handling Systems like conveyors or overhead hoist systems. However, these SNS are still associated with various issues, which still have to be resolved before a widespread use becomes feasible. The presentation touches some of these challenges by the example of Roth & Rau - Ortner's SNS SCOUT®.

Biography
Dr. Karli Hantzschmann: - Division Manager Fab Automation - Roth & Rau-Ortner (since 2011) - Department Manager Global Customer Support Turnkey Lines - Roth & Rau - Ortner (2009-2011) - Senior Manager Automation - Qimonda (2008-2009) - Lead Engineer Automation Projects & Innovation - Infineon (2004-2008) - Lead Engineer Automation Operations & Maintenance - Infineon (2003-2004) - Systemexperte Automation / CIM - Semiconductor300 (1998-2002)

van Ulsen, Paul
CEO
Salland Engineering (Europe) BV

Biography
Paul van Ulsen Chief Executive Officer and President Paul is responsible for all aspects of corporate governance for Salland Engineering worldwide. Paul joined Salland in 1993 as a test applications engineer. He became Manager of the Test Applications business unit and soon demonstrated his sales skills as Managing Director for Salland Europe. Investors and managers recognized that Paul had a vision to build Salland into a major player in the market for semiconductor test and he was appointed CEO in 2001. His leadership has guided Salland to becoming one of the largest suppliers of test productivity products and services in the world. Prior to Salland, Paul worked for Rood Testhouse International as a mixed-signal applications engineering. He is a graduate of Windesheim Technical University in electronics and computer engineering.

Next Generation Track Processes for EUVL, DSA, NIL, E-Beam

Goeke, Mark
Product Manager
SCREEN SPE Germany GmbH

Abstract
The future of semiconductor IC patterning is at cross-roads between multiple lithography options. Many technolgies are being explored for complementary or alternative use, such as Immersion ArF multi-patterning, EUV, Multi-E-beam, Directed Self-Assembly (DSA), etc., with 450mm wafer size transition being on the horizon. In this environment, SCREEN is utilizing efficiently the industry model for semiconductor manufacturing, in which equipment and materials development is managed by pre-competitive collaboration for success. This talk will give an insight into cutting edge technologies and related challenges. In addition we will present viable options on the path down to the TN 14nm and below technology nodes.

Biography
Mark Goeke received his Master of Science in Photo Engineering from the University of Applied Science, Cologne in 1994. After holding various positions in lithography engineering he started working with Dainippon SCREEN Mfg.Co. (now SCREEN SPE Germany)in 1999. Here he moved to hold the position of the European Product Manager, responsible for technology and marketing for lithography and single wafer cleaning equipment.

SEMI Fab Investment and Secondary Equipment Market update

Tseng, Clark
Sr. Research Manager
SEMI

Abstract
SEMI will present latest year-to-date figures and forecast into 2016 of fab investment trend. The data will cover fab equipment spending trend by regions and by major product segments. With the rise of IoT opportunities, we will discuss the outlook of 150mm/200mm fabs capacity and investment trend at worldwide level as well as Europe-specific status. We will also look into secondary equipment market opportunities that is on the rise in recent years. We will provide our perspectives on the market drivers and possible future transitions.

Biography
Clark is a senior research manager at SEMI. His major responsibility is to track and evaluate semiconductor front-end fab investment in Asia Pacific region. His research also spans over LED, flat panel display and PV industries. His expertise includes in-depth analysis of the industry dynamics, as well as the fundamentals of market forecasting, competitive analysis, and strategic planning. Prior to SEMI, Clark worked for Qimonda as the manager at Strategy and Business Development division, where he managed market & competitive intelligence function in Asia/Pacific. Clark Tseng received a Bachelor of Business Administration and a Bachelor of Arts in International Relations from National Chengchi University in Taiwan.

van Nooten, Bas
Founder
Semi Consulting

Biography
Sebastiaan (Bas) van Nooten graduated with a Master's degree from the Technical University Delft in 1971. After his military service he was involved in processing and design of integrated circuits till 1981 at Telefunken, Germany. After his return to Holland he went to an IC design house as group leader. In 1985 he moved to the semiconductor equipment industry in several positions, mainly as European product specialist for several equipment types. He joined ASM in 1989, first heading the German office in Munich, later as Sales Manager Europe in the Dutch head office. In 2007 he was appointed as Director of European Cooperative Programs, where he was engaged in several European cluster programs, like the Steering Group Technology of Catrene and as project coordinator for ENIAC projects and two 450mm related FP7 Support Actions. Since last year he is an independent consultant to the semiconductor and semiconductor equipment industry. He is the current spokesman of the Steering Committee of the 450mm Equipment & Materials Initiative EEMI450. He has several patents on his name.

Altimime, Laith
President
SEMI Europe

Biography
Laith Altimime joins SEMI as president of SEMI Europe, as of October 1, 2015. Laith Altimime has more than 25 years of international experience in the semiconductor industry. Most recently, he held senior director position in business development at imec. Prior to this, Laith Altimime held leadership positions at Infineon/Altis, Qimonda, KLA-Tencor, Communicant Semiconductor AG, and NEC Semiconductors. Laith Altimime holds an Honors Bachelor's Degree in Applied Physics and Semiconductors Electronics from Heriot-Watt University in Scotland.

Georgoutsakou, Rania
Director Public Policy
SEMI Europe

Biography
Rania (Ourania) Georgoutsakou is Director of Public Policy for Europe with SEMI, the global industry association representing the manufacturing supply chain for the semiconductor and related industries. Her role is to support SEMI's global membership in evaluating and complying with European policies and legislation and to liaise with decision-makers to promote a balanced business environment and reinforce Europe's global competitiveness. Rania's areas of activity include EU institutional law, innovation, regional policy, health and social policy, Environmental Health & Safety and EU market access rules. She was previously Director for Lobbying and Thematic Coordination for the Assembly of European Regions, the largest European network of regional politicians, where over 10 years she led their work on the European Lisbon Treaty, health and social policy and e-innovation. Rania holds an LL.M in European Law and a MSc.Econ in European policy making.

Suvorov, Evgeny
Regional director
SEMI Russia

Biography
Evgeny Suvorov is responsible for SEMI development in Russia and CIS. He joined SEMI in January 2014. Prior to joining SEMI Evgeny worked 4 years for the Russian state corporation Vega operating in the radiolocation and telecommunication fields where he coordinates R&D activities of affiliated companies. Evgeny had a degree in Moscow State University, department Applied Math and Cybernatics in 1996. In 2006 Evgeny got a diploma of MBA in Russian Academy of National Economy and State Service (Presidential program).

Challenges in failure analysis of power and automotive microelectronics

Dallmann, Gerald
Division Manager Microelectronics
SGS INSTITUT FRESENIUS GmbH

Abstract
Semiconductor devices are rapidly entering new markets and applications. Power transistors are used in motor control applications like steering gears or in inverters for PV or wind power applications. To reduce volume and cost the transistors are combined with microcontrollers and new package types, requiring new technologies and material combinations and leading to additional failure and degradation mechanisms. On the other hand the automotive industry requires a zero failure policy and forces suppliers to understand every field failure in short time. The classical semiconductor device qualification procedure is very limited in statistics and is not capable to demonstrate and assure a zero failure level. Additional information has to be considered to understand reliability mechanisms and to improve quality. The talk shows some typical failure mechanisms found in a lab acting as a service provider for many different companies. Some weak spots are discussed with recommendations for improvements.

Biography
Division Manager at SGS Institut Fresenius GmbH in Dresden, Germany, since 2009. Main focus on material and failure analysis of semiconductor devices of client companies. 1995 Director for technology development at Siemens, Infineon, Qimonda, responsible for process integration, yield enhancement and material and technology development of DRAMs. 1990 Product manager microelectronics at Institut Fresenius in Dresden. Main Focus on failure analysis of semiconductor devices. 1986 Department manager electron microscopy at Zentrum Mikroelektronik Dresden (ZMD). 1986 Diploma in Microelectronics Technology and Semiconductor Devices.

Combine Stacked Metal Etch and Photo Resist Strip into a fully integrated efficient solution

Klaushofer, Thomas
Project Development
Siconnex

Abstract
Today the market demands increased productivity and reduction in costs. Siconnex exclusively brings Metal Etching, Cleaning and Resist Strip into one fully integrated package that inherently delivers high throughput and can bring >50% savings over other wet processing concepts. There is only one solution that can bring both Siconnex BATCHSPRAY^®. Productivity is driven by uniformity, yield and throughput. Siconnex BATCHSPRAY^® metal etch for example is outstanding in improving uniformity across the wafer and batch to batch at a much faster cycle time to single wafer wet or dry processes. Furthermore, the savings in cost come from overall cost of ownership improvements such as small footprint, less maintenance, reduction in chemical and DI water usage, exhaust, etc. At Siconnex continuous R&D and 100% focus throughout the company on its Siconnex BATCHSPRAY^® technology makes it the most robust process available. Typical etch uniformity rates of less than 2% within wafer and wafer-to-wafer are guaranteed, from smaller wafers through 200mm to even 300mm. Real time Optical End Point Detection of the etch process will also achieve excellent batch to batch uniformity, and furthermore makes the process independent from the actual composition - age - of the chemical. A typical process example is Al (and its alloys such as AlCu, AlSi, etc.) metal etch followed by Ti/TiN/Ti barrier layers and resist stripping with our mature SicOzone^TM process. Up to 5 processes in one sequence. Dry in - dry out.

Biography
Thomas Klaushofer is part of the Project Development department of Siconnex where he is responsible for discovering new process possibilities and cooperation with customers and research institutes. Further he is analyzing current wet processing equipment of existing fabs and detecting cost saving opportunities. Prior to this role, Mr. Klaushofer was in the R&D of Siconnex. He holds a master degree in mechatronics from the University of Linz.

The Role of MES in Industry 4.0

Labots, Sjaak
Delivery Manager
Siemens Product Lifecycle Management Software Inc.

Abstract
We are now mobile, connected and more automated than ever before. So what does that mean to semiconductor manufacturers? While each company will answer that for themselves, Germany's Industry 4.0 is one effort to outline what manufacturers can do to compete successfully. It paints a vision of smart factories using smart machines and materials to make smart products. Leveraging the Industrial Internet of Things (IIoT), certain parts of the physical and digital value chains can merge in a connected world. By its nature, an Industry 4.0 implementation will be incremental, not big bang. Manufacturing will still need people and centralized information applications in addition to the new IIoT data for the next several decades. This means that modern manufacturing execution systems (MES) will be required. Find out how semiconductor manufacturers can prepare themselves for Industry 4.0.

Biography
Over the last 14 years, Mr. Labots has extensively worked with Siemens' Camstar Enterprise Platform product suite in Semiconductor, Electronics and Medical Device industries. As a Delivery Manager, Mr. Labots is responsible for the successful delivery of Camstar Manufacturing solutions to Siemens customers. Mr. Labots has experience with Camstar's full project methodology and has actively participated in all implementation phases from business development and scope definition to system design. In addition, Mr. Labots has an extensive knowledge on the vertical integration with ERP systems and Equipment Automation layers. Prior to joining Camstar (now part of Siemens PLM), Mr. Labots spent 19+ years in manufacturing and systems design for customers in the Semiconductor, Electronics and Medical Device industries. Mr. Labots has worked in global multi-site projects for both manufacturers and integrators and has support over 25 implementations in 8 countries; and has the experience to recognize the challenges involved in complex MES projects. Mr. Labots has a Bachelor of Science degree in Computer Science from Hogeschool Utrecht (The Netherlands).

3D MEMS WAFER LEVEL PACKAGING USING TSVs & TGVs

Liljeholm, Jessica
R&D Project Manager
Silex Micorsystems

Abstract
Future demand for smaller size and lower cost MEMS devices will inevitably lead to the need for fully integrated sensor solutions which are much smaller than today's available form factors. In the area of 3D MEMS Wafer Level Packaging, Silex Microsystems has been focusing on developing solutions for heterogeneous integration and is now presenting interconnects with Through Silicon Via (TSV) and Through Glass Via (TGV). These 3D interconnection technologies enable vertical chip stacking by bonding, decreasing the packaging size (highly dense packaging) as well as the costs, thanks to the reduction in volume and mass. The TSVs enable shorter redistribution layers (RDL) and the smaller size translates to better performance since the signal travels a shorter route and parasitic capacitances decrease, thereby further improving the system performance. Silex will describe the manufacturing of metalized TSVs and TGVs for RF applications, where characterization showed low insertion losses for both TSVs and TGVs, with less than -0.04 dB per coplanar TSV at 5 GHz frequency, and around -0.006 dB at 5 GHz for the TGVs. Further, in a joint effort with MASER Engineering, an extensive reliability and failure analysis was conducted, focusing on understanding TSVs' failure mechanism. X-ray inspection was used to quickly identify defective TSVs. The ongoing quality and reliability investigation now focuses on identifying weak links through the application of high currents and the use of heat tomography technique to detect hot spots. A through molded via element was also created in collaboration with Fraunhofer IZM, using Chip in Polymer (CiP) reconfigured wafers, where the TSV interposers and CMOS biosensor chips were interconnected using a PCB-based redistribution layer, enabling low-cost heterogeneous integrated packaging, as well as separation between electrical connections and the active biosensor's wet I/Os. Silex will also present a solution for thin glass wafer handling.

Biography
Jessica Liljeholm, born 1987, received the Master of Science degree in Chemistry and Chemical engineering from Royal Institute of Technology (KTH) in 2011. She did her M.Sc. work at Expancel's R&D department and started to work at the same department as an Analyst engineer. Thereafter she started at Silex Microsystems, the largest pure play MEMS foundry, as a R&D Project Manager in 2011. She has been active in several of Silex customer programs as well as EU programs related to new TSV developments such as CAJAL4EU and EPAMO. She is now starting at an industrial PhD position at Silex Microsystems, which will aim for research within polyMEMS - Polymer-Based Integration Platforms for Future Generation Miniaturized Heterogeneous MEMS Systems. In 2013, she received the Best Paper for the 2013 IWLPC in San Jose, CA.

Lan, Albert
Senior Director
Siliconware Precision Industries Co., Ltd. (SPIL)

Biography
Albert Lan is the senior Director of Engineering Center in SPIL (Siliconware, Taiwan), which is 3rd biggest assembly house in the world now. He has over 20 years of job experience on semiconductor industry, especially focus on bumping and flip chip advanced assembly technology. Currently, he also take on vice chairman of Semiconductor Equipment and Materials International Taiwan Association and the chairman of TILA (Taiwan Intelligent Leader Association).

COLD SPLIT - a laser sabor for crystal it is

Drescher, Wolfram
Managing Director
Siltectra GmbH

Abstract
Crystalline materials are grown in large slabs of material, so-called ingots, while industry processes often require wafers, material slices of varying thickness and surface quality. Wafering of brittle semiconductor materials is frequently achieved using diamond- or slurry-based wire sawing processes. These sawing processes not only lead to kerf-loss of potentially precious material, but also impart surface roughness and subsurface damage to the crystal. These aspects of wafering using sawing processes lead to required polishing and grinding steps in the wafer manufacturing process, causing additional material losses and processing costs. In order to address these issues with conventional semiconductor material wafering, kerf-free technologies have been developed that promise to reduce - if not eliminate - kerf-loss, subsurface damage and grinding steps. In particular, so-called spalling processes use temperature-induced stresses to separate crystalline materials along crystal planes with well-defined thickness. We have developed the COLD SPLIT process that makes use of differences in coefficients of thermal expansion between a brittle material and a polymer adhering to the material surface. Cooling the conjoined materials below the glass transition temperature of the polymer induces stresses that lead to lateral material separation. Spalling processes, however, tend to be limited in their control of the achieved wafer thicknesses, and tuning the vertical location of crack propagation is complicated. As a solution, Siltectra has developed a laser conditioning process that can be easily integrated into the process chain. Here, the lateral plane of crack propagation is defined through laser conditioning of the material using short laser pulses and high-numericalaperture optics. The plane of laser conditioning can be arbitrarily set and is defined through the focal plane of the focusing optics, which allows for single-micron-precision.

Biography
Dr. Wolfram Drescher received his doctorate at Dresden Technical University's Faculty of Electrical Engineering. He gained his initial experience in industry at Applied Materials Inc. of Santa Clara, California. In 1999, he founded Systemonic AG Dresden, which was later acquired by Philips Semiconductors (now NXP). There, Dr. Drescher held the position of Advance Development Director, and made major contributions to the research, development and market placement of a wide variety of commercial chip sets in the field of mobile communications systems. In 2008, he established the start-up Blue Wonder Communications GmbH, where he held the position of the managing director. The fast growing LTE-chipset developer was acquired by Infineon Technologies AG, respectively Intel Corp. By end of 2012 Dr. Drescher joined Siltectra GmbH, Dresden, as CEO. Under his leadership Siltectra's "Cold Split" process evolved beyond PV application towards utilization in the optoelectronics and high-power semiconductors industries.

Nano and macro porous membranes à la carte

Lelonek, Monika
CEO
SmartMembranes GmbH

Abstract
Nano porous anodic alumina is a widely studied material that is used for corrosion protection of aluminum sur-faces or as dielectric material in microelectronics applications. For more than 40 years porous alumina has been the subject of investigations. It exhibits a homogeneous morphology of parallel pores which grow perpendicular to the surface with a narrow distribution of diameters and interpore spacings, the size of which can easily be controlled between 20 and 400 nm. Monodomain porous alumina templates with very high aspect ratios can also be synthesized by using lithographic preparation. The combination of self-assembly and lithography allows the preparation of porous alumina templates with various configurations of pore arrangement that are not accessible by other state-of-the-art methods. Macro porous silicon, prepared by an electrochemical process, has also gained interest in research for many applications which have a demand for mechanical and chemical stability as well as a high order of the pores. The pore diameters can differ from 700 nm up to 10 µm using lithographic pre-structuring. The standard deviation of pore diameter and interpore distance is lower than 5 %. Because of the lithographic pre-structuring technique macro porous silicon with its high ordered structure represents an ideal 2-D photonic crystal (PC) exhibiting novel properties for the propagation of infrared light within the pores. Because of the above mentioned unique properties, nano porous alumina and macro porous silicon can be used in a wide range of applications, such as filters, as platforms for multi-functional and micro mechanical sensors, for fuels cells, as platform for microsystems technology and microfluidics, and especially as templates for the fabrication of nanometer-scale composites, such as nanotubes or nanowires by electrochemical deposition or by using polymer melts.

Biography
About the presenter: Monika Lelonek studied chemistry at the Westphalian Wilhelms-University in Muenster. She focused on physical chemistry and started to work on her PhD thesis in the fields on nano porous alumina layers and their behavior on non-planar surfaces. During that time she founded the company SmartMembranes with Dr. Petra Goering in the city of Halle. As the CEO of that company she is responsible for the finances and sales. About SmartMembranes: SmartMembranes was founded by Dr. Petra Goering und Monika Lelonek in Halle (Saale) on 20th July 2009 as a spin-off from the Fraunhofer Institute for Mechanics of Materials. The company is the leading manufacturer of high-ordered porous materials from alumina and silicon with defined and adjustable membrane properties and structure parameters. SmartMembranes manufactures not only membranes on customers' request, they also develop new processes and products around the core business.

How innovation and eco-system in Europe can enable future requirements in automotive electronics

Boudre, Paul
Chairman and CEO
SOITEC

Abstract
Exciting new applications such as autonomous cars are driving electronics industry growth and contributing to innovations. Today's automobile designs have nearly 100 microprocessors; this number is expected to double in just five years (according to Clemson University's International Center for Automotive Research). Automotive electronics is a large market and is going through a major transition, as cars have increased computing power in both the drive train and the dashboard, for advanced driving assistance and infotainment for example. On the way to the autonomous car, increasing functionalities and new features will require the most advanced technologies while reliability, low-power and cost remain key. A European innovation like FD-SOI technology is a key enabler to meet future requirements in automotive electronics, such as high reliability, excellent soft-error performance, and well-managed leakage in high temperature environment (150°C). In addition, Europe has a leading position at all levels in the automotive industry. Automotive electronics is a great opportunity for Europe to provide a unique value proposition throughout the whole value chain, from substrate to cars manufacturers, giving Europe strong leading position on this growing market.

Biography
Paul Boudre joined the company in 2007. He was appointed Chief Executive Officer with effect from 16 January 2015. A semiconductor-industry veteran of more than 30 years, Paul Boudre gained extensive international experience through his previous positions managing industrial operations for IBM Semiconductor, STMicroelectronics, Motorola Semiconductor, and Atmel. From 1997 to 2006, he managed European operations for KLA-Tencor, one of the world's top five semiconductor equipment manufacturers. He was subsequently appointed Vice President for both the US and Europe. Paul Boudre holds a graduate degree in chemistry from France's Ecole Nationale Supérieure de Chimie de Toulouse.

Engineered substrates for low-power IoT devices

Piliszczuk, Thomas
Senior Vice President, Marketing, Business Development and Global Sales
SOITEC

Abstract
The ever-expanding number of mobile consumer electronics devices such as smartphones, tablets, cars, and wearable devices, we use in our daily lives, is driving the semiconductor industry growth, exceeding US$340 billion in sales per year. The Internet of Things (IoT) with its promising 50 Billion connected devices is expected to become the next fast growing technology mega-trend. In mobile consumer electronics and IoT markets, the end-user stringent requirements include faster processing, increased data rates, longer battery life and lower cost. In an effort to bring more performance, more functionality or less power consumption, innovation starting at the substrate level has demonstrated significant achievements. This includes radio-frequency silicon-on-insulator (RF-SOI) technology which is today in 99 percent of Smartphones. RF- SOI provides significant die cost advantage with increased performance and functionality for integrating RF front-end modules. In addition, fully-depleted SOI technology extends Moore's Law beyond 28nm to meet power/performance/cost requirements for low power SoCs. Concerning FD-SOI, the industry today is at a tipping point with strong industry support and a growing ecosystem including major leading foundries and fabless companies. Its low-power, significant performance, and cost benefits are making the FD-SOI technology attractive for mobile, wearable devices, and the Internet of Things, as well as automotive and networking applications. In this presentation, we will show how engineered substrates enable device performance and cost effective SoCs for fabless and foundries in digital, RF, power and other emerging applications for low power IoT devices.

Biography
Thomas Piliszczuk joined Soitec in 2009 as Senior Vice President of Marketing, Business Development and Global Sales. He is managing a large international team to support Soitec business at the worlwide level. Prior to Soitec, Thomas Piliszczuk was with KLA-Tencor, where he held various senior management positions related to business strategies and alliances with largest semiconductor companies worldwide. During his tenure there, Thomas Piliszczuk had responsibility of European Operations. Earlier in his carrier, Thomas Piliszczuk worked at Sematech managing advanced lithography projects. Thomas Piliszczuk received his Ph.D degree from the Ruprecht-Karls-Universitat Heildelberg in Germany, an electrical engineering degree from the Gdansk Polytechnic University in Poland and business degree from Stanford University.

Sovtest Micro LLC

Krekoten, Theodore
General Director
Sovtest Micro

Abstract
Founded in 2009 as a hi-tech startup company with support of #1 test equipment supplier in Russia, Sovtest Micro LLC has become a commercially viable semiconductor test equipment designer and manufacturer in the Russian and CIS markets. Located in Zelenograd, Moscow region, at the heart of Russian semiconductor industry, Sovtest Micro team has accumulated 250+ years of fruitful engineering experience and is ready to share it with the rest of the World. Our invariable motto is WE DO LIKE WHAT WE DO!

Biography
General Director in LLC «Sovtest Micro» Place of birth: Moscow, Russia Date of birth: 21/03/1980 Education: In 2002 graduated from the National Research University of Electronic Technology in Zelenograd, Moscow region, Russia In 1997 graduated from secondary school with advanced study in physics and mathematics with silver medal award in Zelenograd, Moscow region, Russia Career: From 2011 till present - LLC Sovtest Micro: General Director, Co-owner, Zelenograd, Moscow region; business occupation - semiconductor test equipment From 2002 to 2010 - OJSC Angstrem: last position held: Department head of manufacturing process automation

Architecture of an Efficient MEMS Final Test System

Brucke, Martin
Head of R&D Department
SPEKTRA Schwingungstechnik und Akustik GmbH Dresden

Abstract
MEMS final test systems face various requirements. On the one hand consumer MEMS require a short time to market and thus an early test qualification for a fast production ramp up as well as the capability to allow large volume production. On the other hand automotive or niche MEMS require an excellent scalability of the test system in order to adapt to the production volume in different product life cycles. This paper suggests a test hardware and software architecture that can be scaled from a two channel desktop system to a several hundred channel multisite production test system. Since the scalability allows the use of the same hardware platform at reasonable low costs in the development department as well as in the mass production, the setup and qualification of tests can already start in development phase and thus shorten the time to market. Furthermore it can be configured very flexibly to adapt to the requirements of new MEMS generations easily while still supporting older generations at the end of their life cycle. By focusing on technical parameters that are typically required for the final test of MEMS devices, all required functions like device power supply, digital interfaces and analog measurement capabilities are integrated on one board allowing an excellent scalability at lowest possible investment. By means of an onboard FPGA digital interfaces like I²C, SPI, SENT, JTAG, PSI5, CAN and others can be easily and flexibly configured on hardware level reducing the software coding effort. Additionally a microcontroller with real-time kernel on each board allows a parallel operation on a variable number of test channels without a high overhead in the communication between host and test system. The coding, qualification and deployment of tests is handled efficiently by a software framework that fits to the system and supports small development systems as well as complete production sites.

Biography
Dr. Martin Brucke received his PhD in Mechanical Engineering from the Technical University Braunschweig, Germany. He works since ten years as head of the SPEKTRA R&D department.

A New Alternative Low Cost Package Solution for High Bandwidth Memory PoP

Tsai, Jensen
Deputy Director
SPIL

Abstract
Package-on-Package (PoP) technology was widely used in mobile phones for the bottom flip-chip chip-scale package (FCCSP) digital AP to stack with a top wirebond low power double data rate (LPPDDR) chip-scale package (CSP). The bottom FCCSP package form factor and its pin up of top solder balls were limited by the LPDDR BGA matrix, which had been defined by JEDEC. Because of high-bandwidth memory requirements for smart phones, a lot of new PoP solutions to accommodate more I/Os between the top LPDDR memory package and the bottom digital application processor package are becoming a reality. In this study, HBW PoP is a 3D structure that combines an "organic substrate interposer" with an embedded mold compound in the bottom package as the connection interface with the top package is introduced. This design will bring benefits, not only providing more I/Os, but also more flexibility to accommodate different package sizes to stack on the top, for non-LPDDR devices like PMIC, RFIC, etc., to form multi-functional system-in-package (SiP) modules, or even the increasingly important applications of wearable electronics or the internet of things (IoT). That is, compared with a traditional PoP without an interposer, an additional organic substrate interposer (with full matrix I/O pad layout) can build a fully functional system and achieve the wide I/O memory goal. This structure, however, will bring some major assembly challenges, such as package warpage, mold compound voiding, and in-line process defect detectability issues. The solutions to solve those defects were developed with considerable engineering efforts. In the study, many mechanical simulation models and design of experiments (DOE) studies were used. Moreover, mold compound and substrate core material properties (such as the coefficient of thermal expansion [CTE] or modulus property adjustment) can effectively reduce package warpage. Subsequently, improvement of over package cost were addressed in the study.

Biography
Jensen Tsai is the Deputy Director of Engineering Center in SPIL (Siliconware, Taiwan), which is 3rd biggest assembly house in the world now. He has over 18 years of job experience on semiconductor industry, especially focus on wire bond and flip chip advanced assembly technology.

PORTELLI-HALE, Chris
Operational Programs Director
ST Microelectronics

Biography
Chris Portelli-Hale holds the post of Operational Programs Director in the Manufacturing Execution Excellence team within the Front-End Manufacturing & Technology R&D organization of ST Microelectronics, based in Rousset France. He holds a degree in Electronics Engineering from the University of Malta and joined ST in 1989 where he has held various positions is Test Engineering and Test Operations Management within different organizations and locations of the company in Malta, France and Singapore. Chris is Chairman of CAST the Collaborative Alliance of Semiconductor Test group which brings together several actors within the test arena from IDMs, Fabless and Equipment vendors.

Kirana: millions of frames per second with a megapixel CMOS image sensor

Turchetta, Renato
CMOS Sensor Design Group Leader
STFC

Abstract
CMOS image sensors are the preferred imaging technology for high-speed imaging. The technology has been slowly improving in terms of pixel rate since their invention and nowadays it is possible to have megapixel sensors achieving a speed of Over 10,000 frames per second. In order to get a step change in speed for the same type of resolution, a new approach was needed. At the Rutherford Appleton Laboratory, we developed a novel sensor. Starting from a standard 180 nm CMOS image sensor (CIS) technology, we developed CCD cells. The combination of these two imaging technologies allowed us to create a megapixel sensor that can both work as a conventional image sensor and continuously output images at a thousand frames per second as well as a framing camera recording almost 200 frames at 5 millions frames per second. In burst mode, the equivalent pixel rate is in excess of terapixels per second, i.e. over 2 orders of magnitude higher than any conventional CMOS image sensor. The talk will review the technology challenges and solutions and the performance achieved. It was also show how the collaboration between industry and a research laboratory could create a unique product that pushes forward the frontier of ultra-high speed imaging.

Biography
Renato Turchetta received the Laurea (Master degree) in Physics at Milan University (Italy) in 1988 and the Ph.D. in Applied Physics from the University of Strasbourg (France) in 1991. He was Assistant Professor there until 1999 before moving to the Rutherford Appleton Laboratory, near Oxford (UK), where, since 2005, he leads the CMOS Sensor Design group, which specialises in CMOS image sensors for scientific and other high-end applications. He is co-author of over 100 papers on solid-state detectors, low-noise, microelectronics and CMOS image sensors in international journals as well as of 8 patents on CMOS image sensors. He was on the technical committee of IISW2009 and is a member of the programme committee of Image Sensor Europe since 2011.

Energy Efficiency Design Rigs for the IoT Ragbag

Abouzeid, Fady
Senior Design Engineer
STMicroelectronics

Abstract
The IoT applications buzz hides a very heterogeneous spread of applications, classified by O Ezzratti in four fields: smart home, machine-to-machine, smart cities, wearable. While machine-to-machine has been existing for more than 10 years, the IoT buzz and expectations is focused on the wearable devices. This presentation reviews design techniques which can be used to optimize energy efficiency of such power constrained applications. The strongest lever to lower circuit power is well known: lower as much as possible the supply voltage until speed, variability or yields drops beyond specifications. Depending on power duty cycle various options can be used, here again the width of the application ragbag prevents us from making a definitive choice between leakage power dominated circuits and dynamic power dominated ones. Some alternatives will be presented. Another way of lowering power is design margins reduction so that the majority of dies do not pay for the low performance of a few. This can be done by addressing low performing devices through fresh process compensation and can be applied either a posteriori of the design or a priori with greater gain in the latter case. Similarly, temperature which adversely affects Ion at low Vdd can be used with great benefits. An alternative to low speed, low voltage option is to dynamically modulate Ion/Ioff by various way of embedded power gating or management either using a rush-to-sleep approach or dynamic voltage scaling. Last, a short review of STMicroelectronics' technology and design solutions enabling this pervasive power quest will be presented, it includes: - FDSOI 28nm with embedded Power Management IPs, dynamic biasing, low power memory and standard cells - 40nm embedded Flash technology

Biography
Fady ABOUZEID received the M.S. (2007) and Ph.D. (2010) in Micro and Nano Electronics from Grenoble University, France. Since 2007 he has been with STMicroelectronics, Central R&D, Crolles, France in a research and development group in charge of hardening and qualifying IPs for space and terrestrial environments, and ultra-low voltage and high energy efficiency circuit design. His current research interests include digital ultra-low voltage circuits for sub-130nm CMOS down to FDSOI 28/14nm and low power EDA solutions.

Le Pailleur, Laurent
Technology Line Management Director
STMicroelectronics

Biography
Laurent Le Pailleur is director for advanced Cmos technology line with STMicroelectronics, Crolles France. He previously enjoyed various positions as head of technology management (semiconductor, packaging and IPs) with ST-Ericsson, audio/power management product line and 2.5G mobile platform/3G mobile digital System-on-Chip product management at ST. This allowed him to develop deep understanding on RF, analog and digital technologies, architecture and system partitioning. Prior to ST, he has been working on mixed-signal video systems and imaging digital processors design with Philips Semiconductors. In 1989, he received the degree in electrical engineering from Caen National Engineering School, the M.S. degree in instrumentation and automation from Caen University and the Business degree from IAE (Enterprise Administration Institute). He participated to numerous international conferences and hold multiple patents.

Grant, Lindsay
Technical Director - Fellow
STMicroelectronics

Biography
Lindsay Grant is a Pixel Technology Expert in the Imaging Division of STMicroelectronics. He was born in Glasgow, Scotland and has a degree in Physics from St.Andrews University. Following university he moved into semiconductors and worked in product, device and process engineering with STC and Seagate. He joined STMicroelectronics, Edinburgh in 1999 at the time of their acquisition of VLSI Vision. With STM he has worked on the development of multiple generations of CMOS Image Sensor pixel & process technology from 5.6um to 1.1um pitch. For 5 years from 2007 he held the position of Process Development Manager for ST Imaging Division. Since 2006 he has managed R&D of Spad devices in CMOS. He has been a member of the steering committee for two European funded programs in Spad development. He has authored or co-authored more than 50 technical papers and conference presentations in imaging technology. He was an invited speaker at the ISSCC Forum on Image Sensors 2005, at the Fraunhofer IMS Workshops in 2006 & 2010, and at ESSDERC 2008; he has been on the Technical Program Committee for International Image Sensors Workshop 2009 - 2015 and between 2008 - 2014, has co-chaired the Image Sensors conference in London. Currently he manages a team working on Spad and pixel development, runs a program of sponsored PhD studentships and is a Director of STMicroelectronics R&D, UK Ltd.

Voltage-Domain BSI Global Shutter Pixels

Raynor, Jeff
Principal Technologist
STMicroelectronics

Abstract
The selling point for many image sensors is the number of pixels and the overall size or cost of the device. Consequently, most imaging pixels are of the "rolling blade" type, as their small size is a significant advantage in this regard. However, rolling blade pixels will create artefacts if the object is moving, and while a human is able to dismiss these artefacts as ugly or curious, these artefacts are a significant problem for machine vision algorithms, hence global shutter (GS) pixels are preferred if data is to be extracted from a moving image. Global shutter pixels include storage elements which allow all of the pixels to simultaneously sample the image and then be read out on a row-by-row basis. Charge domain pixels store the photo-generated charge and were preferred due to their smaller size and lower readout noise. Voltage domain pixels convert the photo-charge into a voltage and then store the voltage. This presentation will describe the operation of both rolling blade and global shutter pixels and examine their performance. It will show how the advances in process technology such as back side illumination (BSI) have allowed the size of voltage domain GS pixels to be reduced in size, as well as improve performance so that voltage domain sensors have larger dynamic range than charge domain pixels. Also discussed are the new features and functionality that voltage domain global shutter pixels offer which are not possible in either rolling blade or charge domain global shutter sensors.

Biography
Jeff Raynor is Principal Technologist at STMicroelectronics Imaging Division. He has designed pixels and imaging systems for many machine vision applications such as optical mice, touchscreens, wearables and biosensors with a diverse range of specifications from high frame rates, low frame rates, operating in UV / visible / IR and X-ray. He has authored more than 20 papers and is inventor on more than 40 granted patents.

Probe Card Identification via RFID

Sapienza, Massimo
EWS Europe - Advanced Automation team leader
STMicroelectronics

Abstract
At Electrical Wafer Sort (EWS), the probe card represents a fundamental and mandatory component of the test cell and hence a key entity for the process. Exactly like tester and prober, the probe card must be unequivocally and automatically identified for performing EWS testing as for any other usage. Once identified, it is possible to verify if it is the correct one for the intended operation. However, when the probe card is manufactured, it is not supplied with a solution for identifying itself automatically. To address this need, a low cost solution, called "Probe Card Identification via RFID", has been identified and implemented at ST EWS: Probe card identification task is achieved through Radio Frequency Identification, RFID. The choice of applying RFID derives from the need of finding a solution not embedded into the test cell, with minimum hardware impact and not introducing any limitation into the regular test cell operability. Likewise, RFID technology offers the big advantage that the reading operation requires neither any physical contact between receiver and transmitter nor line of sight. Probe card name acquisition carries other benefits: - securing the process integrity as automation is able to perform accurate probe card data validation avoiding misprocessing - yield improvement through probe card status monitoring as well as reduction of retests due to probe card issues - ensuring full probe card traceability as probe card relevant events throughout its lifetime can be traced and associated to the correct probe card - strengthening process traceability through touchdowns tracking allowing both to perform scheduled maintenance operations and continuous benchmarking for all suppliers - quality improvement by reducing squashes on final passivation and preventing any exposure of underlying PAD layers This paper describes the RFID Probe Card Identification solution design and development, field results and its implementation in the EWS test manufacturing process

Biography
Massimo Sapienza holds a master degree in Electronic Engineering from the University of Catania, Italy. He joined STMicroelectronics in 1999 where he worked for 10 years in Electrical Wafer Sort department in Catania holding several roles linked to Automation and System and data administration. In 2009, he joined Front-End Manufacturing and Technology EWS Europe & EWS Technology - Test Engineering R&D and Automation leading the team of Advanced Automation & Process Flow Standardization Project Management.

Why is fully depleted SOI best for ultra-low power?

Haond, Michel
Director
STMicroelectronics

Abstract
Depleted devices are definitely the solution to maintain Moore's Law trends. We will explicit the advantages of the use of depleted channel devices for reaching very low threshold voltages, thanks to an aggressive electrostatic allowing a tight control of the short channel effects. This helps a lot for one of the key application fields for these devices: Low Voltage and Low Power applications for the handheld, the mobile or any other IOT business. 2 alternative process constructions are proposed today: one 2D silicon film running over an oxide (UTBB FDSOI) or a 3D vertical thin wall (or fin) wrapped around by a Gate (FinFET). However, we will explain why FDSOI has some additional features allowing to further lower the applied supply voltage to the device and therefore better suited for Low Voltage applications : firstly, its undoped channel provides better variability control with a better Vt mismatch and a lower SRAM Vmin; secondly, its unique access to back-biasing allows to further reduce locally and/or temporally the Vt of the transistors by appling a forward body biasing through the virtual back gate formed by the underlying substrate through the Buried Oxide in the 2D FDSOI construction.

Biography
Received a MS Degree from Université Lyon1 in 1976 and an Electrical Engineering degree from Ecole Nationale Supérieure des Télécommunications (ENST) de Paris in 1978. He joined France Telecom Research Center (CNET) in Paris, where he worked on III-V Laser Diode Optoelectronics for Optical Communications. In 1981, he moved to CNET in Grenoble, where he was engaged in Material studies: Rapid Thermal Anneal of implanted junctions; SOI Material fabrication and characterisation. He became Team leader for PDSOI integration of a CMOS 2 µm process. He led the advanced CMOS & BiCMOS Process Integration Department. In 1996, he joined ST-Crolles as Process Integration Manager and developed the 0.18 and the 0.13µm CMOS. In 2000 he was assigned by ST to set-up a Central R&D research group for the future CMOS & Interconnect in connection with CEA-Leti. He was nominated Technical R&D Director, leading the 90 nm, the 45 and 40nm CMOS developments. In 2010 he launched the FDSOI Project with the 28FDSOI Integration and in 2012 the 14FDSOI. He authored or coauthored over 100 publications and owns more than 30 patents. He has been a Member of the Technical or Steering Committee of major Conferences (IEDM, IEEE SOI/S3S Conference, ESSDERC, ULIS-EUROSOI). He is presently Technical Director and Fellow, managing the 14FDSOI Project.

History and trend of Power electronics in automotive body systems

Letor, Romeo
Technical marketing manager
STMicroelectronics

Abstract
Year by year enhancement of passenger car comfort and safety that started in the 90's, requires a consequential constant increasing of installed electric power in the car. Challenged by the weight of compulsory massive wire harness that is in contrast with CO2 reduction, the architecture of car electric distribution evolved with the introduction of solid state power actuators and with the multiplexing of commands/diagnostics. Also improved efficiency for minimizing the current rating of the alternator is made possible by the way of new technologies. From the many car body systems we can mention as examples: *** Smart Junction Box using solid state relay in M0 vertical integrated power technology allowing wire harness optimization and ECU space/weight reduction. *** Migration to solid state solution with power LED and dedicated drivers allow reducing drastically the current rating of the lighting systems. *** System on Chip using technologies with high gate and high power densities allow implementation of small and cheap drivers for light and efficient brushless motor that substitute traditional brushed DC motors. *** Audio amplifiers evolving with high efficiency power stage in class D. This trend is stimulating from one side the system specification and on the other side the power technologies to be used. The presentation will show this evolution and the new challenges for the car body power devices.

Biography
Received Electrical engineer Degree from University of Naples (Italy) in 1985 and hired by STMicroelectronics in 1985. Its Main experiences are in Power electronics, Power management and automotive electronics. He has several patents and he wrote many papers for most important worldwide conferences. He is advisory board member in PCIM and ESRF. Actual Focus is on the definition of new Power and Integrated Smart Power devices dedicated to automotive emerging systems.

Deployment of Human Performance in High Volume Semiconductor Manufacturing : The next step in Improving Manufacturing Excellence

Decroix, Daniel
Engineering Manager for New Technologies
STMicroelectronics

Abstract
STMicroelectronics' 200mm manufacturing facility in Rousset France is a leading supplier of semiconductor electronic components for the automotive industry. With automotive manufacturers looking to reduce their sourcing footprint, the increasing pervasion of electronic components inside each vehicle, and the strict quality requirements of the industry, it is imperative to be absolutely perfect in manufacturing quality to remain a viable competitor. In Rousset operations, human errors causing scrap were a detractor to manufacturing quality, and, reducing human errors was difficult. We had already implementing many technical programs and we still had major quality excursions due to human error, many minor quality excursions, and near misses. We tried many different improvement techniques, methods, and organizational changes: we were able to temporarily make improvements, but we were unable to sustain the results over the long term. In 2010 we benchmarked with AREVA, a French leader in the nuclear power industry. During this benchmark, we discovered techniques and methods to reduce human errors during operations. We developed specific training for all our technical and management teams and we created management and technical opportunities to implement and deploy these best practices. We started with maintenance but later deployed to other organizations like Process Engineering, and Information Technology. We called this program the Human Performance Program and we introduced this program into our global initiatives called "Excellence in Manufacturing". Subsequent to the deployment of this program, we have seen a dramatic reduction in Scraps and the number of major quality excursions caused by human error. We have also seen a subsequent reduction in minor quality excursions and near misses. We have concluded we have established a sound foundation and management culture to continuously improve and proactively manage human related errors.

Biography
Daniel Decroix received his PhD In Sciences des Matériaux from Paris VII university. In 1986, he joined GaAs Department of Thomson-CSF Orsay France as Molecular Beam epitaxy Process Engineer. Then, in 1989, he took over the position of Optical & Electronic Lithography Process Manager. In 1996, he moved to Ulm Germany as Lithography Section Head, for the start up of UMS, a Thales & EADS joint venture. He joined ST Microelectronics Rousset France in 1997, working, first, as Lithography Engineering Manager, then as Etch Engineering Manager. Since 2010, he is working as Engineering Manager for New Technologies Industrialization

The "Internet of Things"- Opportunities for the Secondary Equipment Market

Bignell, Gareth
FE Equipment Purchasing Director
STMicroelectronics

Abstract
Previously the industry has seen the emergence of the PC and then the portable telephone, both of which created enormous demand, opportunities and change. Who could have imagined the impact today of the smart phone? when just a few short decades ago the first bulky, cumbersome (barely) portable phones arrived. The next technology wave is going to be even bigger and impact our lives even more. This wave is the IOT. Today we are just at the beginning of this great adventure, where the possibilities of the IOT are only limited by our collective imaginations. Both the PC and the telephone pushed Moore's law along and were at the leading edge, forcing change from micron to sub-micron to single digit nanometer technologies. The IOT is different and requires broader technologies - sensors, MEMS, power management, connectivity and microcontrollers. The leading edge technology race will surely continue, driven by next generation microprocessors and ever denser memories . But in parallel, many of the new and innovative IOT technologies will not require the latest process equipment. The sweet spot to economically produce these devices will be reusing, recycling and repurposing trailing edge equipment mainly focused on 200mm. Clearly the secondary equipment market has a great role to play.

Biography
Gareth Bignell has been responsible for the sourcing of ST's fab equipment, spare parts and maintenance contracts for all ST sites worldwide for the last 7 years. Prior to this, he was the equipment selection program manager for the Crolles2 Alliance where he closely worked with Freescale and NXP on sourcing all of the 300mm tools for this successful multi-company alliance. He started his career as an equipment engineer in Inmos UK before holding various engineering and management roles at ST's Agrate and Crolles sites. Gareth has worked in the semiconductor industry for more than 30 years since graduating from the University of Wales, Newport.

How G450C Activities are Driving Productivity in the Industry

Farrar, Paul
General Manager of G450C
SUNY Polytechnic Institute

Abstract
The talk will focus on productivity gains that are being advanced by work being lead by G450C. Initiatives such as Notchless wafers , 1.5mm exclusion zone, advances in metrology and process capabilities will be highlighted. In addition, 450mm process data and tool performance metrics will be discussed.

Biography
As General Manager of the Global 450mm Consortium (G450C), Paul Farrar oversees the coordination, administration and management of G450C's strategic, operational and financial missions, including external collaborations with international partner companies, program staffing, and interactions with the G450C Management Council. In addition, he serves as CNSE Vice President for Manufacturing Innovation, where he is responsible for the expansion of CNSE's intellectual know-how and state-of-the-art programs to convert longterm prospective innovations into business opportunities and economic development programs across New York. In this role, he also collaborates with educational organizations throughout New York State to implement educational programs and training opportunities in nanoscale and green energy manufacturing. Farrar joined CNSE with more than 36 years of experience in the semiconductor industry. He most recently served as IBM Vice President for Albany Expansion and Strategic Initiatives, where he was responsible for joint development alliances, the growth of the Albany ecosystem, and IBM's collaborative model, as well as management of the capital budget for the Microelectronics Division. During Farrar's tenure at IBM, he managed 700 IBM and partner research and development engineers and scientists, and as Vice President for Semiconductor Process Development, was responsible for unit process, lithography and characterization. Additionally, he held numerous positions in manufacturing and development, led IBM's semiconductor fab in Burlington, Vermont, managed IBM's SRAM and DRAM businesses, spent seven years in process development, and negotiated numerous strategic alliances with semiconductor equipment manufacturers and IDMs. Farrar received a bachelor's degree and a master's degree in Materials Engineering from Rensselaer Polytechnic Institute.

Where Might Future Semiconductor Productivity Enhancements Come From?

Liehr, Michael
Executive VP for Innovation & Technology
SUNY Polytechnic Institute

Abstract
The nanoelectronics industry has enjoyed decades of productivity gains driven by lithographic scaling. However, scaling slowed due to delays in the introduction of extreme ultraviolet (EUV). However, to maintain the pace of die-level cost reduction, a different set of approaches are needed in addition to using EUV. The advantages of time to market of any productivity enhancement require a model that assures rapid transfer of novel concepts from a lab environment to the fab. Improvements in time to market in the CNSE model will be described. The significant investments required for the development of future scaled technology favor a collaborative government-industry co-investment model. Recent additions to the SUNY Poly technology portfolio will also be discussed. Specific productivity enhancement for future semiconductor technologies will be elaborated: the performance of the first generation of EUV production scanners, system-level improvements incorporating photonic components and new device materials.

Biography
As CNSE Executive Vice President of Innovation and Technology, Michael Liehr focuses on the creation of new business opportunities and manages integrated industry-university consortia and public-private partnerships. He is also responsible for the effective and efficient operation of the CNSE core strategic CMOS and SiC power semiconductor and packaging partnership engagements, including the IBM, GLOBALFOUNDRIES, General Electric, SEMATECH, AMAT, TEL, and LAM partnerships. Prior to this assignment, he led the Global 450mm Consortium through the start-up phase as the General Manager. Dr. Liehr is further the Vice President for Research at the College of Nanoscale Science and Engineering in Albany, NY. In this role, he leads the State University of New York's Network of Excellence in Materials and Manufacturing. Prior to joining CNSE, Dr. Liehr served as an IBM executive responsible for Worldwide Semiconductor Manufacturing Strategic Production Alliances for leading-edge semiconductor products.

Springless Diaphragm Valves with Replaceable-Seat from Swagelok®

Bruettinger, Moritz
Field Engineer
Swagelok Co.

Abstract
Swagelok® is pleased to announce two new high purity products for our customers working with chemical canister applications. The Swagelok® DPX and DFX Replaceable-Seat, Springless Diaphragm Valves offer repeatable seat replacement and a seat seal that protects against chemical and thermal swelling and process chemistry degradation. Building on the proven performance of the Swagelok® DP and DF series valves, the DPX and DFX valves are designed to enable advanced chemistry processing in thin film deposition applications. Unlike typical replaceable seat valves, the DPX and DFX valves' tight-fitting seat designs have minimal entrapment areas and low profiles to guard against flow area reduction, pressure drops, restricted flow, and inefficient purging; providing the added reliability and assurance users need to achieve more with their application. Swagelok® has also created a DPX and DFX Replaceable-Seat, Springless Diaphragm Valve Tool and Maintenance Kit. This includes seat removal and installation tools and an innovative seat carrier to enable precise installation into the valve body.

Biography
Moritz Bruetinger has a degree of Industrial Engineering. He began his career with Swagelok in 2009 with Swagelok Stuttgart/Karlsruhe as a Salesman in South-West-Germany. In his sales area Moritz had the whole spectrum of Swagelok key-markets. His focus was on Chemical and Petrochemical applications, Research Labs, pump manufacturer and analytical instrumentation. In 2013 Moritz joined Swagelok Company as a Field Engineer for Central and Eastern Europe.

Wafer Signature Detection - Automatic Defect Recognition and Classification

Schaaf, Andre
Software Developer
SYSTEMA GmbH

Abstract
Root cause analyses have shown that back side scratches and signatures are a major cause of wafer breakage during semiconductor process steps. However, wafer back sides can have 100k+ of defects that avoid critical defect identification. Auto-classification of defect signatures is difficult and their calculation time-consuming. Hence, manual review is still common operational procedure. HSEB develops, designs, and manufactures high-throughput AOI systems including for wafer back side inspection. SYSTEMA is a global specialist in integration of high-tech manufacturing IT. SYSTEMA and HSEB are presenting a solution for wafer signature detection to automatically pre-filter, recognize, and classify defects allowing real-time statistical process control even for very high defect densities.

Biography
About the Speakers André Schaaf, born in 1985, is an expert for Signature Detection of silicon wafers with a 12-year experience in both, Semiconductor and the Gaming Industry. The Senior Software Architect supports chip and wafer manufacturers in comprehensive projects, e.g. for (web) application frameworks. Before joining SYSTEMA in 2013, he has been working self-employed in a variety of projects as Senior Software Architect and Lead Developer. One of his current activities is about porting algorithms to GPUs to harvest more computing potential. Susan Duerigen, PhD, is an application expert for wafer back side inspection. She started working in semiconductor industry in 2006 and joint HSEB in 2014 being by now responsible for the Key Account Globalfoundries Fab 1.

Energy-efficient Analog and RF Circuits and Systems for Communications

Ellinger, Frank
Prof.
Technische Universität Dresden

Abstract
We will present energy-efficient analogue and RF circuits and systems for wireless and wired communications. Adaptivity regarding performance versus dc power can be used to reduce the power consumption of communication systems. In this regard, we present power amplifiers where the dc supply voltage can be adapted in real-time. Moreover, we will discuss bandwidth-adaptive circuits. A further very efficient approach is based on the combination of high performance receivers and simple low power consuming wake-up receivers. By using duty-cycle approaches these wake-up receivers consume only a few tens of microwatts. It will be shown that even at frequencies up to a few hundreds of GHz it is possible by advanced architectures and by using fastest BiCMOS technology to realise very efficient circuits. Since very large bandwidth can be achieved, the energy per bit can be very low. A further possibility to improve the tradeoff between performance and power is based on smart antenna combining. In this regard, we will present control elements with reduced phase errors. Last but not least we will present low power consuming TOLAE (thin film and organic large area electronic) circuits. The first fully integrated active data receiver is demonstrated which is fully integrated on a sheet of plastic. Because no rigid chips are required, the receiver is mechanically flexible and bendable. IGZO is used for the fabrication.

Biography
Frank Ellinger graduated from the University of Ulm, Germany, in electrical engineering (EE) in 1996. He received an MBA, PhD and habilitation degree in EE from ETH Zürich (ETHZ), Switzerland, in 2001, 2004 and 2004, respectively. Since August 2006 he is full professor and head of the Chair for Circuit Design and Network Theory at the Dresden University of Technology, Germany. He is the coordinator of the FAST zwanzig20 program with more than 80 partners (most of them from industry) and has been member of the management board of the Cool Silicon e.V. He is the coordinator of the DFG priority program FFlexCom. From 2001-2006, he has been head of the RFIC design group of the Electronics Laboratory at the ETHZ, and a project leader of the IBM/ETHZ Competence Center for Advanced Silicon Electronics hosted at IBM Research in Rüschlikon. Prof. Ellinger was the coordinator of the EU funded projects RESOLUTION, MIMAX and FLEXIBILITY. He has published more than 300 refereed scientific papers and his group has received more than 20 awards. Frank Ellinger has e.g. received the Alcatel-Lucent Science Award, the IEEE MTT-S Outstanding Young Engineer Award and was an IEEE MTT-S Distinguished Lecturer.

Bipolar SiC diodes for high-power medium-voltage drives

Filsecker, Felipe
Research assistant
Technische Universität Dresden

Abstract
A 6.5-kV, 1-kA SiC bipolar diode module for megawatt-range medium voltage converters is presented. This comprises a short description of the die and module technology and a device characterization. The results are compared to a commercial diode module. With the electro-thermal models of the devices, an estimation of the maximum converter output power, maximum switching frequency, losses and efficiency in a 4.16-kV three-level neutral-point-clamped converter operating with SiC and Si diodes is presented.

Biography
Felipe Filsecker was born in Viña del Mar, Chile. He received the Electrical Engineering degree from the Pontificia Universidad Católica de Valparaíso, Chile, in 2009. He is currently working as a research assistant at the Chair of Power Electronics at Technische Universität Dresden, Germany, and finishing his doctoral studies. He has worked mainly in the field of device characterization for high-power, medium-voltage applications. Currently, he is working on reliability and life-time monitoring of IGBTs.

Big Data in Cyber-Physical Systems (CPS)

Aßmann, Uwe
Chair of Software Engineering
Technische Universität Dresden

Abstract
We presume that there are two dominant forms of systems in the future internet of things: world databases and cloud-based robots. Both will create massive amount of data and rely on efficient real-time online query processing. First, a world database is an online query system to a pertinent domain of the world, i.e., it creates insights about all physical things in that domain in time and space. Second, cloud-based robots are combining world databases with actuators, i.e., they provide a specific form of cyber-physical system, in which sensors, actuators, embedded system and cloud technology have to play together reliably. Future industry-4.0 systems will massively rely on world databases and cloud robots, because individualized products, ordered by singular customers, can only be built just-in-time, if a swarm of cloud robots collaborates effectively, relying on real-time data analytics. Thus, both forms of CPS rely thoroughly on query processing (big data). However, due to the hierarchical structure of physical space, we need other types of data than relational: data about real things is usually hierarchical, so that new query languages and calculi have to be developed that treat hierarchies efficently and effectively. We present several projects at Technische Universität Dresden to research important aspects of big data for CPS, such as energy efficiency, context-adaptivity, and parallel processing.

Biography
Uwe Aßmann holds the Chair of Software Engineering at the Technische Universität Dresden. He has obtained a PhD in compiler optimization and a habilitation on "Invasive Software Composition" (ISC), a composition technology for code fragments enabling flexible software reuse. ISC unifies generic, connector-, view-, and aspect-based programming for arbitrary program or modeling languages. His group is member of the research centre "Center for Advancing Electronics Dresden (cfAED)", working on novel code composition techniques for many-core architectures and modern hardware structures. In the subproject "Highly-Adaptive Energy-Efficient Computing (HAEC)", the group develops energy autotuning (EAT), a technique to dynamically adapt the energy consumption of an application to to the required quality of service, the context of the system, and the hardware platforms. In the last years, a lot of work has been devoted to context-aware programming techniques and languages for cloud-based robots.

Strecker, Markus
CEO
Teiimo

Biography
Markus Strecker is the CEO and founder of Teiimo. Teiimo is a technology company specialized in the field of conformable electronics. It creates its own innovative and high quality products, develops systems and components from concept to series production, and takes care of the system integration. In 2014 Teiimo introduced its first product: the iilation Jacket, a fashionable luxury leather jacket that heats the shoulders, back, neck, kidneys, serves as a Bluetooth hands free calling device, plays music, and offers cell phone charging capability. The iilation Jacket is a perfect example for the power of conformable electronics and sets new standards in integration level and functional density for smart garments. Mr. Strecker is an international executive and a renowned expert in wearable electronics and product development. He is an experienced manager in big corporations, as well as in start-up environments. As one of the pioneers in the wearable technologies market, ten years ago Mr. Strecker developed "the Hub" the first mass produced wearable electronics jacket for O'Neill. It was the first communication and entertainment jacket worldwide. Many more iconic products for different brands followed under his technical lead. For example the MP3Blue by Rosner, the Zegna Energy harvesting jacket, as well as the "KnowWhere" jacket, which was a technology demonstrator. Before starting Teiimo Mr. Strecker was Director for Electrical Engineering at adidas where he lead the concept and electronics development of the miCoach Elite Team System, the most comprehensive and technically advanced training system for professional soccer teams, which is used for example by the German National Team, numerous professional soccer teams in Europe and the complete Major League Soccer in the US. Mr. Strecker is listed as a technology expert for the European Commission. He has a broad international background having worked in Europe, Asia, and North-America.

Challenges and opportunities for wafer-scale CCD and CMOS image sensors

Bosiers, Jan
R&D Director
Teledyne DALSA Professional Imaging

Abstract
Wafer-scale imagers are used in applications like photogrammetry, scientific, astronomy, and X-ray medical imaging. The talk will focus on the design and manufacturing challenges, but also aspects related to testing, assembly and operation of these very large imagers will be presented. The commonalities and differences between CCD- and CMOS- based technologies will be explained. The presentation will start with some examples of existing wafer-scale imagers for various applications, from different vendors. Then the challenges related to wafer-scale CCD imagers will be analyzed. Several design and technology concepts will be presented by using the example of a 250M-pixel 10cm x 8cm CCD developed by Teledyne DALSA for photogrammetry applications. The second part of the presentation will focus on the development of, and applications for, wafer-scale CMOS imagers. A 11cm x 15cm CMOS imager with 99x99 μm² pixels developed for medical applications will be used to illustrate how very large CMOS imagers, with the right design and technology choices, have become the leading technology for dynamic medical X-ray imaging systems.

Biography
Jan Bosiers graduated as Electronic Engineer from the Catholic University in Leuven (Belgium) in 1980. He worked at the ESAT Laboratory of the University and at the Naval Research Laboratory in Washington D.C. before joining Philips Research in Eindhoven, the Netherlands, in 1986. At Philips, he worked on CCD development and project management. He became R&D Director of DALSA Professional Imaging in 2002, after the acquisition of the Philips professional CCD business by DALSA. Since the acquisition of DALSA by Teledyne in 2011, his responsibilities as R&D Director include the R&D of CCD and CMOS imagers and CMOS-based X-ray detectors.

Presto! A test element driven test program Generator for Test Probe

Schiessl, Uwe
Production Test Engineer
Texas Instruments Deutschland Gmbh

Abstract
New technologies in semiconductor industries in the last 10 years trend to grow more and more complex. State of the art technologies today are supporting > 70 flows and > 100 technology elements. Those elements can be technology design components (MOS/Bipolar transistors, diodes, resistors etc. ) or Fab control structures like Vias, contacts, GOI etc. Whereas Scribe Line test programs for wafer test probe in the past, consisted of ~100 tests, today the generation of several thousand tests per program is necessary to provide support for all the requirements specified in a Process Control Document. Utilizing adaptive test in combination with component based test is a modern strategy in wafer test probe to handle multiple flow and component technologies. This reduces the sustaining effort by maintaining only one test program per technology. Latest trends in Scribe line layout start to implement strategies, which no longer place all the Scribe Line modules of a given technology on each device, but limit the module placement to those, supporting only technology elements, which are crucial for device layout and functionality. This trend, however, increases the sustaining effort for the supporting test engineer considerably - he must now support multiple programs for a given technology. To allow a test engineer to still handle such requirements, new tools need to be provided. The authors are presenting Presto! an innovative element driven test program generator for test probe. It can cut down development times of several days to several hours. Presto associates to each technology element a parameterized test sequence with one/more variable groups (Patent TI-74851). Additional concepts like multiple sub element support, as well as Inter/ Intra Dut/module provide a flexibility to 100 % port mature manually generated programs to an automated test platform. Once generated, test sequences can be easily reused in a building block manner or ported to other technologies.

Biography
Uwe Schiessl joined TI in 2000 as a characterization engineer in the parametric test group. He is a Member Group Technical Staff since 2015 and has a physics diploma from the University of Heidelberg. Istvan Bauer joined TI in 2011 as a Product Engineer in the TSDS group working on multiple parametric test optimization projects. He has a MS EE diploma from University of Texas at Dallas. Shannon Wilmes joined TI as a co-op in 1994 and currently works as a software design engineer. He has primarily worked on automation solutions related to physical design, final test program generation and parametric test program generation. He has a BS degrees in Electrical Engineering and Mathematics from Southern Methodist University in Dallas, TX.

MOOI, a method to maximize the output of installed Fab capacity without additional investment

Schulz, Ulrich
Manufacturing Development Manager
Texas Instruments Germany

Abstract
High costs of production are a key differentiator and a continuous challenge between Semiconductor factories in Europe compared to the rest of the world. A substantial method to reduce the cost per wafer is to increase the capacity without or with minor investment. Capacity installation and expansion plans over the years never assumed the technology & product mix of today. Minor changes in certain tool categories can result in significant increases of the overall Fab capacity. In a first step a project leader was assigned to systematically compare and analyzes the actual demand with the Fab capacity. After identifying the top operational gaps, a task force is initiated with all stakeholders to find actions to increase that specific capacity applying a standardized toolkit which was developed for this purpose. The project ends with the implementation and verifications of the defined actions. In addition to expansion projects, MOOI ('M'ore 'o'ut 'o'f 'I'nstalled tools) can also be used to reduce the number of (legacy) tools in the Fab or gain additional clean room area. Co-Author Eva Schaefer EDUCATION: Diploma in Mechanical Engineering from the University of Erlangen Germany EXECUTIVE SUMMARY: - Capacity Management, Texas Instruments Freising - 2002 - 2009 Manufacturing Operation Section Manager responsible for photolithography, epitaxy and ion implant - Started at Texas Instruments in 2000 as Line Supervisor in epitaxy and ion implant in Freising FAB.

Biography
EDUCATION: Diploma / PHD in Physics, University of Göttingen, Germany. EXECUTIVE SUMMARY: - Manufacturing Development Manager, Texas Instruments Freising - worked 27 years in Semiconductor Operations, Engineering and Process Integration as Photo Section Manager, Process Yield manager, Branch Manager for Engineering & electrical Yield Improvement

The Ferroelectric Memory Company: Bringing Ferroelectrics to Fabs

Müller, Stefan
Co-founder
The Ferroelectric Memory Company (i.G.)

Abstract
FMC will be formed to commercialize a groundbreaking material innovation to build next generation embedded memory products. Our proprietary technology enables customers to plug-in FMC memory IP right in their advanced System-on-Chip architectures. Today, Fabless Chip Companies and IDMs are not able to scale down their System-on-Chip (SoC) designs in the same way as transistor logic is surging ahead. This is due to the fact that all current non-volatile memory solutions have scaling problems, so that SoCs cannot be manufactured in a cost- and area efficient way. The customer problem is therefore a lack of scaling and cost reduction in the embedded memory sector. FMC will offer an embedded memory solution at 28 nm and beyond uniquely addressing the scaling issues in advanced system-on-chip architectures. Our single-transistor FeFET solution based on ferroelectric hafnia enables chip manufacturers to implement embedded memory blocks at the latest SoC technology nodes. FMC will deliver IP products (IP cores) to fabless customers and Integrated Device Manufacturers (IDM) around the world. For 2018 YOLE is reporting that the emerging nonvolatile memory (NVM) market is crushing the 2 Billion USD line. The market will grow at a CAGR of + 46% with mobile phones, smart card and enterprise storage as main growth drivers. FMC will enter this market with products that ideally meet the growth driving applications by focusing on advanced energy efficiency standards and currently unresolved scaling issues.

Biography
Stefan Mueller received the joint master's degree in Microelectronics from the Technical University Munich, Germany, and Nanyang Technological University Singapore in 2011. He also holds a diploma degree in Mechatronics and Information Technology as well as a bachelor's degree in Mechanical Engineering both from Technical University Munich, Germany (2011/2008). In 2011, he joined NaMLab gGmbH, Dresden, Germany, as a PhD student working on ferroelectric devices. Since 2015 he is project leader of a publicly funded research transfer project which will result in the formation of FMC, "The Ferroelectric Memory Company".

An OEM's view of the secondary system's market.

Shekel, Eyal
Senior Vice President TEL Europe
Tokyo Electron

Abstract
The secondary equipment market has become an established option in today's manufacturing environment, adding capacity or technical capability. Over the last five years OEM's like TEL have developed their range of secondary products, giving FAB's OEM quality solutions at an affordable level of investment. Many companies specialise in this marketplace, however, it is principally the OEM's who can provide the broad-based solutions from a global network which meet today's customer needs. This presentation will articulate the value propositions that OEM's offer as well as discuss how we in TEL can offer innovative "hybrid" manufacturing solutions allowing TEL CUE (Certified Used Equipment) to remain commercially attractive as well as supporting new process integration on to mature platforms. Additionally, this presentation will discuss how TEL can provide affordability programs enabling FABs to control their OPEX expenditure.

Biography
Eyal has 23 years of experience in the semiconductors industry. After graduated the Technion (Israel institute of technology), in mechanical engineering, he has joined Applied Materials in 1993. Eyal has served 5 years on engineering roles in Etch and CVD, working with customers in Europe and US. In 1997 he has joined Tokyo Electron and established its subsidiary in Israel, ending this position in 2004 as the General Manager. In 2005 Eyal was appointed as the Vice President of TEL Europe looking after service, through the UK headquarters. In 2009 Tokyo Electron started to build its Field solution business unit, and Eyal took a leading role in developing the used equipment business, being the first region out of Japan, and creating a local European refurbishment centre in Holland. In 2013 Eyal was promoted and is now Senior Vice president for service and support operations. He is 52 years old and leaves in Israel.

Silicon for Power Electronic and Detector application

Jensen, Leif
Senior Silicon Specialist
Topsil Semiconductor Materials A/S

Abstract
High quality silicon substrates are used for many types of discrete devices. The Topsil Group is a leading manufacturer of high performance silicon wafers for the power market and for niche applications in the semiconductor and the photo voltaic industries. Utilizing proprietary Float Zone and CZ Epi technology to manufacture customized wafers for the most demanding applications, the high quality wafers are manufactured under strict quality standards. Market segments like energy saving devices IGBTs, lightening devices like LEDs, infra-red detectors and wireless communication require a special set of optimized silicon parameters. Even scientific instruments require high quality silicon for detectors to meet today's requirements for high sensitivity when measuring high energy particles and radiation. New application areas require a higher level of quality and improved material parameters for Gallium Nitride, GaN film growth for improved LEDs and power devices. The Topsil Group covers a wide range of products by offering Neutron Transmutation Doped, NTD silicon for very high power devices. Preferred Float Zone, PFZ for Power applications. High Resistivity Silicon, HPS for Detector applications, High Resistivity silicon, HiRes® for communication devices. High Transparency silicon, HiTran® for Infra-Red applications. Photo Voltaic Float Zone, PV-FZ® for high efficiency solar cells. CZ Epi Medium and low power devices.

Biography
Leif Jensen, MMT eMBA, Senior Silicon Scientist at Topsil Semiconductor Materials A/S, Denmark. More than 25 years of experience in developing silicon wafer products for the semiconductor industry, and background in electronic engineering. Current position is to find emerging new technologies and create new business.

Specialty CIS process in a foundry environment

Strum, Avi
Vice President, GM of CIS BU
TowerJazz

Abstract
Although CIS process is basically CMOS based, the process flow is unique to each type of imager. For example, a process flow for X-Ray medical sensor in completely different than the one used for high end photography and both are completely different than the one required for 3D gesture recognition sensors for the gaming market. In addition, unlike very high volume CMOS digital products, the volume per each process flow is significantly lower and thus, creates flow diversity within the fab and makes the production line control a very challenging task. The talk will focus on how a specialty foundry such as TowerJazz can support fabless customers with state of the art imaging technology alongside with high flexibility of customizing the process flow to the customers' needs, allowing it to compete well with leading sensor IDMs. The talk will focus on the main specialty markets such as high end photography, medical X-Ray sensors, industrial global shutter market, automotive and security and the new, fast growing 3D gesture recognition sensor market.

Biography
Dr. Strum is the VP and GM of the CIS business unit at TowerJazz. Previously he was VP and GM of the Specialty Business Unit since September 2008. He joined Tower in 2004 and served as GM of Tower's design center in Netanya and Device and Integration Department Manager. Prior to joining Tower, Dr. Strum served as the President and COO of TransChip Inc. and from 1996 to 2001, he served in various positions with Intel Corp., both in Israel and the US. From 1990 to 1996, he was the R&D Manager of SCD and was in charge of all the Infrared Detectors development in SCD. Dr. Strum received his Ph.D. and B.Sc. in Electrical Engineering from the Technion - Israel Institute of Technology in 1990 and 1985 respectively.

Agile value chain for medium volumes custom MEMS manufacturing, packaging and integration.

Gaff, Vincent
Business Unit Manager
Tronics Microsystems Sa

Abstract
MEMS technologies are enabling a wide range of new sensor and/or actuator functions of (inertial sensors, micro-mechanics, optical and RF microsystems, BioMEMS, etc.. ). At the heart of product innovation, those technologies are driving the future of growing markets like industrial instrumentation, aeronautics & security, medical and pharmaceutical devices. The functions created are very diverse and call for wide range of manufacturing, packaging and integration technologies that are neither well mastered by customers not available at a single sub-contractor manufacturing location when needed. To address these new product integration challenges tight relationships between solution providers and customers need to be established. An agile and sustainable model must be implemented so that the hurdles of cost, performance and integration can be lowered. Specialized in the manufacturing of highly differentiated, high-value add, custom MEMS products for medium volume applications, Tronics has set-up agile manufacturing strategies to address those diverse requirements. With a mix of in-house capabilities and an ecosystem of solutions providers, Tronics manages supply chain to deliver OEMs functions they can easily integrate into their systems.

Biography
Vincent Gaff is Manager of the Business Unit "Microsystems Solutions" at Tronics Microsystems. He manages the custom MEMS development and foundry services for the company. Vincent Gaff joined Tronics Microsystems in 2000 as marketing and sales engineer. He led the marketing and business development activity of the company from 2005 to 2011 and then took charge of the main business unit of the company. He was previously project manager at CEA-Leti from 1998 to 2000.