Wednesday, October 7, 2015
Session 1

Market view from automotive to healthcare and IOT

Chair Laurent Le Pailleur, Technology Line Management Director, STMicroelectronics
Laurent Le Pailleur

Laurent Le Pailleur
Technology Line Management Director
STMicroelectronics

Biography
Laurent Le Pailleur is director for advanced Cmos technology line with STMicroelectronics, Crolles France.
He previously enjoyed various positions as head of technology management (semiconductor, packaging and IPs) with ST-Ericsson, audio/power management product line and 2.5G mobile platform/3G mobile digital System-on-Chip product management at ST. This allowed him to develop deep understanding on RF, analog and digital technologies, architecture and system partitioning.

Prior to ST, he has been working on mixed-signal video systems and imaging digital processors design with Philips Semiconductors.
In 1989, he received the degree in electrical engineering from Caen National Engineering School, the M.S. degree in instrumentation and automation from Caen University and the Business degree from IAE (Enterprise Administration Institute).
He participated to numerous international conferences and hold multiple patents.

13:00 Introduction
13:10

Keynote

 
Low Power Technology and it's application in SoC, Energy Efficient Designs and IoT - From Foundry Perspective
  Rutger Wijburg, Senior VP and General Manager Fab Management, GLOBALFOUNDRIES
Low Power Technology and it's application in SoC, Energy Efficient Designs and IoT - From Foundry Perspective
Rutger Wijburg

Rutger Wijburg
Senior VP and General Manager Fab Management
GLOBALFOUNDRIES

Abstract
We were used to walk down Moore's Law road over the last decades. This road brings our industry into the land of highly scaled technologies: 14, 10 and 7 nanometer. However economically one need to look on the next "hype" building up: "Internet of Things". Going down this road it is more critical to have the "right" technology at a certain "cost point" with focus on the application and with "build in connectivity".
This automatically leads to Fully Depleted technologies with optional embedded RF capability as well as 28/22nm patterning with no need of extensive use of double patterning or new light sources for lithography.
28nm is known as the "sweet spot" in Foundry Industry for yield/performance AND cost. This node is in high volume production and will be the basis to add technology features like embedded RF, Flash, High Voltage (HV) or other value add solutions and is already predicted to have a long lifetime in our industry. In particular embedded RF and HV are key do communicate with the outside analog world in an power efficient and user friendly way.
22nm FD SOI is to a big portion technology wise proven in 28nm. FD SOI can operate at voltages down to approx. 0.4V with decent performance. This technology meets the desire of IOT products to be ultra mobile and enables small form factors. In addition this technology setup is simpler, requires much lower number of mask layers and is ideal for a broad range of IOT applications at lower cost.
22nm FDSOI makes "Faster, cooler, simpler" a reality and extends the "sweet spot" of 28nm to an even longer lifetime.

Biography
Dr. Rutger Wijburg is Senior Vice President and General Manager of GLOBALFOUNDRIES Fab 1 in Dresden, Germany.
He is responsible for GLOBALFOUNDRIES' highend 300mm manufacturing operations in Europe.

Prior to joining GLOBALFOUNDRIES in 2011, Rutger Wijburg was Senior Vice President and Operations Manager Front End at NXP Semiconductors (formerly Philips Semiconductors) in the Netherlands. In this role, he was responsible for the company's seven wafer fabs, led outsourcing and building strategic partnerships, and was in charge of real estate and facilities management.

Rutger Wijburg has also held leadership positions with Mesa Research Institute in the Netherlands and CSEM SA in Switzerland.
He holds both a Master of Science degree and Ph.D. in Electrical Engineering from the University of Twente, the Netherlands.

Session 2

Smart and energy efficiency silicon technologies

Chair Thomas Mikolajick, scientific director, NaMLab Gmbh / TU Dresden
Thomas Mikolajick

Thomas Mikolajick
scientific director
NaMLab Gmbh / TU Dresden

Biography
Thomas Mikolajick received the Diploma (Dipl.-Ing.) in electrical engineering from the University Erlangen-Nuremberg in 1990 and his phD in electrical engineering in 1996. From 1996 till 2006 he was in the semiconductor industry developing CMOS processes,ferroelectric memories, emerging non-volatile memories and Flash memories first at Siemens Semiconcuctor and later at Infineon. In late 2006 he moved back to academia taking over a professorship for material science of electron devices and sensors at the University of Technology Freiberg, and in October 2009 he started at Technische Universität Dresden were he now holds a professorship for nanoelectronic materials in combination with the position of scientific director at NaMLab GmbH. Since April 2010 he is the coordinator of the "Cool Silicon" Cluster in Dresden. Prof. Mikolajick is author or co-author of about 220 Publications in scientific journals or at scientific conferences and inventor or co-inventor of about 50 patents.

13:40
Why is fully depleted SOI best for ultra-low power?
  Michel Haond, Director, STMicroelectronics
Why is fully depleted SOI best for ultra-low power?
Michel Haond

Michel Haond
Director
STMicroelectronics

Abstract
Depleted devices are definitely the solution to maintain Moore's Law trends. We will explicit the advantages of the use of depleted channel devices for reaching very low threshold voltages, thanks to an aggressive electrostatic allowing a tight control of the short channel effects. This helps a lot for one of the key application fields for these devices: Low Voltage and Low Power applications for the handheld, the mobile or any other IOT business.
2 alternative process constructions are proposed today: one 2D silicon film running over an oxide (UTBB FDSOI) or a 3D vertical thin wall (or fin) wrapped around by a Gate (FinFET). However, we will explain why FDSOI has some additional features allowing to further lower the applied supply voltage to the device and therefore better suited for Low Voltage applications : firstly, its undoped channel provides better variability control with a better Vt mismatch and a lower SRAM Vmin; secondly, its unique access to back-biasing allows to further reduce locally and/or temporally the Vt of the transistors by appling a forward body biasing through the virtual back gate formed by the underlying substrate through the Buried Oxide in the 2D FDSOI construction.

Biography
Received a MS Degree from Université Lyon1 in 1976 and an Electrical Engineering degree from Ecole Nationale Supérieure des Télécommunications (ENST) de Paris in 1978. He joined France Telecom Research Center (CNET) in Paris, where he worked on III-V Laser Diode Optoelectronics for Optical Communications. In 1981, he moved to CNET in Grenoble, where he was engaged in Material studies: Rapid Thermal Anneal of implanted junctions; SOI Material fabrication and characterisation. He became Team leader for PDSOI integration of a CMOS 2 µm process. He led the advanced CMOS & BiCMOS Process Integration Department. In 1996, he joined ST-Crolles as Process Integration Manager and developed the 0.18 and the 0.13µm CMOS. In 2000 he was assigned by ST to set-up a Central R&D research group for the future CMOS & Interconnect in connection with CEA-Leti. He was nominated Technical R&D Director, leading the 90 nm, the 45 and 40nm CMOS developments. In 2010 he launched the FDSOI Project with the 28FDSOI Integration and in 2012 the 14FDSOI.
He authored or coauthored over 100 publications and owns more than 30 patents. He has been a Member of the Technical or Steering Committee of major Conferences (IEDM, IEEE SOI/S3S Conference, ESSDERC, ULIS-EUROSOI).
He is presently Technical Director and Fellow, managing the 14FDSOI Project.

14:15
28/22nm RF Technology status and future roadmap
  David Harame, CTO RF Technology and Enablement, Global Foundries
28/22nm RF Technology status and future roadmap
David Harame

David Harame
CTO RF Technology and Enablement
Global Foundries

Abstract
The IoT with billions of connected devices will require wireless connectivity, faster processing, faster data rates, longer battery life and lower cost. For the wireless connectivity, especially IOT, low power, cost, and RF performance are the most important considerations. FDSOI offers a unique combination of low cost, low power, and RF performance which nicely meets these targets. This presentation will focus on the RF performance.
All RF designs require RF passives including RF capacitors (MOMs), Inductors, Varactors, and Resistors, supported with models tuned to S-parameter data. An RF custom PDK with RF models for all RF devices is provided.
22FDX transistors have excellent electrostatics compared to bulk. The HiK Metal Gate stack and short gate length (Lg) provide high transconductance (gM > 2mS/um) with low gDS. The high gM, and low gDS gives a high self gain, important for all RF/Analog applications. The FDSOI transistor is architected for effective body biasing. The Back Gate Bias (VBG) enables reducing the threshold voltage (FBB) for increased current drive or increasing the threshold voltage (RBB) for decreased leakage.
The RF performance of 28nm FDSOI has been published by Lucci as fT= 380 GHz and fMAX= 390 GHz (2015 IMS Symposium). This combination of high fT and fMAX is amongst the highest achieved for any RFCMOS technology and clearly demonstrates the performance potential of FDSOI technologies.
Simulations show 22FDX has better AC gain than bulk 28nm SLP technology. Using the back gate to lower Vt expands the voltage range over which a high gM is found. This expanded dynamic range is also true for fT and fMAX.
In Summary, FDSOI makes an excellent RF technology.

Biography
David Harame joined GLOBALFOUNDRIES in 2014. David is a Global Fellow and the Chief Technical Officer for RF Development and Enablement. Prior to GLOBALFOUNDRIES worked for IBM where he was an IBM Fellow and was also the CTO for RF Development and Enablement. David has worked in the area of RF technology for over 30 years. In 2005 David was awarded the IEEE Daniel E Noble Award "For the development of manufacturable Silicon Germanium, HBT Bipolar and BiCMOS technologies." He also received the IEEE BCTM Award for his work in SiGe BiCMOS. David is an IEEE Fellow.

14:40
Ferroelectric Hafnium Oxide: Material Innovation for Ferroelectric Memories
  Johannes Müller, Group Manager NVM, Fraunhofer IPMS
Ferroelectric Hafnium Oxide: Material Innovation for Ferroelectric Memories
Johannes Müller

Johannes Müller
Group Manager NVM
Fraunhofer IPMS

Abstract
The first research and development efforts focusing on ferroelectric random access memory (FRAM) were started more than 60 years ago. Even though new and promising nonvolatile device concepts have emerged since then, the right to exist for FRAM is still provided by its excellent energy efficiency, fast rewrite speed and low voltage operation capability. Compared to the heat induced switching in PCRAM, spin transfer in STTRAM, ion conduction in RRAM or hot electron injection in NOR-FLASH, the electron efficiency of the polarization induced displacement current in FRAM remains unchallenged. Nevertheless, besides some temporary upturns and the launch of a few niche products, the focus of attention has notably shifted away from FRAM. This is mainly due to the challenging integration and limited scalability of capacitor-based (1T-1C) as well as transistor-based (1T) ferroelectric memory cells. These issues are decisive upon the future of FRAM and can be traced back to the choice of the ferroelectric itself. The commonly utilized perovskites, e.g. PZT or SBT, do not provide the thickness scalability and CMOS-compatibility required for cost efficient, high density 1T-1C or 1T memory solutions. However, utilizing ferroelectric hafnium oxide based memory devices, this scaling and integration dilemma can be overcome. Highly scaled 1T memory cells at the 2X nm node, as well as the possibility of a DRAM-like 3D-integration of 1T-1C FRAM has been demonstrated. In this contribution the current status of this disruptive technology will be critically reviewed and its future potential assessed.

Biography
Dr. Johannes Müller is heading the group for Non-Volatile Memories at the Fraunhofer Institute for Photonic Microsystems (IPMS) in Dresden, Germany. He received the diploma degree in Applied Natural Science from the Technical University Freiberg, Germany, in 2007 and later joined the Fraunhofer Center for Nanoelctronic Technology (CNT), Dresden, Germany, which since 2013 operates as business unit of IPMS. In 2014 Dr. Müller received his Ph.D. in electrical engineering from the Technical University Dresden for his research on next generation high-k dielectrics and the investigation of ferroelectricity in hafnium and zirconium oxide. To date Dr. Müller has authored/co-authored 29 peer-reviewed journal papers, 32 contributions to international conferences, including invited presentations at IEDM, ECS, NMTS and SSDM, and several patents. He was awarded the "Georgius-Agricola-Medal" from the Technical University Freiberg in 2008, the "Scientific Paper Award" from Fraunhofer in 2012 and the "Cool Award" from the leading edge Cluster Cool Silicon in 2014. Dr. Müller is an active member of IEEE and serves as an expert for ferroelectric memories and devices in the Emerging Research Devices Working Group of the ITRS.

15:05
Engineered substrates for low-power IoT devices
  Thomas Piliszczuk, Senior Vice President, Marketing, Business Development and Global Sales, SOITEC
Engineered substrates for low-power IoT devices
Thomas Piliszczuk

Thomas Piliszczuk
Senior Vice President, Marketing, Business Development and Global Sales
SOITEC

Abstract
The ever-expanding number of mobile consumer electronics devices such as smartphones, tablets, cars, and wearable devices, we use in our daily lives, is driving the semiconductor industry growth, exceeding US$340 billion in sales per year. The Internet of Things (IoT) with its promising 50 Billion connected devices is expected to become the next fast growing technology mega-trend.
In mobile consumer electronics and IoT markets, the end-user stringent requirements include faster processing, increased data rates, longer battery life and lower cost.

In an effort to bring more performance, more functionality or less power consumption, innovation starting at the substrate level has demonstrated significant achievements. This includes radio-frequency silicon-on-insulator (RF-SOI) technology which is today in 99 percent of Smartphones. RF- SOI provides significant die cost advantage with increased performance and functionality for integrating RF front-end modules. In addition, fully-depleted SOI technology extends Moore's Law beyond 28nm to meet power/performance/cost requirements for low power SoCs. Concerning FD-SOI, the industry today is at a tipping point with strong industry support and a growing ecosystem including major leading foundries and fabless companies. Its low-power, significant performance, and cost benefits are making the FD-SOI technology attractive for mobile, wearable devices, and the Internet of Things, as well as automotive and networking applications.

In this presentation, we will show how engineered substrates enable device performance and cost effective SoCs for fabless and foundries in digital, RF, power and other emerging applications for low power IoT devices.

Biography
Thomas Piliszczuk joined Soitec in 2009 as Senior Vice President of Marketing, Business Development and Global Sales. He is managing a large international team to support Soitec business at the worlwide level.
Prior to Soitec, Thomas Piliszczuk was with KLA-Tencor, where he held various senior management positions related to business strategies and alliances with largest semiconductor companies worldwide. During his tenure there, Thomas Piliszczuk had responsibility of European Operations. Earlier in his carrier, Thomas Piliszczuk worked at Sematech managing advanced lithography projects.
Thomas Piliszczuk received his Ph.D degree from the Ruprecht-Karls-Universitat Heildelberg in Germany, an electrical engineering degree from the Gdansk Polytechnic University in Poland and business degree from Stanford University.

15:30 Coffee Break
Session 3

Energy efficient design technics

Chair Johannes Müller, Group Manager NVM, Fraunhofer IPMS
Johannes Müller

Johannes Müller
Group Manager NVM
Fraunhofer IPMS

Biography
Dr. Johannes Müller is heading the group for Non-Volatile Memories at the Fraunhofer Institute for Photonic Microsystems (IPMS) in Dresden, Germany. He received the diploma degree in Applied Natural Science from the Technical University Freiberg, Germany, in 2007 and later joined the Fraunhofer Center for Nanoelctronic Technology (CNT), Dresden, Germany, which since 2013 operates as business unit of IPMS. In 2014 Dr. Müller received his Ph.D. in electrical engineering from the Technical University Dresden for his research on next generation high-k dielectrics and the investigation of ferroelectricity in hafnium and zirconium oxide. To date Dr. Müller has authored/co-authored 29 peer-reviewed journal papers, 32 contributions to international conferences, including invited presentations at IEDM, ECS, NMTS and SSDM, and several patents. He was awarded the "Georgius-Agricola-Medal" from the Technical University Freiberg in 2008, the "Scientific Paper Award" from Fraunhofer in 2012 and the "Cool Award" from the leading edge Cluster Cool Silicon in 2014. Dr. Müller is an active member of IEEE and serves as an expert for ferroelectric memories and devices in the Emerging Research Devices Working Group of the ITRS.

15:50
Energy Efficiency Design Rigs for the IoT Ragbag
  Fady Abouzeid, Senior Design Engineer, STMicroelectronics
Energy Efficiency Design Rigs for the IoT Ragbag
Fady Abouzeid

Fady Abouzeid
Senior Design Engineer
STMicroelectronics

Abstract
The IoT applications buzz hides a very heterogeneous spread of applications, classified by O Ezzratti in four fields: smart home, machine-to-machine, smart cities, wearable. While machine-to-machine has been existing for more than 10 years, the IoT buzz and expectations is focused on the wearable devices. This presentation reviews design techniques which can be used to optimize energy efficiency of such power constrained applications.
The strongest lever to lower circuit power is well known: lower as much as possible the supply voltage until speed, variability or yields drops beyond specifications. Depending on power duty cycle various options can be used, here again the width of the application ragbag prevents us from making a definitive choice between leakage power dominated circuits and dynamic power dominated ones. Some alternatives will be presented.
Another way of lowering power is design margins reduction so that the majority of dies do not pay for the low performance of a few. This can be done by addressing low performing devices through fresh process compensation and can be applied either a posteriori of the design or a priori with greater gain in the latter case. Similarly, temperature which adversely affects Ion at low Vdd can be used with great benefits.
An alternative to low speed, low voltage option is to dynamically modulate Ion/Ioff by various way of embedded power gating or management either using a rush-to-sleep approach or dynamic voltage scaling.
Last, a short review of STMicroelectronics' technology and design solutions enabling this pervasive power quest will be presented, it includes:
- FDSOI 28nm with embedded Power Management IPs, dynamic biasing, low power memory and standard cells
- 40nm embedded Flash technology

Biography
Fady ABOUZEID received the M.S. (2007) and Ph.D. (2010) in Micro and Nano Electronics from Grenoble University, France. Since 2007 he has been with STMicroelectronics, Central R&D, Crolles, France in a research and development group in charge of hardening and qualifying IPs for space and terrestrial environments, and ultra-low voltage and high energy efficiency circuit design. His current research interests include digital ultra-low voltage circuits for sub-130nm CMOS down to FDSOI 28/14nm and low power EDA solutions.

16:25
Integrated Voltage Converters in Energy Harvesting Applications
  Peter Spies, Groupmanager, Fraunhofer IIS
Integrated Voltage Converters in Energy Harvesting Applications
Peter Spies

Peter Spies
Groupmanager
Fraunhofer IIS

Abstract
Energy Harvesting uses ambient energy like light, thermal gradients or vibrations to generate electrical energy for powering electronic devices. In that way, power cords or batteries can become redundant and real self-powered systems are possible. Typical energy transducers to convert ambient energy into electrical energy are solar cells, thermoelectric generators, inductive generators or piezo-electric materials. Most promising devices to be powered with energy harvesting are wireless sensors and sensor networks, but also displays or actuators in various application fields like the home automation business sector and the area of condition monitoring.
The power management composed by voltage converters is a key element in energy harvesting systems. Highly optimized semiconductor circuits adapt the voltage and current profile of energy harvesting transducer to meet the requirements of typical applications or storage elements.
In the presentation, the generic architecture of an energy harvesting system will be introduced and typical performance values of state-of-the-art transducers will be given. Several integrated voltage converters and charge circuits will be explained and performance data presented. Finally, a couple of practical applications of energy harvesting systems are presented.
In self-powered tracking systems, vibration transducers are employed to use the mechanical excitation from the vehicle to power a GPS-GSM-module. In a wireless window monitoring system, energy from light and thermal gradients powers sensors and a wireless transceiver. In a Bluetooth wristband, the heat of the human body is used to supply sensors and a Bluetooth module. An oval-wheel counter uses the energy of the fluids to power signal processing electronics and a GSM module.

Biography
Dr. Peter Spies studied Electrical Engineering at the University of Erlangen / Germany and graduated with a Dipl.-Ing. degree in 1997. In 2010, he finished his PhD thesis on the topic of power saving in mobile communication devices.
Since 1998, he is with the Fraunhofer IIS, power efficient systems department. He was working on the field of multi-standard front-ends and system simulations for communication applications. Since 2001 he is group manager of the "Integrated Energy Supplies" group where he is doing research and design on the field of power and battery management, energy transmission and energy harvesting. Focus of his group is integrated circuit and system design as well as software development. Most important applications are wireless sensor networks or hybrid and electrical vehicles.

16:50
Energy-efficient Analog and RF Circuits and Systems for Communications
  Frank Ellinger, Prof., Technische Universität Dresden
Energy-efficient Analog and RF Circuits and Systems for Communications
Frank Ellinger

Frank Ellinger
Prof.
Technische Universität Dresden

Abstract
We will present energy-efficient analogue and RF circuits and systems for wireless and wired communications.
Adaptivity regarding performance versus dc power can be used to reduce the power consumption of communication systems. In this regard, we present power amplifiers where the dc supply voltage can be adapted in real-time. Moreover, we will discuss bandwidth-adaptive circuits.
A further very efficient approach is based on the combination of high performance receivers and simple low power consuming wake-up receivers. By using duty-cycle approaches these wake-up receivers consume only a few tens of microwatts.
It will be shown that even at frequencies up to a few hundreds of GHz it is possible by advanced architectures and by using fastest BiCMOS technology to realise very efficient circuits. Since very large bandwidth can be achieved, the energy per bit can be very low.
A further possibility to improve the tradeoff between performance and power is based on smart antenna combining. In this regard, we will present control elements with reduced phase errors.
Last but not least we will present low power consuming TOLAE (thin film and organic large area electronic) circuits. The first fully integrated active data receiver is demonstrated which is fully integrated on a sheet of plastic. Because no rigid chips are required, the receiver is mechanically flexible and bendable. IGZO is used for the fabrication.

Biography
Frank Ellinger graduated from the University of Ulm, Germany, in electrical engineering (EE) in 1996. He received an MBA, PhD and habilitation degree in EE from ETH Zürich (ETHZ), Switzerland, in 2001, 2004 and 2004, respectively. Since August 2006 he is full professor and head of the Chair for Circuit Design and Network Theory at the Dresden University of Technology, Germany. He is the coordinator of the FAST zwanzig20 program with more than 80 partners (most of them from industry) and has been member of the management board of the Cool Silicon e.V. He is the coordinator of the DFG priority program FFlexCom. From 2001-2006, he has been head of the RFIC design group of the Electronics Laboratory at the ETHZ, and a project leader of the IBM/ETHZ Competence Center for Advanced Silicon Electronics hosted at IBM Research in Rüschlikon. Prof. Ellinger was the coordinator of the EU funded projects RESOLUTION, MIMAX and FLEXIBILITY. He has published more than 300 refereed scientific papers and his group has received more than 20 awards. Frank Ellinger has e.g. received the Alcatel-Lucent Science Award, the IEEE MTT-S Outstanding Young Engineer Award and was an IEEE MTT-S Distinguished Lecturer.

17:15
Ultra-Low Power Computational Sensing: Challenges and Opportunities
  Luca Benini, Professor, ETH Zurich
Ultra-Low Power Computational Sensing: Challenges and Opportunities
Luca Benini

Luca Benini
Professor
ETH Zurich

Abstract
The "internet of everything" envisions trillions of connected objects loaded with high-bandwidth sensors requiring massive amounts of local signal processing, fusion, pattern extraction and classification. Higher level intelligence, requiring local storage and complex search and matching algorithms, will come next, ultimately leading to situational awareness and truly "intelligent things" harvesting energy from their environment.
From the computational viewpoint, the challenge is formidable and can be addressed only by pushing computing fabrics toward massive parallelism and brain-like energy efficiency levels. We believe that CMOS technology can still take us a long way toward this vision. Our recent results with the PULP (parallel ultra-low power) open computing platform demonstrate that pj/OP (GOPS/mW) computational efficiency is within reach in today's 28nm CMOS FDSOI technology. In the longer term, looking toward the next 1000x of energy efficiency improvement, we will need to fully exploit the flexibility of heterogeneous 3D integration, stop being religious about analog vs. digital, Von Neumann vs. "new" computing paradigms, and seriously look into relaxing traditional "hardware-software contracts" such as numerical precision and error-free permanent storage.

Biography
Luca Benini is the chair of digital Circuits and systems at ETHZ and a Full Professor at the University of Bologna.
He has served as Chief Architect for the Platform2012/STHORM project in STmicroelectronics, Grenoble. He has held visiting and consulting researcher positions at EPFL, IMEC, Hewlett-Packard Laboratories, Stanford University.
Dr. Benini's research interests are in energy-efficient system design and Multi-Core SoC design. He is also active in the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications.
He has published more than 700 papers in peer-reviewed international journals and conferences, four books and several book chapters. He is a Fellow of the IEEE and a member of the Academia Europaea.

17:40
Energy Harvesting for Sensor-Near Electronics - Challenges and Solutions
  Dieter Hentschel, Head of Department, Fraunhofer IKTS
Energy Harvesting for Sensor-Near Electronics - Challenges and Solutions
Dieter Hentschel

Dieter Hentschel
Head of Department
Fraunhofer IKTS

Abstract
Structural Health Monitoring (SHM) applications in many industrial fields have gained significant attention. One of the most important physical method to achieve SHM is the detection of (material- inherent or stimulated) acoustical lamb waves. To detect lamb waves in (mostly larger) technical structures, it is necessary to implement a sensor network inside the structure.
These sensor networks are often "in the field", that means far away from any power supply. Furthermore, the usage of cabling is not desirable in many applications. Examples are the aircraft industry (each cable produces more weight) and rotor blades of wind energy plants (to avoid lightning flash damages). Completely in carbon fibre reinforced plastics (CFRP) embedded sensor nodes should also be wireless, because any additional cable could weak the stiffness of the structure.

For this reason, there is a need for completely wireless, self-sufficient sensor nodes.
Along the leading edge technology project »CoolSensornet« initiated and led by my Fraunhofer group and based within the leading edge technology cluster named »Cool Silicon« Fraunhofer IZFP and IKTS jointly develop energy autonomous and wireless sensor systems together with IMA GmbH Dresden, Technische Universität Dresden, ZMDi AG and RHe Microsystems GmbH. Those sensor systems are due to be used for monitoring large sized aircraft structures and wind power rotor blades long term. First results of the project revealed that with wireless acoustical lamb wave based sensors it is possible to detect damages after impact in CFRP materials.

Biography
Dr. Dieter Hentschel

Dr. Dieter Hentschel was from 2004 until 2013 business unit leader aerospace in the Fraunhofer Institute for Nondestructive Testing (IZFP) in Dresden. He is now working on the fields Structural Health Monitoring and Quality Assurance in the Fraunhofer-Institute for Ceramic Technologies and Systems IKTS in Dresden.
Dr. Hentschel is member of the CoolSilicon Cluster Management since its founding.

18:05 Networking Reception
Thursday, October 8, 2015
Session 4

Market view from automotive to healthcare and IOT

Chair Laurent Le Pailleur, Technology Line Management Director, STMicroelectronics
Laurent Le Pailleur

Laurent Le Pailleur
Technology Line Management Director
STMicroelectronics

Biography
Laurent Le Pailleur is director for advanced Cmos technology line with STMicroelectronics, Crolles France.
He previously enjoyed various positions as head of technology management (semiconductor, packaging and IPs) with ST-Ericsson, audio/power management product line and 2.5G mobile platform/3G mobile digital System-on-Chip product management at ST. This allowed him to develop deep understanding on RF, analog and digital technologies, architecture and system partitioning.

Prior to ST, he has been working on mixed-signal video systems and imaging digital processors design with Philips Semiconductors.
In 1989, he received the degree in electrical engineering from Caen National Engineering School, the M.S. degree in instrumentation and automation from Caen University and the Business degree from IAE (Enterprise Administration Institute).
He participated to numerous international conferences and hold multiple patents.

09:00

Keynote

 
Analyst view on IoT market evolution
  Yole Developpement
Session 5

Automotive SoCs challenges and solutions

Chair Laurent Le Pailleur, Technology Line Management Director, STMicroelectronics
Laurent Le Pailleur

Laurent Le Pailleur
Technology Line Management Director
STMicroelectronics

Biography
Laurent Le Pailleur is director for advanced Cmos technology line with STMicroelectronics, Crolles France.
He previously enjoyed various positions as head of technology management (semiconductor, packaging and IPs) with ST-Ericsson, audio/power management product line and 2.5G mobile platform/3G mobile digital System-on-Chip product management at ST. This allowed him to develop deep understanding on RF, analog and digital technologies, architecture and system partitioning.

Prior to ST, he has been working on mixed-signal video systems and imaging digital processors design with Philips Semiconductors.
In 1989, he received the degree in electrical engineering from Caen National Engineering School, the M.S. degree in instrumentation and automation from Caen University and the Business degree from IAE (Enterprise Administration Institute).
He participated to numerous international conferences and hold multiple patents.

09:30 TBD
09:55
Automotive multi-core architectures in the tension field of autonomy and hybridization
  Bjoern Steurich, Sr. Automotive System Manager, Infineon Technologies AG
Automotive multi-core architectures in the tension field of autonomy and hybridization
Bjoern Steurich

Bjoern Steurich
Sr. Automotive System Manager
Infineon Technologies AG

Abstract
Automotive industry is today mainly driven by three mega trends that can be described by the buzzwords electrification, automated driving and connectivity. The 1st includes all forms of electrification of belt driven mechanics, from auxiliary pumps till fully electrical vehicles, which is mainly driven by the ever increasing emission and fuel consumption regulations. The progress towards the 2nd thereby involves in several steps (starting with basic capabilities as e.g. traffic jam assistance). Even if the fully self-driving vehicle might need some decades till market maturity, the possible customer benefits are compelling (less traffic victims, additional fuel savings, reduced traffic congestion and a potentially increased productivity of the occupants). The latter is certainly the main motivation factor for the engagement of companies like Google and Apple and closely related to the last megatrend - connectivity. Connectivity includes the integration of consumer devices (tablets & smartphones), the connection of the car to the cloud (e.g. for remote diagnostics and potential software updates) as well as the car to car and car to infrastructure communication.
As a result, we see an evolution of the entire board net architecture away from distributed control (incl. almost one electronic control unit per mechanical function) to distributed computing with functions clustered in domains and connected by high-performance networks. Besides a considerable increase of the required computing performance, solutions are required to keep the autonomous car operational in the case of an error. Apart of the advantages of opening the car to the cloud, it also increases the attack surface so that a combined safety and security risk analysis will be required (incl. a potential extension of the ISO26262). Based on all these considerations an automotive multi-core architecture will be presented taking those requirements into account through innovative system on chip solutions.

Biography
Dipl.-Ing. Bjoern Steurich studied General Electrical Engineering at Saarland University. He started his career in 1995 at Siemens AG as a CMOS-ASICS designer.

Changing in 1997 to system engineering, he worked as microcontroller expert on a couple of customer projects (beyond others on an airbag ECU with Siemens Automotive).

After his change to product marketing, he was responsible for three generations of TriCore 32bit Microcontroller and from 2006 to 2009 for Infineon's regional automotive Microcontroller business in the US.

Since his return from US, he is working in Infineon's Automotive System Group focusing on powertrain, security and connectivity.

10:20 Coffee Break
Session 6

Think global : energy efficient systems (Healthcare and IoT)

Chair Fady Abouzeid, Senior Design Engineer, STMicroelectronics
Fady Abouzeid

Fady Abouzeid
Senior Design Engineer
STMicroelectronics

Biography
Fady ABOUZEID received the M.S. (2007) and Ph.D. (2010) in Micro and Nano Electronics from Grenoble University, France. Since 2007 he has been with STMicroelectronics, Central R&D, Crolles, France in a research and development group in charge of hardening and qualifying IPs for space and terrestrial environments, and ultra-low voltage and high energy efficiency circuit design. His current research interests include digital ultra-low voltage circuits for sub-130nm CMOS down to FDSOI 28/14nm and low power EDA solutions.

10:45
FD-SOI a new era for energy efficiency
  Olivier Thomas, Project leader, CEA Leti
FD-SOI a new era for energy efficiency
Olivier Thomas

Olivier Thomas
Project leader
CEA Leti

Abstract
Abstract- As electronic devices become increasingly integrated into our everyday environment, the design of energy efficiency from component to system becomes more important than ever. This talk will first present the research work performed in CEA Leti to design energy efficient computing systems and Ultra-Low-Power (ULP) Internet of Things (IoT) devices in 28nm FD-SOI technology. Then Silicon Impulse, the new Leti initiative to accelerate the development and the production of innovative industrial design solutions powered by leading edge technologies, will be introduced.

Biography
Olivier THOMAS received the M.S. Electrical Engineering degree from ISEN in 2001 and the Ph.D. degree from the Telecom ParisTech in 2004. He joined the CEA-LETI Laboratory in the Center for Innovation in Micro & Nanaotechnology (MINATEC), Grenoble, France in 2005. From 2005 to 2014 his research work was focused on advanced low-power digital and memory design in leading edge SOI technologies (PDSOI, FDSOI) and heterogeneous technology co-integration (ReRAM, 3DVLSI). From 2010 to 2012, he was a visiting researcher at Berkeley Wireless Research Center (BWRC) of University of California at Berkeley. He worked on methodologies to characterize on large-scale static/dynamic SRAM performances. From 2012 to 2014, he launched and led the Leti's advanced memory design activity. Since 2015, he is the project leader of Silicon Impulse for Leti. He is author or co-author of 75 articles in international refereed journals and conferences and 25 patents.

11:10
Ultra low power microsystems for IOT and wearables
  Simon Gray, Head of Marketing & Sales, CSEM
Ultra low power microsystems for IOT and wearables
Simon Gray

Simon Gray
Head of Marketing & Sales
CSEM

Abstract
There is no doubt IOT is changing the world we live in. From Smart Cities to E-Health, from Wearable technologies to Industry4.0, the way we work, live and play will be transformed in the coming years as new products and services are introduced. However for the market to reach the $19 trillion forecast a number of challenges remain. One of the main obstacles to further deployment is energy autonomy; increased functionality is often at the expense of battery life. Balancing additional functionality with greater autonomy requires optimization of each component in the product (sensors, ICs, communications) as well as network access and configuration. This presentation will review the practical limitations of IOT and Wearable devices in terms of energy budget and, by way of some recent examples, show how co-design of hardware and software can lead the way to robust low power systems.

Biography
Simon Gray is responsible for marketing and business development in CSEM's Integrated and Wireless Systems Division. CSEM has been a pioneer in low power ASIC design and is today one of the leading design centers in Europe for ultra low power wireless sensing SOCs and systems. Prior to joining CSEM he held senior technical and marketing positions in the semiconductor industry for companies including Philips, Xemics and Semtech. He has a BSc in Physics from Nottingham University and an MBA from Open University.

Session 7

IoT systems challenges

Chair Olivier Thomas, Project leader, CEA Leti
Olivier Thomas

Olivier Thomas
Project leader
CEA Leti

Biography
Olivier THOMAS received the M.S. Electrical Engineering degree from ISEN in 2001 and the Ph.D. degree from the Telecom ParisTech in 2004. He joined the CEA-LETI Laboratory in the Center for Innovation in Micro & Nanaotechnology (MINATEC), Grenoble, France in 2005. From 2005 to 2014 his research work was focused on advanced low-power digital and memory design in leading edge SOI technologies (PDSOI, FDSOI) and heterogeneous technology co-integration (ReRAM, 3DVLSI). From 2010 to 2012, he was a visiting researcher at Berkeley Wireless Research Center (BWRC) of University of California at Berkeley. He worked on methodologies to characterize on large-scale static/dynamic SRAM performances. From 2012 to 2014, he launched and led the Leti's advanced memory design activity. Since 2015, he is the project leader of Silicon Impulse for Leti. He is author or co-author of 75 articles in international refereed journals and conferences and 25 patents.

11:35
22nm FDSOI Technology & Devices for Energy-Efficient Applications
  Maciej Wiatr, Senior Manager Device Integration, Globalfoundries
22nm FDSOI Technology & Devices for Energy-Efficient Applications
Maciej Wiatr

Maciej Wiatr
Senior Manager Device Integration
Globalfoundries

Abstract
Current estimates forecast 26-30 Billion devices will be connected wirelessly to each other and to the Internet by 2020 forming the so called Internet Of Things (IoT). The ability of IoT devices to network and perfrom complex tasks with limited CPU, memory and power resources introduces special requirements to the IoT systems and the underlying semiconductor technologies. Globalfoundries develops new semiconductor technologies supporting the long-term vision of Billions and Billions IoT devices constrained by resources and power. 22 FDSOI technology from Globalfoundries offers unique characteristics suitable to serve IoT systems with the required balance between ultra-low power operation at adequate performance.

Biography
Maciej Wiatr graduated in the field of Solid State Electonics in 1997. During his PhD study at University of Kiel, Germany he focused on compact modeling of partially and fully-deplested SOI devices. After his PhD (2003) he joined the Design Enablement (modeling) group at Philips Semiconductors in Hamburg. In 2005 he joind AMD Dresden and worked on technology & transistor integration in 65, 45, 32 and 28nm technologies. He acompanied the transistion of GlobalFoundries from IDM (AMD) to Foundry business and has been assigned Senior Manager Device Integration in Dresden in 2014. His responsibilities include integration concepts of transistors, NONFETs and most recently also "More-Than-More" technology extensions like RF and NVM for 28/22nm technologies. Electrical parameter monitoring as well as definition of electrical monitoring structures and methodologies complete the field of his duties.

12:00
Efficient low power architectures design for wireless Security systems - Intrusion Alarms
  Philippe VIVANCOS, Security System Hardware Manager, Hager Security
Efficient low power architectures design for wireless Security systems - Intrusion Alarms
Philippe VIVANCOS

Philippe VIVANCOS
Security System Hardware Manager
Hager Security

Abstract
Hager Group is an independent Franco-German family-owned company operating worldwide.
Hager is a leading supplier of complete solutions and services for electrical installations in residential, commercial and industrial buildings. Product's offer ranges from Energy distribution through Cable management and wiring accessories to Building automation and Security systems including alarm systems, smoke detectors and access control devices.

Based on a full wireless architecture for both the power and the communication, most of the Intrusion Alarm devices are designed and developed under strong and challenging constraints in terms of low power consumption, long lasting battery life, radio performances as well as efficient sensor signal conditioning.

The content of the presentation will explain how low power consumption is addressed during the design and the development phases of wireless products in the Security domain.
Topics will cover both the hardware and the firmware design aspects.

Biography
- 1992, I received my engineering degree from Polytech'Grenoble in Industrial Computer Science, Instrumentation and Electronics.

- 1994, I started my professional life working for a System Integrator in Montpellier specialized in industrial automation and process control systems design. During two years, in addition to oversee the department of Automation & Electrical engineering, I participated to the design and the development of multiple projects in relation with the food industry, water treatment, quarries ...

- 1996, I joined Adaptive Micro Systems Europe in Grenoble, a brand new European subsidiary of an international U.S. company doing business in indoor & outdoor electronic LED displays signs (Billboards & Message Centers). During 18 years, I had the chance to fulfill different complementary positions such as Principal Architect for Hardware & Software designs, Project & Product Manager and finally Engineering Manager. This work experience gave to me a great opportunity to acquire and develop strong competences both in hardware, firmware and software in the following technological & technical fields: Embedded PC controllers, µC & FPGA based system architectures, High speed PCI-x video boards, Industrial communication & data acquisition gateways ...

- 2012, I joined Hager Group at the R&D Center located in Crolles where I hold the position of Hardware Manager for the entire Security systems product range.

12:25 Cool Silicon Award
 
12:45 Closing Remarks
  Laurent Le Pailleur, Technology Line Management Director, STMicroelectronics
12:50 Lunch