Friday, November 16, 2018
Session

Lithography

Chair Ayo Kajopaiye, Project Coordinator, Collaborative Technology Platforms, SEMI
Ayo Kajopaiye

Ayo Kajopaiye
Project Coordinator, Collaborative Technology Platforms
SEMI

Ayo Kajopaiye

Biography
Ayo is a Project Coordinator for SEMI and works in the Collaborative Technology Platforms group. His current work focuses on helping connect major players in various industries through SEMI’s Technology Communities. These groups help promote progress and address topics that impact their specific industry. He currently serves as the coordinator for the Smart Manufacturing Technology Community - America’s Chapter and helps manage certain activities for the Electronic Materials Group (EMG). Before joining SEMI, Ayo worked as a Project Coordinator at an architect firm in the Bay Area where he helped manage various retail projects for Apple Inc.

10:00
EUV Lithography optics - current status and outlook
  Dirk Jürgens, Program Systems Engineer, Carl Zeiss SMT GmbH
EUV Lithography optics - current status and outlook
Dirk Jürgens

Dirk Jürgens
Program Systems Engineer
Carl Zeiss SMT GmbH

Dirk Jürgens

Abstract
The year 2018 is generally perceived as year of breakthrough for EUV lithography. The introduction into HVM is currently being executed by multiple chip manufacturers and thus secures the continuation of Moore's Law far into the next decade. Furthermore, the development of High-NA EUV lithography as the next-generation lithography technology is well underway. This presentation provides an overview of the major performance improvements of EUV lithography optics achieved to until today and how High-NA EUV enables unprecedented resolution at high productivity.

Biography
Dr. Dirk Juergens studied Physics and Applied Optics at the University of Stuttgart, Rose-Hulman Institute of Technology, IN, USA, and University of Konstanz and received his doctorate degree in 2004. He joined ZEISS in 2004 as a scientist and worked on several positions in R&D and in systems engineering. Since 2018 he is Program Systems Engineers EUV in Carl Zeiss SMT GmbH.

10:25
From 2D to 3D SEM In-line metrology innovation
  Shimon Levi, SEM Metrology Application & Marketing Development, Applied Materials
From 2D to 3D SEM In-line metrology innovation
Shimon Levi

Shimon Levi
SEM Metrology Application & Marketing Development
Applied Materials

Shimon Levi

Abstract
Imagine that your CDSEM can measure on wafer, pattern edge slope or visualize undercut. For advanced 3D devices monitoring it can be a breakthrough. Imagine it can reconstruct pattern surface to reflect roundness or morphology variation. Such information can be obtained using cross section or delayering, but these methods are destructive and usually performed on a relatively small statistical sample. In recent years we have been developing 3D-SEM imaging capabilities to measure in-line, 3D pattern characteristics. Tilted beam imaging to measure pattern height, edge slope, undercut and foot. Height reconstruction method to measure pattern surface variation. Today these methods are being used in-line, offering measurements with large statistical sample supporting process monitoring, yield enhancement and enable acceleration of development cycle time. In this talk we will explore these innovative metrology methods, demonstrate measurement results, some of which performed in manufacturing fabs and review correlation to a reference metrology.

Biography
B.Sc and M.Sc in chemistry, the Technion, Israel Institute of Technology. Held positions of lithography R&D Eng for six years and Design for manufacturability section manager at TowerJazz Semiconductor for five years. Joined AMAT ten years ago, for the last six years positioned in Applied Materials marketing and technology group, SEM product line. In his current work he is focused on research and development of next generation metrology applications. Shimon has authored over 30 publications and holds several U.S patents.

10:50
Full wafer scale NanoImprint and Mask Less Lithography status and synergies for advanced manufacturing and pre prototyping at LETI
  Stefan Landis, Group Leader for Massively Parallel Electron Beam Lithography & Lithography Lab Deputy Manager, CEA-LETI
Full wafer scale NanoImprint and Mask Less Lithography status and synergies for advanced manufacturing and pre prototyping at LETI
Stefan Landis

Stefan Landis
Group Leader for Massively Parallel Electron Beam Lithography & Lithography Lab Deputy Manager
CEA-LETI

Stefan Landis

Abstract
In the lithography landscape, extreme-UV (EUV) lithography technology is now implemented in manufacturing lines. Meanwhile, 193nm immersion lithography, with multiple-patterning strategies, is still widely supporting the industry requirements for advanced-node develop¬ments, despite the tremendous effort required for process controls. Although these two options are suitable for high volume manufacturing, more affordable technologies are still needed for R&D evaluations, pre-prototyping and small scale productions. In such landscape, lithography alternatives maintain promise because they may present competitive compromises for the industry. Massively parallel electron-beam and nano-imprint lithography techniques remain highly attractive, as they can provide noteworthy cost-of-ownership benefits. In addition, directed self-assembly (DSA) lithog¬raphy shows promising resolution capabilities and appears to be an option to reduce multi-patterning strategies, and therefore the associated mask-set budgets. Even if large amount of efforts are dedicated to overcome the lithography side issues of these new patterning solutions, they introduce also new challenges and opportunities for the integration schemes. Through three collaborative R&D programs, IDEAL for Directed Self-Assembly Lithography, IMAGINE for Massively Parallel Electron Beam Lithography and INSPIRE for NanoImprint Lithography, CEA-Leti is currently assessing and boosting the development of these alternative technologies through strategic partnerships and innovative mix of them. In this paper, we will present how the development of the Massively Parallel Electron Beam Lithography may contribute to strengthen the supply chain of the NanoImprint Lithography through master manufacturing capabilities. We will review both Massively Parallel Electron Beam and NanoImprint Lithography technology status at CEA-LETI and then show some realizations.

Biography
Stefan LANDIS, Senior Scientist, received his Master’s Degree in Engineering in Physics and Solid State Physics, from the INPG Grenoble Engineering School and his Master of Science (MSc) in Quantum & Statistical Physics from Grenoble University. After a PhD thesis in patterned magnetic media for ultra-high density recording, he joined in 2001 the Lithography Laboratory of CEA-LETI to develop high resolution Ebeam lithography processes for CMOS devices. Then he has been in charge of the NanoImprint lithography activity for 14 years and recently managed the Multi Electron Beam Lithography Project at LETI for the development and qualification of the Mapper Lithography solution. He is now working on business development for patterning activities and services available at LETI. Author or co-author of more than 70 papers and 30 patents, Stefan Landis has edited two books Nanolithography and Lithography (ISTE-Wiley, 2011) and contributed to Plasma Etching for CMOS Device Realization book (ISTE Press- Elsevier, 2017).

11:15
Front-to-Back Alignment and Metrology Performance for Advanced Packaging
  Gareth Kenyon, Senior Applications Engineer, Ultratech
Front-to-Back Alignment and Metrology Performance for Advanced Packaging
Gareth Kenyon

Gareth Kenyon
Senior Applications Engineer
Ultratech

Gareth Kenyon

Abstract
Foundry customers and makers of leading-edge devices have established TSV for next-generation 3D and 2.5G packaging. Scaling the diameter of TSV’s is a major driver for improving system performance and cost but requires tighter back-to-front overlay. The transmission of IR wavelengths through silicon is utilised for embedded feature alignment and subsequent metrology. IR alignment can also be used for die to wafer, wafer to wafer bonding and photonics applications that are gaining in traction. Via Last applications enable distinct advantages for process integration, minimising the impact on BEOL processing and removing the requirement for TSV reveal processing. The Via Last TSV process introduces a requirement for lithography alignment, typically through thinned silicon to embedded targets. Performance enhancements can be realized by scaling TSV’s and landing pads, creating a critical parameter for overlay. In contrast, photonics devices require front alignment through full thickness silicon to marks on the back surface to a high degree of tolerance. The lithography system used in this investigation has a top IR alignment package with wavelengths that support back-to-front side alignment and metrology applications through full thickness 300mm silicon wafers. This paper details system methodologies used for both alignment and overlay metrology including routines to diagnose and compensate for measurement error due to focus and for Tool Induced Shift (TIS), critical for determination of system measurement error. We also discuss alternative use cases borne from the development including die-to-wafer misalignment. The in-line optical registration data was then correlated to detailed electrical measurements performed on the same wafers at the end of the process to provide independent assessment of stepper self metrology accuracy. Long term experimental overlay data was collected to determine robustness and repeatability of experimental wafer lots over a two month period.

Biography
Gareth is a Senior Applications Engineer based in Scotland, supporting customers worldwide. He has been employed with Ultratech for 26 years with an active involvement in the semiconductor industry for some 35 years, observing plenty of changes in that time! He has authored numerous publications on lithography & process technology. A graduate of Glasgow University, Gareth achieved an MBA with merit. When spare time permits, he is a keen golfer with a passion for Highland pursuits such as hiking and whisky.

11:40
Direct Imaging Solutions for Advanced Fan-Out Wafer-Level and Panel-Level Packaging
  Mark Goeke, Manager Product Engineering, SCREEN SPE Germany
Direct Imaging Solutions for Advanced Fan-Out Wafer-Level and Panel-Level Packaging
Mark Goeke

Mark Goeke
Manager Product Engineering
SCREEN SPE Germany

Mark Goeke

Abstract
In recent years, the increasing use of smartphones and other mobile devices has created a demand for even higher integration, speed and miniaturization of devices. As scaling according to Moore´s Law is slowing down, the industry is focusing to boost device performance by advancing in 3D integration and packaging. This trend has motivated SCREEN to develop an entire line-up of direct imaging systems for both application spaces - Wafer-Level and Panel-Level Packaging. This talk will outline the specific challenges an exposure tool has to cope with in the packaging arena. A unique method of image creation by using a proprietary spatial light modulator will be presented as well as image correction functions, that automatically adjust exposure data to prevent alignment errors. This feature resolves the previously challenging issue of positional deviation when rearranging the individual dies for fan-out processing.

Biography
Mark Goeke received his Master of Science in Photo Engineering from the University of Applied Science, Cologne in 1994. After holding various positions in lithography engineering he started working with Dainippon Screen Mfg.Co. (now Screen SPE, Germany) in 1999. Here he moved to hold the position of the Europen Product Engineering Manager, responsible for engineering, technology and product marketing for Screen´s product lines of lithography and single wafer processor equipment.

12:05 End