Tuesday, October 25, 2016
Session 1

Market and Solutions

Chair Steffen Kroehnert, Director of Technology, NANIUM S.A.
Steffen Kroehnert

Steffen Kroehnert
Director of Technology
NANIUM S.A.

Steffen Kroehnert

Biography
Dipl.-Ing. Steffen Kröhnert received his Master of Science degree in Electrical Engineering and Microsystem Technology at Technical University of Chemnitz, Germany, in 1997. In the same year he started his professional career as Development Engineer in the Corporate Package Assembly, Interconnect and Test Development Center for Semiconductors of Siemens AG in Regensburg, Germany. After carve out of the Semiconductors Business Unit to Infineon Technologies AG in 1999, he worked as Project Manager and moved to Infineon Dresden GmbH & Co. OHG in 2002 to support local setup of Package Development Department for Memory Products. He became R&D Area Manager Component Development and took over Technology Platform ownership for FBGA products. From 2006 he was working as Senior Manager in Qimonda Dresden GmbH & Co. OHG, the carve out of the Memory Products Business Unit of Infineon Technologies. Begin 2007 he was assigned to Qimonda Portugal S.A. to setup and lead Package Development team at volume production site. Since 2009 he is Director of Technology at NANIUM S.A. in Vila do Conde, Portugal. Steffen is author and co-author of 23 patent filings in the area of Packaging Technology. He is member of IEEE CPMT, IMAPS, MEPTEC, SMTA, VDI, VDE and GPM. He actively contributes as Co-Chair to SEMI Europe’s Advanced Packaging Conference (APC), as Technical Committee member to IEEE Electronic Components and Technology Conference (ECTC), IEEE Electronics System-Integration Technology Conference (ESTC) and IMAPS European Microelectronics Packaging Conference (EMPC), and as Assistant Technical Co-Chair (Europe) to IMAPS Device Packaging Conference and International Symposium on Microelectronics. Begin of 2016 he became chair of the SEMI Special Interest Group ESiPAT (European SEMI integrated Packaging, Assembly and Test).

13:30 Introduction
13:35
Welcome
  Yann Guillou, Membership Manager EMEA, Russia and CIS, SEMI
Welcome
Yann Guillou

Yann Guillou
Membership Manager EMEA, Russia and CIS
SEMI

Yann Guillou

Abstract
SEMI is welcoming you.

Biografie
Yann joined SEMI in 2011 and is managing the Membership Services of SEMI Europe. He started his career at STMicroelectronics as a New Technology Marketing engineer. He then worked in the CTO Office and Back End Sourcing organizations of ST-Ericsson, responsible for TSV and Advanced Packaging activities. Yann received a master degree on Materials and NanoTechnologies from the National Institute of Applied Sciences (INSA) as well as a specialized master on Innovation and Technology Management for Grenoble Business School(GEM).

13:40

Keynote

 
Market Drivers and Packaging Trends for Automotive: Leveraging Mobile Device Packaging Technology
  Jan Vardaman, President, TechSearch International
Market Drivers and Packaging Trends for Automotive: Leveraging Mobile Device Packaging Technology
Jan Vardaman

Jan Vardaman
President
TechSearch International

Jan Vardaman

Abstract
Electronic content in automotive applications has increased dramatically over the past few years. Automobiles are on the threshold of a radical change in technology. Vehicles have increased connectivity, improved self-diagnostics, a greater number of safety features including crash avoidance technology and advanced driver assistance. Mobile devices, including smartphones continue to drive unit volume growth and semiconductor packaging developments. While today’s WLPs, PoPs, and stacked die CSPs will remain popular—along with a number of other packages such as QFNs and FBGAs, can these packages meet the strict requirements of automotive electronics? Will the new mobile phone on wheels be able to leverage the technology developments and the economies of scale introduced by the mobile device era? This presentation explores the drivers for automotive packaging and examines the potential use of packaging and assembly technology from mobile devices.

Biografie
Jan is the editor of Surface Mount Technology: Recent Japanese Developments, co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbun), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia and on the US mission to study manufacturing in China. She is a member of IEEE CPMT, IMAPS, SMTA, and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. She received her BA in Economics and Business from Mercer University in Macon, Georgia in 1979 and her MA in Economics from the University of Texas at Austin in 1981. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

14:10
Advanced Laminate Substrate with Ultra-fine Wiring and High Density Interconnects
  Jeannette Koernert, Principal Technician Technology & Development, Globalfoundries
Advanced Laminate Substrate with Ultra-fine Wiring and High Density Interconnects
Jeannette Koernert

Jeannette Koernert
Principal Technician Technology & Development
Globalfoundries

Jeannette Koernert

Abstract
The established and widely used configuration for the lateral integration of multiple mid to large size silicon dies into a single package is based on conventional build up laminate substrates. Although a cost effective solution, the achievable routing and interconnect density is limited. On the other end of the spectrum, Silicon Interposer based consumer products were recently introduced to the market. These high performance products take advantage of the very high density interconnect and routing capabilities of Silicon technology to achieve a leading edge system-performance-to-power ratio and packaging density. To bridge the gap between these two technologies, SHINKO developed the “i-THOP®” (integrated Thin film High density Organic Package) technology. The “i-THOP®” substrate is based on the robust SHINKO laminate build up technology and combines this with newly developed fine line routing layers. By keeping the large size panel technology and using established processes and materials as well as existing supply chains, “i-THOP®” can provide significant cost advantages compared to Silicon Interposer. The new fine line layers offer a minimum 2 µm line/space (L/S) which is significantly better than conventional substrate technology. For many consumer and networking applications this routing capability is sufficient. A collaboration project between SHINKO, Amkor and GLOBALFOUNDRIES was established. The goal of this collaboration is to understand the feasibility of an “i-THOP®” based multi-chip module packaging technology and to prove the concept with an early reliability assessment (ERA). In support of the project, the partners developed a test vehicle (TV) consisting of a 15 mm x 21 mm “i-THOP®” substrate and two identical 9 mm x 9 mm silicon top dies. The substrate features two fine line top layers (FL) with L/S = 3/3 µm (FL1) and L/S = 2/2 µm (FL2). The substrate and the top dies are connected by Cu micro pillars manufactured at AMKOR at a 40µm pitch.

Biografie
Jeannette Koernert started her career at AMD’s (Advanced Micro Devices) wafer fabrication facility (Fab36) in Dresden, Germany. After various positions in Manufacturing Operations and the transition of the site to GLOBALFOUNDRIES Fab1, she is now the Principal Technician of the Packaging Development group. As such, she is the GLOBALFOUNDRIES project lead for the joint development project between GLOBALFOUNDRIES, SHINKO ELECTRIC INDUSTRIES and Amkor Technology, to proof feasibility of SHINKO’s i-THOP® technology.

14:35
Challenges of Ultra-thin LGA Package for Fingerprint Sensors
  Jensen Tsai, Deputy Director, Siliconware Precision Industries Co., Ltd
Challenges of Ultra-thin LGA Package for Fingerprint Sensors
Jensen Tsai

Jensen Tsai
Deputy Director
Siliconware Precision Industries Co., Ltd

Jensen Tsai

Abstract
Biometric features, such as Fingerprint, Face and etc, are good and convenient personal identifications for the mobile electronics application. Fingerprint recognition is one of the mature and popular detection methods. Its applications include not only smart phones but also banking card, credit card and wearable devices. Since the space is very limited inside Cards and wearable devices, ultra-low profile will be a Must for those applications. Therefore, a Land Grid Array (LGA)package with ultra-thin profile is employed for the assembly packaging. By using an ultra-thin substrate, thin molding and accuracy mold clearance control, it provides low profile and high sensitivity for the Fingerprint sensor. With thin substrate and the big sensor die, the major challenges of this ultra-thin LGA come from the warpage during the package assembly process. In order to diminish the warpage, lots of experiments were conducted extensively to reduce the package warpage, including molding compound selection (which focus on its CTE and Tg adjustments), post-mold cure optimization, and so on. In this paper, a test vehicle (10x10mm2 body size) with ultra-low profile (0.3mm package total height) was evaluated. Stress simulation was conducted to determine the package construction and work out the bill of material. Screen and corner DOEs which includes molding compound selection and post-mold cure parameters were performed to come out the optimal material and process window. Functional test and Reliability test have been passed as well. This ultra-thin LGA package has been proven to be a feasible and reliable packaging for the Fingerprint sensors.

Biografie
Deputy Director

15:00
Advanced Die Attach Platform for Advanced Packages
  Hugo Pristauz, VP Technical Development & Advanced Technology, Besi
Advanced Die Attach Platform for Advanced Packages
Hugo Pristauz

Hugo Pristauz
VP Technical Development & Advanced Technology
Besi

Hugo Pristauz

Abstract
The Internet of Things comes with a variety of new challenges in the More-than-Moore domain, driving enhancement for advanced semiconductor packages which are demanding for more advanced die attach machine technology. While still seeing flip chip as the dominant advanced package there are GPU and HPC applications requesting 2.5D/3D packaging technology. For form factor driven low/mid end IoT package stuff advanced SiP packages and wafer/panel level fan-out & embedded packages are becoming popular. On die attach side Besi is responding to this new advanced packaging trends with the "8800 advanced" platform which supports die attach technology for flip chip, fan-out packages, 2.5D/3D packages and advanced SiP's. The simple world of a 10µ flip-chip/dipping process has to be enhanced by substrate/wafer/panel level formats, wafer/tape&reel presentations, face-up/face-down placement with substrate/bond head pulse heat options, requiring placement accuracies down to 2µ@3sigma and enhanced bond control for thermo compression processes.

Biografie
Since begin of the millennium Dr. Hugo Pristauz has been working in equipment business for emerging semiconductor packaging technologies. After making his PhD in the field of control science at TU Graz in 1990 and starting his industrial career in an automation company he entered semiconductor business by joining Datacon in 1999, soon being assigned to a product manager position in order to manage the development and marketing of the successful 8800 Flip Chip platform, followed by a VP R&D position for Datacon's entire R&D activities. After acquisition of Datacon by Besi Hugo Pristauz was assigned in VP position to emerging business responsibilities for RFID Assembly (2005+), the entire Besi Flip Chip product line (2009+), and Besi Thermo Compression Bonding & Wafer Level Fan-Out business (2014+). Since begin of 2016 Hugo Pristauz is focusing on technology scouting and networking in order to support Besi's roadmap alignment process for advanced die attach equipment, supervising equipment key technology developments while coaching top flight R&D teams.

15:25 Coffee Break
Session 2

Technology and Modelling

16:00

Keynote

 
Rapid introduction of new technologies for future automotive systems
  Gabriele Ernst, Engineering Director, Robert Bosch GmbH
Rapid introduction of new technologies for future automotive systems
Gabriele Ernst

Gabriele Ernst
Engineering Director
Robert Bosch GmbH

Gabriele Ernst

Abstract
Advanced driver assistance systems, automated driving features, and comprehensive vehicle connectivity are key selling features for current and future automobiles as they have direct impact on the driver’s perception, comfort and safety. The race of car manufacturers towards smart mobility is both, a major challenge and an opportunity for the automotive electronics industry. Smart mobility requires highly integrated solutions with technology and packaging features and performance known from consumer electronics, but designed and approved for safety-relevant automotive applications under harsh conditions. Heterogeneously integrated packaging solutions will significantly increase technical complexity, although longer development cycles are not acceptable. At the same time automotive quality standards and lifetime requirements for the entire system have to be fulfilled, knowing that trends in automotive electronics will push the limits for certain applications to even higher levels than today. Therefore future packaging solutions in the automotive environment will be most probably not a “one fits all” but a tailored approach. The increasing number of packaging solutions with dramatically growing complexity rise the question of an economically viable qualification strategy. Key capabilities to be successful are a profound knowledge of technology features, the related failure modes, and quantitative characterization of materials and interfaces. Those will be the basis for improved simulation-based engineering already in early design phases. Different aspects of this methodology will be discussed, giving some examples and an outlook on future areas of improvement.

Biografie
Gabriele Ernst has studied physics in Tübingen, Grenoble and Cologne. She joined the group of Prof. von Klitzing in Stuttgart for her PhD specializing in semiconductor physics. For her thesis, she received the Otto-Hahn-Medal of the Max-Planck-Society. After her PhD she worked in the material science research lab of Bell Labs in Murray Hill, New Jersey before joining Bosch in 1998. At Bosch she held several positions in ASIC product engineering, manufacturing and development. Currently she is director for semiconductor technologies, assembly and EDA tools in IC engineering.

16:30
Lifetime modeling for packages with galvanic isolation
  Rainer Schaller, Development Engineer, Infineon Technologies AG
Lifetime modeling for packages with galvanic isolation
Rainer Schaller

Rainer Schaller
Development Engineer
Infineon Technologies AG

Rainer Schaller

Abstract
In More-than-Moore applications, the number and complexity of those micro devices increases, which are directly integrated into control units of power electronic systems that typically operate at working voltages in the range of 220-1000Vrms. This paper describes the methodology for finding a lifetime (LT) model of such semiconductor devices. In focus is design for reliability as well as keeping test time short to reduce time to market. A model function is presented based on a physical description of fail modes and the effects of environmental conditions. The investigated device is a magnetic field current sensor. The methodology explains the way from laboratory test to LT calculation. To reduce test time accelerated stress tests are used. Occurring physical effects and their relevancy for the product have to be understood. One example is partial discharge. Voids in material layers are of great concern as they strongly contribute to the isolation behavior. The acceleration stress is a high temperature, high humidity and voltage biased test e.g. Ttest=85°C, r.H.test=85%, Vtest=1400V DC. The current sensor has a galvanic isolation between sensor IC and a portion of the leadframe (measurement path). The device is specified with functional isolation 600Vp and a measurement current up to 50A. The acceleration drivers voltage, relative humidity and temperature have various physical influences on the aging effects and are therefore represented in different acceleration terms in the model function. The LT of our device is given by the equation: tlife=ttest*eβ(Vtest-Venv)*(rHtest/rHenv)n*e Ea/kBT(1/Tenv-1/Ttest) The LT tlife is calculated by multiplication of the test time ttest with the acceleration factors. The parameters β, n and Ea stand for certain failures. A statistical distribution of failure rate can finally be calculated. Folding with mission profiles from applications an accumulated degradation can be derived as well as definitions for test setup to proof a quality target.

Biografie
study of physics in Würzburg received diploma degree in 2011 diploma thesis: "Transport phenomenons in Quantum-Hall and Quantum-Spin-Hall-Regime" at the chair of Experimental Physics for Low Temperature physics, quantum transport and spintronics since 2011 with IFX 2.5 years as process engineer for optical wafer inspection in Front End production since march 2014 development engineer at Sensor Package Development Working on Ph.D. thesis "Insulation Coordination and Lifetime Modeling for Current Sensors" in parallel.

16:55
Thin copper wire under extreme HTSL stress duration: Crack failure mechanism characterization
  Alberto Mancaleoni, Senior Member of Technical Staff (Principal Realibility Engineer), STMicroelectronics
Thin copper wire under extreme HTSL stress duration: Crack failure mechanism characterization
Alberto Mancaleoni

Alberto Mancaleoni
Senior Member of Technical Staff (Principal Realibility Engineer)
STMicroelectronics

Alberto Mancaleoni

Abstract
Mission profiles for specific automotive applications are becoming more and more demanding from reliability point of view. Translating this challenging requirements into reliability targets, it means performing trials for longer duration, or using more accelerated conditions (increasing temperature or voltage, etc…). This study is focused on the failure mechanism understanding and characterization of a thin copper wire over Aluminum pad submitted to a very long stress duration at high temperature: more than 5000hrs @150°C. Going beyond AEC-Q100 (1000hrs @150°C) and AEC-Q006 (2000hrs @150°C) specified conditions for copper wires, it has been possible to observe the effects of the isothermal stress experienced by the Cu/Al bonding system, until the wearout. After thousand hours at high temperature a crack between Cu ball and CuxAlx intermetallic propagates from the ball edge to the ball center, affecting all the bonding area, causing an open contact. Crack propagation has been evaluated as second order effect of intermetallic growth and evolution, so its appearing is predictable by the Arrhenius law. Starting from the electrical results and the experimental evidences, the activation energy for the failure rate prediction has been estimated.

Biografie
Alberto Mancaleoni has 22 years of experience at ST in the field of integrated circuits reliability and qualification. From 2005 he has been working in ST Automotive Product Group, developing a specific know-how in plastic package failure mechanisms and reliability interactions between package and silicon technology. Riccardo Enrici Vaion received the M.Sc. degree in Electronic Engineering from Cagliari University, Italy, in 2009. Since 2011 he has been working in STMicroelectronics, Automotive Product Group, as product quality and reliability engineer. His activity is focused on the failure mechanism understanding of the microcontroller products,both from package and silicon point of view.

17:20
Heterogeneous Material Integration Enabled by Advanced Wafer Bonding
  Thomas Uhrmann, Business Development Director, EV Group (EVG)
Heterogeneous Material Integration Enabled by Advanced Wafer Bonding
Thomas Uhrmann

Thomas Uhrmann
Business Development Director
EV Group (EVG)

Thomas Uhrmann

Abstract
Combining compound semiconductors with different materials as well as integrating compound semiconductors with CMOS circuits or integrated photonics are growing trends to produce higher-performance electronic devices as well as enable many new applications. Wafer bonding has proven to be an enabling technology to achieve high-quality and cost-efficient production of such devices. For instance, low temperature plasma activated wafer bonding is now considered a core technology for III-V CMOS integration. Today, the rising demand for product applications, such as vertical SiC and GaN power devices as well as multi-junction solar cells, is driving the need for new developments in direct wafer bonding that allow for electrically conductive interfaces. Such developments can also open the door for implementing novel device concepts. Furthermore, new concepts like wafer-level die transfer bonding can bring compound semiconductor manufacturing into 200-mm and 300-mm production lines and enable greater integration of compound semiconductor manufacturing into the silicon world. This presentation will review plasma activated wafer bonding for compound semiconductor integration and a novel approach to oxide-free direct wafer bonding that demonstrates the ability to achieve an interface that has sufficient bond strength and electrical conductivity between materials of different properties—making heterogeneous integration of compound semiconductors a reality.

Biografie
Dr. Thomas Uhrmann is director of business development at EV Group (EVG) where he is responsible for overseeing all aspects of EVG’s worldwide business development. Specifically, he is focused on 3D integration, MEMS, LEDs and a number of emerging markets. Prior to this role, Uhrmann was business development manager for 3D and Advanced Packaging as well as Compound Semiconductors and Si-based Power Devices at EV Group. He holds an engineering degree in mechatronics from the University of Applied Sciences in Regensburg and a PhD in semiconductor physics from Vienna University of Technology.

17:45
Plasma Dicing 4 Thin Wafers
  Reinhard Windemuth, Sales Director Microelectronics Europe, Panasonic Automotive & Industrial Sales Europe GmbH
Plasma Dicing 4 Thin Wafers
Reinhard Windemuth

Reinhard Windemuth
Sales Director Microelectronics Europe
Panasonic Automotive & Industrial Sales Europe GmbH

Reinhard Windemuth

Abstract
Recently many issues came up when using conventional dicing methods. Such conventional methods are mechanical sawing (blade dicing) or laser dicing or stealth dicing. Relevant applications are thin wafers, brittle materials and wafer singulation for very small devices or LED or discretes. Plasma dicing is a recommended method to overcome many challenges of wafer separation. Damage free, water free, particle free and high throughput dicing can be realized by using plasma trench etch (dry etch) technology for dicing. Several technical and equipment aspects will be presented and discussed accordingly. Plasma dicing technology can provide solutions for high rate dicing, beautiful chip shape without any chipping and high bonding strength. Cost aspects: The throughput of a plasma chamber depends mainly on wafer thickness and is quite independent from wafer size or chip size. By using plasma for dicing the throughput can achieve more than 4 or 5 wafers per hour. Such cannot be achieved by any line-by-line dicing method as long as small chips are required. Significant cost savings can be expected. Advantages of plasma dicing are described in detail such as a. Damage Free / Chipping Free. b. Increase quantity of chips per wafer c. Water Free process d. Flexible Chip Shape e. Etching speed and characterisation f. Total Dicing Process Flow New materials for semiconductor devices are recently coming up on the market. Such as SiC base material and GaN-on-Silicon for power devices and discretes. Future challenges such as SiC dicing or GaN-on-Silicon dicing will be discussed. Typical topics on Plasma Dicing equipment are explained

Biografie
Degree of Diplom-Ingenieur in Process Engineering on Technical University in Munich / Germany in 1988. Since then Project Management & Sales for different kinds of Industy, mainly in chemical Industry. Since 1998 Sales & Project management in Microelectronics & Semiconductor Industry for F&K Delvotec, Wirebonding and Diebonding Technology. Profund experience in handling packaging projects in both Semiconductor and Device-Manufacturing Industry. Since 2006 Sales Director for Microelectronics Equipment at Panasonic Factory Solutions Europe (PFSE). Main target is to establish new PFSE business fields in the Backend and Frontend Industry in Europe: Dieattach, Flipchip, Plasma Cleaning and Plasma Etch Technolgies.

18:10 Networking Reception
Wednesday, October 26, 2016
Session 3

Testing and Qualification

Chair Peter Cockburn, Senior Product Manager - TCI, Xcerra Corporation
Peter Cockburn

Peter Cockburn
Senior Product Manager - TCI
Xcerra Corporation

Peter Cockburn

Biography
Peter Cockburn has worked in the ATE industry for over 25 years at Schlumberger, NPTest, Credence, LTX-Credence and now Xcerra. He has developed real-time and GUI software for ATE systems, managed the launch of several SOC ATE systems and new analog test options and provided marketing and sales support in USA, Asia and Europe. As Senior Product Manager in the Test Cell Innovation team, he is now defining new ways to reduce time-to-volume and test cost, increase uptime and improve quality when testing semiconductors. He has an Engineering degree from the University of Southampton, UK.

09:00 Introduction
09:10

Keynote

 
Semiconductor Test: A moving target cost, A changing landscape
  Cedric Mayor, Chief Technology Officer, PRESTO ENGINEERING
Semiconductor Test: A moving target cost, A changing landscape
Cedric Mayor

Cedric Mayor
Chief Technology Officer
PRESTO ENGINEERING

Cedric Mayor

Abstract
Traditionally, semiconductor test cost has been viewed as a quality component that tracked COGS reduction like transistor cost shrink. With adoption of connected and smart automotive applications and the internet of everything, new test requirements will drive the cost portion of COGS up; those requirements include secure chip testing, new RF connectivity transcievers, millimeter wave, etc. We will discuss how those costs component goes up and how they can be managed.

Biografie
Prior his inception as Chief Technology Officer at Presto Engineering, Cedric served as corporate program manager for Philips Semiconductor and then NXP semiconductor where he was responsible for Silicon New Product Introduction in advanced process nodes. In charge of product line yield maturity, he managed external foundries transfer of front-end specialty options for RFBiCMOS, and BCD in high volume manufacturing. Cédric holds a MS-EE from Ecole Centrale in France, four patents in the area of chip design and DFX, and contributed to several publications in the field of design and semiconductor product test.

09:40
Looking on Modern Automotive Aspects for Chip Assembly, Chip Testing, and Chip Qualification
  Joachim Kusterer, Technical Manager SCM, RoodMicrotec
Looking on Modern Automotive Aspects for Chip Assembly, Chip Testing, and Chip Qualification
Joachim Kusterer

Joachim Kusterer
Technical Manager SCM
RoodMicrotec

Joachim Kusterer

Abstract
In recent years demands on quality and reliability of electron devices for automotive applications have increased significantly. Depending on particular applications, device failure rates are often as low as 1 to 5 ppm for 0km and field rejects. Hence, qualification procedures according to AEC Q100/101/200 are in most cases not sufficient any more. Therefore, state of the art are application targeted qualification methods based on principles of “Robustness Validation”. The heart of such investigations are “Mission Profiles” describing specific device application. In this presentation critical aspects of chip assembly will be discussed such as tight lead pitches, thermal mechanical stress and fatigue, multiple row QFNs, cracks and voids in solder joints, and wettable flanks for sidewall metallisation. Furtheron, we will show potential qualification routines based on statistical analysis of failure modes of sufficient numbers of devices from different fabrication lots in order to specify margins of a device used in a certain application. Finally, aspects of device test will be presented such as wafer test and final test under different ambient temperatures, stress tests at high voltage and high frequency, statistical analyses like PAT or Good Die Bad Neighborhood. All parts of the discussion will include results of our failure analysis lab for illustrations of different failure types and failure mechanisms.

Biografie
Technical Manager RoodMicrotec GmbH Stuttgart

10:05
Wafer/ Package Test, WLCSP Test Contacting Performance and Reliability
  Bert Brost, Product Manager, Xcerra - Multitest
Wafer/ Package Test, WLCSP Test Contacting Performance and Reliability
Bert Brost

Bert Brost
Product Manager
Xcerra - Multitest

Bert Brost

Abstract
This paper will describe new high performance spring probes and how they are being designed and deployed to meet the electrical requirements of today's WLCSP DC to GHz bandwidth testing environment, without sacrificing mechanical performance. In addition, the paper will provide information on new WLCSP test socket standards required for single and multisite high parallelism contacting in automated test and manual/hand test. Described is how new WLCSP spring probe contactors designs are reducing the cost to acquire and the cost to use contactors while increasing WLCSP test throughput.

Biografie
Bert Brost Product Manager Xcerra - Multitest 4444 Centerville Road St. Paul, MN 55124 USA Biography Bert Brost has worked in semiconductor test for 35 plus years. His career includes developing IC test handlers and IC test measurement electronics and firmware. In his spare time, Bert is an armature radio operator . Bert says he is lucky because electronics are both his hobby and his job. Bert has several under graduate degrees and an MBA. Most recently, Bert joined Xcerra as a Multitest product manager.

10:30
Non-Equilibrium Gas-Dynamic Effects in Inertial Sensors
  Cristian Nagel, Ph.D. Student, Robert Bosch GmbH
Non-Equilibrium Gas-Dynamic Effects in Inertial Sensors
Cristian Nagel

Cristian Nagel
Ph.D. Student
Robert Bosch GmbH

Cristian Nagel

Abstract
MEMS acceleration sensors have been systematically analyzed across a wide temperature range [1]. Failure mechanisms such as offset drift (TCO) and sensitivity drift (TCS) induced by the thermal mismatch of different materials are mostly understood [2]. However, in complex electronic devices (e.g. smartphones) the distances between adjacent components are small. Thus, power intensive (hot) components like microprocessors can create non-equilibrium temperature distributions in small components in their vicinity. [3] The influence of those temperature gradients on MEMS sensors has never been investigated before. Therefore, a measurement system has been developed to apply a static temperature difference (ΔT=T2-T1) between the bottom and top side of a sensor. The temperatures T1 and T2 are controlled by two Peltier elements that are connected to copper inserts. The sensor (soldered onto a PCB) is placed between those copper inserts and clenched with soft thermally conductive pads on the top side of the sensor and the bottom side of the PCB. The system rotates in the earth’s gravitational field to investigate the signal offset and sensitivity. Detailed analysis were carried out using a LGA-type inertial sensor (BMI160 provided by Bosch Sensortec). The temperature gradient ΔT across the stack sensor/PCB was varied between 0 K and ±5 K, representing maximum values for smartphones [3]. The offset of the z-axis shows a linear dependency on the temperature gradient with a maximum offset deviation of 100 mg. The CTE mismatch of different materials can be excluded as root cause for this effect. Presumably, the effect must be attributed to the temperature distribution of the gas within the MEMS cavity. Different physical hypothesizes including classical momentum transfer, heat induced fluid motion and non-continuum effects (such as Knudsen forces or thermal creep forces) are presented and their correlation with experimental results discussed.

Biografie
Cristian Nagel is a Ph.D. student at the Applied Research Department of Robert Bosch GmbH in Renningen, Germany. He has joined the team in January 2015 and is since working on gas dynamic effects in MEMS (micro-electromechanical systems) acceleration sensors and advanced interconnects for MEMS on foil and MEMS embedding in foil. Cristian Nagel was born in Zwickau, Germany on 18th December 1990. After college in 2009 he started his Bachelor's studies in mechatronics at TU Chemnitz. Before graduating in 2012, Cristian engaged in electronic nanosystems at Frauenhofer Institute (ENAS) and invented and simulated microfilters for blood filtration. In the same year he started his Master´s studies in micro- and nanoelectronics while working on DSMC gas flow simulations and reduced order modeling of MEMS accelerometers. In 2014, Cristian successfully graduated from University of Chemnitz with a Master of Science.

10:55 Coffee Break
Session 4

Application and Processes

11:45

Keynote

 
Application-Driven Challenges in Automotive Packaging
  Tobias Helbig, Sen Director CTO Innovation Management & Programs, NXP Semiconductors
Application-Driven Challenges in Automotive Packaging
Tobias Helbig

Tobias Helbig
Sen Director CTO Innovation Management & Programs
NXP Semiconductors

Tobias Helbig

Abstract
The automobile is in the middle of a transition. Seamless connectivity within and towards other cars enable a seamless entertainment and advanced safety. Increasing transition to advanced driver assistance and ultimately self-driving cars make driving less stressful and much more save. While increases in energy efficiency reduce CO2 emissions significantly. Making these transitions poses high requirements on the performance, quality and reliability of electronics, ICs and ultimately packaging. Must-haves in automotive are zero defect from day one together with meeting extended robustness and temperature ranges for the lifetime of cars. The presentation motivates the requirements on packaging resulting from automotive applications and provides examples how to meet them. This touches on material choices and processing capabilities for classical packages, solutions for additional optical inspection to safeguard zero defect, mastering Cu bonding for zero defect AEC-Q100 Grade 0 products, driving package size reductions and meeting highest performance requirements for automotive radar applications.

Biografie
Tobias Helbig is Senior Director Innovation Management & Programs with NXP Semiconductors BU Automotive CTO. He is responsible for steering the innovation and technology roadmapping and program definition of NXP’s automotive business. NXP is market leader in automotive semiconductors and active in automotive ICs for sensors, entertainment, advanced analog, microcontrollers and advanced driver assistance. Prior to that, Tobias was in Philips Research leading teams as well as program definition in the short-range and cellular communications domain. He managed the global development of NXP’s car entertainment business. And he lead NXPs product line audio amplifiers as general manager. Tobias holds a Master and PhD degree in Computer Science from University of Stuttgart, Germany.

12:15
Effective EMI Shielding for Semiconductor Packages through Novel Conformal Coating Solutions
  Jinu Choi, Market Development Manager, Henkel
Effective EMI Shielding for Semiconductor Packages through Novel Conformal Coating Solutions
Jinu Choi

Jinu Choi
Market Development Manager
Henkel

Jinu Choi

Abstract
Wi-Fi and Bluetooth modules, power amplifier modules, memory systems and other wireless transceiver chipsets enable innovative and optimal user experiences largely influenced by the growth of Internet of Things (IoT) applications. However, these radio-frequency (RF) emitting devices require effective isolation to limit the propagation of their interference to neighboring components to protect the end device from performance degradation. Consequently, advancement in electromagnetic interference (EMI) shielding technology is continuing to become a critical factor in electronics design as various industries move toward miniaturization, lighter weight and higher speeds than the previous generation. So far, the industry norm has been to use custom designed metallic cans. However, due to its drawback of consuming large, valuable space and requiring complex and inflexible board layouts, alternative solutions to metallic cans are increasingly gaining interest, including sputtering and spraying. While metal sputtering can be used for conformal coating, package designers are finding out that this physical vapor deposition method presents an inherent challenge as it always requires pre-treatment on organic surfaces, temperature control and substantial capital for to its large vacuum chamber machine and supporting materials. To address these challenges, Henkel has developed a unique, organic silver coating-based material with rheological properties that provide reliable performance in stressful electronic conditions. The thinly coated material (as low as 3 um thick) provides high shielding effectiveness, uniform coating coverage, excellent adhesion to untreated organic surfaces and is applied at room temperature. Furthermore, this novel material technology allows easy production scalability and design flexibility with minimal cost of ownership.

Biografie
Jinu Choi is a Market Development Manager at Henkel Electronics responsible for global product strategy and business development of advanced materials. He has extensive experience in engineering and product management driving innovative solutions to market in various technology industries including mobile communications, consumer electronics, and telecommunications with products ranging from semiconductors to end user devices. He is based in Henkel Electronics headquarters in Southern California, and holds a BS degree from KAIST and an MBA from Paul Merage School of Business at University of California, Irvine.

12:40
Silicones: a key material to support innovation in the Semiconductor Packaging industry
  Thomas Seldrum, Associate Application Engineer Specialist, Dow Corning Europe s.a.
Silicones: a key material to support innovation in the Semiconductor Packaging industry
Thomas Seldrum

Thomas Seldrum
Associate Application Engineer Specialist
Dow Corning Europe s.a.

Thomas Seldrum

Abstract
The constant search for a smaller package form factor, higher integration (2.5D and 3D) and higher device density raises some questions about the impact on the reliability due to generation of thermal stress and mechanical stress on the device. This paper presents some of the innovations developed by Dow Corning in order to meet some of today’s semiconductor packaging industry challenges. A variety of products, targeting the different phases of the assembly process are being developed: die-attach adhesives, lid-seal adhesives and thermally conductive interface materials. The intrinsic properties of silicones bring key benefits for the reliability of microelectronic devices: high thermal resistance over the operating temperature range and very low modulus to release the stress induced during the process steps or the operation of the device in the field. The presentation will detail the reliability results achieved on last generation die-attach adhesives with very thin bond line thickness; thermal interface materials with a high thermal conductivity (4.3W/mK) and low thermal impedance (6mm²°C/W); and a lid-seal adhesive developing adhesion on a broad variety of substrates (metals, plastics, cured silicones and others) and curing quickly at low temperature (15 minutes at 100°C). Smaller form factors, higher device density and vertical integration of devices are technology trends which are all pointing in the same direction: the need of a stress release material will become more and more a requirement to meet the reliability standards and silicones are probably one of the best candidates to meet these challenges.

Biografie
Primary Responsibilities Dr. Thomas Seldrum is a member of the Application Engineering group in the Electronics Solutions division at Dow Corning. Based at the company’s European headquarter in Seneffe, Belgium, he is responsible for the technical support of European customers using Dow Corning’s Compound Semiconductor Solutions (SiC substrates) and Silicone Solutions. Experience and Expertise Thomas joined Dow Corning in 2011 as an application engineer, bringing the technical expertise needed to initially develop the silicon carbide business in Europe. Over the next years, his field of responsibilities has been extended to microelectronics and power electronics applications where silicones are used as protective and assembly materials. He is providing technical support to implement disruptive technologies developed by Dow Corning. More recently he extended his responsibilities further and joined the Automotive Electronics team to develop and implement innovative technologies in the design of next generation electronics modules. Thomas’ ability to understand customer needs and drive new technology to market will help Dow Corning to support the electronics industry in addressing the challenges created by world’s major societal trends. Education Thomas holds a Master degree and PhD in Physics and a Master degree in Economics from the University of Namur, Belgium.

13:05
Increasing Die Strength & Device Yields Using Plasma Dicing
  Richard Barnett, Product Manager, Etch Products, SPTS Technologies Ltd
Increasing Die Strength & Device Yields Using Plasma Dicing
Richard Barnett

Richard Barnett
Product Manager, Etch Products
SPTS Technologies Ltd

Richard Barnett

Abstract
Plasma dicing promises significant benefits to device manufacturers and packaging houses, including increased wafer throughput and die per wafer, which contribute to lowering the cost per die. Recent work has also proved that the low damage plasma processing can also significantly increase die strength, which may be a primary concern for devices which have to operate in harsh environments or subject to regular impact or vibrations. In this work we have investigated the hypothesis in greater detail to quantify the difference in die strength across a range of plasma dicing processes to compare the effects of notch size and sidewall roughness which occur to some degree in all dicing techniques. Many users will wish to avoid an additional and relatively costly photolithography step, or have non-silicon layers in the dicing lanes which need to be removed before plasma dicing. Therefore techniques using both mechanical saw and laser etching to pre-define the dicing lane prior to plasma etching were also investigated. Neither technique requires an additional masking step, but the user would compromise some of the potential benefits of the new technology, e.g. limiting ultimate minimum dicing lane width, restricting use of the more flexible die shapes and some of the potential for increased throughput. It was found that there is approximately two times improvement in die strength gained from employing plasma dicing techniques than from conventional blade or laser methods. There is some variation due to the patterning method adopted, but not overly significant. However, if the plasma processing is not controlled correctly, resulting in “notching” under the die at the tape interface, then the die strength is lower than that from the conventional singulation techniques. This presentation will introduce how the effective use of end-point control and pulsed-bias is essential to manage the overetch and notching of the die to deliver stronger die and more good die per wafer.

Biografie
Richard Barnett is Etch Product Manager at SPTS, and has 20 years’ experience in the semiconductor and electronics manufacturing industries. Prior to his current role, Richard worked in product management and as a process engineer at both Aviza and Surface Technology Systems (STS), prior to their merger to form SPTS. Earlier in his career Richard worked at Pure Wafer plc, Lucas Aerospace and European Semiconductor Manufacturing, and began his career with LG Semiconductor as a member of their first overseas fab engineering team in the diffusion/wet-etch process group. Richard holds a Bachelor’s degree in Engineering for Material Engineering and Electronics from the University of Nottingham, and has published technical articles related to silicon DRIE and delivered multiple presentations on wafer processing technologies.

13:30 Closing Remarks