A To top
Amkor Technology Inc Amkor Technology Inc John, Gerard
MEMS Sensor Testing - Yesterday, Today and Tomorrow (an OSAT's perspective)
John, Gerard

John, Gerard
Sr Director Advanced Test
Amkor Technology Inc

John, Gerard

Abstract
The concept of MEMS sensor testing has evolved from a fantasy to a reality over the last two decades. What was once considered impossible in high volume manufacture has now become mainstream in the industry. Initially, MEMS sensor devices were introduced as an alternative to bulky technologies, with lower performances than their predecessors. However, today's MEMS devices with proven reliability and performances have surpassed their predecessors and are competing with their high-cost and high-end counterparts. Examples of such MEMS sensor devices can be seen in the MEMS microphones whose early specifications started off as a simple audio transducer, now has morphed into high-fidelity MEMS device, competing with the high-end studio microphones. Testing such “high-performance” MEMS sensor devices in high volumes at the lowest possible costs with little or no compromises calls for an innovative combination of test techniques and close cooperation between the OSAT and the MEMS design engineers, product engineers and the applications engineers. Areas that are often overlooked are, the form factor of the device under test, the use of test techniques that can provide a higher throughput than electrical testing and the final end application. The ability to include self-test and self-calibration structures into the design will reduce the test burden. The main challenge faced during MEMS sensor test is in the stimulus development, while the electrical testing can be easily accomplished by a low-end tester. When creating MEMS test specifications, a careful balance needs to be drawn between too much and too little test coverage. This keynote focuses on the evolution, challenges, and opportunities for MEMS sensor testing spanning the yesterdays, today and will provide a vision for the future of lower cost MEMS sensor test.

Biography
Gerard joined Amkor in 2005, and has supported and managed hardware and software test development for a variety of Amkor packaging. He currently serves as an advanced test technical expert for MEMS, 2.5D, WLFO, HDFO, fine pitch probe and optical devices, supporting customers in the US and Europe. Prior to joining Amkor, Gerard worked in various semiconductor test positions for Conexant Systems, Flarion Technologies (acquired by Qualcomm) and Motorola. He holds a BA degree in electronics and telecommunications engineering from Osmania University and an MBA from Gainey School of Business in Michigan. He holds multiple patents in the field of MEMS Test.

APC
Atotech Deutschland GmbH Atotech Deutschland GmbH Walter, Andreas
Electroless ternary nickel alloys for under bump metallization (UBM) on power semiconductors for high temperature process conditions or applications
Walter, Andreas

Walter, Andreas
Electroless Team Manager
Atotech Deutschland GmbH

Walter, Andreas

Abstract
The presentation will show benefits and feasibility results for electroless plating of different ternary nickel alloys in comparison to the standard electroless phosphorous-containing nickel for packaging in growing power electronics or automotive industry. Standard electroless phosphorous-containing nickel for ENEP* or ENEPIG** under bump metallization has the disadvantage that at temperatures above 350°C a phase transition occurs which leads to a layer stress change and may cause cracks in the under bump layer. Ternary nickel alloys reveal no phase transitions up to 600°C, and are an excellent alternative to the standard electroless medium or high phosphorous-containing nickel for high temperature processing post nickel deposition, and high temperature soldering or applications. The paper will showcase results of the advanced properties of three different electroless ternary nickel alloys in comparison to a standard medium phosphor and a low phosphor nickel, with regards to thermal behavior, stress shift, and facture toughness. *electroless nickel, electroless palladium ** electroless nickel, electroless palladium, immersion gold

Biography
Andreas Walter has more than 18 years experience in the semiconductor industry and is currently working as head of application for electroless plating processes for Semiconductor Advanced Packaging at Atotech. Prior to joining Atotech in 2009, he worked for 3 years as an Senior Engineer at Qimonda for process integration of new memory systems, and for 7 years as a Development Engineer at Infineon, where he was responsible for material development and process integration in 300 and 200mm fab for D-RAM and resistive memories. Andreas received his Diploma and PhD in chemistry at the Martin Luther University in Halle, where he started as a scientist for synthesis of OLED dyes and organic semiconductors.

Power Session
Atotech Deutschland GmbH Atotech Deutschland GmbH Schmidt, Ralf
Enhanced Mechanical Properties of Copper for Fan-Out Wafer Level Packaging Applications
Schmidt, Ralf

Schmidt, Ralf
R&D Manager, Semiconductor
Atotech Deutschland GmbH

Schmidt, Ralf

Abstract
Redistribution layers are essential to a variety of packaging technologies, as it is with more RDLs that I/O density is increased. Increasing the I/O count allows for more complex, high speed die to be packaged and supports improved reliability performance. Next generation devices for FOWLP require decreasing the RDL pitch down to 2x2µm. Successful formation and plating of such fine features, however, pose a challenge for both suppliers and manufacturers, with the primary plating challenge being the simultaneous plating of ultra fine L/S, large Cu pads, and filling of microvias with a deposition rate that optimizes throughput. Additionally, the mechanical properties and impurity requirements for the Cu deposition become more difficult to control and optimize with sub 10µm L/S: 1) (large) optimum grain size, polygonal Cu crystal structure for high (ductility) mechanical strength and low resistivity which impacts electrical performance; 2) low internal stress for minimized wafer warpage and good adhesion – both of which impact yield; and 3) low organic co-deposition for minimized micro voiding. Electroplating with standard Cu electrolytes results in micro voiding that amass after thermal cycle testing and may lead to failures or breakages in the Cu metal lines. To overcome this, the bath conditions, additives, and current density should be adjusted to optimize their influence on the deposit properties in terms of impurities and grain size. This paper will discuss how the mechanical properties of Cu can enable higher reliability, and will present plating results achieved with a new electrolyte.

Biography
For the past 6 years Ralf Schmidt has held various roles related to R&D at Atotech Deutschland GmbH, wherein he focused primarily on the development of innovative copper plating processes. He was Team Manager for the central R&D team New Methods & Technologies and has recently assumed the role of R&D Manager Semiconductor Advanced Packaging. He started at Atotech in 2011 in the central R&D team, where he focused on a variety of topics including additives for electrolytic and electroless Cu deposition as well as electrolytic and electroless Ni processes. Ralf recieved his PhD in Chemistry at the Julius-Maximilian University of Würzburg, Germany, where he began his career as scientist for the synthesis of dyes for organic electronics.

APC
C To top
CEA Leti CEA Leti Fournier, Jacques
Secure packaging for addressing hardware security challenges
Fournier, Jacques

Fournier, Jacques
Senior scientist
CEA Leti

Fournier, Jacques

Abstract
The advent of the IoT has put the device on the centerstage of security-related debates. Attacks on the device itself can have a severe impact on the provided services (e.g. attacks on the Philips Hue lamp). Conversely, the device can be an attack entry door for the entire system (e.g. the connected cameras used making a D-DoS on DNS servers). Protecting the device does not only mean that we need to protect the way the device is architectured, the way the embedded applications are implemented but also the way the device is manufactured and packaged. In this presentation, we shall first introduce the underlying hardware security issues before focusing on physical attacks like reverse-engineering, side channel analysis and fault attacks. We shall then explain how some of those issues can be addressed with a secure packaging. We shall provide an overview of existing secure packaging technologies and conclude on the remaining challenges for innovative secure packaging solutions.

Biography
Dr Jacques Fournier is a Senior Scientific Advisor in embedded systems’ security at the CEA Leti which he joined 2009. Prior to that, he held several technical positions in the Security Lab of smart card manufacturer Gemalto from 2001 to 2009. Jacques obtained his “Habilitation” from the University of Limoges (FR), a PhD from the University of Cambridge (UK), an MSECE from Georgia Tech (USA) and an engineering degree from the French Grande Ecole Supélec.

APC
Cohu Cohu Waldauf, Alex
Advanced package test solution for the automotive market
Waldauf, Alex

Waldauf, Alex
VP of Platfrom Engineering
Cohu

Waldauf, Alex

Abstract
Consumer demand and competitive pressure have pushed automotive manufacturers to build greater intelligence into automobiles and trucks. For example, the Chevy Volt uses nearly 100 microprocessors running about 10 million lines of code in total, placing the Chevy Volt's software content close to that of the Boeing 787 Dreamliner. As with that electric vehicle, mainstream automotive design is increasingly relying on more sophisticated electronic systems. Indeed, advances in automotive technology revolve around five key trend: • Advanced Driver Assistance System (ADAS) and autonomous driving • Advanced Motor Control • Engine/Energy Management Systems • Graphical Interfaces and entertainment • Vehicle System of Systems in the Internet of Things These growing trends require new advanced packages which had not been used to such an extent in harsh automotive environment in the past, e.g. combination of dedicated vision processors, multicore CPUs and vision software. For motor control new MCU and FPGA Solutions, for IOT, new combo MEMS, 5G for wireless external connectivity and extended bus systems for internal subsystem links. Most of these developments were possible by integrating more and more functionality into one package and maintaining the stringent automotive safety and reliability requirements. New Backend test and handling systems had to be developed to address the new package requirements to ensure robust functionality. This breakthrough technology provides: • the lowest CoT for High Volume Manufacturing • Tri-temp for WLP, Fan-out and other small and mid-size packages including vision inspection • Stimuli for Combo MEMS • Fine pitch Kelvin contacting

Biography
Alexander J. Waldauf - Vice President of Platform Engineering Alex Waldauf was one of the founders of Cohu's Rasco subsidiary in 1998 and has been Vice President of Platform Engineering since July 2017. Mr. Waldauf was Vice President and General Manager of Rasco since January 2011, previously responsible for the Test-In-Strip product line, Managing Director of Rasco and global Vice President of Sales and Service. Prior to founding Rasco, Mr. Waldauf spent 6 years at Multitest and held key positions in engineering. Mr. Waldauf has a Mechanical Engineering degree from the Austrian School of Technology in Salzburg (HTL).

APC
D To top
Dialog Semiconductor GmbH Dialog Semiconductor GmbH Nandhivaram Muthuraman, Balaji
Thermomechanical reliability of Large Wafer Level Chip Scale Packages (LWLCSP) in Board Level reliability thermal cycling qualification test
Nandhivaram Muthuraman, Balaji

Nandhivaram Muthuraman, Balaji
Package & Material Simulaiton Engineer
Dialog Semiconductor GmbH

Nandhivaram Muthuraman, Balaji

Abstract
In this paper , for very first time in industry , we discuss about a Large Wafer Level Chip Scale package (LWLCSP) of size 12 mm* 4.6 mm, with an estimated solder interconnect/pin counts(IOs) of 442 IOs along with different die thickness (6mils and 10 mils) and underfill conditions. Four different Test vehicles were constructed with thinner (6 mils) / thicker (10 mils) silicon chip with and without underfill material. To assess the device reliability, extensive Board Level Reliability Temperature Cycling Test (BLR-TCT) qualification was conducted with a temperature cycling range between -40°C till +85°C until significant solder joint fatigue failures are observed. As an interesting fact, the failure mode with underfill devices and non-underfill devices were quite different. No-Underfill Large Wafer Level Chip Scale Package (No UF LWLCSP) devices experienced solder joint bulk cracks, whereas the UnderFill Large Wafer Level Chip Scale Package (UF LWLCSP) experience cracks on the intermetallic layer between the silicon chip and Re-distribution Layer (RDL). To evaluate BLR-TCT qualification tests, Finite Element Method (FEM) simulations were carried out. Parameters like RDL size, Aluminium Pad(AP) thickness and the routing method of RDL – AP layer interconnection is evaluated using numerical techniques. Critical parameters were extracted from the numerical model to correlate the shift in failure mode mechanism observed in BLR qualification measurement tests. Numerical simulation model results show a clear correlation with the failure observed in BLR Qualification tests. Large WLCSP devices with underfill experienced a higher peeling stress on RDL-AP interface. After design optimizations, relevant solutions have been found. This research work can answer the technical challenges faced in large WLCSP packages and the necessary optimization technique that can reduce the critical stress locations in the integrated circuits.

Biography
Balaji Nandhivaram Muthuraman is working as Packaging and Material Simulation engineer in Dialog Semiconductor GmbH, Germany. He obtained his Bachelor's degree in Aeronautical Engineering from Anna University, Chennai,India. Followed by, Master's degree in Computational Mechanics of Materials and Structures from University of Stuttgart, Germany. His current area of working interest are Board level reliability of electronic packages, Developing fatigue model for reliability assessment of Dialogs products.

APC
DISCO HI-TEC EUROPE DISCO HI-TEC EUROPE Klug, Gerald
Solutions for thin and tiny dies with high die strength and for thinning WLCSP and eWLB wafers
Klug, Gerald

Klug, Gerald
General Sales Manager
DISCO HI-TEC EUROPE

Klug, Gerald

Abstract
DISCO Corporation is a leading manufacturer for equipment and tools for wafer thinning/dicing. “Bringing science to comfortable living by Kiru (Dicing), Kezuru (Grinding) and Migaku (Polishing)” is DISCO’s mission. By combining these three core technologies, DISCO provides total solutions to meet the demanding requirements of the Semiconductor industry in terms of manufacturing thin dies with high die-strength and several new approaches for advanced packaging. A wide range of devices tend to have narrow street widths (cut margins), partially covered with low-k or ultra low-k layers in order to maximize the number of dies formed on a wafer. Furthermore, mobile and IoT consumer products incorporate an ever-increasing number of such circuit components. Quality requirements of consumer products are heading for same level as automotive products or even exceed those. In order to fulfil all these requirements, DISCO proposes several solutions focusing on avoidance of side wall cracks and interfacial layer damages. DISCO will update on latest status of Stealth Dicing, high quality laser grooving, multi beam ablation laser cutting, dicing wafers with the active side facing to the tape, applying plasma dicing and remote plasma as well as combinations of these technologies in one process flow. WLCSP and eWLB applications are facing issues in wafer thinning, as the wafers, due to consisting of resin mold and Silicon dies while having high bumps on the front side, tend to easily break when thickness becomes lower than the bump height. Nevertheless, such low thickness is required due to increasing bump thickness. DISCO offers a unique technology to grind wafers with 200 µm high bumps down to 50 µm wafer thickness. DISCO HI-TEC EUROPE GmbH, having its facilities close to Munich airport, offers certified Dicing and Grinding Production Services, so that customers can utilize most of the afore mentioned DISCO technologies in production, even without investing into DISCO equipment.

Biography
Gerald Klug Biography Gerald Klug studied business engineering at the University of Siegen and graduated in 1998 as Dipl.-Wirt.-Ing., completing his thesis at BMW in Munich. He started his career as a designer of coil processing lines for nearly 3 years at a German machine manufacturing company, Heinrich Georg GmbH. At the end of 2000, he joined DISCO as a Sales Engineer for the area of Scandinavia. Meanwhile he has been almost 18 years at DISCO, nowadays operating as General Sales Manager for the whole of Europe

APC
DuPont DuPont Im, Sejin
High Performance Thermal Conductive Substrates for Power Module Packaging
Im, Sejin

Im, Sejin
Global Segment Leader
DuPont

Im, Sejin

Abstract
Increased adoption of hybrid and electrical vehicles as well as renewable energy systems are driving the innovation in power module packaging. Thermal substrate, one of the major components of power modules, is not an exception, and technological advancements are necessary to meet increased reliability requirements. Herein, we show that a high-performance power electronic substrate can be designed with newly developed highly thermally conductive polyimide film to address potential issues industry strives to solve. The most widely used ceramic based substrates tend to degrade severely with prolonged thermal cycles, a typical requirement of EVs and HEVs, reducing the reliability and lifetime of the power electronic device. Also, common design of the power module requires many layers that adds thermal resistance at each bonding surface. DuPont’s new Temprion™ Organic Direct Bond Copper (ODBC) has been developed and designed to address aforementioned problems, increasing thermal durability and reliability as well as enabling system layer suppression. Temprion™ ODBC’s dielectric layer, Temprion™ DB film will absorb thermo-mechanical stress from the metals due to CTE mismatch, dramatically improving durability of the system. In addition, various kinds of metals including Cu and Al can be easily bonded to Temprion™ DB films through simple process. There are no thickness limitations on bonding metal sheets and metal attached at the bottom can be used as an integrated heat sink/baseplate. This presentation will provide an overview of the power module market, highlighting current challenges and alternative solutions to address them.

Biography
Sejin has over 10 years of experience in the automotive and chemical industry in various disciplines including business planning and strategy, product management and engineering. Currently he works at DuPont with teams and partners to help the industry solve one of its biggest challenges – thermal management – with DuPont’s latest technology. Sejin holds a BSME from University of Wisconsin at Madison and an MBA from Kellogg School of Management at Northwestern University.

APC
E To top
Eindhoven University of Technology Eindhoven University of Technology Bol, Ageeth A.
Atomic layer deposition for the synthesis and integration of 2D materials for nanoelectronics
Bol, Ageeth A.

Bol, Ageeth A.
Associate Professor
Eindhoven University of Technology

Bol, Ageeth A.

Abstract
Graphene and other layered 2D materials have been the focus of intense research in the last decade due to their unique physical and chemical properties. This presentation will highlight our recent progress on the synthesis and integration of 2D materials for nanoelectronics applications using atomic layer deposition (ALD). ALD is a chemical process that is based on self-limiting surface reactions and results in ultrathin films, with sub-nm control over the thickness and wafer-scale uniformity. Two of the critical issues in unlocking the potential of graphene are the ability to deposit ultra-thin high-K dielectrics on grapene and fabricate low resistance contacts to graphene. Technologically, it is desirable to use atomic layer deposition (ALD) for this purpose. The inert nature of graphene however has made ALD on graphene very challenging. This presentation will give an overview of ALD techniques that were developed in our lab to initiate oxide and metal ALD on graphene to form ultrathin dielectrics and low-resistance contacts, without deteriorating graphene’s electrical properties. In addition, ALD might prove as a key enabler for tackling the current challenge of large-area growth of 2-D materials with wafer level uniformity and digital thickness controllability. We have implemented plasma-enhanced ALD to synthesize large-area MoS2 thin films with tuneable morphologies i.e. in-plane and vertically standing nano-scale architectures on CMOS compatible SiO2/Si substrates. The large scale 2D in-plane morphology has potential applications in nanoelectronics, while the 3D nanofin structures could be ideal for catalysis applications such as water splitting.

Biography
Ageeth Bol is associate professor of Applied Physics at Eindhoven University of Technology, the Netherlands. She received her MSc and PhD in Chemistry from Utrecht University, the Netherlands. After obtaining her PhD degree in 2001 she worked for Philips Electronics and at the IBM TJ Watson Research Center in the USA. In 2011 she joined the faculty of Eindhoven University of Technology. In 2012 she received a prestigious VIDI grant from the NWO (Netherlands Organization for Scientific Research) and in 2015 she was awarded a Consolidator Grant by the ERC (European Research Council). Her current research interests include the fabrication, modification and integration of 1-D and 2-D nanomaterials for nanodevice applications and catalysis.

Materials
Eltek A/S Eltek A/S Schmidt, Odd Roar
GaN - the future for rectifiers.
Schmidt, Odd Roar

Schmidt, Odd Roar
Project director r&d
Eltek A/S

Schmidt, Odd Roar

Abstract
New devices based power converters and systems Keywords—Wide band Gap semiconductor used in rectifier with focus on GAN transisitor When dealing with power conversion in a data center, the efficiency and cost-effectiveness is key! Due to the size and capacity of a modern data center, even small efficiency improvements in the power conversion from the incoming AC to the server load have great impact in terms of cost saving. Over time, Eltek has been exploring wide band gap technology, using GaN transistors instead SiMoS Fets in order to achieve higher efficiency and reliability. Together with Infineon, Eltek have for more than 2 years participated in an EU research program which now has resulted in a new 3kW/48Vdc rectifier with a peak efficiency of 97,8%. The combination of Eltek’s proven High Efficiency (HE) technology and Infineon’s GaN transistors has enabled a truly cost effective rectifier in the Super High Efficiency range. With modern silicon devices it is feasible to raise efficiency in the 230Vac-48Vdc conversion step to 98%, but based on the experience from our extensive research we are convinced that this efficiency can better be achieved by utilizing the GaN technology; simpler, more reliable and more cost effective. In our Super High Efficiency rectifier, we have been using totem pole topology with a lot of different technical issue. The PFC has a peak efficiency of approx. 99% and the rectifier has peak efficiency of 97.8% Totem pole PFC This paper will describe how and why GaN is the key to achieve reliable 98%+ efficiency.

Biography
Odd Roar Schmidt(m): R&D Project Director with Eltek. MSc in power electronics from NTNU. He has an extensive experience, 37 years,from industrial R&D and industrialisation of power converters. Formerly, director for Telecom division in Power-One where he was responsible for System, Controller and Rectifier/Converter technology and products. He has also been technical director for Power-One and Eltek.

Power Session
EV Group EV Group Uhrmann, Thomas
Collective Die Bonding Technologies for Heterogeneous Integration in Advanced Packaging
Uhrmann, Thomas

Uhrmann, Thomas
Business Develoment Director
EV Group

Uhrmann, Thomas

Abstract
As die area is constantly reduced especially for small package sizes and heterogeneous integration with high interconnect density becomes crucial. For large packages sizes heterogeneous integration and die segmentation gets an increasing role of processing applications. Here, heterogeneous integration leads to an overall increased yield, mainly as smaller dies generally can be produced with higher yield. In the same time and most importantly, memory, processors, sensors and such from different sources can be combined using heterogeneous integration. Aforementioned yield improvements by splitting dies into several parts and improving the performance cost. Combining the segmented dies in an advanced package can be done by two different bonding technologies, namely sequential die bonding or a collective die bonding approach. For the collective bonding, individual dies are populated and tacked either on an interposer or a so-called handling carrier, depending on the bonding technology applied. In case of tacking die face-down on an interposer or other active silicon die, bonding is usually being done by thermal bonding. Here, heating and cooling of the substrates are only done once, considerably reducing process cost and thermal budget of the underlying substrate. The second case is tacking the dies face up on a carrier substrate. This reconstructed dies on a carrier can now be processes again on wafer scale, this means preprocessing steps such as direct bonding can be done before bonding the wafers using fusion or hybrid bonding. In this presentation we will show different integration approaches for collective die bonding for both thermal bonding as well as fusion / hybrid bonding. For both processes, results in terms of die placement and sequential alignment accuracy of the integrated process will be compared and discussed, together with current and potential applications of these processes for future devices.

Biography
Dr. Thomas Uhrmann is director of business development at EV Group (EVG) where he is responsible for overseeing all aspects of EVG’s worldwide business development. Specifically, he is focused on 3D integration, MEMS, LEDs and a number of emerging markets. Prior to this role, Uhrmann was business development manager for 3D and Advanced Packaging as well as Compound Semiconductors and Si-based Power Devices at EV Group. He holds an engineering degree in mechatronics from the University of Applied Sciences in Regensburg and a PhD in semiconductor physics from Vienna University of Technology.

APC
F To top
Fraunhofer-Gesellschaft Fraunhofer-Gesellschaft Pelka, Joachim
Pelka, Joachim

Pelka, Joachim
Deputy Director
Fraunhofer-Gesellschaft

Pelka, Joachim

Biography
Dr. Joachim Pelka is the Deputy Director and Strategy Advisor of the business office for the Fraunhofer Group for Microelectronics. He studied electrical engineering, with an emphasis on semiconductor technology, at Berlin's Technical University and was awarded a doctorate there for his work on semiconductor components. He has been with the Fraunhofer-Gesellschaft since 1983. After several years of Research in process simulation, he was heading the Business Office of the Fraunhofer Group for Microelectronics from 1996-2018. As managing director he was responsible for strategic planning and for the coordination of work in the microelectronic institutes of the Fraunhofer-Gesellschaft. In keeping with deepening European integration, Dr. Pelka today functions as the main contact person for other European research facilities such as CEA-Leti, CSEM, IMEC and VTT. He represents the Group, complementing the Chairman of the Group, in the Heterogeneous Technology Alliance HTA and in the Electronics Leaders Group of the European Commission. Dr. Pelka is a member of the AENEAS Scientific Council.

The Future of Smart Computing Session
Fraunhofer IISB Fraunhofer IISB Schellenberger, Martin
Predictive Probing: A novel approach to minimize efforts at final test
Schellenberger, Martin

Schellenberger, Martin
Group Manager Equipment and APC
Fraunhofer IISB

Schellenberger, Martin

Abstract
Quality control plays a crucial role in the manufacturing of premium products. Measures for quality control are implemented, on the one hand, right after crucial process steps to ensure single process quality. On the other hand, the application of sophisticated test procedures during final test guarantees high quality of the final product. For instance, in LED manufacturing, high effort is spent to probe every single LED chip: in dedicated probing equipment, ultra-thin needles are used to contact an LED and measure its brightness, color and electrical properties. With thousands of LED chips to be tested per wafer, this is a time-consuming and expensive step. Predictive probing aims at significantly reducing the probing time and effort in final test and follows two objectives: (1) Identify a limited set of chips that have to be tested. (2) Reconstruct the parameters also from those chips that were not probed; this includes the detection of defect chips. To achieve these objectives, up-stream metrology data is utilized. A set of machine learning algorithms (including a neural network) takes these data to identify critical chips and to predict probing results. This concept was developed and demonstrated in a 3-years R&D project together with an LED manufacturer. As a result it is possible now, to omit the measurement of 93% LED chips on a wafer, which leads to a drastic decrease in overall measurement time and cost, and still predict the brightness, color and electrical parameters of all LEDs – with an accuracy that fulfils the specification of the manufacturing partner. The principles of the approach and the knowhow gained during the development can be transferred and applied to other applications and industries, where predictive probing can significantly lower cost and efforts in quality control.

Biography
Martin Schellenberger received the diploma in electrical engineering in 1998 and a Ph.D. in electrical engineering in 2011, both from the University of Erlangen-Nuremberg, Germany. From 1998 to 2006, he was a Research Assistant with the Fraunhofer Institute of Integrated Systems and Device Technology (IISB). Since 2007, he is Group Manager at Fraunhofer IISB, responsible for equipment and advanced process control. His research interests include equipment development and optimization for semiconductor processes, manufacturing science solutions for quality control, predictive methods for process control, equipment automation and productivity enhancement.

Metrology
Fraunhofer IZM Fraunhofer IZM Tekin, Tolga
Photonics for Next Generation Computing
Tekin, Tolga

Tekin, Tolga
Group Manager
Fraunhofer IZM

Tekin, Tolga

Abstract
Main bottleneck to the realization of next generation computing systems for all big-, secure-data applications and related industries, including System-in-Package and System-on-Chip based solutions, is the lack of off-chip (off-core) interconnects with low latency, low power, high bandwidth, and high density. The solution to overcome these challenges is the use of photonics. Photonics as an underlying technology is addressing the following main technological challenges of the next generation computing systems such as i) Off-chip interconnects, ii) Massive switching matrix, iii) Disruptive system architectures, iv) Cooling concepts, v) New peripheral component interconnect express, vi) Memory fabric, vii) Novel computing functions in order to enable Quantum- & Neuromorphic Computing, AI. Next Generation Photonics Platform will enable the disruptive computing technology and photonics enabled architectures, leading to faster, cheaper, power efficient, secure, denser solutions for applications and industries. Further, generic co-integration with all building-blocks of computing technology will be possible, since photonic based standard interfaces between building blocks are introduced and implemented.

Biography
Tolga Tekin received the Ph.D. degree in electrical engineering and computer science from the Technical University of Berlin, Germany. He was a Research Scientist with the Optical Signal Processing Department, Fraunhofer HHI, where he was engaged in advanced research on optical signal processing, 3R-regeneration, all-optical switching, clock recovery, and integrated optics. He was a Postdoctoral Researcher on components for O-CDMA and terabit routers with the University of California. He worked at Teles AG on phased-array antennas and their components for skyDSL. At the Fraunhofer Institute for Reliability and Microintegration (IZM) and at Technical University of Berlin, he then led projects on optical interconnects and silicon photonics packaging. He is engaged in photonic integrated system-in-package, photonic interconnects, and 3-D heterogeneous integration research activities. He is group manager of ‘Photonics and Plasmonics Systems’ and coordinator of ‘PhoxLab - Independent Platform for Photonics in Data Centers (PIH)‘ at Fraunhofer IZM . He is coordinator of European flagship project ‘PhoxTroT’ and European H2020 project ‘L3MATRIX’ on optical interconnects for data centers.

The Future of Smart Computing Session
H To top
Henkel Electronic Materials Henkel Electronic Materials Wu, Kily
Innovative Adhesive Developments for Next Gen Sensing Modules
Wu, Kily

Wu, Kily
Product Development Manager
Henkel Electronic Materials

Wu, Kily

Abstract
As electronics industry enters a new era of IoT devices, more and more sensing modules are becoming essential to make devices “smart” and "intelligent". Representative ones are camera modules, proximity and ambient light sensors, biometric (3D ID) sensors and MEMS devices. As signal sensing and processing become more advanced and demanding, the adhesives used need to meet more stringent requirements of process flexibility, application accuracy, adhesion strength, drop test and reliability. Henkel evolves together with leading sensing module makers by further developing specialized adhesives for them. For example, in camera modules, low temperature cure and low shrinkage are critical for active alignment and enabling ultra-high image quality. Hybrid resin and curative designs enable cure below 80°C while achieving ultra-low cure shrinkage and excellent adhesion to various substrates. A versatile chemistry toolbox - incl. epoxy, acrylate, silicone and hybrid resins - is used to develop new adhesives for MEMS with a wide modulus range (1 MPa up), stable modulus during operation and high toughness. Through catalyst selection, different UV and/or thermal cure mechanisms are entailed to enable different application processes with higher output. For each chemistry, the adhesive rheology must be tailored to fit challenging aspect ratios using needle dispensing, jetting, printing or laser assisted transfer. For image sensor, lid, cap and stiffener attach and grounding, various levels of electrical and/or thermal conductivity are incorporated by specially developed resin and filler systems. Finally, adhesive FILM is getting preferred over liquids due to advantages in bond line thickness control, tight keep-out zone, low warpage and low stress by low temperature cure, latent catalyst selection and B-stage processing. This presentation will give a clear overview of the sensor assembly challenges AND innovative adhesive solutions to enable Next Gen Sensing Module developments.

Biography
Kily Wu is Product Development Manager with Henkel Electronic Materials and based in Shanghai. His team is developing specialized Semiconductor Die Attach and Sensor Assembly adhesives. Kily has a Master degree in Chemistry with “Macromolecular Chemistry and Physics” as major.

APC
I To top
IMEC IMEC Dekoster, Johan
Dekoster, Johan

Dekoster, Johan
Program Manager
imec

Dekoster, Johan

Biography
Johan Dekoster received the M.S. degree in Exact Sciences (Physics) in 1988 from the KU Leuven, Belgium. In 1993 he received the Ph.D. degree (Physics), also from the KU Leuven. From 1993 till 1999 he held postdoctoral fellowships from the Research Council and the Fund for Scientific Research at the Institute of Nuclear and Radiation Physics of the KU Leuven. In 1999 he joined the OTN business unit of Siemens. He was project leader for several hardware firmware development projects for data, voice, video and LAN. In 2007 he became program manager OTN at Nokia Siemens Networks. In April 2008 he joined imec as R&D manager of the Epitaxy group with responsibility on epitaxial deposition of group IV and III-V semiconductor materials. Since November 2012 he is program manager for equipment and materials suppliers collaborations at imec.

Materials
IMEC IMEC Mongillo, Massimo
Towards wafer-scale Qubits
Mongillo, Massimo

Mongillo, Massimo
Device Engineer
IMEC

Mongillo, Massimo

Abstract
In this talk I will present the recent progress made by IMEC in the fabrication and integration of basic quantum circuits targeting qubits into a 300mm FAB. Quantum Computing holds promise for solving complex computational problems which are intractable by classical calculators. The basic ingredient for the implementation of a quantum computer is the availability of a two-level system mimicking the classical bit “0” and “1”(the qubit), on which we can encode the basic information. The exceptional computation power of a Quantum Computer originates by the quantum-mechanical property of superposition, according to which the qubit state is defined as an arbitrary linear combination of the two constituent bit states. At the qubit level, two main solid-state implementations are currently explored at IMEC. They are based on individual spins in Silicon and Superconducting circuits. Spins in silicon have demonstrated the longest coherence time in any solid-state device as a result of the lack of hyperfine interaction coupling the spins of the nuclei and the electronic spins. Another approach makes use of Superconducting devices, which, to date, represent the most advanced solid-state implementation of a qubit. Although this technology has proven to be mature for the implementation of basic Quantum Algorithms, it presents unique challenges in term of integration of a large (millions) array of qubits, necessary for error-correction. Given the rather large foot-print of an elemental Superconducting qubit, this platform need to demonstrate its viability in terms of up-scalability. In the long term, both qubits platform need to be integrated into a larger system comprising the control electronics routing the necessary signals to the physical qubit layer. In IMEC we are pursuing these research lines leveraging the extended know-how in terms of large-scale integration and system architecture.

Biography
Massimo Mongillo holds a Master degree in Physics from University of Naples in 2005 and a PhD in Nanophysics from University Joseph Fourier in Grenoble in 2010. His research has focused on the physics of Silicon nanoscaled devices, Quantum Transport and Superconductivity. In 2015 he has joined IMEC to develop devices based on two-dimentional materials. Since 2017 he is in the Quantum Computing group for the integration of Superconducitng and spin Qubits.

The Future of Smart Computing Session
Intel Research and Development Ireland Ltd Intel Research and Development Ireland Ltd Capraro, Bernie
Capraro, Bernie

Capraro, Bernie
Research Manager, Silicon Technology
Intel Research and Development Ireland Ltd

Capraro, Bernie

Biography
Bernie received a Masters Degree in Engineering (MEng) from Newcastle upon Tyne Polytechnic (now University of Northumberland) and has been working at Intel for the past 21 years holding various Engineering and Management roles across the wafer fabrication facilities. Bernie is currently responsible for all silicon nanotechnology research involving Intel Ireland, helping to deliver potential solutions to Intel for materials, devices, equipment and processing techniques required for the future technology nodes in collaboration with Research Centres, Academia and Industry across Ireland and Europe. Bernie’s semiconductor career spans 31 years, with other Process and Equipment Engineering positions held at Telefunken GmbH (Ge), Nortel/Bell Northern Research (UK/Canada), Applied Materials (UK) and Newport Wafer Fab (UK). In addition, Bernie is instrumental is developing Intel Ireland's relationships with third level Education Institutions, working on Policy, Talent pipeline and Research initiatives.

Metrology
N To top
NXP NXP Kamphuis, Tonny
Two side molded WLCSP
Kamphuis, Tonny

Kamphuis, Tonny
Assembly Industrialization Manager
NXP

Kamphuis, Tonny

Abstract
Increasingly WLCSP are used as solution for packaging, especially when the area needed for I/O matches the area needed for the function. Industry trend is to go thinner devices and smaller pitches. The mechanical integrity of WLCSP’s is stressed not only in the application, but also during board assembly at the customer. The breakthrough technology presented provides protection for both the top and bottom of the product, thus protecting the 8 corners of the device during handling at manufacturing and customer. Different material sets and molding technologies for encapsulation of the WLCSP were investigated, each with their own merits. The challenges experienced to create the two side encapsulated concept and way forward to overcome them will be shared. First results on Board Level Reliability will be shared. The encapsulation concept to achieve full encapsulation is demonstrated at supplier site and the building blocks towards a true industrial solution is shared. Balancing the front and back side thickness of the compound enables reduction of the overall height while at the same time improve the BLR performance compared to more well-known 5 side protected WLCSP in the same package thickness.

Biography
Tonny Kamphuis received his master in Mechanical Engineering at Twente University in 1986. The same year he joined Philips Semiconductors in the field of IC assembly equipment. He worked in Kaohsiung Taiwan from 1991 to 1992, after which he joined the discrete assembly equipment development department in Nijmegen. He has developed die bonders, wire bonders, molding machines as well as all type of handling equipment for both reel to reel and strip to strip based industrializations. Since the year 2000 he is focusing on assembly process development and industrialization for IC again. In 2007 NXP was founded, at NXP, he has filed several patents related to wafer processing, package concepts and process improvements.

APC
O To top
Okmetic Oy Okmetic Oy Lempinen, Vesa-Pekka
Advanced substrates for MEMS and photonic applications
Lempinen, Vesa-Pekka

Lempinen, Vesa-Pekka
Senior Manager, Customer Support
Okmetic Oy

Lempinen, Vesa-Pekka

Abstract
Requirements for lower cost and higher volumes are driving towards miniaturization of MEMS and photonic devices. Requirements for reliability and performance improvements on the other hand drive for improvements in precision of BSOI materials, and use of hermetically sealed structures enabled by Cavity SOI (C-SOI) wafers or wafer level packaging. Following examples of advanced substrate-based solutions are shown and discussed: • Use of thick SOI or C-SOI for manufacturing released MEMS structures. Comparison of different SOI substrates from process integration and manufacturing complexity point of view. Benefits of SOI and C-SOI based approach for flatness and dimensional precision of the released structures. • Combination of C-SOI based MEMS and wafer level packaging by patterned capping wafers with poly Si TSVs. Properties of advanced C-SOI and TSV substrates. • C-SOI based approach for high performance inertial sensors, with benefits in process integration, reliability and performance optimization. • Thick SOI based optical waveguides using E-SOI substrates for maximum efficiency. Okmetic’s new turnkey solution of providing full C-SOI process flow, from silicon crystal growth to cavity patterning and SOI wafer manufacturing, from one source is introduced. Fully in-house C-SOI processing allows an industrial-scale solution to C-SOI manufacturing, and enables the sensor manufacturers to focus on their core competencies in the directly sensing-related parts of the manufacturing process. Integrating the reliability-critical fusion bonding part of the MEMS process as a part of starting wafer manufacturing enables also streamlining of the manufacturing process flow, simplified process integration, and improved long- term reliability of the MEMS devices. In-house crystal growth and substrate wafer manufacturing enable full customization of material properties, such as Si layer resistivity and orientation, of each layer of the C-SOI structure.

Biography
Mr. Lempinen received his M.Sc. in Materials Physics from Helsinki University of Technology in 1999. Mr. Lempinen has over 15 years of experience in Silicon based material engineering. He has worked for Okmetic since 2000 and held various positions related to R&D, process engineering and applications support. Currently he is working as Senior Manager, Customer Support being responsible for the company’s global technical customer support organization. Prior to his time at Okmetic, Lempinen was involved in photovoltaic research in Electron Physics laboratory of Helsinki University of Technology, Finland and Microelectronics Research Center of Iowa state University, U.S.A.

APC
ON Semiconductor gmbh ON Semiconductor gmbh Paglia, Massimo
Design of a 10kW Three Phase PFC with Silicon Carbide
Paglia, Massimo

Paglia, Massimo
Application Engineer
ON Semiconductor gmbh

Paglia, Massimo

Abstract
A typical On Board battery Charger application for electric vehicles consists of a power factor correction stage (PFC) and a DCDC converter stage, both require the highest efficiency possible in order to deliver as much power as possible to the battery pack. Focus of this work is the 3 phase 10 kW PFC based on Silicon Carbide Mosfet which regulates the output voltage to 700V starting from a nominal input voltage of 230Vrms at 50Hz. Three parameters measure the performances of the system: total harmonic distortion, power factor and efficiency. Ideally they should be zero, one and 100% respectively. The configuration selected is typically known as inverter, made by 3 half bridges with each central point connected to a dedicated boost inductor, and each high side drain and low side source connected to the bus capacitor. 1200V SiC MOS 80m devices were used together with the recently released ON Semiconductor dedicated SiC gate driver, NCV51705. A digital control has been adopted by means of a mid-range microcontroller. The implemented strategy is based on a field oriented control approach where the rotating DQ domain has been selected aligning the D axes with the input voltage space vector. The selected HW together with the digital implementation represents a bidirectional system, therefore power can flow either ways by modification of the D axis reference current sign. The control strategy works on an interrupt running at 20 kHz using one ADC, 12 bits 1Mbs and one sample and hold. PWM frequency set to 70kHz. Experimental results demonstrate that the PFC was able to achieve as high as 98.7% at 6.6kW with a consistent efficiency above 98% at higher power output. THD was well below 5% from 3kW onwards and PF is above 0.99 from 4kW. All evaluated at nominal input voltage, 230Vrms.

Biography
Massimo Paglia received his B.Sc and M.Sc degree in Electrical Engineering from University of L'Aquila in 2004 and 2008 respectively. From 2009 to 2014 he was with the R&D team at Whirlpool Europe where he worked on the development of 3 phase motor control algorithms. In 2014 he joined ON Semiconductor as part of the Solution Engineering Center supporting the European Sales & Marketing group. His actual assignment is development of smart algorithms for three phase systems in power applications.

Power Session
Oxford Instruments Plasma Technology Oxford Instruments Plasma Technology Knoops, Harm
Advancing Atomic Layer Deposition and Atomic Layer Etching
Knoops, Harm

Knoops, Harm
Atomic Scale Segment Specialist
Oxford Instruments Plasma Technology

Knoops, Harm

Abstract
Atomic scale processes such as atomic layer deposition (ALD) and atomic layer etching (ALE) are increasing in popularity with more and more applications requiring or benefitting from atomic level control. ALD and ALE provide the control they do because they are based on self-limiting surface processes. This contribution will discuss the basics for both techniques and discuss how they can be further advanced. For ALD two trends will be discussed: i) controlling the ion energy in plasma ALD to tune material properties. Generally processes are optimized to have minimal ion energies to avoid potential damage. Interestingly, for these low damage plasma sources, the ion energy can be increased by substrate biasing providing additional knobs for tuning film properties. Key examples are stress-control of oxides such as achieving near-zero stress in TiO2 and reduction of the resistivity of conductive nitrides (e.g. for TiN, HfNx, and NbN). ii) Usage of novel plasma gases. For instance H2S plasma gas mixtures have been shown to allow growth of 2D-MoS2 at low temperatures and SF6 plasma was found to allow ALD of AlF3, which could be of interest as an optical coating or for batteries. For ALE the basics will be discussed and how these can be used for applications. More and more processes are being developed (e.g. ALE of GaN, AlGaN, Si, SiO2 & 2D materials). Interestingly besides the exact control of etch depth, other aspects of ALE might turn out to be more important for certain applications. For instance ALE of AlGaN was found to reduce the surface roughness, while generally plasma etching would increase the surface roughness somewhat. Other advances for both ALD and ALE are expected to be in the form of combinations with other techniques. Therefore clustering of ALD and ALE tools with 2D materials growth can allow precise control of interfaces and allow avenues into selective growth, surface cleaning and etching.

Biography
Dr.ir. Harm Knoops is an Atomic Scale Segment Specialist for Oxford Instruments Plasma Technology (OIPT) and holds a part-time assistant professorship position at the Eindhoven University of Technology. His work covers the fields of (plasma-based) synthesis of thin films, advanced diagnostics and understanding and developing plasma ALD and similar techniques. His main goals are to improve and advance ALD processes and applications for Oxford Instruments and its customers. He has authored and co-authored more than 40 technical papers in peer-reviewed journals.

Materials
P To top
PLASUS GmbH PLASUS GmbH Schütte, Thomas
Establishing smart plasma process control in production lines
Schütte, Thomas

Schütte, Thomas
President / CEO
PLASUS GmbH

Schütte, Thomas

Abstract
While metrology tools are getting more advanced and providing plenty of valuable data of process and product, there is still a lack in evaluating and combining these information for an integral process analysis and real-time control. In plasma processing optical emission spectroscopy is well known and often established as a process monitor by observing a single emission line e.g. to detect an endpoint or to survey the process stability. However, using the spectroscopic plasma monitoring technique all acquired spectroscopic data is evaluated simultaneously and in real-time and thus, provides a more comprehensive insight in the plasma chemistry, the composition of the plasma and its temporal evolution. Combing the spectroscopic plasma monitoring data with other real-time plasma metrology data will complete the picture of the plasma process. In order to scope with the more complex and advanced processes for next generation products it is essential to interconnect the metrology tools and its data and data analysis as it is addressed by IoT or Industry 4.0. In an example from solar cell production the benefits of the advanced spectroscopic plasma monitoring technique are illustrated and the advantages of combining metrology tools are outlined.

Biography
Dr.-Ing. Thomas Schütte studied Electrical Engineering at the Technical University Munich and the University of Southern California in Los Angeles and received his Diploma and MSEE, respectively. During his PhD at the University Stuttgart he specialized in plasma physics and plasma spectroscopy and in 1996 he established the company PLASUS where he acts as CEO and technical director of PLASUS GmbH now. He was and still is dedicated to develop and realize plasma monitor and process control systems for production lines for all types of plasma applications.

Metrology
R To top
Robert Bosch GmbH Robert Bosch GmbH Gómez, Udo
MEMS – One Product one process?
Gómez, Udo

Gómez, Udo
Senior Vice President
Robert Bosch GmbH

Gómez, Udo

Abstract
The demand and variety of applications for MEMS sensors has been growing steadily since the first series applications in the automotive sector in the early 1990s. Especially since the rise of fast-moving consumer markets, quick and efficient design has become increasingly important. However, in particular for MEMS, the strong interaction of product design and manufacturing processes is a major challenge. The growing number of applications for sensing of various physical and increasingly chemical parameters, often require specific solutions in MEMS production, chip level packaging and component testing as well. Fast and market-driven product development is only possible through innovative design concepts and the provision of modular process building blocks. A deep understanding of the interrelationships and the development of corresponding simulation tools are further key competencies. As market leader in MEMS sensor business and one of the first MEMS pioneers, BOSCH is continuously pushing forward the development of MEMS technology. The extension of our process platform originally defined for automotive applications to consumer products opens up new possibilities in the realization of complex 3D structures. This enables new product designs that are reflected in high-performance sensors for both automotive and consumer electronics applications. The presentation gives a short overview of the different requirements on MEMS technology compared to standard IC design and manufacturing. It provides insights into the future development in the field of surface micromechanics and highlights challenges and solutions of MEMS technology development and manufacturing as well as design methodology. In addition, we give examples of new design and product concepts and finally question: Does the old MEMS law "one product, one process" continue to apply?

Biography
Dr. Udo-Martin Gómez Senior Vice President Sensor Engineering, Robert Bosch GmbH Dr. Gómez is Senior Vice President of Robert Bosch GmbH. He is heading the Sensor Engineering at Bosch Automotive Electronics (AE/NE-SE) in Reutlingen, Germany, the world’s largest MEMS supplier serving the Automotive, Consumer Electronics and IoT industry. Having completed his doctorate in physics, Dr. Gómez started his career at Robert Bosch GmbH in 1999 at Corporate Sector Research and Advanced Engineering (MEMS technology). Before joining Bosch Automotive Electronics in April 2018, he worked in various management positions at Bosch and also held the position of Chief Expert for MEMS sensor technology. From 2013 to March 2018, he was Chief Technical Officer of Bosch Sensortec GmbH - a fully-owned subsidiary of Robert Bosch GmbH, responsible for research and development of micro-electro-mechanical sensors (MEMS) for consumer electronics, smartphones, security systems, industrial technology and logistics. Since 2014, Dr. Gómez is Deputy Chairman of the Board of VDE/VDI-Society Microelectronics, Microsystems and Precision Engineering (GMM). Since 2015, he is also member of the GSA (Global Semiconductor Alliance) EMEA Leadership Council.

Fab Management Forum (FMF)
S To top
SEMI SEMI Amano, James
SEMI Standards: Update on Fan-Out Panel Level Packaging Standardization
Amano, James

Amano, James
Sr Director, Int'l Standards
SEMI

Amano, James

Abstract
Fan-Out Panel Level Packaging (FO-PLP) technology is an enhanced packaging technology, embedding die in a low-cost substrate which is patterned to allow higher density of IOs than would otherwise be supported by the chip size. A number of different formats – including circular and rectangular – have been proposed for the panels into which the die are embedded, with a large number of different rectangular sizes. This wide range is delaying broad acceptance of FO-PLP technologies, as the tools must be customized for each different format. Panel substrates today range from 300 mm to 920 mm. Cost advantages depend on package and substrate size, and lack of standardization is a barrier to high volume manufacturing. Despite its advantages, fan-out packaging has challenges to overcome. To address these issues, the SEMI Standards Fan-Out Panel Level Packaging Task Force is currently developing standards focusing on panels, targeting dimensions, ID marking and orientation, edge exclusion, and other parameters such as total thickness variation (TTV), bow, and warp. Created in 1973, the SEMI International Standards Program brings together industry experts to exchange ideas and work towards developing globally accepted technical standards. SEMI provides the forum for the essential collaborations that must be achieved to move new and existing markets forward efficiently and profitably.

Biography
James Amano has led the SEMI International Standards Program since 2008. Prior to joining SEMI, he worked as the Silicon Valley sales engineer for Matsusada Precision, and as a trade specialist for the Japan External Trade Organization (JETRO). He holds degrees in Economics and Environmental Conservation from the University of Colorado at Boulder.

APC
Soitec Soitec Guiot, Eric
Innovative Compound Semiconductor Based Engineered Substrates for Photonics, Power, Solar and RF Applications
Guiot, Eric

Guiot, Eric
Product Development Manager
Soitec

Guiot, Eric

Abstract
The Smart Cut ™ technology applied to the fabrication of SOI, is used in volume manufacturing by SOITEC, serving digital, RF, power and photonics markets. Application of this technology using ion implantation to transfer thin films of compounds semiconductors has also been developed. The Smart Cut ™ process has technical and economical advantages. Transfer of thin layers onto many various materials with both a good thickness homogeneity and a high crystalline quality has been demonstrated. From an economic point of view, the possibility of reusing the remainder of the implanted substrate helps to reduce costs, especially for the III-V materials. We will focus on the application of the Smart Cut ™ technology for two different materials, InP and GaN. InP is widely used for the optoelectronic market. The Smart Cut ™ technology, has been tuned to this material. In addition to the cost advantage of the recycling, different receiver substrates such as GaAs, Sapphire or Si have been evaluated to enable new functions: receiver lift off, lower fragility, better integration. Using the InP-on-GaAs engineered substrate combined with direct wafer bonding, Soitec together with Fraunhofer ISE and CEA Leti have demonstrated wafer bonded 4-junction solar cells with highest conversion efficiency of 46.1 %. We will discuss also how the Smart Cut™ technology can enable the use of InP for RF 5G products. Regarding GaN, Smart Cut ™ technology enables the layer transfer of up to 1 µm thick GaN films either from bulk GaN or GaN on sapphire. We have demonstrated up to 3 cycles of reuse of the GaN donor substrate. Different receiver substrates such as Sapphire, Molybdenum and polycrystalline Aluminum Nitride have been evaluated. Through this innovative engineered GaN substrate, we have demonstrated a 20µm GaN epi growth. This breakthrough could enable new vertical GaN devices for high power application such as electric vehicle powertrain and RF power products serving the 5G market.

Biography
Dr. Eric Guiot, Materials Science Doctor (Ph.D. from Paris University, Pierre et Marie Curie), now is product development manager for compound semiconductors in Soitec. He is graduated from the Ecole Centrale engineering school in France. He made his PhD on the development of epitaxy of iron oxide targeting giant magnetoresistance materials. He then joined Corning Fontainebleau Research Center in France for the development of integrated optics devices for telecommunication. In 2002 he joined Soitec in France. He has been working on the development of advanced engineered substrates targeting various applications covering digital application at advanced nodes and optoelectronics. He is now leading the product development group focused on compound semiconductor engineered substrates targeting power, solar, photonics and RF application.

Materials
SPIL SPIL Wang, Yu-po
Advanced Packaging Solution for High Performance Computing and AI
Wang, Yu-po

Wang, Yu-po
Sr. Director
SPIL

Wang, Yu-po

Abstract
For years the IC industry has been driven by the demand of Smartphone and tablet. IoT was most expected as the next growth engine but all of sudden, high performance computing (HPC) and AI have emerged as the major driving forces thanks to the booming of crypto-currency mining and both cloud computing and edge computing. There are assembly challenges for HPC and AI, first of all, to achieve high computing performance, the logic IC is bigger and generates high thermal dissipation. And the bigger the die size, the lower the manufacturing yield rate. Secondly, the interconnection between logic IC and the memory needs to be very quick so it won’t slow down overall system performance. Finally, a variety of SiP are required to realize AIoT (AI of Things) To properly address those assembly challenges, a variety of advanced packaging solution are in development. For high power consumption, advanced silicon node is applied for large FCBGA to save the power, and advanced thermal interface material (TIM) with higher thermal conductivity is in development for more thermal dissipation. Furthermore, one big IC can be redesigned as several identical smaller ones with higher manufacturing yield rate, and by utilizing 2.5DIC technology, an interposer with fine lines is introduced for homogeneous integration. As for heterogeneous integration between logic IC and the memory, they are packaged together with 2.5DIC technology or Fan-Out MCM based on fine line requirement for faster interconnection. As for SiP, not only for small form factor, but also better EMI and antenna in SiP are in development for better and faster wireless communication. In this paper, technical risks of each advanced packaging solutions mentioned are reviewed, and possible actions of each risk are explored. And with the ready of these advanced packaging solutions, HPC and AI are off and running.

Biography
Dr. Yu-Po Wang Director CRD Center SPIL Education: Ph.D., Mechanical Engineering, State University of New York at Binghamton, New York, U.S.A. Experience: 1997-1998 Gintic Institute of Manufacturing Technology, Singapore 1998-Present SPIL, Taiwan

APC
SPTS Technologies Ltd SPTS Technologies Ltd Hopkins, Janet
Optimising Surface Chemistry After Plasma Dicing (SPTS Technologies & Versum Materials US, LLC)
Hopkins, Janet

Hopkins, Janet
Etch Applications Manager
SPTS Technologies Ltd

Hopkins, Janet

Abstract
Authors: J. Hopkins, O. Ansell, R. Barnett (SPTS Technologies) & M. Phenis, D. Pfettscher, R. Peters, M. Sistern (Versum Materials US, LLC) Plasma dicing has shown many benefits over other dicing techniques such as increased die strength, smaller/thinner die and reduced cost of ownership. This dicing process uses the established Bosch Process, with alternating etch and deposition steps to etch through the silicon wafer. The nature of the process means that there will be F residues remaining at completion due to the CFx polymer layer deposited on the wafer surfaces[1]. This can be removed by an O2 plasma however when solder bumps are present and subjected to the same dicing/Bosch process, the bumps can react with F radicals to form SnF2 which cannot be removed by an O2 plasma alone. An additional plasma process can be performed to reduce the F levels further, however, this still leaves F present. Studies are underway to determine whether this is an issue for subsequent steps or indeed whether the presence of F may help solderability[2]. However, in this work, the effectiveness of post-dicing wet cleans to remove the SnF2, and avoid any potential issues, is investigated. Tests were carried out comparing plasma DAG (dicing after grind) processes with different post residue treatments. A screening test was carried out using several different wet etch formulations, and two suitable formulations were identified. Further tests were carried out to optimise the conditions and check the tape compatibility. The F levels, measured by EDX, were reduced to <1% at a level comparable to the control sample (with no plasma dicing). The work has shown that a wet chemistry post plasma dicing treatment is capable of removing F residues and is compatible with the plasma dicing process flow. References 1. “Method of Anisotropically Etching Silicon” F. Lärmer, A. Schilp, , German Patent DE4241045 2. Hosoda et al, Proceedings of ECO design 2003, Tokyo, Japan, December 8-11, 2003, p 710-713

Biography
Janet Hopkins is the Etch Applications Manager at SPTS Technologies, currently focusing on plasma dicing. Janet joined the company in 1995, as Process Engineer in the Si etch group. During her career, she has worked in developing different plasma sources and processes, including early commercialisation of the Bosch Process for deep silicon etching of MEMS. She is the author of many papers and patents. She holds a BSc in Physics and Chemistry of Materials from The University of Durham and a PhD in Plasma Surface Modification.

APC
ST Microelectronics ST Microelectronics Parker, David
Impact of Plasma Dicing Singulation Techniques on Die Breakage Strength and Robustness
Parker, David

Parker, David
Project Manager
ST Microelectronics

Parker, David

Abstract
For all end applications where a semiconductor device is used, there is a constant demand for improved performance under all environmental conditions. One such application, which we all use regularly, is the smartcard chip. This secure microcontroller can be found predominantly in our bank or travel cards and passports, where it may receive much physical punishment in normal usage. The demands for severe robustness criteria for these card-based applications are continually increasing to ensure that the packaged chips are able to withstand more rigorous treatment without breaking. Key to achieving these exacting standards is the singulation of the chips in a way that does not generate any inherent mechanical weakness. The standard blade sawing process has so far met existing requirements but the technology roadmap for such devices has presented new challenges with the deployment of fragile ultra-low k BEOL dielectrics. This has prompted the introduction of laser grooving before dicing to minimise damage to these materials caused by the sawing blade but this, in combination with mechanical dicing can itself cause weakening of the die and a higher risk of failure. This paper will examine the relationship between die strength and some new approaches to die singulation with a strong focus on plasma dicing, in which die separation is achieved by etching the silicon in the scribe lane. As there is no mechanical element we should expect significant improvements in die strength so we will explore the inherent performance with this method as the etching output parameters and masking steps are varied. Additionally, this technique requires that the silicon is exposed in the scribe street, which must be free of metals and dielectrics before etching. Again laser grooving can be used to meet these conditions and we will describe how sequential laser grooving and plasma etch processes affect the die strength and reliability performance versus the more severe test criteria.

Biography
Mr Parker graduated in Chemistry from The University of Manchester, UK in 1981. Since the start of his career in semiconductors with Inmos Ltd the following year he has spent over 30 years with ST Microelectronics both in Agrate, Italy and Rousset, France. Beginning as a process engineer, mainly in deposition and patterning, he has extensive experience of front-end operations, including device engineering, process integration and technology transfer. In recent years he has taken on a project management role to lead ST's interests in plasma dicing within the Back-end Manufacturing and Technology R&D team that is based in Grenoble.

APC
T To top
Technische Hochschule Ingolstadt Technische Hochschule Ingolstadt Bhogaraju, Sri Krishna
New automatic transient thermal analysis equipment to inspect the quality of sintered interconnects
Bhogaraju, Sri Krishna

Bhogaraju, Sri Krishna
Scientific Research Assistant
Technische Hochschule Ingolstadt

Bhogaraju, Sri Krishna

Abstract
The ability to test the quality and reliability of interconnects of semiconductor packages conclusively through non-destructive tests gains importance with increased requirements. Sintered interconnects depend critically on the surface quality of the contact pads and metallic sinter particles. Unstable chemistry of the paste can also cause failures. While X-Ray or acoustic microscopy hardly detect these, thermal methods are sensitive to identify these failures. By TTA measurements the transient thermal impedance Zth is obtained and the thermal resistance Rth is calculated as per JEDEC51-14. But the measurement and data evaluation is time consuming and often requires experts. The relative thermal resistance measurement method is applied in the paper using the automatic tester to evaluate the thermal path and the thermal resistance, wherein the sensitivity and thermal load are not measured but are obtained by thermal path normalization to good samples whose values are known. LEDs are sintered on substrates, measured initially (0-hour quality) and subsequently after hours/cycles of accelerated stress testing (reliability) using the automated TTA tester. The measurement electronics are mounted on a movable 3-axis system to enable use of short cables with low parasitic inductance. To resolve the thermal resistance between the LED die and substrate the forward voltage of the LEDs after current switching needs to be measured well below 10μs. The developed current source allows very fast switching within 100ns and stabilize the detection current within 5μs. In addition an In-Situ tester measures thermal impedance providing additional data to support analysis. In this paper automated TTA test equipment and In-Situ tester are presented which enable to measure the transient thermal impedance and by that identify the thermal integrity of the interconnect after assembly and within accelerated reliability tests. By known good reference samples failures are automatically identified.

Biography
Sri Krishna Bhogaraju Scientifc Research Assistant - IIMo - Technische Hochschule Ingolstadt Education: 2010-2012 - Master of Engineering - International Automotive Engineering, University of Applied Sciences, Ingolstadt, Germany. 2006-2010 - Bachelor of Engineering - Mechanical Engineering, University Visvesvaraya College of Engineering, Bangalore University, Bangalore, India. Work Experience: Jan 2018* - Scientific Research Assistant - IIMo - Technische Hochschule Ingolstadt. Feb 2016 - Dec 2017 - Process Design Specialist - Corporate Rules & Standards, Corporate Quality & Environment, Continental AG, Hannover, Germany. Apr 2014 - Jan 2016 - Project Co-Ordinator & On-Site specialist - ContiTech Power Transmission (Sanmen) Ltd., Sanmen, P.R.China. Nov 2013 - Mar 2014 - Project Co-Ordinator - Roulunds Rubber Korea Co. Ltd., Busan, South Korea. Oct 2012 - Oct 2013 - Project Co-Ordinator - ContiTech Power Transmission Ltd., Sonepat, India. Mar 2012 - Sept 2012 - Product Manager - Asia - ContiTech Fluid Shanghai Co. Ltd.

APC
TechSearch International, Inc. TechSearch International, Inc. Vardaman, Jan
Advanced Packaging Developments—Where Are We Going?
Vardaman, Jan

Vardaman, Jan
President and Founder
TechSearch International, Inc.

Vardaman, Jan

Abstract
The semiconductor industry packaging and assembly business continues many changes. The smart factory is the new industrial revolution, driving sensors, machine-to-machine communication, as well as data storage and analysis. The adoption of 5G and ADAS changes the package designs and materials. Growing demand for datacenters and artificial intelligence or machine learning is pushing us to the next semiconductor nodes at a faster rate. The adoption of the next advanced semiconductor nodes will present challenges that must be met with new package developments. In addition, the next 10 years is likely to see new drivers for advanced packaging. This presentation describes some of the applications and the challenges for advanced packaging.

Biography
Jan Vardaman is the President and Founder of TechSearch International,Inc., which has been providing licensing and consulting services in semiconductor packaging since 1987. She is co-author of Nikkan Kogyo’s How to Make IC Packages (in Japanese), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a member of IEEE CPMT, IMAPS, MEPTEC, and SEMI.

APC
Trinity College Dublin Trinity College Dublin Nicolosi, Valeria
Advanced imaging of novel low-dimensional nanostructures
Nicolosi, Valeria

Nicolosi, Valeria
Professor of Nanomaterials and Advanced Microscopy
Trinity College Dublin

Nicolosi, Valeria

Abstract
Low-dimensional nanostructured materials such as organic and inorganic nanotubes, nanowires and platelets are potentially useful in a number of areas of nanoscience and nanotechnology due to their remarkable mechanical, electrical and thermal properties. However, difficulties associated with their lack of processability have seriously hampered both. In the last few years dispersion and exfoliation methods have been developed and demonstrated to apply universally to 1D and 2D nanostructures of very diverse nature, offering a practical means of processing the nanostructures for a wide range of innovative technologies. To make real applications truly feasible, however, it is crucial to fully characterize the nanostructures on the atomic scale and correlate this information with their physical and chemical properties. Advances in aberration-corrected optics in electron microscopy have revolutionised the way to characterise nano-materials, opening new frontiers for materials science. With the recent advances in nanostructure processability, electron microscopes are now revealing the structure of the individual components of nanomaterials, atom by atom. Here we will present an overview of very different low-dimensional materials issues, showing what aberration-corrected electron microscopy can do for materials scientists.

Biography
Prof. Nicolosi received a BSc in Chemistry from the University of Catania (Italy) in 2001 and a Ph.D. in Physics in 2006 from Trinity College Dublin. In 2008 she moved to the University of Oxford as a lecturer and in 2012 she returned to Trinity College Dublin as Research Professor. Today she is the Chair of Nanomaterials and Advanced Microscopy in Trinity College Dublin, and a PI in the SFI Centres AMBER and I-Form. She is the first woman to have reached the position of Chair in the School of Chemistry since the foundation of Trinity College Dublin in 1592. She has published more than 200 high-impact-papers, including Science, Nature, Nature Nanotechnology, Nature Materials amongst the others, and delivered more than 100 invited and plenary presentations at major conferences/institutions/public events. Over the years she has won numerous awards: the RDS/Intel Prize for Nanoscience 2012, the World Economic Forum Young Scientist 2013, EU Woman in Technology Award 2013, SFI President of Ireland Young Researcher Award 2014, SFI Irish Early Stage Researcher 2016, TCD ERC Awardee 2017, Women Business Forum Women of the Decade in Science & Innovation 2018. Prof. Nicolosi is the only 5 times ERC awardee in Europe: she received a €1.5m Starting Grant in 2011, followed by 3 Proof-of-Concept top-up grants to bring results of frontier research closer to the market, and a €2.5m Consolidator Grant in 2016. This brings her total research funding awarded in the past 5 years to over €15 million. Her research has found direct commercial impact, being licenced to companies like Samsung Korea, Nokia, LEGO and Ferrari Formula 1. In several occasions she has accompanied the President of the European Research Council, Prof. Jean-Pierre Bourguignon, to high level meetings at the European Parliament and with the government of Ireland, where she further demonstrated her pioneering work and her commitment to the future of research. The European Parliament Commissioner for Research, Science and Innovadion, Carlos MOEDAS, chose her to accompany him at a press conference called to celebrate the ERC 10th anniversary at the headquarters of the European Commission in March 2017. On the 9th of November 2017 she gave a keynote speech at the Falling Walls Conference in Berlin. This remarkably prestigious conference celebrates this historic event focusing on the future walls to fall in science and society. German Chancellor Angela Merkel, the German Federal President and distinguished international government representatives have keynoted the past conferences. “The brightest minds on the planet” meet at the Falling Walls Conference, BBC London stated and according to the New York Times it is „the most exceptional science conference in the world“.

Metrology
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Westsächsische Hochschule Zwickau Westsächsische Hochschule Zwickau Taudt, Christopher
One-Shot, nm-precise metrology for in-line applications
Taudt, Christopher

Taudt, Christopher
researcher/PhD student
Westsächsische Hochschule Zwickau

Taudt, Christopher

Abstract
The manufacturing of power chip technologies, semiconductors and thin-film structures demand quality, precision and reliability regarding the manufacturing processes. Therefore, appropriate in-line ready, integrated and fast characterization methods are required. One of the key requirements for such a system is the ability to gather e.g. precise topography data without the need of mechanically moving parts in order to ensure a fast data acquisition and minimal uncertainties. Within this work an alternative approach based on a white-light interferometer is presented which is designed to comply with these requirements. The interferometer is equipped with a supercontinuum white-light source and defined dispersion over the given spectral range. Due to the known dispersion characteristics, it becomes possible to calculate the surface profile with nm-precision from the phase-varied spectral data. In a two-dimensional approach the surface profile is encoded in one dimension as spectral modulations (z-coordinate) while the second dimension holds information about the spatial distribution of the profile (y-coordinate). The talk explains the data analysis model, calculations of theoretical resolution as well as the experimental setup and its results. Experimental results are presented from samples such as a precision height standard, Si-wafers, MEMS pressure sensors and spin-coated polymer layers. It could be shown that the resolution in the z-coordinate during the experiments was in the order of 2 nm while the resolution in the y-coordinate was in the range of 5 µm. The results of the interferometric measurements where furthermore evaluated with other techniques such as a confocal scanning microscope. Additionally experiments under varying temperature conditions proved a high stability with only 0.15 nm/K drifts. The interferometric method has advantages in fast, in-line metrology applications as it has shown high accuracy and robustness during different experiments.

Biography
My name is Christopher Taudt. I`ve received a Bachelor’s degree in Mechanical Engineering from the Institute of Technology Sligo, Ireland as well as a diploma degree in Mechanical Engineering from the University of Applied Sciences Zwickau, Germany. Furthermore, I successfully completed a research period in the USA (University of Pittsburgh) and did freelance work in programming for the automotive industry. Currently I’m a PhD student at the University of Applied Sciences Zwickau and the Technical University Dresden, Germany. Additionally, I`m a team manager at the Fraunhofer Application Center for Optical Metrology and Surface Technologies in Zwickau, Germany. My main working area is optical metrology, especially low-coherence interferometry. In this research area I’m mainly interested in the characterization of materials such as semiconductors and polymers during the different processing steps. This can include topographic, optical and other properties of the aforementioned materials. One of the most important aspects in my research is the strong cooperation with industrials partners in national and international projects.

Metrology
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Xcerra Xcerra Brost, Bert
Interpretation and Application of Test Socket and Probe Head Specification
Brost, Bert

Brost, Bert
Product Manager
Xcerra

Brost, Bert

Abstract
Decisions should be supported with verifiable and repeatable performance data. This is true when selecting contactors, test sockets, and probe heads for test. This intent of this paper is to describe and define the data used to specify contactors, test sockets, and probe heads for test. This includes the source methodology and process for developing the lab data describing the performance of contactors, test sockets, and probe heads for test. With this the paper will lead the way to interpret and apply the statistically predicted field performance of the test probe as qualified in a test lab. Presented will be lab data describing the performance of several mainstream probe architectures for contacting Wafer Level Chip Scale Packages (WLCSP). The goal of this paper is to create a common understanding of how to read, interpret, and communicate data for selecting the right probe technology for WLCSP test applications. The paper goes beyond the probes and speaks to other factors that contribute to the overall performance of the contactors, test sockets, and probe heads for test. For example, the probe head housing design and materials used are important aspects that need to be understood for optimized performance. The success of the data-driven probe selection approach is reliant upon the quality of the supplier data. The paper will describe the reports provided including the WLCSP Metrology reports. Focus Content: • Interconnect technologies for improved performance and reliability • The role of material, and material development for higher reliability • Metrology and inspection methods

Biography
Bert Brost Biography Bert is a Senior Product Manager for Xcerra Corporation. With more than 35 years of experience in backend test, Bert has held senior management positions with Johnstech International and Control Data Corporation. Bert started his career in engineering with Micro Component Technology (MCT) designing test electronics and later worked as an engineer for Sick Optik Elektronic GmbH. Bert holds several undergraduate degrees and a MBA from the University of St. Thomas, Minnesota.

APC
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Yole Développement Yole Développement Rosina, Milan
GaN and SiC power device: market overview
Rosina, Milan

Rosina, Milan
Senior Analyst, Energy Conversion and Emerging Materials
Yole Développement

Rosina, Milan

Abstract
Wide-band gap (WBG) materials, in particular Silicon Carbide (SiC) and Gallium Nitride (GaN) devices have demonstrated the large potential for power electronic applications. According to Yole estimates, the market for SiC and GaN-on-silicon devices in power electronics will reach 10% of market share in five years. The first commercially available SiC diode has arrived to the market 18 years ago and since then progressively replaced silicon diodes in many applications. SiC MOSFETs has also become commercially available. The 2016-2018 period is crucial for SiC MOSFETs as well as for the whole SiC industry. Actually, SiC MOSFET manufacturers have improved the device reliability and performance. SiC MOSFET is gaining confidence of numerous customers and has penetrated into different applications. The availability of SiC transistor has enabled the realization of full-SiC power modules, providing the strongest benefits compared to silicon-based power modules. The SiC technology market adoption is accelerating. Today, the development efforts have been refocused to the manufacturing issues to drive the cost down: technology transfer to 6-inch wafers, improving manufacturing yield and ramp-up of high volume production. GaN on Silicon power devices are less mature compared to SiC power devices. But several GaN-on-Silicon power devices suppliers have also entered the mass production phase. The market is driven by low voltage high frequency applications such as Lidar, wireless power, where GaN has its unique selling point as well as consumer power supply market where the weight and size is extremely important. For high voltage industrial applications, the reliability issues are still hindering a larger penetration of GaN devices. In this presentation, we will give an overview of the market, technology and the industrial supply chain.

Biography
Dr. Milan Rosina is a Senior Analyst for Power Electronics and Batteries at Yole Développement. Before joining Yole, he worked as a Research Scientist and a Project Manager in the fields of photovoltaics, microelectronics, and LED. Dr. Rosina has more than 15 years of scientific and industrial experience with prominent research institutions, an equipment maker, and a utility company. His expertise includes new equipment and process development, due diligence, technology, and market surveys in the fields of renewable energies, EV/HEV, energy storage, batteries, power electronics, thermal management, and innovative materials and devices.

Power Session
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1979 1979 Goetze, Christian
Acceleration in packaging development through 5G and mmWave applications
Goetze, Christian

Goetze, Christian
Member of Technical Staff
1979

Goetze, Christian

Abstract
The next network generation will enable high bandwidth applications like Ultra HD videos for mobile devices and at the same time support wireless Virtual Reality (VR) gears. Smart city and smart home applications are requiring a high flexibility in integration of different devices into the network. IoT and wearables are less demanding in terms of data rate, but mean a tremendous increase of connected devices and at the same time a strong demand for super low power. Beside these applications, advanced health care, connected cars and autonomous driving are emerging. These mission (?) critical applications are requiring a high data rate together with the absolute reliability of the systems. GLOBALFOUNDRIES’ new 22FDX-mmw technology is targeted to serve ultra low power, digital data processing and analog IP integration and allows system architects to design IP into one single SoCs. To package these mixed signal SoCs, our industry is facing complex challenges by a high number of digital I/Os, sophisticated power and ground networks and highly sensitive RF signal routing. The packaging integration of millimeter Wave, in combination with high frequency antennas needs new levels of chip-package-co-design and thorough usage of advanced packaging materials. In this presentation, we will show the challenges associated with mmWave based mobile networks, packaging solutions that can be adopted and how the design flow can improve system integration and overall performance.

Biography
Christian Goetze is Member of Technical Staff in the global Packaging Technology Integration group at GLOBALFOUNDRIES, based in Dresden, Germany. He is leading several RF-packaging development projects for 5G, mmWave and IoT applications incorporating advanced silicon technology nodes such as 45RFSOI, 28nm and 22FDx. In this role Goetze is the main interface to RnD institutes and supports lead customers in the network industry in product enablement. Christian Goetze joined Globalfoundries in 2010 and managed multiple packaging development and qualification programs with close collaboration to global Assembly and Test houses. Prior to joining Globalfoundries, Goetze worked as process and integration engineer at NOKIA-SIEMENS-Networks, Qimonda and Infineon. In these positions he worked on the second level assembly process development and optimization for memory modules and communication boards. Christian Goetze received a Master of Science degree in Electrical Engineering from the Dresden University of Technology, Germany. In his Master’s work, a cooperation of TU Dresden and SIEMENS, he studied the interfaces in Pb-free second level interconnects and their influence to the board level reliability.

APC