Lepelletier, Guillaume
Increasing Fab Productivity through Variability reduction
Lepelletier, Guillaume

Lepelletier, Guillaume
Advanced Manufacturing Tools & Methods Senior Staff Engineer

Abstract
STMicroelectronics manufacturing model is based on high mix Fabs. In such a model, variability reduction is an important lever to increase manufacturing productivity, especially for the variability due to internal elements (equipment, process, product arrivals). Historically, ST approach is to guarantee customers service by integrating the equipment variability in Fab capacity models with relevant metrics. Starting 2012, a further step has been initiated through a worldwide program focusing on equipment variability reduction. This has led, in just one year, to a major improvement of overall productivity in all ST Fabs. This year, we are enlarging the scope to cover next sources of variability. Thanks to the very high level of automation of Crolles 300mm, the most advanced ST Fab which serves a wide range of products in nodes from 120nm down to 14nm, the program takes a new dimension with a deeper characterization of variability components. First encouraging results give us clear directions and opportunities to concurrently optimize assets utilization and customer service.

CV of presenting author
GUILLAUME LEPELLETIER is senior staff engineer at STMicroelectronics. He received Engineering degree in Operations and Production Management from INSA de Lyon, France and master of sciences in "Advanced Modelling Systems" from Brunel University, Uxbridge, UK in 1997. He has 15 years of professional experience in Industrial Engineering in the semiconductor industry. He is working on capacity planning, cycle time management, discrete event simulation, industrial reporting and equipment performance tracking. His email address is guillaume.lepelletier@st.com.

Fab productivity (TechARENA)
3 To top
3D-Micromac AG Zuehlke, Hans-Ulrich
TLS-Dicing - Enabling technology for separation of SiC wafers
Zuehlke, Hans-Ulrich

Zuehlke, Hans-Ulrich
Market Development Manager
3D-Micromac AG

Abstract
The new TLS-Dicing (thermal laser separation) tool microDICE from 3D-Micromac AG is an enabling dicing tool for new products and materials. The tool helps to overcome several disadvantages of known dicing technologies like chipping, pealing of backside metal or thermal induced defects. Even SiC-based products can be separated with low costs, no tool wear and with very high throughput. In the microDICE tool thermally induced mechanical stress is used to separate brittle materials [1]. TLS-Dicing is a one pass cleaving process and runs with up to 300 mm/s (also for SiC!). Brittle materials like wafers are separated by thermal induced mechanical stress. Hence front and backsides are free of chipping. Back side metal, as typical for many SiC and Si-power devices, is separated in the same step with no delamination and very smooth edges. Metalized patterns inside the dicing street can be removed by using the scribing laser without influence on the throughput. TLS-Dicing has no negative thermal impacts on the separated devices, proved by electrical measurements of leaking current [2]. The presentation covers an introduction to the technological principle of TLS-Dicing technology with special consideration of SiC-wafers. Typical application results will be presented. An overview on the modular and in terms of throughput and cost scalable microDICE tool architecture will be given. The presentation will be concluded with a consideration on the aspects of throughput and cost of ownership for a typical SiC-wafer project. [1] H.-U. Zühlke: "Thermal laser separation for wafer dicing"; Solid State Technology, 2009 [2] D. Lewke et al.: "High quality and high speed cutting of 4H-SiC JFET wafers including PCM structures by using Thermal Laser Separation"; MRS Spring Meeting, 2014

CV of presenting author
Hans-Ulrich Zuehlke studied instrument engineering at Friedrich Schiller University Jena. In 1998 he received his PhD from this university. He has active more than 15 years experience in the laser business. Last ten years in the field of laser applications for the semiconductor industry. Beginning of 2014 Hans-Ulrich Zuehlke joint 3D-Micromac AG Chemnitz as Market Development Manager for semiconductor equipment.

Advanced Packaging Conference (APC)
Exhibitor Presentations: Packaging (TechARENA)
3D PLUS Noiray , Jerome
Application of WDoDTM technology for the manufacturing of SiPs in the medical domain and in the defense and industrial domain
Noiray , Jerome

Noiray , Jerome
R&D Engineer
3D PLUS

Abstract
Based on Wire free Die on Die disruptive technology (WDoDTM), complex SiPs can be manufactured in a small factor package size. Stacking known good rebuilt wafers allows high yields while integrating high performance devices. Wafer processing is done with e-WLB technology and a specific redistribution layer (RDL) is designed to match with 3D PLUS bus metal edge interconnect technology. 300 mm rebuilt wafers are processed and thinned down to 200 µm before stacking and polymer bonding. Bonding alignment is within ±5 µm allowing small lateral pitches demonstrating WDoDTM versatility with denser IO products such as FPGA. Besides, this new process integration scheme allows the stacking of both conventional boards with SMDs not available at wafer level together with rebuilt wafers made of known good dies. WDoDTM technology has been successfully used with different kind of products in the defense and medical markets. A calculator node including a 484 I/O FPGA with 2 mDDR and an EEPROM in addition to more than 150 decoupling capacitors was manufactured and is exhibiting better electrical performance when compared to the 2 dimensions version. Moreover, a pacemaker has been successfully developed embedding 2 ASICS and several PICS capacitors allowing an 8 times shrink of the electronics compared to advance lead based pacemakers.. With this new technology, 3D PLUS is highlighting the way to highly integrated System in Package (SiP) and demonstrates its know-how in the three dimensional integration.

CV of presenting author
[1] Christian Val, "Stacking of Known Good Reconstructed Wafer without TSV; Applications to Memory-only and Heterogeneous SiP", Proc 13th Electronic Packaging Technology Conf, Singapore, Dec. 2011, pp. 469-473. [2] J. Noiray, C. Val, P. Couderc, T. Ferrara, "Stacking of Known Good rebuild wafers for high performance memory application to high speed DDR3", Minapad 2012, April 25-26, Grenoble, France [3] P. Couderc , J. Noiray, C. Val, "Stacking of Known Good rebuild wafers for high performance memory application to high speed and SiP", IMAPS 2013, October, Orlando, USA

Advanced Packaging Conference (APC)
A To top
A.M. Fitzgerald & Associates, LLC Fitzgerald, Alissa
Letting Process Drive Design: The RocketMEMS#CHR:trade# Model
Fitzgerald, Alissa

Fitzgerald, Alissa
Founder and Managing Member
A.M. Fitzgerald & Associates, LLC

Abstract
For decades now, new MEMS have been imagined by designers and then pushed to the foundries, who have the difficult job of stabilizing and qualifying the unique process flow dictated by the designer. This contract manufacturing model has led to the current industry situation of "one product, one process" - four words by JC Eloy that succinctly express the inefficiency, costs, and long time to market resulting from a lack of process standardization. OEMs who want to incorporate MEMS into their products do not have the patience nor funds for lengthy MEMS development projects. They typically don't need cutting edge sensor performance, nor do they care about novelty - they just want chips that will work in their application. There is a real risk to the MEMS industry that a huge business opportunity to serve OEMs will be lost if we cannot find a better way to quickly provide them with the MEMS they seek. To address this problem, AMFitzgerald has created a new model for MEMS development, called RocketMEMS. The development starts with the selection of foundry-qualified MEMS process modules or flows, which have been perfected by the foundry to produce specific MEMS functions or sensor types, respectively. Then, we create reference designs within the boundaries of the process capabilities. The reference design can be quickly custom-tailored (e.g. chip size, sensitivity, operating voltage, etc.) to meet specific customer needs, and working MEMS on the first run is possible because a fully-qualified process is being used. This model for development works well for all parties, because the major risk and cost of a new process development is eliminated. We believe that our model of designer-foundry collaboration should be widely adopted by the industry as the best way to serve OEM customers who do not have the option to purchase off-the-shelf MEMS.

CV of presenting author
Dr. Fitzgerald founded A.M. Fitzgerald & Associates in 2003. She has over 19 years of engineering experience in MEMS design, fabrication and product development. Having developed more than a dozen distinct MEMS devices, such as piezoresistive cantilevers, ultrasound transducers, and infrared imagers, she advises clients on the entire technology development cycle, from business and IP strategy, to initial design and prototyping, to foundry transfer. She is a recognized expert on reliability of brittle materials. Prior to founding AMFitzgerald, Dr. Fitzgerald worked at the Jet Propulsion Laboratory, Orbital Sciences Corporation, Sigpro, and Sensant Corporation, now part of Siemens. She received her bachelor's and master's degrees from MIT and her doctorate from Stanford University in Aeronautics and Astronautics. Dr. Fitzgerald has numerous journal publications, holds seven patents, and is a frequent lecturer at UC Berkeley, Stanford University and professional meetings. She currently serves on the Governing Council of the MEMS Industry Group. In 2013, she was inducted into the MEMS Industry Group's Hall of Fame.

International MEMS Industry Forum
ABB Semiconductors Kraxenberger, Manfred
Kraxenberger, Manfred

Kraxenberger, Manfred
VP
ABB Semiconductors

Biography
Manfred Kraxenberger is currently factory manager for ABB's BiMOS wafer fab and assembly line in Lenzburg, Switzerland. Manfred Kraxenberger studied physical engineering and started working as process engineer at Siemens Semiconductor Munich in 1986. Over the last 25 years, he has held several engineering and management positions in manufacturing as well as R&D at Siemens/Infineon/Qimonda and Globalfoundries. Prior to his current position he was in charge of ABB's Bipolar factory.

18th Fab Managers Forum
adixen Vacuum Products Davenet, Magali
AMC contamination management strategy for 450mm
Davenet, Magali

Davenet, Magali
R&D Collaboration and Funding Manager
adixen Vacuum Products

Abstract
Airborne Molecular Contamination (in short AMC) was demonstrated to be critical for yield, especially and quality in the semiconductor manufacturing. Sub ppb levels of contamination such as acids or HF can strongly degrade process performance and decrease product yield. Fab airbone molecular contamination should be managed, as stated by ITRS guidelines, especially for next generation devices with small dimensions and large wafer substrates (450 mm) In this article, we propose to propose and discuss AMC contamination management strategy for 450mm fab. We will review and discuss the various R&D projects launched on AMC contamination management. Especially, roadmap and development status for 450mm AMC advanced solutions as well as European R&D activities on AMC in the context of 450mm challenges will be reviewed and discussed. Finally, we will conclude with a review and discussion on a proposed strategy for AMC contamination management for coming challenges.

CV of presenting author
adixen Vacuum Products is leader in AMC solutions since 2008 and participates to numerous European collaborative R&D projects, including next generation 450mm project. Magali Davenet (Graduate in Optical Engineering school in 2000 and graduate in Executive International MBA in 2014) is responsible for collaboration and funding at adixen.She is involved in various microelectronic projects, including advanced 450mm projects.

450mm
Advantest Europe GmbH Ainslie, Stuart
Advantest F7000 leading e-beam lithography tool
Ainslie, Stuart

Ainslie, Stuart
Director Business Development
Advantest Europe GmbH

Abstract
Authors: Takayuki Nakamura, Kiichi Sakamoto, Masahiro Takizawa, Stuart Ainslie Advantest 's F7000 e-beam lithography tool is equipped to meet the wide demands of the semiconductor industry offering high resolution, enhanced through put and high availability. The tool can be used to write wafers or masks. Addressing the needs of advanced R&D the lithography tool is mask less and can write leading edge structure sizes in the 1x nm range achieving smooth edges and good accuracy. Introducing variable shaped beam and character projection capabilities the tool is versatile to write diverse and complex shapes while achieving leading through puts. F7000 has been engineered to achieves highest uptimes and offer high utilisation. The tool has unique self-cleaning capabilities and requires reduced preventative maintenance to be carried out.

CV of presenting author
Biography Stuart Ainslie: With over 25 years experience in the semiconductor industry Stuart Ainslie has been with Advantest for 19 years and is currently Director of the business development group located in Munich. In Advantest Stuart worked as an applications engineer before joining the marketing group in 2000. Stuart originally studied Electronics and Electrical Engineering in his native Fife Scotland and in 2008 was awarded an MBA from the Open University (UK). Stuart is married with two children and lives in Munich.

Lithography: What lithography options for tomorrow? (TechARENA)
AIRBUS Pons, Philippe
Advanced components packaging in Avionics, challenges and perspectives
Pons, Philippe

Pons, Philippe
Electronics Senior Expert
AIRBUS

Abstract
Airbus delivers high performance - reliable - cost effective systems & equipments, considering that foundations rely on electronic components (incl. technologies, packaging, interconnections with PCB). In a competitive context, avionics uses mainly COTS components grasping opportunities for new functions, higher performance & integration, but shall adapt to technologies & components trends ruled by commercial - high volume - low cost oriented applications, & characterized by rapid changes while avionics has high requirements & constraints (reliability, life time, etc). For A350 program, new components packages (BGA-1508 1mm; BGA-96 0,8mm; single row QFN) were introduced. For future designs, assessment of various highly integrated packages (BGA-1936 1mm; BGA-228 0,5mm; double row QFN-164 0,5mm; LGA-133 1,27mm; power-pad QFN; 0201; etc) is on-going on test vehicles (aging tests), by simulation approach & on functional demonstrators, considering Tin-Lead or in Lead-Free assembly process. Among COTS components trends for satisfying higher integration & performances or lower manufacturing costs, complex 2D, 2,5D, 3D packaging technologies (incl. Cu pillar, TSV, etc), new materials (incl. cheaper wire bonding for ex), are emerging; they could introduce new failure mechanisms with respect to avionics environmental constraints & impact avionics expectations in terms of reliability & life time. This will open probably a new investigation area & a challenge for demonstrating suitability of these advanced technologies in avionics. Presentation will stress on: Avionics context highlighting challenges & main drivers; Embedded electronics requirements & constraints for avionics; Example of current approach for assessing assembly & reliability of component packages, & associated results; Overview of avionics roadmap in terms of COTS components packages & associated PCB & assembly technologies, new challenges face to advanced emerging technologies in the field of components packaging.

CV of presenting author
Company: Airbus - Avionics and Simulation Products (Toulouse, France). Past activities: -Electronics Engineer in 1979. -First with THOMSON CSF, CAMECA Division: developed electronic boards for scan automation of electronic microscopes. -Then with THOMSON CSF, CIMSA & CIMSA SINTRA Division: led the electronic development of defence on-board computers for the processing of artillery fire trajectories. -Joined Aerospatiale / Airbus and the Avionics and Simulation Products Direction in 1991: was in charge of electronics design an activities of Flight Control Avionics for the A340 program; then for the A380, A400M programs and the beginning of the A350 program, led the physical design of the Avionics equipment boards and packaging developing the electronic manufacturing technologies activities. Present activities: Since 2009: Electronics senior expert and Technical advisor. -Define the electronic technical and technological orientations, and the electronic research axis satisfying Avionics objectives and requirements in term of performance, integration, reliability, environment, and cost. -Coordinate the electronic research activities and develops technical exchanges and cooperations. -Lead the Electronic Program for Embedded Systems in the frame of the French "Pôle de Compétitivité Aerospace Valley" and is an IMAPS France member.

Advanced Packaging Conference (APC)
AIS Automation Dresden GmbH Schulze, Mirko
Automation challenges for secondary equipment
Schulze, Mirko

Schulze, Mirko
Head of Business Unit
AIS Automation Dresden GmbH

Abstract
The secondary equipment market has a second face which is not so well known like the trade with complete tools. It's the possibility to turn an old tool into a new by doing a so called tool refurbishment. Many tools of the elder generation have several issues: no spare parts, decreasing throughput, increasing instability. Most of the tool owner see only the way to replace the tool after many years with a new one. But the process results on the old tool have been good over the years - if there would not be these terrible issues ... We will show you a way to go and the challenges on it. On this way the good (most) parts of the tool are kept for the second life time, obsolete parts will be replaced. Typically the core problem is a special main controller with special hardware and special development environment, and typically all these things are no longer available - experts to work with these things included. We provide a solution based on state of art control software with an open architecture for easy extension. The usage of standard automation components from the free market ensure independence from any special hardware design. These components can be easily exchanged with components from another supplier in future. Some of these refurbishment projects are challenging due to special requirements or missing documentation. We can show how to turn challenges into solutions.

CV of presenting author
Mirko Schulze was born in Dresden on Dec-15 in 1968. After school time he started his first professional education in communication technology. After that he studied automation technology at Technical University Dresden 1989-1994. He has been with AIS since October 1994, startet as software application engineer until end of the nineties. Around 1999 Mirko took over management tasks, worked as group leader and project manager. His role turned into department manager, experiences with small and big teams & projects worldwide. He is the head of business unit "Equipment control" at AIS since 2012.

Secondary Equipment (TechARENA)
AIS Automation Dresden GmbH Kinauer, Jochen
Innovative Semiconductor Solutions supplied out of Silicon Saxony
Kinauer, Jochen

Kinauer, Jochen
Director Business Development/ Sales Semiconductor
AIS Automation Dresden GmbH

Abstract
Saxony has developed itself to the largest semiconductor area in Europe, based on its versatile ecosystem of research, universities, suppliers and manufacturing. As a fact, the 1st 1 MB Chip in Eastern Europe was manufactured in Dresden in 1989 and the 1st 300mm Testline was installed in Dresden in 2000. One reason for this success are the agile activities within Silicon Saxoy Cluster. To continue this success story, Silicon Saxony has started the working group SET-UP 4 FIFTY (Saxon Equipment Team - Update for Future Innovation Fab Technology) in the year 2013, This cluster of institutes and companies out of Saxony, are working together on next generation semicondcutor technologies and solutions. This presentation will supply an overview of the companies and activites of the Silicon Saxony SET-UP 4 FIFTY Cluster and the competencies that are bundled in the Silicon Saxony Area. Examples of european funded projects for technology, automation and equipments, supplied by companies out of Saxony will demonstrate the innovationpool of our cluster members.

CV of presenting author
Jochen Kinauer: Jochen Kinauer is Director for Sales and Business Development at AIS Automation Dresden GmbH, a company within the Meyer Burger Group with its headquarter in Dresden, Germany and operations around the globe. AIS Automation specialises in equipment automation as well as MES installation and has more than 80 MES installations and automation projects worldwide. Jochen Kinauer previously worked as project manager for several hardware and software automation projects in the PV & semiconductor industry and is Leader of the Silicon Saxony 450mm and RFID Cluster. He holds a degree in Electrical Engineering, Controls & Automation from the Technical University of Munich.

450mm
Aixtron Ltd Jouvray, Alex
Scaling up Chemical Vapour Deposition Graphene to 300 mm Si substrates
Jouvray, Alex

Jouvray, Alex
Engineering Project Leader
Aixtron Ltd

Abstract
Graphene is a 2D carbon material with unique properties such as high mobility, wideband optical transparency and large thermal conductivity. To make use of these characteristics in high performance electronic applications, it is necessary to grow and integrate graphene using modern Si chip manufacturing processes. This paper discusses the growth of graphene by Chemical Vapour Deposition. The synthesis process begins with the deposition and crystallization of a nucleation layer, namely thin film Cu. We study the characteristics of this Cu film and the subsequent graphene growth kinetics and formation. Once Graphene is produced, it is transferred from the Cu film to the target substrate using a variety of integration techniques such as polymer-based or electrolytic transfer. Monolayer Graphene on Si or Cu/Si wafers are commercially available in sizes up to 100mm and are typically used to develop and characterise graphene device performance. There are currently only few organizations able to produce high quality monolayer graphene on wafer in sizes exceeding 100mm in diameter. To enable the commercialization of graphene as a large scale product, significant and successive cost reduction must be achieved. Here, we report the development of CVD tools in both scaling up the CVD production of graphene from 100mm to 300mm wafers but also report the increase in throughput from 1x100mm wafer in 2 hours to 2x300mm wafer in under 1 hour.

CV of presenting author
Dr Alex Jouvray received his PhD in CFD from Warwick University in 2004. He is currently the Engineering Project Leader for Aixtron's NanoInstruments products. He has significant experience of managing the development of new products and systems for a range of industial and scientific applications. He has managed several publicly funded projects and is the author / co-author of sevral papers and patents.

2D (TechARENA)
Aldebaran Robotics Gelin, Rodolphe
Imaging for companion humanoid robots
Gelin, Rodolphe

Gelin, Rodolphe
Research Director
Aldebaran Robotics

Abstract
Created in 2005, Aldebaran Robotics designs, develops and manufactures the humanoid robot NAO. Today more than 6000 NAOs have been sold all over the world for research and education purposes. If NAO appears to be a very efficient and appreciated development platform for these academic markets, the final objective of the company is to make humanoid robot a real companion for domestic applications. This objective of domestic applications brings severe constraints for the perception of the robot: it should detect objects and people in a rather unstructured environment under not controlled lightning conditions. Furthermore, the mass market envisaged for the Aldebaran's robot adds new constraints on the cost of the sensor equipment. Last, but not least, the humanoid shape of the robot limits the size and the number of the sensors and the computation power that can be embedded on the robot. Because Nao is dedicated to the human-robot interaction, the first vision development made at Aldebaran has concerned people detection. Using its 1.5 Mpixels cameras and its ATOM 1.6GHz CPU, Nao is able to detect and track a face and to recognize a person. But 2D vision has also been used to recognize objects and to perform localization and mapping by looking for artificial or natural visual beacons in the environment. In order to go further in exploiting the vision sensing, Aldebaran is experimenting new technologies. A prototype of stereo-head has been developed for Nao to get 3D information from the 2D cameras. It made possible to have accurate 3D positioning of the user's face and to localize object accurately enough for autonomous grasping of small objects. But processing stereo signal is quite heavy for the CPU that is the reason why Aldebaran is looking for smart sensors (able to preprocess the signal sent to the main CPU), for 3D sensors (best solution to have gesture recognition) and even thermal sensor that can detect human beings in a very robust and efficient way.

CV of presenting author
Rodolphe Gelin (1965) is engineer from the Ecole Nationale des Ponts et Chaussées (1988) and Masters of Science in Artificial Intelligence from the University of Paris VI (1988). He started his career at CEA (French Atomic Energy Commission), he has been working there for 10 years on mobile robots control for industrial applications and on rehabilitation robotics. Then he had been in charge of different teams working on robotics, virtual reality and cognitics. From 2006 to 2008, he was in charge of business development for Interactive System Program. He has participated to the European Coordinated Action CARE that supports the ETP EUROP on robotics in charge of the robotic roadmap for the European Community. In 2009, he joined Aldebaran Robotics as head of collaborative projects. He is the leader of the French project ROMEO that aims to develop a human size humanoid robot. Since 2012, he is Research Director at Aldebaran Robotics. He is member of the board of the directors of the euRobotics association.

Imaging Conference
Amkor Clark, David
Clark, David

Clark, David
Senior Director Product Management - Adv. Products BU
Amkor

Biography
David currently holds position of Senior Director Product Management within Advanced Porducts Business Unit at Amkor Technology Europe. Prior to that he has held roles in sales and business development at FlipChip International, research posts at University of Cambridge, application and process engineeing at Vistec Lithography and Agilent Technologies. David has an Honours degree from Univesity of Glasgow in Electronic, Electrical and Optoelectronic Engineering.

Advanced Packaging Conference (APC)
Analitycal Pixels Technology Colinet, Eric
MEMS as gas detectors and their use in gas chromatography
Colinet, Eric

Colinet, Eric
R&D Manager
Analitycal Pixels Technology

Abstract
There is a need today with great business opportunities for new generations of analytical equipment to determine in situ the composition of gas mixtures, avoiding the collection of samples and a remote analysis in a specialized lab. While the gold standard method is gas chromatography (GC), this demand can be satisfied by implementing the critical functions of a GC analyzer on silicon chips manufactured with CMOS and/or MEMS/NEMS technologies, resulting in portable, low-cost and easy to use equipment. We will present such a piece of equipment where injection, chromatography separation and gas detection are all implemented on silicon chips. The detection stage in particular will be described in full detail. At his heart relies a NEMS resonator operating as a gravimetric sensor. For some kinds of molecules, it gives the system a level of performance which is close to the gold standard "Flame Ionization Detector" (FID) without requiring hydrogen intake. It will be also compared with a "Thermal Conductivity Detector" (TCD) which is the standard MEMS based sensor used is competing portable system. This comparison will show the full potential of associating the NEMS and TCD in the same system. The presentation will include also the implementation of chromatography and injection of silicon chips as well integration issues on the system level in the context of different application fields ranging from in gas and petrochemical industries, indoor and outdoor air quality control.

CV of presenting author
Eric Colinet graduated from INSA-Lyon France in 2002 and received a PhD from SUPELEC PARIS in 2005 and a HDR from INP- GRENOBLE in 2010. From 2006 through 2010, he was a senior staff scientist at CEA-LETI, Grenoble France, where he coordinated various projects between NEMS/MEMS designers and IC designers. From 2010 through 2012, he was a visiting scientist at Caltech in Professor M. L. Roukes group where he worked on NEMS array for gas chromatograph, mass spectrometry applications. In 2011, he co-founded Apix-Technology, a start-up company from CEA-LETI/CALTECH specialized in Nano-Sensor based gas analysis systems, where he is now managing the research and development activities. His field of expertise covers micro & nano electromechanical systems (MEMS-NEMS), sensors & actuators, control theory & signal processing, solid-state electronics & IC, MEMS-CMOS Integration. He is the author of more than 70 scientific papers and holds over 20 patents.

International MEMS Industry Forum
ANSYS Toublanc, Jerome
Optimize Power Consumption and Delivery from RTL to GDS
Toublanc, Jerome

Toublanc, Jerome
Business Development Manager
ANSYS

Abstract
Energy efficiency could have different meaning depending of final applications or technologies. Most of the time, it could be translated into 3 main challenges for the project: minimize the power consumption in "standby" operational mode, boost the performance/power ratio in "functional" mode and certify the power delivery integrity. To optimize overall power efficiency, each of these items needs to be addressed during the design cycle. Such a methodology involves many power consumption analyses and budgeting, for multiple operational modes and early enough to eliminate wasted power and anticipate physical implementation requirements. Complementary, with advanced process and reduced power supplies, the accuracy of the Chip-Package power delivery network co-analysis is critical. ANSYS's innovative technologies connect PowerArtist, an RTL power analysis and optimization solution, and RedHawk, a SoC power integrity and sign-off solution, to enable a comprehensive power-efficient methodology - from early in the design process to silicon sign-off. The presentation provides an overview of early RTL power prediction and analysis-driven power reduction associated with accurate power Integrity and Reliability analysis from virtual prototype to tape-out stages.

CV of presenting author
Jerome is a business development manager in Europe and is driving ANSYS-Apache's Power and Noise solutions for full System Integrity. Prior experiences focused on different SoC implementation tools such as Place & Route or Power Analysis and also include analog/digital full-custom circuit design. He received his Engineer Degree in Microelectronics from ESIEE-Paris (France) in 2000.

Low Power Conference
Applied Materials Stolley, Tobias
Roll-to-Roll Plasma Enhanced Chemical Vapor Deposition for Next Generation Thin Film Electronic Device & Ultra High Barrier Applications
Stolley, Tobias

Stolley, Tobias
Dipl.-Ing.
Applied Materials

Abstract
Roll-to-Roll (R2R) production of thin film based display components combine the advantages of the use of inexpensive, lightweight & flexible substrates with high throughput production. Significant cost reduction opportunities can also be found in terms of processing tool capital cost, utilized substrate area and process gas flow when compared with batch processing systems. Nevertheless, material handling, device patterning and yield issues have limited widespread utilization of R2R manufacturing within the electronics industry. Recently, significant advances have been made in device patterning enabling the mass production of a variety of flexible electronic devices. These techniques are now so advanced that feature sizes of less than 40 nm can be produced on thin film layer stacks deposited on 50 µm thick polymeric substrates. Significant challenges also exist in terms of the deposition technologies used in R2R manufacture of these devices. Unlike traditional semiconductor or display based cluster tool platforms, R2R systems require to process substrates in a continuous fashion with rolls up to several kilometers in length. Depending upon the process itself, this imposes a limitation in terms of the mean time before cleaning (MTBC) and in some cases the particle management strategy. This has lead to the implementation of "deposit up" or vertical winding configurations in PECVD tool designs. Applied Materials has developed a variety of different web handling & coating technologies/platforms to enable high volume R2R manufacture of thin film silicon TFT active matrix backplanes and ultra-high barriers for organic electronics. The work presented in this paper therefore describes the principal challenges inherent in moving from lab/pilot scale manufacturing to high volume manufacturing of flexible display devices using CVD for the deposition of active semiconductor layers, gate insulators and high performance barrier/passivation layers.

CV of presenting author
Mr. Stolley is a technologist and project manager for PECVD Web Coating at Applied's Technology Center in Alzenau, Germany with 18 years of experience. He is engaged in the development and implementation program for flexible TFT backplanes for the next generation of thin film electronic devices. He was a researcher at `Fraunhofer Institute for Surface Engineering and Thin Films IST´ in Braunschweig from 1995 to 1998. He switched jobs into the industry. He joined Leybold Systems and in 2006 Applied Materials. He has worked with a wide variety of clients on start-ups of coating machines, research and development including architectural glass, display and web applications. He is skilled in project management, layer development and developing innovative solutions for coating machines.

Plastic Electronics - PE2014
Arizona State University Raupp, Gregory
HIgh Performance Flexible Electronics on Plastic for Display, Imaging and Sensing Technologies
Raupp, Gregory

Raupp, Gregory
Professor and Director ASU MacroTechnology Works Initiative
Arizona State University

Abstract
Significant advances in flexible microelectronics over the last decade have laid the foundation for a tremendous opportunity to create new revolutionary transformational engineered products and systems with unique and desirable form, fit and function. Nano-, micro-, and macro-scale devices can be integrated on plastic sheets to produce valuable multi-functional products that are characteristically thin, lightweight, flexible, conformable, and ultra-rugged. In biomedical and health technologies, one can envision ultra-biocompatible "in-body" implantable flexible systems, "on-body" smart bandages that conform to the contours of the patient's body, or "wearable" systems for real-time unobtrusive health and human performance monitoring and user feedback. High value sensing and detection products for safety, security and surety can likewise be envisioned, from transportation systems security to structural health monitoring (SHM) for our built environment. Before this compelling future is realized, however, major advances in manufacturable flex-compatible thin film transistor (TFT) devices must be achieved. Amorphous silicon, oxides or organic based transistors suffer from low carrier mobility and instability, and cannot achieve the high-speed, long lifetime, and robust digital and analog circuitry that would be required for the most demanding applications. Nanowire-based TFT devices offer a promising option for the required breakthrough performance due to their excellent electrical characteristics, durability, and mechanical flexibility. Mobilities well into the hundreds or even thousands are readily possible depending on material selection, enabling ultra-high performance. Recently "graphene-like" two-dimensional materials have generated significant interest and excitement. In this context the state-of-the-art will be reviewed, remaining technical challenges to be overcome will be highlighted, and possible effective development paths to be identified.

CV of presenting author
Professor Gregory B. Raupp is currently the Director of ASU's MacroTechnology Works Initiative out of the office of Knowledge Enterprise Development (OKED). His technology expertise and professional experience span many technical disciplines from engineering, materials science, manufacturing and product design to ultra-biocompatible implantable medical devices and chemistry of sustainable green processes. Professor Raupp received his B.S with Distinction and M.S. degrees from Purdue University and his Ph.D. from the University of Wisconsin, Madison. He began his academic career with Arizona State University in 1985 where he advanced to become Professor in 1994. From 1999 - 2002 he was Associate Dean for Research in the College of Engineering and Applied Sciences, and then was promoted to Associate Vice-President for Research in 2002 (concurrent with President Michael M. Crow's coming to ASU). In these roles he was responsible for crafting and managing a diverse portfolio of interdisciplinary research initiatives, which included such unique ventures as ASU's Biodesign Institute; the Arts, Media and Engineering Program; and the Center for Conflict and Religion. While he was Associate VP he led the winning ASU proposal effort for the National Flexible Display Initiative competition, and became the Founding Director of the Flexible Display Center at Arizona State in 2004 through a US$94M, 10-year Cooperative Agreement with the U.S. Army Research Laboratory. Under his leadership, a world-class industry-government-university partnership model was created, one that enabled organizations with dramatically different missions and scales to collaborate effectively to advance science and technology on a broad front and create a portfolio of enabling commercial manufacturing technologies. In January 2010 he accepted a dual post at City University of Hong Kong as their Vice President for Research and Technology (VPRT) and the Dean of Graduate Studies. With a redirected emphasis on large-scale collaboration, international partnerships and funding opportunities, CityU enjoyed several 20% year-on-year increases in total research funding (after three straight years of decline), including a 12x increase in funding from Mainland China, and a 10x increase from other international sources. Under his direction IP licensing deals were also ramped up significantly, with revenues at 8x the level realized over the past 4-5 years. In December 2012 he returned to ASU, but maintains an active adjunct Professor position at CityU

Plastic Electronics - PE2014
Arkema Domingues Dos Santos, Fabrice
Fluorinated Electroactive Polymers for Printed Electronic
Domingues Dos Santos, Fabrice

Domingues Dos Santos, Fabrice
CEO Piezotech
Arkema

Abstract
Since the discovery of piezoelectric and pyroelectric properties of Poly Vinylidene Fluoride (PVDF), fluoride-based polymers have attracted great research interest due to their potential applications in the fields of sensors, actuators, medical imaging, IR detectors, or underwater acoustic transducers. Printable PVDF derivatives such P(VDF-TrFE) copolymers are now developed at industrial scale. These materials can be processed with the emerging printed electronic technologies, such as inkjet printing, screen printing, roll-to-roll and some other solution deposition methods to obtain ferroelectric, piezoelectric and pyroelectric devices. Recently, thanks to the richness of fluorinated polymer chemistry, a new class of polymers has been developed: the relaxor ferroelectric polymers. These printable terpolymers are based on vinylidene fluoride (VDF), trifluoroethylene fluoride (TrFE) and a third monomer [chlorofluoroethylene (CFE) or chlorotrifluoroethylene (CTFE)] which modifies the crystalline structure from normal to relaxor ferroelectrics. These new materials exhibit large deformation and stress under applied electric field, high dielectric constant and electrocaloric properties. Recent developments have been focussed on the association of these electroactive fluorinated polymers with other printable materials for the design of printed devices such as sensors, memories, OTFT, actuators or speakers. The combination of this new class of material with the technologies of printed and flexible electronic promises new development opportunities in applications such as smart packaging, haptic, microfluidic, integrated smart systems or large area printed sensors.

CV of presenting author
Dr Fabrice Domingues Dos Santos was born in 1970. He received the diploma of engineer of Physics and Chemistry from the ESPCI (Physic & Chemistry school of Paris). He worked in the condensed matter laboratory at the College de France where he studied wetting dynamics. He got his Phd from Pierre & Marie Curie University , Paris, in polymer Science in 1999. He joined Arkema in 2000 where he worked as a scientist and a research director until 2009. Since 2010 he is president of Piezotech (Arkema group)

Plastic Electronics - PE2014
Arkema Cayrefourcq, Ian
DSA materials status for HVM
Cayrefourcq, Ian

Cayrefourcq, Ian
Director of Emerging Technologies
Arkema

Abstract
Since the emergence of microelectronics, lithography has been at the heart of Moore's Law by enabling devices scaling. Wavelength reduction and optics have been the key drivers for such technological feat. This path remains the preferred one as illustrated by the development of EUV lithography for more than a decade. However, facing complex technical challenges in developing efficient and stable light sources, EUV has been delayed. Therefore, the industry has been extending 193nm lithography by introducing immersion lithography and complex integration schemes, such as multi patterning, at the expense of cost. In this context, for a few years, Block Copolymer Directed Self Assembly has been considered has a high potential complementary technology to further push 193nm technology. BCP DSA is a disruptive technology based on polymers that self-organize with a period and structure that is defined by the characteristics of the material (i.e: polymer composition defines structure, Molecular weight defines pitch). In this paper, we will present the state of the art of this disruptive technology and we will demonstrate, through few examples (both at the material and integration level), the readiness of DSA technology for large scale implementation.

CV of presenting author
Dr Ian Cayrefourcq is currently Director of Emerging Technologies at Arkema. He is in charge of both Renewable Energies and Electronics R&D portfolios. Before joining Arkema, he has been in charge of various positions including head of R&D departments, Management of large international R&D projects as well as heading a group in charge of New Business Development and Diversification in several high tech companies such as Thales, Corning and Soitec. Dr Ian Cayrefourcq owns an engineering degree in Material Science, a master Degree in Solid Physics and a PhD in microelectronics. He is author or Co-author of more than 70 publications and 20 patents.

Lithography: What lithography options for tomorrow? (TechARENA)
ARM Hartley, Tim
The Benefits of GPU Compute on ARM Mali GPUs
Hartley, Tim

Hartley, Tim
Staff Engineer
ARM

Abstract
GPU Computing on the ARM Mali-T600 and Mali-T700 series of GPUs offers a host of benefits: accelerating data-parallel computation while simultaneously reducing system work load; reducing platform energy consumption while increasing system throughput; and enhancing your system's value by consolidating functionality while reducing programmers' effort. This presentation will illustrate and analyse real-life examples from our ecosystem partners that have enabled such benefits. Applications discussed include: ISP processing, HDR photography, panorama stitching, gesture user interfaces, HEVC and VP9 codecs, computer vision and more.

CV of presenting author
Based at ARM's Cambridge HQ Tim is a graphics and GPGPU engineer working within the Media Processing Group. He specialises in all things compute with a particular focus on Computer Vision within the mobile and embedded space. His role encompasses working with developers new to the Mali GPU, helping spread the word about optimal heterogeneous software design on this exciting platform. Previously Tim worked as a producer for the BBC, leading a research and development team in the use of multimedia in television training. Tim is married with two children and lives in the Chiltern hills just outside London.

Imaging Conference
ASE Yannou, Jean-Marc
Semiconductor packaging and test trends: a supply chain challenge'
Yannou, Jean-Marc

Yannou, Jean-Marc
Technical Director
ASE

Abstract
Latest trends in the semiconductor industry are prompting the need for lower power, higher performance, and greater integration, largely driven by the anticipated proliferation of wirelessly connected devices infiltrating global lifestyles. Poised to constitute the 'next big thing', the 'Internet of Things' is more commonly referred to as IoT, and encompasses limitless applications enabled through scale. IoT encompasses different devices and end markets, each with their specific market drivers and requirements. But the one resounding driver ultimately required to make IoT happen is integration. Integration is required on many levels, integration of software within hardware, of digital within analog electronics, of digital processing within sensing, and, of RF within power management. Semiconductors are playing a significant role in enabling IoT. As a result, the industry is seeking ways to develop, streamline and optimize an effective ecosystem, encompassing design, manufacture, packaging and test. IoT is pushing system complexity to new levels, and packaging technologies are being developed accordingly, with innovations in MEMS, sensors and SiP finding particular prominence. It is recognized that the supply chain needs to evolve alongside technologies. To make IoT mainstream will require a complete and organized ecosystem, as well as a solid supply chain. As the industry in Europe rises from a downturn decade, this changing environment represents a dynamic opportunity for many European semiconductor design, assembly and test companies. We will present an overview of technologies developed for miniaturized and efficient modules. We will identify specific technical challenges and emphasize the importance of establishing a strong supply chain, drawing from some pertinent examples. This talk will then explore opportunities within the automotive and sensor segments, particularly as these are both strongholds of the European semiconductor industry.

CV of presenting author
Jean-Marc Yannou is technical director at ASE Group in Europe. Before, Jean-Marc worked in various positions in the semiconductor industry for 18 years. He worked for Texas Instruments in test and product engineering and for Philips (then NXP semiconductor) where he served as Innovation Manager for System-in-package technologies, then for Yole Développement as a senior market analyst.

Advanced Packaging Conference (APC)
16th European Manufacturing Test Conference (EMTC)
Asia Optical Ether Lusinchi, Jean Pierre
Evolution of Design and Manufacturing of optical modules for mobile phone.
Lusinchi, Jean Pierre

Lusinchi, Jean Pierre
CTO AOEther
Asia Optical Ether

Abstract
More than 80% of the lenses produced today are used in the cameras for mobile phones. The particular constraints they impose in term of physical dimension and performances are then the major driver in design and manufacturing techniques for lenses used in the visible spectrum. However, some emerging applications are extending the spectrum to the Near Infrared (NIR), and even to the Far Infrared (FIR), which require using different material for the lenses and different design techniques. The quasi totality of lenses produced today is based on the Snell law on light refraction, and their performances are limited by this law, particularly the depth of field imposing the usage of autofocus, or alternative techniques like those implemented in Light Field cameras. Others limitations stem from the mere structure of the sensors which makes a sampling of the image, and from the pixel size and F#, which constitutes an unsurpassable limit to the resolution. Within this limit the demand for improved performances fosters many developments in image processing, made possible by increased computing power and fast access to large memory. Nevertheless, before any post processing is applied, the lenses are more and more complex, using aspheric surfaces to correct geometric aberrations and sophisticated materials to correct chromatic aberrations and thermal drifts. Difficult tradeoffs are often necessary to arbitrate between performances and manufacturing constraints. Another way to improve performances would be to make a curved sensor matching the field curvature. We review these limitations in performances and discuss the different solutions, and we make a short overview of lenses manufacturing techniques in glass, injection plastic or thermoset materials, discussing their advantages in cost and performances. Finally, we evoke the development of new kind of lenses, flat lenses or pinhole "lenses", addressing specific applications, with their advantages and present limitations. JP LUSINCHI

CV of presenting author
Engineer in Electronics Master of Sciences.Major in Physics PhD ( Signal Processing) 38 years with STMicrolectronics, from 1968 to end 2006. R&D Engineer Design Manager Product Manager General Manager . Video Division and Imaging Division Group Vice President.Optical Operations. From May 2007 : CTO of Ether Optronics / AO-Ether Focus on : Glass molding technology to make lenses for mobile phones, as an alternative to epoxy ( wafer lenses) for reflow assembly. Mixed Glass/Plastic lens stacks. Investigations on new Auto Focus technologies Liquid lenses MEMS Active alignment techniques. Development of design techniques for Near IR and Far IR collimating and Imaging lenses.Development of molding techniques of chalcogenide glasses

Imaging Conference
ASM Europe BV Herbschleb, Cornelis
The dawn of 450mm production: Batch and single wafer equipment and process exploration
Herbschleb, Cornelis

Herbschleb, Cornelis
Process Engineer
ASM Europe BV

Abstract
C.T. Herbschleb, T.G.M. Oosterlaken, R. De Blank, S. Strausser, J. Cossins, M. Boy (Siltronic) ASM was involved in the 450 mm transition from an early stage, and has designed and developed 450 mm pilot systems. Currently, two systems are installed in the Global 450 mm consortium clean room in Albany, New York. The first system is a single reactor batch furnace, capable of dry and wet oxidation processes, hydrogen cures, and in situ DCE cleans up to temperatures of 1000 C. Its load size is 100 product wafers; it comprises one load port and intermediate wafer storages. An exchange track dominates the appearance of the backside of tool, which facilitates easy maintenance, as tool components have increased in size and weight. The general hardware of the furnace will be described, as well as data on uniformity for thin dry oxides and thick wet oxides. In addition, designs used and tested in the 450 mm tool which can be back-integrated into 300 mm equipment of ASM will be covered, and their benefits for logistics, serviceability, and thermal performance will be explained. The second ASM 450 mm system at G450C to be described is a processing tool having four dual chamber modules capable of PECVD and PEALD applications. This system has been in operation since mid-2012, and an overview of the performance data achieved to date will be given, as well as a general description of the tool and some of its key features for 450 mm.

CV of presenting author
Cornelis (Kees) Herbschleb graduated from Leiden University in 2006 and obtained a PhD at the same university in the interface physics group. In 2011 he joined ASM as a process engineer, specifically for process development on the 450 mm equipment; currently he is the lead technical engineer on the 450 mm tool, concerting activities on this equipment of partners within European 450 mm projects including EEMI450 and SEA4KET.

450mm
ATREG. Inc. Silver, Barnett
Shared Manufacturing Model - An Alternative Approach for Semiconductor Companies
Silver, Barnett

Silver, Barnett
Senior Vice President / Principal
ATREG. Inc.

Abstract
As production costs continue to rise in the semiconductor industry, companies are beginning to reevaluate their approach to manufacturing. A pure fabless model provides the benefit of limited capital costs, but comes with manufacturing allocation risk and potential price spikes. The pure IDM or fab ownership model provides a higher degree of manufacturing control, but has associated costs and risks of ownership. In an attempt to balance risks and benefits, many companies have adopted a fab lite model in which they own fabs and use foundries for some production. Is there an alternative approach that can provide a better solution than fab lite? One alternative being considered is the joint venture model as it allows multiple parties to share loading within a fab and enjoy the benefits of fab ownership without having to be responsible for 100% of the associated costs. In this session, Barnett Silver, Senior Vice President & Principal of ATREG, presents a first hand experience of working on joint venture models and the benefits and challenges associated with structuring such a partnership. Attendee takeaways & benefits - Explore the motivations driving alternative manufacturing models - Preview a joint venture structure available in the market today - Understand the key issues and concerns facing potential partners during the transaction process

CV of presenting author
As a Senior Vice President and Principal with ATREG, Barney brings over 15 years of experience in finance, real estate, and investment banking. Barney works with ATREG's clients across the semiconductor spectrum in Asia, Europe, and North America on acquisition, disposition, and complex strategy assignments. He has recently worked with Freescale Semiconductor, IDT, Qimonda, Renesas, Texas Instruments and TowerJazz. In addition to leading client assignments, Barney is responsible for the company's operations, focused on developing new business opportunities and growing the ATREG platform. Prior to joining ATREG, Barney held a variety of senior management and advisory roles. Most recently, he served as President of one of the largest independent mortgage banking firms in the Pacific Northwest. Prior to relocating to Seattle, Barney worked in the Investment Banking and Debt Capital Markets divisions of Morgan Stanley at the company's New York headquarters. During his tenure, he was involved in raising debt and equity capital for public and private companies as well as advising clients on mergers and acquisitions. Prior to Morgan Stanley, Barney worked in the Investment Banking division of LaSalle Partners. Barney received his AB degree from Dartmouth College and his MBA for the Wharton School at the University of Pennsylvania. He currently serves on the board of Wellspring Family Services, one of the oldest non profit agencies in Seattle serving families in need. Prior to this, he serves as Chair Emeritus of the MIT Enterprise Forum of the Northwest, a non profit affiliate of MIT in Cambridge that educates entrepreneurs around the world.

International MEMS Industry Forum
Audi Hellenthal, Berthold
Driving solutions - intelligent sensor systems
Hellenthal, Berthold

Hellenthal, Berthold
Robust Design, Semiconductor Strategy
Audi

Abstract
To facilitate piloted driving a car needs "supernatural" abilities beyond the human senses. IR/Nightvision, radar, ultrasonic, laser scanner and cameras to name some of the sensors necessary for mapping the surrounding and the driving situation. All these "new" senses are enabled by semiconductors. Still, it is not the semiconductor the OEM is looking for, but a sensing solution. Taking the growing possibilities of packaging, i.e. system-in-package, system-in-module, and the more-than-moore advances into account, intelligent sensor systems can be developed offering a new solution space. This miniaturization facilitates an advanced and updateable technology platform to take advantage of the latest semiconductor developments allowing new functions, faster time-to-end customer, in a smaller space, at equal or less cost. This new solution dimension changes the value chain as well as the competences needed to develop, validate and mass produce intelligent sensor systems. Semiconductor companies will need to understand the application and provide eco-systems and solutions as well as Tier1 companies need semiconductor packaging know-how and experience. The industry will change or be changed by new players. The presentation will explain the OEM perspective and semiconductor strategy using an imaging sensor example.

CV of presenting author
Dipl.-Ing. Berthold Hellenthal joint Audi in 2008 as a member of the management team. Working in the Electronic Development Department, he comprehensively supports all Audi electronic development out of a competence center especially in the areas of hardware reviews, analysis and semiconductors. Mr. Hellenthal is also responsible for the comprehensive Audi Semiconductor Strategy, the Audi Progressive SemiConductor Program (PSCP).

Imaging Conference
AWAIBA CMOS IMAGE SENSORS Waeny, Martin
Miniaturization trends in medical imaging enabled by full wafer level integration if micro camera modules
Waeny, Martin

Waeny, Martin
CEO
AWAIBA CMOS IMAGE SENSORS

Abstract
The merge of MEMS and O-MEMS based technologies with wafer level optics, CMOS image sensor technologies and wafer level chip scale packaging technologies allows the realization of full wafer level assembled micro camera modules with unprecedented size miniaturization. The large economy of scale introduced to the traditionally "artisanal" endoscopic equipment manufacturing allows for one time use equipment, mitigating operational cost and risks associated with sterilization. The availability of miniature size high resolution imaging modules, (having all dimension smaller than 1mm) at a controlled cost allows the realization of novel medical imaging applications on equipment and in procedures where previously visualization was not possible or existing visualization was strongly limiting the versatility of the tools and providing limited resolution only. This talk gives an over view of key enabling technologies and application potentials.

CV of presenting author
Martin Wäny graduated in microelectronics IMT Neuchâtel, in 1997. In 1998 he worked on CMOS image sensor at IMEC. In 1999 he joined the CSEM, as PHD student in the field of digital CMOS image sensors. In 2000 he won the Vision price for the invention of the LINLOG Technology and in 2001 the Photonics circle of excellence award of SPIE . In 2001 he co-founded the Photonfocus AG. In 2004 he founded AWAIBA Lda, (www.awaiba.com) were he is CEO. AWAIBA is a design-haus and supplier for area and linescan image sensors specialized on high speed and high dynamic range sensors and miniature wafer level camera modules for medical endoscopy and portable miniature vision. Martin Wäny was member of the founding board of EMVA the European machine vision association and the 1288 vision standard working group. He is member of IEEE and SPIE societies.

Imaging Conference
B To top
Beneq Shuo Li, Shuo
Excellent Moisture Barrier by Plasma Enhanced Atomic Layer Deposition Aluminum Oxide for plastic electronics applications
Shuo Li, Shuo

Shuo Li, Shuo
Senior Scientist
Beneq

Abstract
Recently, aluminum oxide (Al2O3) by atomic layer deposition has become the most attractive material for ultra moisture barrier property for organic light-emitting diodes (OLEDs), organic photovoltaics (OPVs), and flexible displays in both scientific and industrial communities. Such plastic based electronics applications usually require low deposition temperature <100 °C,and ultra low water vapor transmission rate from 1x10e-4 to 1x10e-6 g/m2day. Plasma enhanced ALD is a promising method to deposit high quality films even at low temperatures. In this paper, Plasma enhanced atomic layer deposition (PEALD) Al2O3 was successfully deposited on different plastic substrates at 90 °C by PEALD with Beneq TFS200 reactor. The film growth rate and refractive index were studied as a function of plasma power and plasma pulse time.With increasing the plasma pulse time from 0.5s to 6s, the film growth rate increased up to 1.6 Å/cycle and then further decrease down to 1.5 Å/cycle, which is much higher than thermal ALD process. The plasma power has significant effect on the film refractive index and film density, which is correlated with the layer barrier property. A very high refractive index n=1.64 was achieved. Such high refractive index has not been reported before by conventional thermal ALD at low deposition temperatures. The film composition was also studied by Time-of-Flight Elastic Recoil Detection Analysis (TOFERDA), which explained the plasma mechanism related film growth property. The mositure barrier properties on plastic substrates was studied by varying the film thickness at different plasma power and pulse time. A very low water vapor transmission rate of <5e-5 at 38°C/100%RH was measured by MOCON Aquatran permeation measurement system.The barrier and passivation performance was also investigated by using Optical Ca and organic light emitting diodes.

CV of presenting author
Mr. Shuo Li is currently leading the industrial process development of moisture barrier for OLED encapsulation and barrier films by plasma enhanced atomic layer deposition in Beneq OY. Beneq is a leading supplier of production and research equipment for thin film ALD and aerosol coatings, as well as the world's premier manufacturer of thin film electroluminescent (TFEL) displays. Beneq equipment is used for applying coatings in solar photovoltaics, flexible electronics, strengthened glass and other emerging thin film applications. Beneq has introduced several revolutionary innovations in its coating technologies, including roll-to-roll atomic layer deposition (ALD) and high-yield atmospheric aerosol coating (nAERO®). Beneq also offers extensive coating services, ranging from experimental concept confirmation to industrial-scale production.

Plastic Electronics - PE2014
Bosch Connected Devices and Solutions GmbH Mueller, Thorsten
Smart connected sensor devices for the Internet of Things and Services
Mueller, Thorsten

Mueller, Thorsten
CEO
Bosch Connected Devices and Solutions GmbH

Abstract
While the history of the internet was dominated by computer-to-computer communication (Web 1.0) and the emergence of social media (Web 2.0), the internet is currently undergoing its next big transformation. In 2015 three quarter of the world's population will have access to the internet. As both sensor and connectivity cost continuously decrease and wireless networks become pervasively available, the next logical step is to connect everyday objects to the internet. This trend is called Web 3.0 or Internet of Things and Services (IoTS). In order to unlock the full value of this fast growing market, three main elements are required: sensors, software and services - the so called "3S" of IoTS. The Bosch Group is active in all three areas, with Bosch Connected Devices and Solutions being a global provider of smart sensor devices and complete customer solutions. Being a pioneer of micro electromechanical system based sensors (MEMS), which were introduced to the automotive market in the 1990s and have find widespread use in consumer electronics since the mid 2000s, we now capitalize our extensive know how in emerging IoTS markets. Combined with a microprocessor, smart algorithms, use case specific radio technologies and a battery for autonomous operation, these sensor devices will find widespread application in domains like smart homes and buildings, transportation and logistics as well as smart factories and wearable devices. By using this technology Bosch Connected Devices and Solutions gives everyday objects senses. We call it the third wave of sensor application, which is projected to significantly exceed the first two waves (automotive and consumer electronics) in number of deployed devices.

CV of presenting author
Thorsten Mueller was born in Duisburg, Germany in 1977. He holds a Diploma in physics from Gerhard-Mercator-University and a PhD in solid state physics from University Duisburg-Essen. In 2013 he completed the Executive Transition Program at European School of Management and Technology in Berlin. He joined the Bosch Group in 2005. During his first assignments as project manager at Corporate Research, he worked on new types of semiconductor sensors as well as on new manufacturing processes for the size reduction of inertial sensors. In 2008 he joined the business development department of the Automotive Electronics division where he was responsible for strategic planning, mergers & acquisitions as well as the division's venture capital activities. In 2010 he was appointed director engineering for inertial sensors in automotive applications (airbag and ESP). He was one of the co-founders of the internal start-up "Connected Things". After successfully having managed the proof-of-concept phase, he was appointed CEO of the newly founded subsidiary Bosch Connected Devices and Solutions GmbH in December 2013.

18th Fab Managers Forum
Bosch Sensortec Forget, Jeanne
The Future of MEMS Sensors in Our Connected World
Forget, Jeanne

Forget, Jeanne
Head of Marketing
Bosch Sensortec

Abstract
From automobiles and smart phones to gaming devices and 'smart home' systems, the products on which we depend are connected wirelessly - to the internet, to wireless sensor networks, and to one another. These products heavily rely on MEMS sensors. Bosch - as a pioneer of MEMS sensors and solutions - has driven their proliferation from the automotive world into the consumer electronics market. Today, cars use up to 50 MEMS sensors, and smart phones up to a dozen different sensors. Now, at the dawn of the Internet of Things and smart wearable devices, MEMS sensors are also becoming critically important to this kind of connected devices. But what is the impact of this development on the MEMS sensor technologies? MEMS technology is commercialized since more than 15 years now. As the product and applications scope extended continuously, there has been also significant progress with regards to technology and process. With the second wave of MEMS commercialization driven by CE applications the focus on size, power consumption and overall system performance drives major technological achievements. This evolution is laying the ground for the next wave of MEMS sensor adaption in the context of "connected sensors everywhere". To reach this goal there are still some technical and commercial challenges ahead. On one hand, the integration drive - multiple sensors in one package or die - leads to sophistication and complexity increase of employed technologies, on the other hand, the demand for additional sensing values increases the number of technologies required. Pairing this with the request of providing integrated smart solutions out of one hand, there are probably only a few players that can tackle future market requirements on a broader scale. Today the future of our connected world seems limitless. With more than 125 years of making complex systems possible, Bosch will be there every step of the way, to ensure that we gain more than we ever imagined from our connected world.

CV of presenting author
Jeanne Forget is Head of Global Marketing of Bosch Sensortec GmbH - a fully-owned subsidiary of Robert Bosch GmbH. She is responsible for strategic marketing planning, product management and marketing communication of micro-electro-mechanical sensors (MEMS) and solutions for the consumer electronics industry such as smart phones, tablets, accessories and wearables. Mrs. Forget studied Sciences of Materials and Mechanics in Grenoble, France. She started her career at Bosch in Corporate Research in 1995 in the field of Thin Film Technologies. Jeanne Forget has joined Bosch Sensortec in June 2013 after several positions in Marketing, Strategic Marketing and Business Development of New Business Fields at Robert Bosch GmbH.

International MEMS Industry Forum
Bosch Sensortec GmbH Lammel, Gerhard
Lammel, Gerhard

Lammel, Gerhard
Senior Manager MEMS
Bosch Sensortec GmbH

Biography
Gerhard Lammel is Senior Manager MEMS at Bosch Sensortec, head of advanced development and part of the founding team of Bosch Sensortec. Before, he was responsible for the process development for an integrated pressure sensor in the business unit Automotive Electronics of Robert Bosch GmbH. He obtained his PhD in 2001 from the Swiss Federal Institute of Technology in Lausanne, Switzerland. Gerhard Lammel studied physics and economics at the University of Munich. He founded two small high-tech companies for computer networks and computer graphics in 1991 and 1995. He is inventor and co-inventor of over 50 patents.

International MEMS Industry Forum
C To top
Cadence Design Systems Inc Binning, Marcus
Using Configurable Processor Technology to achieve power efficient architectures
Binning, Marcus

Binning, Marcus
Senior AE Manager
Cadence Design Systems Inc

Abstract
This discussion will centre around how "configurable and extensible" processor technology can be leveraged to create highly power efficient processor cores for such diverse domains as "always-on" functionality (including voice triggering and sensor fusion applications) and highly efficient complex Image and video processing. We will explore some of the fundamentals of the Cadence® Tensilica® Xtensa® technology, and use some examples from the above domains to illustrate how the Xtensa architecture can be used to create these apparently diverse, but highly efficient, solutions and their associated software tools. Finally we will explore how these architectures can be seamlessly integrated into state-of-the-art implementation flows in a very short time, targeting high efficiency implementations whether the emphasis is on lowest power or highest performance.

CV of presenting author
Bio - Marcus Binning Having spent his early career in digital and embedded software design, Marcus Binning spent eight years deploying and supporting complex EDA tools (Zycad HW accelerators and emulation tools, and formal verification tools from Chrysalis Symbolic Design) into a variety of European customers. Since 2000 he has headed up the application engineering effort in Europe for the Tensilica® Xtensa® configurable processor technology (now owned by Cadence Design Systems, Inc.). As an acknowledged expert in the ASIP (Application Specific Instruction set Processor) field, he has been involved with (and directly contributed to) a number of successful, complex customer designs in companies both small and multi-national. He holds a Bsc. (Hons) in Electrical and Electronic Engineering from the University of Bristol, and currently works in the UK office of Cadence Design Systems.

Low Power Conference
Caeleste Dupont, Benoit
Custom image sensors for high performance application
Dupont, Benoit

Dupont, Benoit
chief designer
Caeleste

Abstract
CMOS image sensors have become preeminent in camera design for many applications ranging from smartphone to security cameras and now scientific and space application. often in scientific and high end imaging, such high performance sensors are not available off-the-shelf and must be tailored to the particular application. In this presentation, we explore the performances that can be reached in custom design image sensor in the following domain: *** Sensitivity *** Spectral response *** Dynamic range *** Noise Through design examples of existing products, we show the different tradeoff spaces linked to custom design of high performance applications. In particular, we show: *** How to reach zero noise sensors ? and for what application? *** How to design extreme HDR sensors ? up to 32M:1 linear dynamic range.

CV of presenting author
Benoit Dupont received his PhD Diploma in physics from the University of Paris-Sud in 2008 and an IC design engineering degree from ISIM, Montpellier in 2002. He worked as digital system engineer and cmos image sensor designer at FillFactory from 2002 and 2005. He made his PhD research in partnership with the LETI and ULIS Company, Grenoble, in the field of readout circuits for bolometer infrared image sensors from 2005 to 2008. He is now co-founder of Caeleste where he is chief designer.

Imaging Conference
Cambridge University Rider, Chris
Innovating in Plastic Electronics within a manufacturing model
Rider, Chris

Rider, Chris
Director, EPSRC Centre for Innovative Manufacturing in Large-Area Electronics
Cambridge University

Abstract
Innovative companies wishing to use plastic electronics in new products are faced with particular challenges in preparing to scale-up for manufacture. As plastic electronics is a relatively new technology, manufacturers often find that they are pioneers and that the challenges of securing the resources to develop high-volume manufacturing processes and optimise them for yield and cost can be significantly greater than would otherwise be the case. This talk outlines a number of these challenges and identifies ways to accelerate the scale-up process and minimise resource requirements, using examples from recent experience.

CV of presenting author
Chris Rider is the Director of the EPSRC Centre for Innovative Manufacturing in Large-Area Electronics, a partnership between 4 UK Universities with a mission to address key research challenges relating to the manufacturing of printed and plastic electronic systems. This new Centre will have a particular focus on system integration for large-area electronics systems in which component functions, such as energy harvesting and storage, printed logic circuits, printed sensors, reflective displays and printed interconnects are brought together with unpackaged silicon where necessary, for applications including smart packaging, anti-counterfeiting, intelligent sensors and smart objects. Prior to his move to Cambridge University in 2009, Chris was a Department Head at Kodak European Research, Cambridge, leading a team of scientists working on various projects to provide technology for Kodak's Displays and Graphic Communications businesses. Within the portfolio were novel inkjet devices and inks, advanced printing plates as well as new processes for patterning active materials combining additive deposition with profiled substrates. At that time, he led R&D programmes in electronic display, solution-processed solar cells, atmospheric spatial ALD and printed transistors. Chris is a co-founder and director of Imbrys, a high-throughput microfluidic manufacturing technology company whose devices are capable of producing monodisperse droplets of one liquid inside droplets of another. He serves on the UK's Plastic Electronics Leadership Group and the Centre for Process Innovation's Technology Advisory Committee. He is a holder of 35 patents.

Plastic Electronics - PE2014
CATRENE Rousset, Denis
450mm specifications will boost the 300mm yield in wafer manufacturing
Rousset, Denis

Rousset, Denis
Office Director
CATRENE

Abstract
The 450 mm wafer transition has been initiated since 2009 with the first attempt to propose a new wafer size. EEMI450 project has been launched by the European Equipment and Materials Industry in order to stimulate activities on 450mm. The semiconductor total demand has recorded a CAGR of 7.6%, extrapolating this growth rate, the amount of silicon shipped would double in just less than 10 years. The challenge for chip maker choosing to adopt 450mm will be to get yielding die similar than 300m. The yield hunting became the main worry. Defect inspection and metrology steps absent or subsidiary in the 300mm wafer manufacturing have been introduced for 450mm. CATRENE and ENIAC has facilitated the creation of projects to deliver solution for preventing all kind of contamination. Process equipment manufacturers develop tools that reduce contamination in the FOUP and are developing cleaning process free from added particles. Wafer manufacturers develop extremely flat wafer substrates with high uniformity roughness. The G450C initiative has allowed the definition of the EPM (Equipment Performance Metrics). This worldwide cooperation has been supported by the emergence of many SEMI specifications solidifying the quality standard of the 450 mm equipment. During the last months a question is circulating : can we adopt the 450mm specifications to the 300mm wafer manufacturing ? The increased 300mm volume will require a steady improvement of the yield. This means smaller process windows and constant reduction of defect density. Obviously the processes will also require continuous monitoring to identify and reduce the cause of process variation. The retrofit of the 450mm specifications to the 300mm equipment will provide a boost to 300mm wafer manufacturing yield and a direct return of the R&D effort spent of the 450mm. In the perspective of cost reduction of the 300 mm, it is mandatory for the actors to keep running initiatives in the 450mm ecosystem to be ahead.

CV of presenting author
Denis has the Director for Programme Technologies at CATRENE (Cluster for Application and Technologies Research in Europe on Nano-Electronics) since July 2012and now he is CATRENE Office Director on top. He is still monitoring a hand full of collaborative projects focusing on Advanced CMOS process, Equipment, New Materials and Manufacturing. Just before, Denis leaded the Public Affairs department at ST-Ericsson, world leader in development of wireless platforms and semiconductors, thus defining and managing worldwide collaborative programs during 4 years. He started his career at Motorola in Toulouse, France, in process engineering, before moving to STMicroelectronics (formerly Thomson Semiconductors) in 1983. From a telecom product engineering manager, he became the telecom marketing manager in charge of North America. Back in Europe in 2001, he became key account manager for Alcatel Mobile Phones and was thus directly involved in the integration of the Alcatel teams following the acquisition of Alcatel's mobile telephone business. In 2002 he also participated in the organization of the first GSM Platform at STMicroelectronics. In 2005, Denis took the responsibility of the key account management for Ericsson's Mobile Platform until the creation of ST-Ericsson, the joint-venture of STMicroelectronics wireless business and Ericsson Mobile Platforms in 2009. Denis holds a Bachelor of Engineering from the Ecole Nationale Supérieure de Radioélectricité of Bordeaux (France) and participated in an executive training program at the Harvard Business School.

450mm
CEA-Leti Clermidy, Fabien
Low-power multiprocessing: from embedded to servers multi-core
Clermidy, Fabien

Clermidy, Fabien
Senior expert
CEA-LETI

Abstract
Energy efficiency is nowadays required for all the multi-core applications, from embedded to servers. Being a natural focus in embedded systems, lessons learnt from this application field can be applied to servers or even High Performance Computing. However, constraints and objectives are different: larger power consumption, higher memory bandwidth and performance objective for servers compared to fixed reduced power budget objective for embedded systems. This comes with large-scale chips for servers while relatively small-size chips are used for embedded systems. In this talk, we will discuss solutions for power efficient multi-core embedded systems and their application to server chips. Advanced technologies such as FDSOI and 3D stacking will also been considered as ingredients useful for closing the gap between these two application fields.

CV of presenting author
Fabien Clermidy obtained his master degree in 1994, his Ph.D in Engineering Science from INPG, Grenoble in 1999 and his supervisor degree from INPG in 2011. He is currently head of the digital design laboratory at CEA-LETI. The lab main activities are targeting multi-core architectures and low-power design with some chips developed in the last few years: MAGALI, a 23-core targeting 3GPP-LTE applications; P2012 (coll. with ST), a 64-core multiprocessor for augmented reality applications; WIOMING (coll. with ST/STE), a DRAM on multi-core platform. Fabien Clermidy has published more than 70 journal and conferences papers and is author or co-author of 15 patents. He is currently associate editor for TCAS-I journal.

Low Power Conference
CEA-Leti Louis, Didier
Louis, Didier

Louis, Didier
International Communication Manager
Cea-Leti

Biography
Since joining CEA-Leti in 1985, Didier Louis has held a variety of positions in microelectronics research. In 2000, he served as the manager of the etching and stripping R&D laboratory, and from January 2004 to December 2007, he was deputy manager of the BEOL Laboratory. In 2008, he was named the deputy manager of Leti's Materials and Advanced Modules Laboratory and public relations manager of the Nano-Electronic Division. In 2010, Louis joins the directorate staff of Leti as Corporate and International communication Manager. He plays an active role in the organization of several International conferences such as IITC (International Interconnect Technology Conference), MNE (Micro and Nano Engineering), PESM (Plasma Etch and Strip in Microelectronics) and AVS-ICMI (during 3 years). He is a member of ITRS committee in the interconnect group. He is a member of SEMI STC and SEMI Award Group. Louis graduated from Electro-chemical en Material Engineering Scholl.

Application driven technology: Nanoelectronic for Healthcare (TechARENA)
CEA-Leti Tedesco, Serge
Tedesco, Serge

Tedesco, Serge
Program Manager
CEA-LETI

Biography
Biography Dr Serge Tedesco: 1979: PhD in Experimental Nuclear Physics from Grenoble University (F). From 1980 to 1981: Work on surface analysis equipment development (ESCA) at Riber SA in Paris. From 1981 to 1987 : Work on electron beam lithography technology at Varian Lithography Product Division in Gloucester Mass. (USA) where he was first responsible for System integration of the raster scan e-beam systems and then Engineering manager . In 1987 he joined the CEA-LETI laboratories in Grenoble to take in charge e-Beam lithography and consequently all Advanced Lithography activities. Since 2003 he manages CEA-LETI Advanced lithography strategy and programs as Business Development Manager. Dr Tedesco has authored or co-authored numerous papers in the field of lithography and he is a Program committee member of the major International lithography conferences. Dr Tedesco has been involved in numerous European projects both as project leader and expert.

Lithography: What lithography options for tomorrow? (TechARENA)
CEA-Leti Lattard, Ludovic
Mask Less Lithography for Volume Manufacturing
Lattard, Ludovic

Lattard, Ludovic
Lithography Laboratory Deduty Manager
CEA-LETI

Abstract
Besides the development of EUV lithography addressing the high volume manufacturing segment for the production of future CMOS nodes, alternative e-beam lithography techniques are under development and may offer credible and low cost patterning solutions for industry. This paper will review the status of multi-beam lithography technology. This evaluation will be based on the result of the first cluster worldwide installed for multi-beam lithography in CEA-LETI and on tool development in Mapper. CEA-LETI received the 1st pre-production platform named MATRIX 1.1, and started to evaluate module by module this platform that will operate 1300 beams for an initial throughput target of 1 wafer per hour. Handling and alignment capability represents two new innovative aspects among the key points introduced in this new generation system. Concerning handling, the development of massively-parallel electron-beam lithography requires strict temperature control and clamping reliability of the wafer during alignment and exposure for the achievement of good overlay performances. The low costs and small footprint of the MATRIX platform does not allow MAPPER to use conventional handling systems. Mapper developed a new type of handling with a Vertical Transfer Robot. To ensure a reliable wafer handling and clamping process, new modules have been developed. CEA-LETI and MAPPER directly investigates the robustness of the different modules in real manufacturing conditions, including the interface of the MATRIX platform with the SOKUDO DUO track. Results on performances in terms of reliability, repeatability and stability will be reported.

CV of presenting author
Mr Lattard is graduated from Lyon University in France. After receiving his Master, he worked in the field of flat panel display until 2002. Starting in 2003 he worked seven years in Germany and he was in charge of process development at Infineon. From 2009, he is working as project manager in CEA-LETI and is working in collaboration with several tool suppliers for process development on advanced lithography. Since 2013, he is deputy manager of the lithography laboratory and lead several projects in the field of lithography.

Lithography: What lithography options for tomorrow? (TechARENA)
CEA-Leti Gouze, Eric
Microsensor for Health applications
Gouze, Eric

Gouze, Eric
Business Development Manager
CEA-Leti

Abstract
T B A

CV of presenting author
After having gained a solid experience in designing advanced integrated circuits, Eric Gouze decided to focus on the development of products, systems and innovative services, both within large groups and startups. Since joining CEA-Leti in 2011, he strives to meet the needs of industrial partners by fostering the emergence of new technologies and relying on the expertise and recommendations of medical teams at the forefront in their field.

Application driven technology: Nanoelectronic for Healthcare (TechARENA)
Cea-Liten Gwoziecki, Romain
Gwoziecki, Romain

Gwoziecki, Romain
Head of Laboratory
Cea-Liten

Biography
Romain GWOZIECKI graduated as an Engineer in Microelectronics in 1996 and obtained a PhD degree in Physics in 1999. From 2000 to 2007, he has been working in the field of Advanced CMOS Silicon technologies with ST Microelectronics in Agrate (Italy) and Crolles (France). In 2007, he joined the Printed Component Laboratory from CEA-LITEN, being in charge of the characterization and modeling of the printed organic components from 2007 to 2013. From 2013, he is in charge of devices and process flow development for printed sensors, actuators and OTFTs circuits as head of the Printed Electrical Components Laboratory in CEA-LITEN. He held 6 patents and authored or co-authored more than 50 papers, act as reviewer for several journal (Organic Electronic and Solid-State Electronic).

Plastic Electronics - PE2014
CEA / Leti /optics and photonics Division Mourey, Bruno
Mourey, Bruno

Mourey, Bruno
Vice President
CEA / Leti /optics and photonics Division

Biography
Graduate from Ecole Supérieure de Physique et Chimie (Paris) and PhD in electronic and instrumentation (Université de Paris VI) Bruno Mourey had different positions in relation with display applications from research to manufacturing in the Thomson group. He was general manager of Thomson LCDs for more than 10 years Bruno Mourey joined CEA LETI in 2003 as Program manager for multimedia applications (display, optical recording***.), He is currently Vice president at CEA LETI in charge of the Optics and Photonics Division

Imaging Conference
CEA LETI MINATEC Frey, Laurent
Spectral filtering on CMOS Image Sensors with metal dielectric multilayers
Frey, Laurent

Frey, Laurent
senior research scientist
CEA LETI MINATEC

Abstract
The traditional technology to achieve spectral filtering for CMOS image sensors includes a combination of polymer resists and external all dielectric multilayer thin film coatings. In this study, we investigate the suitability of metal dielectric interference stacks as a completely integrated solution. Silver and copper are the metallic materials considered for various applications ranging from colour imaging to ambient light sensing and time-of-flight in the near infrared domain. The compatibility with the CMOS process is shown through technological demonstrations. The performances and limitations of the on-chip filters are detailed, including robustness to process errors in the prospect of large scale manufacturing.

CV of presenting author
Dr Laurent Frey got optics education from Ecole Supérieure d'Optique Graduate School (1996). He obtained a PhD in optics and photonics from Paris Sud University (2000), after a thesis in the domain of photorefractive materials. He joined CORNING European Research Center in Fontainebleau with activities focused on the development of optical components for ultra-high speed telecommunications (2000-2003) in close connection with the US teams. Since 2003, he has been working in CEA, LETI, MINATEC as research scientist and project leader for several photonic application domains such as holographic mass storage, superconducting detectors, silicon integrated photonics and imaging. He has also been responsible for roadmapping activity in optical systems for imaging. His current topic is focused on the development of spectral filters and nanostructures for industrial visible image sensors with improved performances. He is author or co-author of 12 publications and 19 patents including 2 pending.

Imaging Conference
CEA, LETI, MINATEC Campus Toffoli, Alain
Toffoli, Alain

Toffoli, Alain
Electrical charactrization research engineer
CEA, LETI, MINATEC Campus

Biography
Alain Toffoli is expert in the field of test methodologies. He received the M.S. degree in engineering from the "Conservatoire National des Arts et Metiers, Paris". He is Head of the Advanced and Statistical electrical characterization Test Team, in the Electrical Characterization and Test Laboratory, of CEA/LETI Minatec-Campus. His team is responsible of the automated electrical characterizations, for all micro and nano technologies activities and projects. His main research interests include test methodologies.

16th European Manufacturing Test Conference (EMTC)
CEA LITEN Bouthinon, Benjamin
Coupled organic photodetector onto a plastic organic thin-film transistor backplane.
Bouthinon, Benjamin

Bouthinon, Benjamin
PhD candidate
CEA LITEN

Abstract
We report the fabrication process and the characterization of a coupled organic photodetector arrays onto a transparent plastic organic thin film transistor (OTFT) backplane. This hybrid integrated system on foil is based on arrays of 1 diode + 1 p-type transistor. The transparency of the OTFT backplane allows us to illuminate the sensor from front and back sides depending of the addressed applications (medical imaging application and human machine interface). The flexible hybrid sensor has a 4*4cm active area, 375µm pitch and 94x95 pixels resolution. The flexible backplane has been developed to meet the OPD requirements using Plastic Logic proprietary process by building a top Gate transistor array on a plastic substrate with p type organic semiconductor. Then, the photodiode panel was entirely printed by slot die technique. This printing technique offers the capability of a high throughput for mass production and an excellent control of the uniformity, reproducibility and thickness of the layer. The process is done at room temperature and in ambient air condition. Main figures of merits of the hybrid photodetector are finely characterized including quantum efficiency, current-voltage characteristics, linearity over 7 decades of power light and time response measurement. Pixel characterization is also addressed. The uniformity of the pixel sensitivity is measured with a 75µm light beam diameter. Other type of hybrid integrated system can be addressed by replacing the photodetector array by temperature sensor, memory array, actuator... Printed p type OTFT backplane is a good opportunity to monitor plenty of fully printed organic devices. The main advantages of such technology is the process compatibility between organic sensors and organic transistor arrays all printed on the same plastic substrate. This corresponds to the main roadmap of our group as OTFT, printed sensors and actuators have been developed separately in the past and can be now integrated together.

CV of presenting author
Benjamin Bouthinon is currently pursuing the PhD degree with the CEA LITEN Institute, Grenoble, France at the Printed Electronics Lab. His current research interests include the caractérization and the modeling of printed organic devices such as OTFT and organic photodetector.

Plastic Electronics - PE2014
CEA tech Serbutoviez, Christophe
From LAB to FAB, review of printing technologies for organic electronics
Serbutoviez, Christophe

Serbutoviez, Christophe
Manager Organic Electronic Division
CEA tech

Abstract
We will report on the challenges associated with the industrialization of printing process dedicated to organic electronics. The presentation will first review the basic principles of printing equipments such as off-set gravure, ,gravure printer, flexoprinter, inkjet, screen print, slot die. On a second part of this talk, we will point out the challenges with production upscaling. A specific focus will be done on the aspect of substrate handling, ink curing and in line organic layer characterizations.

CV of presenting author
Dr. Christophe Serbutoviez (49) received his PhD in the area of organic materials for optoelectronics in 1992. He started his career Philips Research Laboratory (NL), on the development of new polymers for liquid crystal displays. He worked for 10 years at Thales Avionics LCD (Fr) as senior process engineer in the field of the industrialization silicon based active matrix. He joined CEA-LITEN in 2005, to develop activities dedicated to printed electronics. Dr Serbutoviez is currently head of the organic printed activities at CEA-Tech and he operates the CEA printing platform "PICTIC" dedicated to printing process industrialization. He has co-authored more than 30 papers and has filed 10 patents.

Plastic Electronics - PE2014
CEA/LETI Aubert, Jean-Jacques
GaN on silicon: A way to low cost power devices
Aubert, Jean-Jacques

Aubert, Jean-Jacques
Program manager Power electronics
CEA/LETI

Abstract
Silicon based electronic components have been widely used in power electronics since the beginning. Development of alternative mobility options pushes to prepare more efficient components to answer a growing market with new expectations in terms of performances and costs. Wide band gap materials have several characteristics that give them real advantages when compared with standard Si technology, such as higher temperature, frequency and voltage operation capacity. Nevertheless, Si power devices are still very popular and SiC did not take the place. Why? GaN on Si seems to be a good option to popularize wide band gap components technology since it offers large diameter low cost substrates and full compatibility with silicon technology. But some of the physical properties of GaN need to set up a specific strategy in terms of power modules to take benefit of the best of the material. GaN on Si technology will clearly reduce costs of power electronics, enhance technical performance and allow consumers to access efficient products in line with European waste reduction targets for coming years.

CV of presenting author
Jean-Jacques AUBERT recieved its PhD degree from University Joseph FOURIER and Institut National Polytechnique in GRENOBLE in 1978. He joined LETI in 1979 as a research engineer in material science for the growth of semiconductor crystals for the microelectronics industry. Envolved in the study of optical materials since 1990, he developed the microchip laser technology and transferred it to the startup NANOLASE. In 2003, he founded the startup company BEAMIND for the fabrication of contactless probers for the PCB industry. Back to LETI in 2009, Jean-Jacques AUBERT is now program manager for the materials for nanoelctronics and power electronics

Power Electronics Conference
CEA/LETI/Minatec Fenouillet-Bearnger, Claire
Technological challenges and applications of 3D sequential integration
Fenouillet-Bearnger, Claire

Fenouillet-Bearnger, Claire
Senior scientist
CEA/LETI/Minatec

Abstract
An alternative approach to conventional planar integration for future nodes is the 3D monolithic or sequential integration. Compared to TSV-based 3D ICs, monolithic offers the possibility to stack devices with a strong alignment precision enabling contacts introduction at the device level. However, this integration has to face the challenge to realize a high performance transistor at the top level without impacting the electrical characteristics of the bottom one. One of the issues consists in integrating transistors with low temperature process steps. The first technological challenge is the realization of a mono-crystalline and defect-free top semiconductor layer at low temperature while keeping a good uniformity to ensure good mobility and performance. The second one is the processing of low temperature top transistor with performance as good as the bottom one. Our previous works have highlighted the fabrication of low temperature devices around 600°C. Recent results demonstrate some integration solutions, such as junction activation by Solid Phase Epitaxy Regrowth below 600°C. In addition, the maximum thermal budget allowed at the top level for future technological nodes has been determined through morphological and electrical characterization. This presentation will review all the main challenges of the 3D sequential process integration and will give some example of applications.

CV of presenting author
Claire Fenouillet-Beranger was born in Grenoble, France in 1974. She received the postgraduate diploma in microelectronics and PhD degree from the Institut National Polytechnique de Grenoble, France, in 1998 and 2001, respectively. In 1998, she joined LETI, Grenoble, where she carried out her PhD. work on the integration and characterization of SOI devices. From 2001 to 2013 she worked as a CEA/LETI assignee in advanced R&D STMicroelectronics center, Crolles, France on FDSOI (Fully-depleted SOI) technology platform development and characterization. Since 2013 she is senior scientist and works as the project leader of the low temperature MOSFETs development for 3D sequential integration. She is the author and co-author of more than 130 publications in major conferences and journals and of more than 20 patents. She was the co-recipient of the Grand Prix du Général Ferrié in 2012 for her work on FDSOI.

3D integration (TechARENA)
CMOSIS nv Meynants, Guy
High Performance Global Shutter Image Sensors - Design and Applications
Meynants, Guy

Meynants, Guy
CTO
CMOSIS nv

Abstract
Many industrial, surveillance and scientific imaging applications require that the image sensor captures all pixels synchronously during the same exposure period. However, most CMOS image sensors use a rolling shutter to control exposure time, rather than the global shutter required for such applications. In the past, low noise global shutter capture was only possible with Interline Transfer CCD devices. But today several CMOS implementations exist with low noise global shutter, thanks to the combination of correlated double sampling and a global shutter pixel architecture with at least one in-pixel storage element. This presentation will summarize the various implementations of CMOS global shutter pixels, and explain the trade-offs that are made in the design of such pixels. Applications can drive the selection of a certain pixel architecture depending on the key parameters that are important for that application. Both charge-domain and voltage domain global shutter pixels will be discussed. Charge-domain global shutter pixels contain a memory element in which the photocharge can be stored after image capture, through a charge transfer and charge storage element. This is realized by an in-pixel 3-phase CCD or an equivalent implementation. This offers low noise readout, with noise levels which are theoretically not higher than a rolling shutter pixel. However, it is difficult to shield the storage area from parasitic light and from photocarriers that diffuse through the silicon. Some shielding techniques will be discussed, which improve the efficiency of the shutter. However, for better shutter efficiency, a voltage domain global shutter pixel can be used. Such pixel samples the signal after charge-to-voltage conversion on an in-pixel voltage sampling stage. Correlated double sampling can be realized if two in-pixel memory elements are foreseen. Pixel implementations and specifications of such pixels will also be discussed.

CV of presenting author
Guy Meynants is founder and CTO of CMOSIS, an independent supplier of CMOS image sensors for professional and industrial applications. Prior to founding CMOSIS in 2007, Guy worked at Imec and at FillFactory (later acquired by Cypress Semiconductor) on CMOS image sensors since 1994. His current research topics include smaller global shutter pixels, backside illumination and increased frame rate of CMOS image sensors. Guy Meynants obtained the Ph.D. Degree in Electronics in 1998 from the Catholic University of Leuven in 1998 and the M.SC. in Electrical Engineering in 1994 from the same University. He is the author of 50+ scientific publications and inventor of 15 patents.

Imaging Conference
CNSE Liehr, Michael
Scaling Options in Relation to 450mm
Liehr, Michael

Liehr, Michael
Executive VP for Innovation & Technology
CNSE

Abstract
The nanoelectronics industry has enjoyed decades of productivity gains driven by lithographic scaling. However, scaling slowed due to delays in the introduction of extreme ultraviolet (EUV). New materials were introduced which help to drive increases in performance or reductions in power consumption. However, to maintain the pace of die-level cost reduction, a different set of approaches have been proposed, only one of which is to use EUV. Two other approaches are being pursued, a transition in wafer size to 450mm and chip stacking. All three face the challenge of becoming cost-effective prior to wide-spread adoption. Lastly, the equipment industry is challenged to develop novel materials solutions as required for device scaling in parallel for 300mm and 450mm. The first generation of EUV production scanners are currently being delivered. One such scanner is being installed at CNSE with the goal of start of development activities in 2Q2014. The scanner will be for development of sub-10nm technology node CMOS, as well as to support advanced resist and mask development. Initial 193nm based directed self-assembly work in support of G450C has led to additional development work on 300mm in CNSE. Chip stacking technologies, either via interposers ("2.5D") or chip stacks ("3D"), are being developed by a wide range of R&D organizations and companies world-wide. No standard integration scheme has emerged yet due to constraints in yield management or limitations in equipment cost of ownership. However, this technology aims at current wafer sizes of 300mm, with a migration to 450mm gated primarily by the general pace of the 450mm transition. The timely availability of novel materials in conjunction with a manufacturable process is critical for continued scaling. The recent re-assessment by G450C of the likely CMOS node for the wafer transition opens up a new set of process options to evaluate, based on the industry introduction of materials needed for sub-10nm CMOS.

CV of presenting author
As CNSE Executive Vice President of Innovation and Technology, Michael Liehr focuses on the creation of new business opportunities and manages integrated industry-university consortia and public-private partnerships. He is also responsible for the effective and efficient operation of the CNSE core strategic semiconductor and packaging partnership engagements, including the IBM, GLOBALFOUNDRIES, SEMATECH, AMAT, TEL, and LAM partnerships. Prior to this assignment, he led the Global 450mm Consortium through the start-up phase as the General Manager. Dr. Liehr is further the Vice President for Research at the College of Nanoscale Science and Engineering in Albany, NY. Prior to joining CNSE, Dr. Liehr served as an IBM executive responsible for Worldwide Semiconductor Manufacturing Strategic Production Alliances for leading-edge semiconductor products.

450mm
Colibrys SA Rudolf, Felix
High Performance Low Volume MEMS for Aerospace Defense, Industrial and Energy Applications
Rudolf, Felix

Rudolf, Felix
CTO
Colibrys SA

Abstract
High performance MEMS are more and more replacing traditional electromechanical solutions in aerospace defense, energy and industrial markets. To reach the required high performance specific technologies for the MEMS components and the associated electronics are needed that are different from those used in automotive and consumer MEMS. High performance applications are often characterized by low quantities (few 1000 to >100'000 devices/y). Thus a single application can rarely fill an even small MEMS fab. IP issues and the cost associated with setting up a specific process make the use of foundries difficult. The Colibrys approach relies on few technology platforms for a range of standard and customized products for various applications having similar performance requirements. Colibrys has a well-established open loop accelerometer product line. A new generation of electronics and MEMS devices is allowing to push the performance further in terms of an order of magnitude gain in signal to noise, nonlinearity, and bias stability while improving robustness with respect to hard multiple shocks, radiation (up to 100 kRad) and temperature (175°C). With these improvements it is expected that current applications can be even better served and new applications such as down-hole drilling, structural health monitoring, and space will be addressed. With a new closed loop accelerometer platform, even higher performance can be reached. A first custom product is currently being developed with Sagem for navigation applications. This technology is expected to be expanded to earthquake monitoring and seismic imaging applications. Colibrys addresses the low volume dilemma of high performance applications by building product families based on few technologies to serve different low volume markets having similar requirements. Currently this strategy is limited to accelerometers but in the future this concept will be expanded to other MEMS based products

CV of presenting author
Felix Rudolf has started his career as a research scientist at the CenterElectronique Horloger (CEH) in Neuchâtel where he started to build a MEMS activity with a focus on watch related applications. In 1984 he joined the Swiss Center for Electronics and Microtechnology (CSEM) where he continued first as researcher and then as manager to drive the MEMS technology and product developments. In this role he developed the basic capacitive accelerometer technology and a number of other MEMS based sensors and actuators. In 2001 he was co-founder of Colibrys and he works at Colibrys since its creation as CTO.

International MEMS Industry Forum
Compugraphics International ltd McCallion, Michael
The Experts Behind the Mask
McCallion, Michael

McCallion, Michael
Business Development Manager
Compugraphics International ltd

Abstract
Compugraphics manufactures 3" to 32" photomasks and possess over 40 years' experience in the Semiconductor, Photonics and MEMS industries. The company is based in: Glenrothes; Scotland, Jena; Germany, Fremont California; USA and Austin Texas; USA. "The Experts Behind the Mask" is an introduction to Compugraphics which will showcase how the company partner with their clients to understand their requirements and ensure their needs are met. The presentation looks at Compugraphics approach to manufacturing high yield photomasks and provides insight into how the organisation is able to offer customers a high level of support. Michael McCallion, Compugraphics' Business Development Manager, will be explaining how the photomask manufacturer has evolved from a small business in Glenrothes, Scotland, to the multinational company it is today. Michael will analyse Compugraphics' approach to customer support and define what makes Compugraphics different from the competition. Compugraphics will be discussing how partnering with their clients has allowed the company to offer advice and help define clients' photomask requirements. The company boasts one of the highest levels of customer support in the photomask manufacturing industry. Their clients regularly rely on their expertise and Compugraphics would like to give insight into how they achieve this.

CV of presenting author
Compugraphics are experts in photomask design and manufacture. The company works closely with hundreds of semiconductor, optoelectronics and MEMS companies, and universities throughout Europe and the USA. Compugraphics manufactured their first photomask in 1970. The company now has over 40 years' experience and is based in: Glenrothes; Scotland, Jena; Germany, Fremont California; USA and Austin Texas; USA. Compugraphics takes pride in providing clients with not only photomask solutions but also offering an excellent level of customer support. The company achieve this through partnering with our clients to understand their needs and ensure the best solution is achieved based our extensive expertise. Compugraphics manufacture photomasks from sizes 3" to 32" and is the supplier of choice for 300mm TSVs. This includes working with company's who need help with their photomask design or helping companies which may not have the best technology get the most out of their tools. Compugraphics work with companies, who are looking to push the boundaries, however may not have the latest technology, to reach their full potential.

Exhibitor Presentations: MEMS (TechARENA)
Continental Automotive GmbH Feuerstein, Robert
Advanced Packages in Automotive Electronics - the necessary, beloved and hated Components
Feuerstein, Robert

Feuerstein, Robert
Director, Head of CEP MT
Continental Automotive GmbH

Abstract
The automotive industry is driven by innovation. New functions are often based on software or hardware that many of us know from smart phones, tablets or other consumer electronic products. The young generation wants to be online always and everywhere including during driving. This creates new challenges for ECUs (electronic control units) in cars, driven by multimedia and by software apps. The buzz word "always on" is not only a well-known slogan, but a concrete market with tremendous opportunities for suppliers. But in this market, two worlds come together, consumer electronics and automotive supplier. Both face the same challenges and risks. One of them is the integration of new and advanced packages into the very specific environment of a car and its ECUs. In this presentation Dr. Robert Feuerstein will give an insight into the approaches of one of the leading automotive supplier, German based company Continental. Automotive specific quality and reliability requirements are crucial when it comes to dealing with advanced packages. Their potentials from a design and R&D perspective have to be leveraged with potential obstacles from a manufacturing and manufacturability view. Furthermore expectations on both sides have to be understood and agreed. Both parties - supplier as well as the user of advanced packages - need to understand each other's requirements and expectations to be successful in this exciting market.

CV of presenting author
Born 1969, Diploma and Ph. D. in mechanical engineering at the University Erlangen, Germany. He started with Continental in 2001 as a technical consultant. Continental is a global leading automotive supplier, based in Hannover, Germany. At Continental, Dr. Robert Feuerstein had several positions in technical and management functions. Among them are head of production & engineering in a greenfield plant and later on focus factory manager. In his current position Dr. Robert Feuerstein is responsible for Manufacturing Technology within the CEP. The CEP - Central Electronic Plants - is a cross-divisional organization within the Automotive Group of Continental, including 30 electronics producing plants as well as dedicated central departments. His department CEP MT is responsible for global standardization of manufacturing processes and equipment, for manufacturability studies and for next generation material and component investigations related to electronics production.

Advanced Packaging Conference (APC)
Corial SAS Parrens, Pierre
Advances in plasma etch & deposition solutions for R&D and production
Parrens, Pierre

Parrens, Pierre
Director, Corial SAS
Corial SAS

Abstract
The drive for fast track development and implementation of new processes in production of MEMS, LED, and general compound semiconductor or optoelectronics processing calls for plasma processing tools with built in flexibility and reactor technology for easy scale up as production volumes or substrate sizes increase. Key features of Corial ICP-CVD, PECVD , RIE and ICP-RIE tools that deliver precise, repeatable processes using robust, low maintenance reactor designs will be explained. Easy handling of multiple substrate sizes & process chemistries with flexible software for process set up, monitoring & control simplifies the transition from R&D process development up to large reactor sizes for production.

CV of presenting author
Pierre Parrens is a physicist, graduating first from INSA Toulouse in 1972 and subsequently from the Joseph Fourier University in Grenoble "(Diploma in Nuclear Engineering 1973). He worked for 8 years at LETI as head of research in microlithography (e-beam, X-rays, optical) where he developed the technique of RIE plasma etching . In 1983, he founded and managed "Nextral" , specialists in the development and commercialisation of machines and processes for plasma deposition and etch. Since 2005 he has been Director of the company Corial. In 2003 he was awarded "Chaptal de la Physique", a national distinction given by the French Society for the Encouragement of Industry.

Fab productivity (TechARENA)
Corning Incorporated Enicks, Darwin
Thin Flexible Glass as an Enabling Material for Conformable, Flexible and Highly Integrated Electronics
Enicks, Darwin

Enicks, Darwin
Manager, Thin Films Research
Corning Incorporated

Abstract
There are important technical and economic challenges that must be addressed if conformable, flexible and highly integrated electronic devices are to be realized. However, just as the last 2 decades have witnessed a remarkable transformation in display technology, the next 2 decades may very well witness the advent and proliferation of flexible/conformable electronics. For certain, numerous barriers to industrialization must be overcome involving material development and integration, manufacturing, processing, and assembly. However, just as glass facilitated the revolution in flat panel technology, thin flexible "R2R compatible" glass is strategically positioned for the next revolution to occur. Glass is unique in that it can withstand a multitude of severe thermal, mechanical, and chemical processes while maintaining its performance enabling properties. The mechanical, chemical, and electro-optical properties of glass have been well characterized. When integrated with other materials, glass imparts a level of functionality, performance and reliability that is unachievable otherwise. This presentation will discuss thin flexible glass as a vital enabler to industrialization in this emerging segment of electronics.

CV of presenting author
Dr. Darwin Enicks currently holds the position of Manager, Thin Films Research with Corning Inc. at their Sullivan Park R&D Campus in Corning, NY Dr. Enicks leads a team of multi-disciplined scientists and engineers that focus on a broad range of thin-film related applications aimed at emerging technologies, new business development, and strategic growth. Prior to joining Corning, Dr. Enicks worked 15 years in the semiconductor industry with ATMEL Corporation where he held various engineering and management positions in Process Development and Integration, device design, Plasma and Wet Etch, Thin Film Deposition, and Ion Implant. Dr. Enicks has published 25 papers in journals and conferences, and currently holds 35 patents and/or patents pending related to thin film transistor applications, semiconductor processes & devices, silicon germanium devices, and SOI substrate technologies. Dr. Enicks received the BS degree in Mechanical Engineering from the University of Oklahoma, and the MS and PhD degrees in Electrical Engineering from the University of Colorado at Colorado Springs where he also taught semiconductor processes and devices.

Plastic Electronics - PE2014
Coventor Welham, Chris
Coventor Software Platform: Speed, Accuracy & Automation in MEMS Development
Welham, Chris

Welham, Chris
Worldwide Applications Engineering Manager
Coventor

Abstract
MEMS devices are finding their way into new consumer and industrial application areas and products every day, many of which are putting unprecedented requirements for functionality and performance on MEMS developers. Engineers have then an insatiable appetite for more speed, accuracy and automation in the design process, and those are the three key areas where Coventor is focusing by developing its MEMS Development Platform. The platform integrates a process modeling tool and MEMS design tools that allow accurate and fast MEMS+IC co-design (e.g. in Cadence Virtuoso), system verification in Mathworks/Simulink as well as manufacturing studies that would otherwise require long build and test cycles.

CV of presenting author
Chris Welham studied at Warwick University in the UK where he gained a BEng in Electronic Engineering in 1992 and a PhD in Engineering in 1996, which was focused on resonant pressure sensors. He then worked for Druck (now GE Druck) developing commercial resonant sensors and interface electronics. He moved to Coventor in 1999 as a Senior Application Engineer for Europe and now manages the Worldwide Application Engineering Group for MEMS CAD Tools from Coventor's Paris Headquarters

Exhibitor Presentations: MEMS (TechARENA)
CSEM S.A. Schaffer, Bernhard
High speed line and area image sensor for industrial and medical applications
Schaffer, Bernhard

Schaffer, Bernhard
Senior R&D Engineer
CSEM S.A.

Abstract
Line scan image sensors are widely used for industrial vision where the object moves perpendicularly to the line of pixels in the image sensor. Most high speed digital line scan sensors on today's market contain 1 or 2 lines x 1'024 to 4'096 pixels with a scan rates of up to 80'000lps (lines per second), though some newer devices have higher resolutions. These sensors have however two issues for colour imaging: first, they require 3 successive expositions with an alternating RGB light, which makes the illumination bulky, reduces the scan-rate by a factor of 3 and introduces colour smearing; and second, the sensitivity decreases when the resolution increases, because small pixels (for example 3.5µm in 16kpix sensors) cannot collect enough photons within the very short exposure time imposed by the high scan rate. To circumvent this, we have devised a somewhat different sensor, which contains 320 x 4(RGBW) lines of rather large but highly sensitive 24µm pixels with selectable small (50ke-) or large (250ke-) full wells. The sensor can acquire in a single shot 4 (WRGB) lines at an unprecedented rate of 4x 200'000lps. Examples of applications for such sensors are high-speed motion processes control, high performance colour sorting systems, surface inspection of various material / pieces, general purpose high-speed machine vision process control, etc. Whereas line image sensors are well adapted for applications in industrial environments, area high speed image sensors open the way to other kind of applications. We have developed high speed area image sensors able to acquire up to 4000 frames per second. Fabricated in a standard CMOS image sensor (CIS) process they use pinned photodiodes (PPD) in a 5T pixel with a 12 um pitch and column-based ADCs. They have been optimized for sensitivity and highest speed. One example of application is in an optical coherence tomography (OCT) system for real-time 3-D imaging of skin morphology.

CV of presenting author
Bernhard Schaffer got a Ms in Digital Signal Processing/Information Theory from ETHZ, Zürich, Switzerland in 1995. From 1995 to 1999 he was a test engineer at Philips Semiconductors, where he was involved in development and implementation of highly innovative test concepts for telecom IC's in order to optimize test & production for cost and quality. In 2000, he co-founded e-vision, where he headed the digital design group. In 2007 he moved to CSEM, where he is currently leading the development of high speed line and area image sensors.

Imaging Conference
CyberOptics Corporation Jackson, Allyn
Increasing Efficiency and Effectiveness of Processes in Lithography Related to Airborne Particle Measurement
Jackson, Allyn

Jackson, Allyn
Field Application Engineer
CyberOptics Corporation

Abstract
Stringent manufacturing requirements and the need to maximize both yields and tool uptimes for Photo Lithography Applications requires best-in-class practices for a contamination-free process environment. Quickly identifying when and where airborne particles originate and the source of the contamination is challenging with traditional surface scan wafer methods. Whether for equipment diagnostics, particle qualification or preventative maintenance, equipment engineers need to identify and troubleshoot airborne particle issues efficiently and effectively. Legacy methods are not real time, may cause long delays for results and are costly in terms of downtime if required to tear down the fab tool or run a series of test wafers. Legacy methods also lead to delays in equipment qualification, equipment release to production and maintenance cycles. CyberOptics will review the advantages of using the wireless wafer-like real-time particle counter method to locate and troubleshoot airborne particles with the ReticleSense Airborne Particle Sensor (APSR) in reticle environments. This solution can quickly check the dozens of particle sensitive chambers that otherwise might take days to check with multiple surface scan wafers. Along with the ParticleView software, particles are recorded to compare past to present as well as tool to tool. APSR follows the Reticle path and can travel to multiple areas of the tool to precisely and accurately detect where particles fall. APSR measurement devices are capable of detecting and counting particles as small as 100 nm (0.1 micron) and transferring accurate real-time data wirelessly to a PC with graphical and numerical analysis. Tests or calibrations can be conducted under production conditions for seamless ease-of-use. The APSR solution improves yields, optimizes maintenance and increases equipment uptime compared to legacy methods. Specific time and cost savings will highlighted.

CV of presenting author
Allyn Jackson is a Field Application Engineer for CyberOptics in the US and Europe. Allyn works closely with equipment and process engineers at major semiconductor fabs and equipment OEMs. His extensive expertise includes collaborating on evaluations and providing training and technical support for wireless semiconductor measurement devices that are used for chamber gapping, leveling, wafer handoff teaching, vibration and airborne particle measurement.

Lithography: What lithography options for tomorrow? (TechARENA)
D To top
D-SIMLAB Technologies GmbH Lendermann, Peter
Operations decision - support for productivity enhancement in a mature Fabs
Lendermann, Peter

Lendermann, Peter
Managing Director
D-SIMLAB Technologies GmbH

Abstract
In times of increasing competition, especially from Asia, semiconductor manufacturers in Europe have to continuously re-invent themselves with advanced products and new technologies to maintain their competitive edge. Over the years this has been leading to further increasing product mixes as well as decreasing volumes, a trend that is expected to continue in future. At the same time, it is equally important to manage and reduce cost effectively. The increased complexity in combination with fast changes in customer demand often leads to situations where it is not possible to pro-actively manage WIP waves on the production floor because they cannot be detected in advance as a result of short time horizons associated with dispatch rules and scheduling techniques which also are not able to sufficiently portray variability in the line. Moreover, the interdependency between capacity and cycle time also changes continuously, making it more and more difficult to understand capacity entitlements and commit order due-dates to increasingly demanding customers. At the same time, many fabs have already been in operation for decades and as such gone through many rounds of technology changes, modifications and upgrades, often resulting in rather heterogeneous IT infrastructure and data landscapes. This presentation will explain how in this kind of mature-fab environment dynamic decision support solutions for managing WIP flow that were developed in cooperation with Infineon Technologies can be implemented and maintained with reasonable effort and illustrate what kind of productivity enhancements can be achieved.

CV of presenting author
Peter Lendermann is the Co-Founder and CEO of D-SIMLAB Technologies, a Singapore-headquartered company providing simulation-based business analytics, decision support and optimisation solutions and services to Semiconductor Manufacturing, Aerospace and other asset-intensive industries. Peter has been engaged in the simulation community since the early 1990's when he worked in multinational research collaboration at the European Laboratory for Particle Physics CERN (Geneva, Switzerland) and Nagoya University (Japan). In 1996 he joined a German consulting firm where he was responsible for business process re-engineering projects with numerous process manufacturing, aviation and automotive clients in Europe, Canada and China. Since 2000 he led the simulation-related research activities at the Singapore Institute of Manufacturing Technology until spinning them off into D-SIMLAB Technologies in 2007. Peter holds a PhD in Applied High-Energy Physics from Humboldt-University in Berlin (Germany) and an MBA in International Economics and Management from SDA Bocconi in Milan (Italy).

18th Fab Managers Forum
Dainippon Screen Deutschland GmbH Goeke, Mark
Wafer Thinning Using a Versatile, State-of-the-Art Single Wafer Processor
Goeke, Mark

Goeke, Mark
Product Manager
Dainippon Screen Deutschland GmbH

Abstract
MEMS have been early recognized for being one of the most promising technologies for the 21st century. In fact, the MEMS market is growing rapidly, mainly caused by the intensive use of MEMS sensors and microphones in consumer mobile and handheld devices. However, also this market is suffering from continuous decline in prices and the industry is looking for ways how to lower manufacturing cost. It is forecasted, that MEMS manufacturing will migrate from 150mm or smaller wafer sizes to 200mm in the next couple of years, which will help reducing cost per good die. In addition, as the microelectronic packaging comprises a significant portion of overall cost per device, a lot of research is done in the field of packaging, looking for more efficient technologies like e.g. TSV interconnects. Consequently wafer thinning will play an even more important role in MEMS manufacturing, not only to answer needs for thinnner sensors or for capping sensitive device elements. Following these market trends, Dainippon Screen decided to offer the multi- purpose single wafer processor SU-2000 for wafer thinning. The SU-2000 belongs to Dainippon Screen´s "Frontier Project" product line up, providing solutions for manufacturing "green" devices. We will present Dainippon Screen´s single wafer processor SU-2000 and the related enhancements required for wafer thinning, including thin wafer handling and chucking. In addition we will discuss to which extend spin parameters are influencing process performance and show results for stress relief Silicon etch. Finally, an in-situ monitoring system will be presented, offering a controlled etch process by maintaining a constant etch amount by time based etch rate variation compensation.

CV of presenting author
Mark Goeke received his Master of Science in Photo Engineering from the University of Applied Science, Cologne in 1994. After holding various positions in lithography engineering he started working with Dainippon SCREEN Mfg.Co. in 1999. Here he moved to hold the position of the European Product Manager, responsible for technology and marketing for lithography and single wafer cleaning equipment. In this function he is also in charge to work on the introduction of SCREEN´s new 200mm single wafer cleaning tool.

Exhibitor Presentations: MEMS (TechARENA)
Dartmouth Fossum, Eric R.
CMOS Image Sensors: Now and Future
Fossum, Eric R.

Fossum, Eric R.
Professor
Dartmouth

Abstract
The talk will discuss the CMOS image sensor used in smart phone cameras, DLSRs, webcams, automotive imaging, medical imaging and numerous other applications. The operation of the CMOS image sensor will be addressed followed by special issues in fabrication. Trends in CMOS image sensors will described and the speakers' work in a possible 3rd generation image sensor technology - the Quanta Image Sensor - will wrap up the talk.

CV of presenting author
Prof. Fossum is the primary inventor of the CMOS image sensor used in billions of camera phones, DSLRs, and many other applications while at the NASA Jet Propulsion Laboratory at Caltech. He co-founded and led Photobit to further develop and commercialize the technology which was eventually acquired by Micron. Subsequently he was CEO of Siimpel which developed MEMS devices for autofocus function in camera phones. He joined the Dartmouth faculty in 2010. He holds over 150 U.S. patents and has published over 260 papers. He was inducted into the National Inventors Hall of Fame and the National Academy of Engineering, and is a Charter Fellow and Director of the National Academy of Inventors. He co-founded the International Image Sensor Society and served as its first President.

Imaging Conference
DAS Environmental Expert GmbH Cavaillier, Juliette
Reduced Utilities Consumption for Single Wafer Clean by using Point-of-Use Scrubber
Cavaillier, Juliette

Cavaillier, Juliette
Key Account Manager
DAS Environmental Expert GmbH

Abstract
In the field of waste gas treatment it is well-established practice to treat exhaust air from wet-chemical processes in semiconductor manufacturing with central wet-scrubbers or, if loaded with VOCs, with central thermal oxidizers. Nevertheless, with single-wafer wet-cleaning tools coming into mass production local wet-scrubbers have advantages. They replace switching boxes, which direct the exhaust air - depending on actual process conditions - to the different central systems. The challenge in the design of a local scrubber for this application was a trade-off to meet the specific restrictions concerning size, efficiency and pressure drop. The point-of-use concept by DAS Environmental Expert was successfully evaluated for this application. The advantages compared to the switching-box concept are smaller and less complex exhaust-piping, smaller load to central treatment systems, reduced loss of clean room air, smaller footprint and higher flexibility for process changes. Low emission concentrations are achieved and salt particle formation from acids and bases is eliminated. Such a concept is described in this presentation.

CV of presenting author
Juliette Cavaillier is Key Account Manager for the Gas Treatment Product Line at DAS Environmental Expert GmbH. She holds a degree in Economics and Business Administration from Paris-Dauphine University and Louis Pasteur (Strasbourg I) University. Juliette first joined DAS in 1996. She gathered many years of international sales and business development experience in the semiconductor industry as Sales Manager for customers in Europe, Asia and the U.S.

Fab productivity (TechARENA)
Debiotech SA Piveteau, Laurent-Dominique
What MEMS can bring to medical devices : selected examples
Piveteau, Laurent-Dominique

Piveteau, Laurent-Dominique
Chief Operating Officer
Debiotech SA

Abstract
MEMS are being used today in many industrial applications, from automotive to consumer electronics. In the field of medical devices their presence is increasing steadily. Debiotech is developing since nearly 25 years highly innovative medical devices and has been among the precursors in introducing MEMS into the medical arena. Through two examples, the JewelPUMP used for the treatment of diabetes and the DebioJect microneedles system for intradermal injection of vaccines, we will show how MEMS devices are generating new opportunities for the benefit of the patients.

CV of presenting author
Laurent-Dominique Piveteau is Chief Operating Officer at Debiotech SA. He holds a MSc from ETH Zurich (Switzerland), a PhD from the University of Fribourg (Switzerland) and an MBA from INSEAD in Singapore and Fontainebleau (France). After his PhD on ceramic bioactive coatings for medical implants, he has occupied different positions in R&D and business development. He was post-doctoral research fellow at MIT in Boston (USA), working on innovative targeted drug delivery systems in the group of Robert Langer. He was head of the scientific marketing for Evologic, a French biotechnology company specialized in controlled evolution. He was Industrial Liaison Officer at the Ecole Polytechnique Fédérale de Lausanne, in charge of establishing partnerships with industry for the School of Life Sciences. Laurent-Dominique is author and co-author of 19 scientific and business papers and 12 patent families.

Application driven technology: Nanoelectronic for Healthcare (TechARENA)
DECISION Coulon, Olivier
World Electronic Industries : 2012 - 2017
Coulon, Olivier

Coulon, Olivier
Consultant
DECISION

Abstract
Based on the latest forecasts on the electronics equipment carried out by DECISION every year since 2001, this presentation will give details on changing market trends, disruptive business models and actors' strategy in the electronics value chain till 2017. The forecasts cover all sectors: - Telecommunications - Computer - Consumer - electronics for Automotive, - electronics for Aerospace / Defense & Security - electronics for Industrial (including medical, energy, automation, etc) And the forecasts are crossed with all regions: - North America - Europe - China - Japan - Other Asia-Pacific - ROW

CV of presenting author
Olivier Coulon has been consultant and associate at DECISION since 2008. He holds a master's degree in industrial economics from the University of La Sorbonne. His professional experience started as economics assistant at STMicroelectronics in UK. Thanks to this market research and forecast background, he is now at DECISION consultant on aerospace & defense and electronics industries. He is more specially the project manager in charge of the World Electronics Industries forecast report 2012 - 2017, a multi-client survey updated yearly since 2001.

Market Briefing (TechARENA)
Department of Bioengineering and Robotics,Tohoku University Tanaka, Shuji
Tiny Tactile Sensor on Bus Network
Tanaka, Shuji

Tanaka, Shuji
Professor, Department of Bioengineering and Robotics and Director, Micro/Nano-Machining Research and Education Center, Tohoku University
Department of Bioengineering and Robotics,Tohoku University

Abstract
In coming super aging society, care robots will play important roles in home and hospitals. Our tactile sensor network provides whole body tactile sensation to such robots for collision detection and advanced man-robot interaction. The tactile sensor has communication function based on CSMA/CD (carrier sense multiple access/collision detection) scheme and directly attached onto a flexible bus network to digitally communicate with a host. A capacitive force sensor is integrated with our original ASIC (application specific integrated circuit) and packaged into a surface-mountable chip as small as 2.5 mm square at wafer level. We demonstrated 45 MHz bus communication, which allows data (85 bits) transfer at 1.6k samples/s from 256 sensors each on the same bus line. This work was performed with Toyota Motor Corporation and TOYOTA CENTRAL R&D Labs. Cyber world is rapidly glowing every day, becoming big "cloud" for us. Our real world is connected with "cloud" often wirelessly, and thus wireless devices need to continuously develop to support more communications in the limited bandwidth. TV white space cognitive radio is new technology to use unused digital TV channels for wireless communication. For this application, an acoustic wave filter is a key device, because to select the unused TV channels sharply without interfering TV broadcasts is the most critical requirement. We developed a tunable SAW (surface acoustic wave) filter, which could electrically change the bandwidth according to the number of available TV channels. The tuning function is realized by BST (barium strontium titanate) varactors, which are monolithically integrated with SAW resonators by laser-assisted film transfer technology. The tunable SAW filter was installed and successfully worked in a cognitive wireless LAN demo system based on the draft of IEEE 801.11af. This work was performed with Murata Mfg., NICT (National Institute of Information and Communications Technology) and Chiba University.

CV of presenting author
Professional carrier: 1996/4-1999/3 Research Fellow, The Japan Society for the Promotion of Science (JSPS) 1999/4-2001/3 Assistant Professor, Department of Mechatronics and Precision Engineering, Tohoku University 2001/4-2003/3 Lecturer, Department of Mechatronics and Precision Engineering, Tohoku University 2003/4-2013/7 Associate Professor, Department of Nanomechanics, Tohoku University 2004/1-2006/3 Fellow, Center for Research and Development Strategy, Japan Science and Technology Agency (JST) 2006/4-Present Selected Fellow, Center for Research and Development Strategy, Japan Science and Technology Agency (JST) 2010/9-2011/3 Guest Professor, Katholieke Universiteit Leuven, Belgium for collaboration with IMEC 2012/4-2014/3 Deputy Director, Micro/Nano-Machining Research and Education Center, Tohoku University 2013/8-Present Professor, Department of Bioengineering and Robotics, Tohoku University 2014/4-Present Director, Micro/Nano-Machining Research and Education Center, Tohoku University Research activity: Micro electro mechanical systems (MEMS), Piezoelectric and acoustic devices, Microfabrication technology, Integration and packaging technology Over 550 papers including 127 journal papers and 200 international conference papers 17 sections of book 10 patents and over 45 filed patents Over 90 invited talks and lectures in conferences and workshops 9 prizes including The Young Scientists' Prize, The Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology (2009) and German Innovation Award, Gottfried Wagener Prize (2012)

International MEMS Industry Forum
DISCO HI-TEC EUROPE GmbH Klug, Gerald
Solutions for thinning, dicing and packaging of power devices made of Si, Sapphire, SiC and GaN
Klug, Gerald

Klug, Gerald
Sales Manager
DISCO HI-TEC EUROPE GmbH

Abstract
Wafer thinning and dicing are essential processes for manufacturing semiconductor products. DISCO Corporation is a leading manufacturer for equipment and tools for wafer thinning and dicing. "Bringing science to comfortable living by Kiru (Dicing), Kezuru (Grinding) and Migaku (Polishing)" is DISCO's mission. By combining these three core technologies, DISCO provides total solutions to meet the more and more demanding requirements of the semiconductor industry in terms of manufacturing thin dies with high die-strengths and several new approaches for advanced packaging. When developing such processes, circumstances for the total process flow from front-end to packaging are actively taken into consideration. We are going to introduce various technologies for thinning, polishing and singulation (dicing) of wafers made of Si, SiC and GaN. Further the technologies of planarization for Cu-Cu bonding, planarization of tape and a process for via hole drilling for interconnecting dies to other dies or substrates are described.

CV of presenting author
Gerald Klug studied business engineering at the University of Siegen and graduated in 1998 as Dipl.-Wirt.-Ing., completing his thesis at BMW in Munich. He started his carrier as a designer of coil processing lines for nearly 3 years at a German machine manufacturing company, Heinrich Georg GmbH. At the end of 2000, he joined DISCO as a Sales Engineer for the area of Scandinavia. Meanwhile he has been almost 14 years at DISCO, currently Sales Manager in charge of major customers in Europe.

Exhibitor Presentations: Packaging (TechARENA)
Docea Power Blanc, Lionel
Explore, track and validate power and thermal targets from architecture specifications to validation
Blanc, Lionel

Blanc, Lionel
Principal Application Engineer
Docea Power

Abstract
Power aware design is more pervasive than ever. In the mobility segment, smart phones, tablets and notebook designs are differentiated by battery life, performance/functionality/features all within a challenging mechanical/thermodynamic form factor. Most designs are thermally limited for reliability/ergonomic and even safety reasons like in automotive. To design modern systems it is imperative to model and simulate the power and thermal behavior across a variety of usage scenarios. Design flows have been traditionally built to cover development and validation of functional requirements. Specifically at the architecture level where most of the power can be saved the industry is still in a handcrafted era dominated by more and more complex spreadsheets which are error prone to estimate power consumption while exploration capabilities are very limited. Docea Power provides innovative software solutions to model, simulate and explore various performance, power and thermal trade-offs of SoC and platform architectures. The presentation will highlight how the power and thermal architects now have the capability to forecast power/thermals earlier in the design phase, explore "what ifs" at system level and validate power/thermal management policies for more optimal hardware and software design over the spectrum of use.

CV of presenting author
Lionel has joined Docea Power in 2013, with a strong power management expertise acquired during his 10 years spent Texas Instruments (Nice) as a system architect and platform modeling technology leader within the OMAP business. Prior to joining TI, Lionel has been a co-founder and principal consultant Engineer at Esterel Technologies. Lionel has been granted a PhD in Computer Science from the University of Nice in 1999.

Low Power Conference
DuPont Teijin Films UK Ltd Rollins, Keith
The development of a manufacturing infrastructure for flexible and printed electronics
Rollins, Keith

Rollins, Keith
Chief Innovation & Marketing Officer
DuPont Teijin Films UK Ltd

Abstract
Manufacturing flexible electronics, which is the underpinning of wearable and disposable electronics, as well as many aspects of the Internet of Things (IOTs), will require a robust supply chain. In this presentation, Dr. Keith Rollins, Chairman of FlexTech Alliance and Chief Innovation and Marketing Officer of DuPont Teijin Films, will review and explain his perspective on the development of a manufacturing infrastructure for flexible, printed electronics. Dr. Rollins will illustrate the impact of industry consortium activity on key tools and materials, as well as describe how project demonstrators foster cooperation and progress across the manufacturing ecosystem. Successful manufacturing often proceeds from lab scale demonstration to pilot line and then volume production. FlexTech-funded R&D projects on printed batteries, sensors and scatterable media will be described by Dr. Rollins in this context. These projects highlight the pathway to integrating various flexible electronics components, which will enable smart packages, conformable displays, physiological monitors and other innovative end products. Dr. Rollins will also present a view of the flexible, printed electronics industry from the perspective of a substrate supplier into multiple applications. The presentation will touch upon the development of this industry over the last 15 years highlighting the focus areas over this period.

CV of presenting author
Keith Rollins is the Chief Innovation and Marketing Officer for DuPont Teijin Films, a joint venture between DuPont and Teijin Limited. He has over 30 years of experience in the chemicals industry with 25 years spent working for the DuPont and DuPont Teijin Films' polyester films businesses. Over the last few years, Dr. Rollins has focused on technology development, strategic planning and business development in the displays and flexible electronics industries. Currently, his focus is on the development and widespread use of the DuPont Teijin Films range of polyester PET and PEN materials in a wide range of applications including flexible displays and electronics applications. Dr. Rollins received his Bachelor of Technology degree with honors in Applied Chemistry in 1979 and his Doctorate in Catalysis Chemistry in 1985 from Brunel University in London, UK.

Plastic Electronics - PE2014
E To top
ECPE European Center for Power Electronics e.V. Harder, Thomas
Power Electronics Research in the European ECPE Network - from Power Devices to Systems
Harder, Thomas

Harder, Thomas
General Manager
ECPE European Center for Power Electronics e.V.

Abstract
ECPE European Center for Power Electronics is an industry-driven Research Network in the field of Power Electronics with about 150 member organisations in Europe, comprising Member companies and Competence Centres. The Network covers the power electronics value chain from the materials and components to the systems and applications. The presentation will address the following topics: - Energy saving potential with Power Electronics - ECPE Network activities including the SiC & GaN User Forum and the ECPE Roadmapping Programme - Overview and highlights from the Network-internal Joint Research Programme

CV of presenting author
Dipl.-Phys. Thomas Harder - Thomas Harder, 51 years old, diploma in physics from University of Kiel, Germany - more than 15 years experience in packaging & interconnection technologies for microsystems as well as multichip and power modules e.g. as a researcher in the Fraunhofer Institute for Silicon Technology (ISIT) in Itzehoe - since 2003 general manager of ECPE European Center for Power Electronics, the industry-driven Research Network headquartered in Nuremberg (ECPE e.V. and ECPE GmbH) - since 2006 also cluster manager of the Bavarian Power Electronics Cluster (beside the European Network management)

Power Electronics Conference
Edwards Cottle, Steve
450mm - it's more than abatement, it's the solution.
Cottle, Steve

Cottle, Steve
Senior Product Manager
Edwards

Abstract
Around the time that 450mm wafers enter mainstream semiconductor chip manufacturing, many new process innovations will be introduced, some of which will initially be rolled-out on 300mm wafers first. This paper looks at the implications of these new processes for exhaust gas treatment and the options for managing the challenges these present. The following will be considered: III-V transistor channels for high speed and low power - these require the use of flammable hydrogen, pyrophoric metalorganics and toxic hydride gases. 3D memory to increase the packing-density of memory chips - this involves the use of deep etching using potent global warming gases like SF6 which are chemically very stable. Use of rare-earth metals like cobalt for high-k metal gates - which are harmful if released into the environment. EUV lithography for producing extremely small features - this requires the use of large flows of flammable hydrogen

CV of presenting author
Steve Cottle received his BSc. in Chemistry at Bristol University and joined Edwards in 1992 as a chemist developing exhaust management solutions for the semiconductor industry. Followed by period working in the Edwards sales force and applications engineering, Steve is currently Senior Product Manager responsible for marketing of integrated vacuum and exhaust management systems for Edwards.

Fab productivity (TechARENA)
450mm
enablingMNT Netherlands van Heeren, Henne
Standards and design rules for microfluidic device manufacturing
van Heeren, Henne

van Heeren, Henne
CEO
enablingMNT Netherlands

Abstract
Microfluidics is a relative new technology to create miniature diagnostic and processing devices. There is a huge interest in this technology from medical and pharma companies. Over 600 companies worldwide are actively developing and using microfluidic components and devices. The potential market is large, those disposable diagnostic products are not only used in the medical and industrial laboratories, there is also a growing market for Point of Care / Point of Use microfluidic devices for health monitoring, food safety etc. One challenge is that the process of moving from a research prototype device to a production device takes too long and is too expensive. This is the case for a wide variety of materials and manufacturing processes. An important part of the challenge is that often developers are designing devices for the first time and stumble over multiple problems that an experienced designer might be able to avoid. The flip side of the same argument is that potential manufacturers are often frustrated when prototype designs presented to them which are difficult, inappropriate or even impossible to manufacture in large volumes at low cost. The recently created Design Guide for Microfluidic Device Manufacturing is a first attempt to overcome this problem. It contains design rules for manufacturing for the different industrial manufacturing technologies for glass and polymer based devices. Besides these design guides, this presentation will give an overview of relevant standardization discussions in microfluidics. As many of the microfluidic devices contain silicon biosensors, this work is also relevant for the semiconductor community. This work is based on the ongoing discussions in the Microfluidic Consortium and in the MFmanufacturing project.

CV of presenting author
After studying chemistry at the University of Utrecht, Henne worked at the University Delft, on rapid solidification of metals. Hereafter he joined Philips Electronics as a Development Engineer. He became responsible for the transfer and industrialisation of the thin film magnetic heads technology from the Philips Research facilities to the Business Unit. As a Waferfab production manager he extended the clean room, bought equipment, hired staff and transformed the production organisation from a low volume work shop to a three shift high volume activity. To expand the scope of the OnStream business, a strategy for expansion of activities in to the area of MST/MEMS was developed and executed by him. Several new processes and products were introduced into the organisation. As a Business Development Manager he changed the MST activity from a sideline show to the business core. Currently Henne is working in his own company (EnablingM3) as a consultant and market researcher in the field of Micro- and Nanotechnology. Henne has published over 60 articles and reviews about the development and industrialization of MEMS/MST products, including the review series about the MNT supply chain. He contributed two chapters to the Mancef roadmap on Micro and nanotechnologies, was a member of the core team that created the next Nexus market review on MST/MEMS. His principal activity is assisting start up organizations in the process of industrialization and commercialization.

International MEMS Industry Forum
Entegris GmbH Lundgren, Jorgen
Next Generation Contactless Shipping Solution for bumped wafers / glass substrates at 80um -1100um thickness
Lundgren, Jorgen

Lundgren, Jorgen
Senior Field Applications Engineer
Entegris GmbH

Abstract
Technology is quickly shifting to a higher overall percentage of thinner and more sensitive wafers. The main driver behind the thinner, more sensitive wafers is the consumer electronics industries need for smaller, higher performing and lower cost device configurations. These devices are used in advanced chip designs for 3D, 2.5D, SOC, MEMS, LED and power semiconductors. These new requirements along with 3D applications are pushing demand for more thin and ultrathin, lens or bumped semiconductor wafers. As wafer thickness decrease, manufacturing challenges arise. Ultrathin wafers are less stable and more vulnerable to stresses, and the die can be prone to breaking and warping. This presentation will be about the new 200mm contactless substrate shipper which helps address shipping requirements for, thin, 3D, lensed or bumped wafers. 200mm CL HWS eliminates the use of TYVEK separators and pink foam cushions and enhance automation compatibility. Presentation will also highlight 150mm and 300mm contactless Horizontal Wafer shipper and vital use of moisture barrier bags.

CV of presenting author
Jorgen Lundgren Entegris GmbH Dresden German. Senior Field Applications Engineer with electronic engineering degree from Sweden. Previously with a Swedish International company for 10 years in a world wide technical support function, whereof 5 of those based in Germany. Worked for Entegris for the last 17 years supporting the Semiconductor Industry in many different technical roles with focus on wafer and reticle handling, transport and contamination control. Heading up key projects such as the first 300mm fab in Dresden, European fab conversions, new product qualifications as well as individual customer development projects. Active contributor to Entegris/CEA-Leti collaboration FOUP polymer contamination/decontamination research Project. Partner in the Catrene 3D European wafer handling Project. Active SEMI participant.

450mm
3D integration (TechARENA)
EPFL Kis, Andras
Single-Layer MoS2 - 2D Devices, Circuits and Heterostructures
Kis, Andras

Kis, Andras
Professor
EPFL

Abstract
Single-layer molybdenum disulphide (MoS2), a direct-gap semiconductor is a typical example of new graphene-like materials that can be produced using the adhesive-tape based cleavage technique originally developed for graphene. The presence of a band gap in MoS2 allowed us to fabricate transistors that can be turned off and operate with negligible leakage currents [1]. Furthermore, our transistors can be used to build simple integrated circuits capable of performing logic operations and amplifying small signals [2] [3]. We have also successfully integrated graphene with MoS2 into heterostructures to form flash memory cells [5] that could be used to extend the scaling of this type of devices. Next, I will show photodetector devices based on MoS2 that have a sensitivity surpassing that of similar graphene devices by several orders of magnitude. Incorporating MoS2 in van der Waals heterostructures can open the way to an extremely diverse range of materials where different layers cam be mixed and matched to different functionalities. This is not only limited to two-dimensional materials: classical 3D semiconductors with saturated dangling bonds can also be integrated with 2D semiconductors, as I will show on the example of p-Si/n-MoS2 heterostructures that behave as diodes and can be used to achieve light emission and energy harvesting in a broad energy range [6]. [1] B. Radisavljevic et al., Nat. Nanotechnol. 6, 147 (2011). [2] B. Radisavljevic, M. B. Whitwick and A. Kis, ACS Nano 5, 9934 (2011). [3] B. Radisavljevic, M. B. Whitwick and A. Kis, Appl. Phys. Lett. 101, 043103 (2012). [4] B. Radisavljevic and A. Kis, Nat. Mater. 12, 815 (2013). [5] S. Bertolazzi, D. Krasnozhon and A. Kis, ACS Nano 7, 3246 (2013). [6] O. Lopez-Sanchez et al., ACS Nano (2014).

CV of presenting author
Prof. Andras Kis was born in 1975 in Croatia where he finished his undergraduate studies in physics in 1999 at the University of Zagreb. In 2000, he moved to Switzerland where he obtained his PhD (Physics) in 2003. In 2004 he was awarded the prestigious Latsis Universiy prize for his PhD work. From 2004 to 2007 he was a postdoctoral researcher at the University of California, Berkeley in the group of Prof. Zettl. At Berkeley he studied electrical and mechanical properties of carbon and boron nitride nanotubes and gained experience in microfabrication techniques at the Berkeley Microlab. In 2007 he returned to Switzerland and joined the Electrical Engineering Institute at EPFL and formed a research group as a tenure track Assistant Professor. Andras Kis and his group study electrical properties of low-dimensional materials such as 2d transition metal dichalcogenides. In 2009, Andras Kis was awarded the ERC starting grant (1.8 million Euros) for a research project (acronym FLATRONICS) in the area of electrical properties of dichalcogenide nanolayers. Profile Weblink: people.epfl.ch/andras.kis

2D (TechARENA)
EpiGaN nv Germain, Marianne
GaN-on-Si for power electronics: large diameter epiwafers
Germain, Marianne

Germain, Marianne
CEO
EpiGaN nv

Abstract
GaN-on-Si technology creates very high expectations for Power Electronics as to provide the next-generation of switching devices. Si switching components are reaching their intrinsic physical limitations, wide bandgap are required to further reduce the losses. The decisive advantage of GaN-on-Si technology to break the Si boundaries for efficient power conversion resides in its excellent and unique combination of performance (breakdown voltage/reduced leakage/lower conducting and switching losses) and cost-efficiency. This mainly thanks to the use of low cost substrates, available in large diameters. Based on more than 14 years of experience in the field of MOCVD-growth of III-Nitrides structures, EpiGaN has established in its dedicated clean-rooms, a unique manufacturing platform supplying GaN epitaxial wafers to the semiconductor industry. As a unique differentiator, the capping of the epiwafers with in-situ grown SiN, is proposed as the optimal surface passivation layer; it enables more robust and more reliable devices. The in-situ SiN passivation further uniquely provides the possibility for reducing transistor dimensions and thus increasing the number of chips per wafer. We'll review the key technical specifications for 650V node GaN-on-Si epiwafers suited for industrial use, today developed on 150mm wafer diameter, as well as latest developments on 200 mm.

CV of presenting author
Marianne Germain is co-founder and CEO of EpiGaN nv. She received in 1999 her PhD degree in Electrical Engineering from the University of Liege (BE), where she conducted research in close collaboration with RWTH Aachen, and as invited scientist in Purdue University (US) and Wuerzburg University (D). In 2001, she joined imec, an international microelectronic research center (Belgium), where she led the development of Gallium Nitride technology for high power/high frequency applications. Since 2004, she became Program Manager of the "Efficient Power/GaN" program, then, group leader of the "III-V systems" group (2007/2010). She also pursued training management course in Vlerick Management School (Gent) in 2008/2009. In May 2010, with her colleagues, Dr Joff Derluyn and Dr Stefan Degroote, she co-founded "EpiGaN", a clean-tech spin-off, manufacturing GaN epiwafers for electronics applications, where she acts as CEO and member of the Board of directors. She has authored and co-authored more than 100 international communications. She co-holds several patents in the field of GaN material and devices.

Power Electronics Conference
Ericsson Di Muro, Rodolfo
Business Growth with Energy Efficient Networks
Di Muro, Rodolfo

Di Muro, Rodolfo
Product Marketing Program Manager
Ericsson

Abstract
The seminar highlights the importance of energy efficiency for Mobile operators, focus on delivering better-performing network with good control of the total cost of ownership. Use case of real deployment with lower power consumption will be shared.

CV of presenting author
Rodolfo Di Muro has over 19 years of experience in Transmission and Telecommunication with know-how in packet and optical networks, radio network, value propositions, and business cases. Experienced and competent in operator business cases, working as Product Marketing Program Manager in Business Unit Networks in Ericsson, Stockholm (Sweden) since 2012. Responsible as product marketing to highlight product benefits and product positioning for all transmission products, working in Coventry (UK) and Genoa (Italy) since 2007. Product strategist with product road map responsibility since 2001 (in Marconi, Coventry, UK). Technology strategy with coordinating University Research projects across Europe, also from 2001. From idea to realization, Rodolfo has followed all the Implementation steps as design, software optimization, and in building prototype in optical amplifier (E-band) in the Nortel, Advanced Research Group in Harlow (UK) in 1997, and working as system network design for Nortel Transmission group (2000). Key professional achievements: Electronic degree (1992, Bologna University), PhD (Parma University 1995), MBA (Warwick University, 2008), IPR technical consultant, IEEE technical reviewer, filed 18 patents (IPRs), published 54 technical papers, Chairman for IET in Coventry and Warwick branch (2001).

Low Power Conference
European Commission van Puymbroeck, Willy
Power electronics key for European industry
van Puymbroeck, Willy

van Puymbroeck, Willy
Head of Unit A4 Components
European Commission

Abstract
In the More-than-Moore area, power electronics is increasingly important. It provides the necessary components and systems to interface between ICs and the real world, that is more and more electrified. The EU is strongly supporting Research and Innovation (R&I) in this area. An overview of recent projects funded through Framework Programme 7 will be given. These projects range from silicon to III-V based power ICs, including the related interconnect and packaging technologies and cover co-integration of power and low voltage ICs which is essential in many applications. Application areas range from automotive to electrical energy management, with focus on renewable energy management and solar energy conversion. The presentation will also give an overview of new funding opportunities under HORIZON 2020, including through ECSEL.

CV of presenting author
Willy holds a Ph.D in physics from the Universitaire Instelling Antwerpen. He joined the European Commission in the late 80's and throughout his twenty-five year career he has been responsible for research initiatives under different European Framework Programmes. He is the author of several articles in the domain of physics, information technology and integrated manufacturing. Since mid-2011 he is Head of Unit in DG INFSO Nanoelectronics. His responsibilities include Horizon 2020 preparation and stakeholder engagement in the field of electronic components, and the technical, scientific, financial and administrative monitoring of projects.

450mm
Power Electronics Conference
European Commission Reynaert, Philippe
A European Horizon on Organic and Large Area Electronics
Reynaert, Philippe

Reynaert, Philippe
Project officer
European Commission

Abstract
The EU strategy for organic and large area electronics under the Horizon 2020 ICT work programme will be presented. The growth potential and importance of organic electronics for various key industrial markets and societal challenges will be explained. An overview of the recently closed call 1 under ICT Horizon 2020 and relevant selected projects will be given. Potential innovation actions for future calls will be outlined.

CV of presenting author
Philippe Reynaert graduated as a civil engineer in Microelectronics in 1978 and obtained a Ph.D. in Applied Sciences in 1983 from the Katholieke Universiteit Leuven. From 1983 to 1996 he has been in the Electronics Design Automation and was Technical Director of European Development Center in Leuven, a development group of Mentor Graphics. In 1997, he joined the European Commission as project officer. He has been project officer in several units like Microelectronics, Embedded Systems and is now in the Photonics unit of the Directorate General Connect, where he is responsible for the research in the area of organic and large area electronics.

Plastic Electronics - PE2014
European Space Agency Meynart, Roland
Imaging Devices in Space
Meynart, Roland

Meynart, Roland
Head of EO instrument pre-development
European Space Agency

Abstract
Space missions use imaging devices since the beginning of the space exploration era. Imaging devices are implemented in instruments of space observatories, planetary exploration missions and Earth observation satellites used for research or monitoring. They are also used in monitoring cameras or star trackers onboard satellites. The spectral range covered by "optical" detectors is very broad, ranging from X-rays to far-InfraRed. The presentation will focus on space requirements and applications of detectors using silicium technology fully or partly, includinng Charge-Coupled Devices, CMOS imagers, hybrid IR detectors and microbolometer arrays. The presentation will illustrate the dichotomy in the imaging market, with the trends for small pixels with moderate performance for high-volume devices and the requirements for larger pixels of very demanding performance for space applications.

CV of presenting author
Roland Meynart is working in the Earth Observation Directorate of the European Space Agency, where is leading the pre-development of optical and microwave instruments for future space missions. His personal expertise principally lies in optical instrumentation and metrology, imaging spectroscopy, lidar systems, optical design and optical detection. He has been managing several developments of new optical detectors for Earth Observation from space.

Imaging Conference
EV Group Pabo, Eric
Temporary Wafer Bonding for Novel MEMS Manufacturing Processes and Products
Pabo, Eric

Pabo, Eric
Business Development Manager MEMS
EV Group

Abstract
Temporary wafer bonding is currently a hot topic for manufacturing three dimensional integrated circuits (3DICs) and advanced ICs for at several reasons. The first is that temporary wafer bonding allows the thinning of wafers to 50µm or less. These thinned wafers can have performance advantages as well as form factor advantages (thinner packages). Also, the ability to process wafers thinned to 50um or less is an enabling technology for many of the 3DIC process flows. However, until recently, temporary wafer bonding has not necessary for MEMS manufacturing ; the primary reason for this many MEMS products already use permanent wafer bonding and then thin one of the wafers after the permanent wafer bonding. In this case the thinned wafer is supported by the wafer to which it is permanently bonded. However, there are several applications of temporary wafer bonding for the manufacturing of novel MEMS devices that are emerging. The first is the use of temporary bonding does allow the thinning of one of the wafers prior to permanent bonding; this allows the backside of the thinned wafer to be bonded to the main wafer. The second is the use of temporary bonding to forma 'virtual' wafer which is populated with singulated die and then bonding the 'virtual' wafer to a normal wafer. This technique can decouple the geometry matching issues experienced with wafer to wafer bonding and partially decouple the yield of the two wafers. This 'virtual' wafer formed by temporarily bonding die to a carrier wafer can also be used when the coefficient of thermal expansion (CTE) mismatch between the two substrates is too great to allow traditional wafer to wafer bonding. In this presentation these applications of temporary wafer bonding for MEMS manufacturing will be presented and briefly reviewed.

CV of presenting author
Eric Pabo is the Worldwide Business Development Manager for MEMS for EV Group; in this role he is responsible for understanding the MEMS market including business, product and process issues. Prior to becoming the Business Development Manager for MEMS he was the Bonding Applications Engineer for EV Group in North America. He has been with EV Group for over 7 years, has 30 years of experience in electronics manufacturing, with 13 years of experience in wafer bonding and wafer level packaging at Hewlett Packard, Agilent Technologies and EV Group. Eric is a registered Professional Engineer in the state of Colorado, is a Six Sigma Black Belt and has a Mechanical Engineering Degree from Colorado State University. Eric occupies any spare time he may have with his hobby of photography.

International MEMS Industry Forum
EV Group E Thallner GmbH Wimplinger, Markus
Nanoimprint status for HVM
Wimplinger, Markus

Wimplinger, Markus
Corporate Technology Development & IP Director
EV Group E Thallner GmbH

Abstract
Nanoimprint Lithography (NIL) has for a long time been praised as the lithography technology of the future. Hopes were placed on NIL as a contender for Next Generation Lithography (NGL) for micro-electronics as a lower cost and less complex alternative to state-of-the-art microelectronics manufacturing technology and more recently EUV on one hand side and furthermore, very generically as a means for low cost, inexpensive patterning at the sub-100 nm-scale. Besides a few very clear target applications such as patterned media (for hard disk drives), the applications needing such patterning capabilities were usually described quite generically without clear boundaries between applications that were better served by conventional lithography and applications where NIL was the better answer. After more than a decade of research in the area of NIL, the technology has reached a level of maturity that enables first applications to transition to high volume manufacturing (HVM) utilizing NIL. This paper reviews the capabilities that NIL provides today and what applications are poised to benefit from those new capabilities. At the same time, the paper also will point out areas where further improvements can assist in enhancing the capabilities of NIL.

CV of presenting author
Markus Wimplinger is the Corporate Technology Development and IP Director at EVG. In this role, Markus oversees EV Group's global Process Engineering team. His further responsibilities include the management of R&D partnerships and contracts with 3rd party organizations such as companies or government related entities, as well as Intellectual Property affairs associated with EVG's process technology development efforts. Markus received his educational background in Electrical Engineering from HTL Braunau, Austria. He started with EV Group as a project manager at the company's headquarters in Austria in 2001 with focus on customer projects. In 2002, Mr. Wimplinger transitioned to EV Group North America in Tempe, Arizona, USA, where he served as the Director Technology North America till August 2006. Mr. Wimplinger's past work includes involvement in design, development, process technology and many other aspects of capital equipment production at both EV Group and at his former job with a capital equipment supplier for non-semiconductor related industries.

Application driven technology: Nanoelectronic for Healthcare (TechARENA)
Lithography: What lithography options for tomorrow? (TechARENA)
EV Group (EVG) Matthias, Thorsten
Hybrid wafer bonding for 3D IC
Matthias, Thorsten

Matthias, Thorsten
Business Development Director
EV Group (EVG)

Abstract
3D Integration by wafer-to-wafer integration offers significant technical advantages over die-to-wafer or die-to-die stacking. Wafer-to-wafer alignment can be performed with very high accuracy in the deep sub-micrometer range at throughputs compatible with high volume manufacturing. This enables the implementation of TSVs with small diameter and small pitch and thereby enables high density TSV architectures. Wafer thinning happens usually after permanent wafer bonding, which means that one wafer acts as permanent carrier for the other wafer. This allows wafer thicknesses of 10µm or even below, which in consequence allows "shallow TSVs" with a moderate aspect ratio. This allows reducing the manufacturing costs for the TSVs significantly. In addition most wafer-to-wafer stacking techniques do not require microbumps or bumps. This "bumpless stacking" allows to further reduce the cost of 3D IC. Hybrid wafer bonding allows to establish the mechanical joint as well as the electrical contact within one process. It is a room temperature bonding process, which enables highest alignment accuracy as there is no thermal expansion of the wafers. After this room temperature bonding the wafer stack needs to be annealed. However, between bonding and annealing the wafer stack can be inspected for defects and if necessary being reworked, which enables very high yields. In this talk recent developments of hybrid wafer bonding for 3D ICs will be presented.

CV of presenting author
Dr. Thorsten Matthias is director of business development at EV Group (EVG) where he is responsible for overseeing all aspects of EVG's worldwide business development. Specifically, he is focused on 3D integration, MEMS, LEDs and a number of emerging markets. Prior to this role, Matthias was director of technology of EV Group North America in Tempe, Arizona. He began his career with EVG in 2002 as the product manager for the SmartView wafer bonding alignment system. Matthias received his doctorate degree from Vienna University of Technology with a thesis in solid-state physics in 2002.

3D integration (TechARENA)
F To top
Fab Owners Association Guttadauro, LT
Change, Challenge and the Enduring Success of Cooperation
Guttadauro, LT

Guttadauro, LT
Executive Director
Fab Owners Association

Abstract
Cost is a key issue in any business environment and the most talked-about challenge facing the semiconductor industry. For integrated device manufacturers (IDMs), foundry-floor efficiencies and overall wafer costs are crucial because their business model is based on manufacturing excellence. Fabless companies address the issue by slicing silicon real estate and driving to smaller geometries, only to see the cost of more advanced processes rise. And, for some OEMs and fabless, off-shoring manufacturing to cheaper locations provides an answer. However, successful IDMs understand that the key to their manufacturing efficiencies is supplier cooperation. Suppliers give the objective view only outsiders can deliver. Cooperation makes it work. This presentation will discuss methods for identifying complementary strengths between IDM and supplier, defining problems, and formulating solutions. Case studies will be cited to demonstrate how a cooperative approach resulted in streamlined processes, improved factory floor efficiencies, and lower costs.

CV of presenting author
L.T. resides in Cupertino, California. He has had a continuous career in the sales, marketing and engineering of integrated circuits since the late 60's, with Transitron, IBM, Zilog, VLSI Technology, Amkor and lastly as worldwide VP of Product Marketing for Tower Semiconductor. L.T. founded the Fab Owners Association, a non-profit semiconductor industry trade association and FOA Purchasing Partners, Inc., a Group Purchasing Organization dedicated to lowering the cost of doing business for semiconductor manufacturers and suppliers to the industry. L.T has a BA degree in Business Administration and Management from Columbia Pacific University.

Secondary Equipment (TechARENA)
Facilities 450mm Consortium (F450C) Maynes, Adrian
Sustainability challenges in the 450mm technology node
Maynes, Adrian

Maynes, Adrian
F450C Program Manager
Facilities 450mm Consortium (F450C)

Abstract
The industry continues to make positive strides with the transition to the next generation 450mm wafer size. Experts in semiconductor development are striving to make 450mm a reality from a technical and manufacturing standpoint. Along with the increase in wafer size, the industry is closely examining impacts to the facility infrastructure, as merely scaling the manufacturing process is not a practical option. The size of the 450mm facility infrastructure and its associated utility consumption projections would simply exceed affordability and resource availability. The facility specialists involved in establishing and later implementing 450mm infrastructure requirements are facing the same degree of challenges as the IC and equipment manufacturers. Global 450 and Facility 450 Consortia leaders are collaborating closely with five of the industry's top IC manufacturers to bring their collective expertise to bear on the most pressing 450mm fab issues. They are also looking to apply lessons learned from 450mm development to existing 300mm wafer fabs. The consortia focus specifically on safety, cost, schedule, sustainability, and environmental footprint, with a goal of reducing the cost of production, increasing productivity for manufacturers, and improving the efficiency of utility consumption. This presentation will address these various infrastructure requirements and challenges for a more sustainable manufacturing process, including recommendations to optimize 300mm manufacturing. The session will be presented by Adrian Maynes, Program Manager of the Facilities 450mm Consortium (F450C).

CV of presenting author
Adrian Maynes was appointed as the M+W U.S., Inc. Program Manager for the Facility 450mm Consortium (F450C) in August of 2013. The Facilities 450mm Consortium (F450C) is a first-of-its-kind partnership at SUNY's College of Nanoscale Science and Engineering (CNSE) that is leading the global effort to design and build next-generation 450mm computer chip fabrication facilities. The collaboration includes 10 of the world's leading nano-electronics facility companies. Members of the F450C are working closely with the Global 450mm Consortium (G450C - Intel, GLOBALFOUNDRIES, IBM, TSMC, Samsung), to identify viable solutions required for 450mm high-volume facility construction, with initial focus areas to include reducing tool installation cost and duration, and improving facility sustainability. Prior to his appointment as Program Manager, Adrian ventured into the heart of Latin America's emerging economy to assemble a business strategy & market growth plan for Mexico. Centrally located to Mexico's business climate in the Federal District of Mexico City, the M+W Mexico Platform was formally established on October 12, 2011. Adrian worked closely with Executive Management to build a lean & local team while retrofitting & furnishing a start-of-the-art 8,000 square foot country headquarters. The Mexico Platform has exceeded $100M USD in sales, and currently employs 30 Mexican nationals. When M+W U.S., Inc. had their sights set on the growing photovoltaic industry in 2008, Adrian directed Business Development efforts to establish market presence. While cultivating business prospects with a skilled team of architects, engineers, and executive management, Adrian's team helped generate $155M in revenue. Upon joining M+W U.S., Inc. in 2006, Adrian served as the Platform Lead for Industrial Engineering, where he worked to engineer facility requirements for much of SUNY's initial semiconductor research & development space. He also helped create preliminary design for AMD's Fab4X - an effort that eventually morphed into the Global Foundries project in upstate NY.

450mm
Fairchild Akram, Salman
Progress in Low and Medium Voltage Power Semiconductor Devices.
Akram, Salman

Akram, Salman
VP R&D
Fairchild

Abstract
Trends to increase power density and performance in Low Voltage (LV) and Medium Voltage (MV) power semiconductors will continue into the foreseeable future with advances in silicon based device structures which remain the workhorse. Advances in superjunction MOSFET and shielded gate trench MOSFETS continue to reduce losses with improve switching performance. In the MV range new materials such as GaN will get introduced into the mainstream application over the next 3 years, driven by the recent progress in this area. These advances in silicon and GaN are being combined with advances in integrated power packaging solutions thereby enabling more efficient systems solutions. This talk will cover the progress in power semiconductor devices in these areas.

CV of presenting author
Salman (Sal) Akram is Vice President of Technology at Fairchild Semiconductor. Dr. Akram leads all semiconductor technology development efforts at the company, including High, Medium and Low Voltage discrete, Analog ICs, EDA and Wafer Level Packaging (WLP). Prior to joining Fairchild he held senior management positions at Philips and Maxim and served in a variety of engineering and management positions with Micron Technology with over 21 years of experience in the industry. Dr. Akram holds a Ph.D. in Electrical Engineering from Rensselaer (RPI). He is the recipient of numerous awards an inventor on over a hundred patents, and has published many papers.

Power Electronics Conference
Fairchild Semiconductor Neyer, Thomas
Neyer, Thomas

Neyer, Thomas
VP R&D
Fairchild Semiconductor

Biography
Dr. Thomas Neyer has received his PhD from University of Technology in Vienna and Cambridge University in 1995. He joined Siemens HL to work on mixed signal Product design and Test. Over the years Dr. Neyer worked on HV and BCD Technologies at Siemens and Infineon Technologies and in 2003 he was entrusted to setup Technology Centers of Competence in Malaysia and China. During the PowerFab start and ramp-up in Kulim, Malaysia in 2005, Dr Neyer was building and leading the Fab engineering and manufacturing teams. Subsequently he was appointed as EVP for R&D and Fab Operation of Grace Semiconductors in Shanghai, China - an advanced Foundry for differentiated, analog Technologies. In 2011, Fairchild Semiconductor founded a R&D center for High Voltage Technologies in Munich and assigned Dr Neyer to spearhead the effort and coordinate all related Silicon and SiC HV development activities covering device design, modeling and High Power package development.

Power Electronics Conference
Fairchild Semiconductor Hong, Steven
Smart Power Module and the Future
Hong, Steven

Hong, Steven
Sr. Manager, Application Engineering
Fairchild Semiconductor

Abstract
Electrical motors consume about 50% of electrical energy worldwide. Inverterization of motor drive has been the most crucial part in improving energy efficiency. Designing and manufacturing inverters has been getting easier thanks to the progress of intelligent power module which has internal gate driver with protection features. It reduces the total number of components required to build an inverter and improve the manufacturability significantly as a consequence. Intelligent power module from Fairchild, Smart Power Module (SPM), consists of three elements; power semiconductor, drive IC and package. In this article trends and the future of each element will be discussed. Power semiconductor typically includes IGBT, MOSFET, and diode. Wide band-gap devices are currently being evaluated and certainly will be used in the future. All the development effort has been focused on increasing current density without sacrificing ruggedness. Field-Stop Trench is the latest technology and has many generations. Short-circuit rating is typically required for motor drive application but at the cost of higher saturation voltage. As over-current protection circuit can sense the over-current situation and respond more quickly, short-circuit withstanding time required for IGBT reduced, and it results in more efficient and cost effective solution. Switching carrier frequency for PWM varies among different applications. There is a trade-off between Eoff and Vcesat, and Fairchild provides two types of SPM optimized for different application needs. MOSFET has inherent body-diode and can be more cost effective for small power motor drive below 200W. Most of planar MOSFET based module has 500V breakdown voltage rating because die size needs to become 57% larger to become 600V at the same Rdson. Super Junction MOSFET overcomes this limitation by adopting pillar structure. Increased current density on top of 600V rating makes Super Junction MOSFET based module very unique and attractive in some applications. Reverse-recovery characteristic is the most important aspect for power diode because of EMI concern together with turn-on switching loss of IGBT. Softness is equally important as reverse-recovery time and reverse-recovery current magnitude because it creates Ldi/dt voltage spikes associated with parasitic inductance of the PCB and the package of the module. High voltage gate drive IC (HVIC) played a significant role in proliferating intelligent power module and inverter solutions. It costs less and easier to put into modules than opto gate drivers, and has been widely adopted in below 7.5kW. Concerns on malfunction and ruggedness of HVIC are being solved. Electrical Over-Stress (EOS) mechanism has been well identified and the necessary measures are being taken. "Power electronics intelligence" will be implemented in HVIC to improve overall system performance. Package technology requires deep understandings of manufacturing capability and long history of experience. How to minimize the process variation and operational mistakes are key challenges. More robust yet cost effective packages are required. SPM products have various types of packages but mainly there are three groups; Direct Bonded Copper (DBC) package, package with ceramic substrate and lead-frame, and full molded package. PQFN packages are getting popular because of its flexibility and low thermal resistance. Lots of efforts are being made to figure out how to increase power capability and how to make manufacturing easier especially for soldering. SPM technology and its trends are reviewed in this article respectively in power semiconductor, drive IC and package point of view. Smart Power Module technology will increase its power capability in higher current and voltage ratings. More energy saving can be achieved through adopting inverter more easily with less cost. The benefit will be appreciated by our children.

CV of presenting author
Steven Hong joined Fairchild Semiconductor in 2011 as a principal application engineer. Currently he is a senior manager in motion control system team. Prior to joining Fairchild he worked for International Rectifier and LG Industrial Systems. He received a B.S. degree and a M.S. degree (specialized in power electronics) in electrical engineering from Seoul National University. He received M.B.A. degree from UCLA.

Power Electronics Conference
Fingerprint Cards AB Johannesson, Jan
Capacitive Fingerprint sensors capturing the mass market
Johannesson, Jan

Johannesson, Jan
Vice President, Strategic Planning and Portfolio Management
Fingerprint Cards AB

Abstract
Fingerprint scanning sensors are available based on several different technologies, suitable for specific market implementations and areas of application. During the last year the world has seen the true advent of mass market adaptation of capacitive Fingerprint scanners spurred by the adoption of the sensors in Smartphones. By the end of 2013, 22 new smartphones with fingerprint sensors have been launched globally. The novelty the sensors brought were highlighted to the broad consumer base by the launch of the Apple iPhone5s and later the Samsung GalaxyS5, both being iconic flagship models from the two major smartphone manufacturers. But why was the choice made to go for the capacitive sensors and rather not any of the other technologies such as optical, thermo or even ultrasonic? This paper discuss the underlying reasons why the capacitive sensing technology captured the lion part of the fingerprint mass market driven by Smartphones, Tablets and PC including some of the integration challenges for this type of sensors. Capacitive technology for fingerprint sensors proves to be the best optimal solution for the mass market of consumer devices with high requirements on power consumption, manufacturability and reliability. The integration of sensors in the devices pose challenges in terms of matching of colors and other aesthetics, resistance to wear and tear and extreme functional performance. Not to forget are the areas such as SW enhancements and advanced algorithms that completes the sensor system. Now when the mass market integration has started it is also important that the ecosystems around the services these sensors enables continues to grow and it will entail a multitude of areas of revenue.

CV of presenting author
Mr. Johannesson holds more than 20 years of experience in Senior Management positions in Marketing, Product & Portfolio management, Business management and Strategy. During his career he has been leading optimizations of product portfolios via advanced business planning, including new business models. His experience includes several different high tech industries beyond Biometrics; Semiconductors, Strategy consulting, Handsets, Fire & Security and Biomedical.

International MEMS Industry Forum
FlexTech Alliance Ciesinski, Michael
Ciesinski, Michael

Ciesinski, Michael
CEO
FlexTech Alliance

Biography
Michael Ciesinski is president of the FlexTech Alliance (www.flextech.org), appointed in April 1995. FlexTech (formerly U.S. Display Consortium - USDC) is a R&D consortium chartered with building the infrastructure for electronic display and flexible electronics manufacturing. FlexTech sponsors and conducts a multi-million dollar technology development program, as well as providing industry technical, financial and market information events. Since 1993, FlexTech has identified 150+projects and coordinated more than $150M in federal R&D directed to the flat panel display (FPD) and flexible electronics supply chain. Industry cost-share funds have exceeded 60% of the total FlexTech R&D program. The consortium has issued reports on a variety of topics including material handing in the FPD industry, near-to-the-eye (NTE) display products, roll-to-roll (R2R) manufacturing, and an analysis of the flexible lighting market. Most recently, FlexTech helped to create and now manages the Nano-Bio Manufacturing Consortium (www.nbmc.org). In addition to directing an aggressive R&D program, FlexTech sponsors capital investment forums with participation from small and mid-cap companies and start-up firms. FlexTech, under Michael Ciesinski's direction, manages a creative R&D program and delivers industry expertise with value-added information on market and technology trends. Ciesinski's prior executive positions include Semiconductor Equipment and Materials International (SEMI) and the New York State Labor-Management Committee. Michael Ciesinski is a graduate of the State University of New York at Albany. He is a member of the Board of Directors of FlexTech Alliance and a member of Dean's Advisory Council (Engineering) at the California Polytechnic State University at San Luis Obispo.

Plastic Electronics - PE2014
Fondazione Bruno Kessler Piemonte, Claudio
Development of Silicon Photomultipliers at FBK for nuclear medicine applications.
Piemonte, Claudio

Piemonte, Claudio
Chief Scientist
Fondazione Bruno Kessler

Abstract
High-energy radiation imaging in medical diagnostic systems, such as Positron Emission Tomography (PET) or Single Photon Emission Computed Tomography (SPECT), is usually based on scintillation detectors. The energetic particle is converted to light in the scintillation material, which is, in turn, detected by a highly-sensitive photo-sensor. The information to be reconstructed are: the interaction position, the energy of the radiation and, depending on the system, also the precise arrival time. Up to ten years ago, the only sensor able to provide the needed information was the Photo-Multiplier Tube (PMT). Recently, a new kind of detector have attracted a lot of attention in this field: the Silicon Photomultiplier (SiPM). It is a solid-state device composed by several hundreds Geiger-mode Avalanche Photodiodes per millimeter square. The advantages over the vacuum-based counterpart are: low operational voltage, compactness, insensitivity to magnetic fields, better detection efficiency and better interconnectivity to the electronics. Fondazione Bruno Kessler (FBK) (Trento, Italy) has been working on SiPMs for nuclear medicine since 2006.Two main development lines are active. The first one is on "analog" SiPMs, in which the sensor is manufactured on custom silicon technology aiming at the best performance in terms of both detection efficiency and noise. The second one is dedicated to "digital" SiPMs. In this case, the sensor is built on standard CMOS technology to include signal digitization on-board. In this presentation, we will give a comprehensive description of the main sensor properties and their functional performance coupled to scintillator crystals typically used in PET/SPECT. Finally, we will highlight pros and cons of the two approaches.

CV of presenting author
Claudio Piemonte was born in Udine, Italy, in 1972. He received the "Laurea" degree (M.S.) in Electronics Engineering from the University of Trieste, Italy, in 1997. From 1999 to 2002, he was with the National Institute for Nuclear Research (INFN), section of Trieste, Italy, as a fellow. In 2002 he joined Microsystems Area of the Fondazione Bruno Kessler (former ITC-irst), Trento, Italy, as a Research Associate. Since 2008 he has been coordinating the SRS group in FBK. His current research interests are focused on the development of silicon radiation detectors and low-level light sensors for high-energy physics experiments and nuclear medicine applications. Claudio Piemonte has co-authored more than 130 papers published in international journals and conference proceedings. In 2006 he received a "Certificate for outstanding contributions to the field of nuclear radiation measurements" from the Radiation Instrumentation Steering Committee of the IEEE Nuclear and Plasma Sciences Society. In 2010, he co-founded the spin-off company AdvanSiD for the commercialization of advanced silicon detectors. Currently he is member of the board and CTO of AdvanSiD.

Imaging Conference
Fraunhofer-Institute for Electronic Nano Systems ENAS Vogel, Martina
Vogel, Martina

Vogel, Martina
Officer of the director of the institute, head marketing/PR
Fraunhofer-Institute for Electronic Nano Systems ENAS

Biography
Martina Vogel officer of the director of Fraunhofer ENAS and manager marketing/PR. Martina Vogel studied physics at the Technische Universität Chemnitz, Germany. She obtained her PhD from the same university in 1994. From 1996 until 2001 she worked as project manager in the GPP Chemnitz mbH. From 2001 until 2006 Martina Vogel was responsible for quality assurance of memory products at ZMD. In 2006 she joined the Center for Microtechnologies of Technische University Chemnitz. Since 2009 she is with Fraunhofer ENAS and works as officer of the executive director and manager marketing/PR.

International MEMS Industry Forum
Fraunhofer ENAS Vogel, Dietmar
Advanced Stress Analysis on TSV Structures
Vogel, Dietmar

Vogel, Dietmar
Group Manager
Fraunhofer ENAS

Abstract
Knowledge and control of local stresses introduced by TSVs in advanced 3D integrated devices is a key to their proper functional behaviour as well as to their thermo-mechanical reliability. Moreover, the introduction of new low-K and ULK materials in BEoL stacks has led to concerns with respect to chip package interaction (CPI), but also related to the impact of TSVs on the BEoL stack. Finite element analysis (FEA), failure modelling and multi-failure analyses are powerful tools to incorporate reliability demands into the development and design of new devices and systems. However, results of complex FEA studies have to be cross-checked by measurements on real components. Past years, new stress measurement methods appeared and known techniques have been improved to provide access to local micro and nano scale stress areas, e.g. as introduced by TSVs. These methods can be used to validate FEA modelling, but as stand-alone technique they provide also a direct stress evaluation. In particular, they are suitable to acquire necessary input stress data for FEA. In the presented talk a particular variety of available stress measurement methods applied with respect to TSV and 3D integration problems is reviewed. Methods are benchmarked regarding their measurement capabilities, their specific suitability to analyse TSV caused stress fields and their readiness level for application in development environments. Among the compared methods are bow, microRaman, FIB based stress relief and x-ray / electron diffraction techniques. Application examples of stress analyses on TSV structures are presented to illustrate their use. The talk also highlights the new FIB based stress relief technique developed a few years ago as well as the goals of a currently launched EC funded project aiming at pre-standardization of measurement techniques and at interfaces to the design rule creation.

CV of presenting author
Dietmar Vogel received his PhD degree in physics in 1980. Since 1993 he has been working with the Fraunhofer Institutes IZM and ENAS. Currently, he is heading the research group "Characterization of micro and nano systems". He has published more than 150 papers in the field of mechanical reliability of electronics and MEMS devices. In 2005 he received the Joseph-von-Fraunhofer-Award in recognition of his achievement in the field of nanoscopic measurement techniques.

Advanced Packaging Conference (APC)
Fraunhofer FEP Hild, Olaf R.
Organic Electronics and Organic Photodiodes
Hild, Olaf R.

Hild, Olaf R.
Head of Department
Fraunhofer FEP

Abstract
Organic Photodiodes (OPD) are representing an interesting research topic for different disciplines: Right choice of materials will determine the spectral response, the device architecture will improve the sensitivity and sensing speed and the integration of OPD to different substrates and/or Systems enables new applications or the replacement of previous technologies. The presentation will give an introduction to OPD, their properties and typical device structures. Opportunities for applications like Color sensors or photoimager will be described.

CV of presenting author
Olaf R. Hild was born in Bremerhaven, Germany in 1971, He performed his Diploma and PhD thesis in Chemistry at University of Bremen. In 2004 he joined Fraunhofer IPMS, later Fraunhofer COMEDD for Research on OFET, OLED and OPV. Fraunhofer FEP merged with COMEDD in June 2014 and the research Topics were shifted towards research on µ-structured OLEDs for Microdisplays and organic photodiodes. Dr. Hild is leading the department Heterointegration CMOS+X and is deputy business unit manager of Microdisplays and Sensors.

Application driven technology: Nanoelectronic for Healthcare (TechARENA)
Fraunhofer IISB Pfitzner, Lothar
Pfitzner, Lothar

Pfitzner, Lothar
Vice President for External Strategic Affairs
Fraunhofer IISB

Biography
Lothar Pfitzner holds an M.S. (Dipl.-Ing.) degree in material science and Ph.D. (Dr.-Ing.) in electronics engineering, both from the University of Erlangen-Nuremberg. From 1976 to 1985 he worked as a lecturer at the Engineering Faculty at the University of Erlangen-Nuremberg. Since 1985 he was heading the department 'Semiconductor Manufacturing' of the Fraunhofer Institute of Integrated Systems and Device Technology (IISB) in Erlangen, performing research and development in the fields of processing technologies and equipment developments in Front-end-of-line and Back-end-of-line, and manufacturing optimization with some focus on advanced process control, metrology, integrated vacuum cluster tools and contamination control. 'In 2003, he was appointed "Professor for Micro-/Nanoelectronics. Since 2014, he is appointed Vice President for External Strategic Affairs of the Fraunhofer IISB.

450mm
Fraunhofer IISB Pfeffer, Markus
Semiconductor Equipment Assessment for Key Enabling Technologies (SEA4KET)
Pfeffer, Markus

Pfeffer, Markus
Group Manager
Fraunhofer IISB

Abstract
This talk gives an update on Semiconductor Equipment Assessment activities within the EU funded project SEA4KET. SEA4KET is the continuation of the European success story SEA, which began 1996 and lasted until 2004. In 2006, Fraunhofer IISB took over the role to drive Semiconductor Equipment Assessment forward by setting up several European Integrated Projects (IPs) taking the consequent step from equipment R&D to equipment assessment qualification. The recent one, SEA4KET concentrates on process and metrology systems for important enablers of future technologies: 450 mm wafer equipment but also SiC material and 3D processing. The talk will also report on AMC and contamination control activities as one specific part for 450 mm equipment assessment and will comment the refocusing on 300 mm aspects.

CV of presenting author
Dr. Markus Pfeffer- Group Manager Fraunhofer IISB Dr. Markus Pfeffer holds a diploma in Electrical Engineering and a PhD (Dr.-Ing.) with specialization in manufacturing optimization both from the University of Erlangen- Nuremberg. Since 2002 he is with Fraunhofer IISB in the department Semiconductor Manufacturing Equipment and Methods. He leads the group Manufacturing Control and is responsible for the analysis laboratory for micro and nano technology at the IISB. He has been engaged in the fields of equipment control, advanced process control, manufacturing optimization, analytical methods, equipment assessment and especially discrete event simulation. He was/is involved in several national and international cooperative R&D projects, e. g. FLYING WAFER, IMPROVE, EEMI450, EEM450PR, SEA-NET, SEAL and SEA4KET in different functions also as coordinator. He is member of the Steering Committee of the 450mm Equipment & Materials Initiative EEMI450 and since 2012 a member of the Factory Integration Group and Yield Enhancement Group of the ITRS.

450mm
Fraunhofer IISB Oechsner, Richard
Energy Efficiency in Semiconductor Manufacturing - Tool and Fab Aspects
Oechsner, Richard

Oechsner, Richard
Head Section Energy Technology
Fraunhofer IISB

Abstract
Due to continuous rising energy costs, energy efficiency in semiconductor manufacturing is a key issue. Main energy consumers are the fab infrastructure as well as tools in idle mode or running processes. In this presentation, both areas will be covered: how can tools run more efficient and what energy concepts are applicable and possible. An overview of the energy consumption and potential areas for energy reduction in a semiconductor manufacturing fab will be presented. Finally, examples for energy saving potentials on tools level (diffusion furnaces) and on fab level (waste gas usage) will be discussed.

CV of presenting author
Richard Öchsner received the M.S. (Dipl.-Ing.) degree in Electrical Engineering and the Dr.-Ing. degree from the University of Erlangen. Since 1991 he is with Fraunhofer IISB and working in the department Semiconductor Manufacturing Equipment and Methods as deputy head of department and leads the group Manufacturing Control and Productivity. He was engaged in the fields of semiconductor equipment assessment, contamination control in equip-ment, equipment control, integrated metrology, advanced process control, manufacturing methods, optimization, productivity and energy efficiency. Since 2012 he is head of section energy technology and working on energy concepts covering creation, storage, distribution and efficient use of energy. Richard Öchsner was/is involved in several European and national co-operative R&D projects also as coordinator. He was active in SEMI standardization and a member of the Factory Integration TWG within ITRS (International Technology Roadmap for Semiconductors).

Fab productivity (TechARENA)
Fraunhofer IOF Brückner, Andreas
Multi aperture camera module with 720p-resolution using microoptics
Brückner, Andreas

Brückner, Andreas
Senior Scientist
Fraunhofer IOF

Abstract
The slim design of portable electronic devices (e.g. smartphones) causes a constant need for miniaturized camera systems. This trend pushes the shrinking of opto-electronic, electronic and optical components. While opto- and micro-electronics have made tremendous progress, the technology for the miniaturization of optics still struggles to keep up. The demand for a higher image resolution and large aperture of the lens (both driven by shrinking pixel size) conflict with the need for a short focal length and a simple, compact design. These conditions impose high demands on the fabrication technology, especially when considering that it has to meet one-hundreds of a percent relative accuracy. Wafer-level optics (WLO) fabrication for camera lenses is a promising candidate, enabling high-volume production with low cost. However, the resolution that is currently available with WLO-technology is limited to 1MP per lens due to material and process control issues. We propose an alternative lens design using a multi aperture scheme which captures different portions of the field of view (FOV) within separated optical channels. The different partial images are joined digitally to reconstruct an image of the full FOV. The segmentation partly decouples the tradeoff between focal length and size of the FOV. The advantage is twofold: A short total track length is created and the microlenses are easier to manufacture. The realization of such multi aperture objectives is feasible with adapted micro-fabrication techniques such as diamond milling, step and repeat micro-imprinting and UV-molding. Alignment and assembly are partially carried out on wafer-level. The optical design, technological realization and test of such a multi aperture system is discussed for the example of a 2mm-thin camera module with 720p resolution.

CV of presenting author
Andreas Brückner graduated in physics from the Friedrich-Schiller-University Jena in 2006. Since then, he has been working as a researcher & optical engineer in the department of Microoptical Systems at the Fraunhofer Institute for Applied Optics and Precision Engineering (IOF) in Jena. In 2011, he received his PhD degree in applied optics from the Friedrich-Schiller-University Jena. He has been leading and participating in several research projects focusing on the miniaturization of imaging optics by applying multi-aperture architectures.

Imaging Conference
Fraunhofer IPA Meßmer, Felix
Mobile robots in industrial service robotic applications
Meßmer, Felix

Meßmer, Felix
Expert Mobile Robotics
Fraunhofer IPA

Abstract
Today's mobile robots are used in more and more industrial applications. With their flexibility and the latest technical developments in robotics research, mobile robots can also be interesting for applications in semiconductor fabs. As an introduction into the topic the talk will cover the following topics: * Overview of the service robotic market * Concepts and functionalities of mobile robots * Application of mobile robots for handling and logistics * Synergies with the semiconductor industry

CV of presenting author
Felix Meßmer is a research associate in the field of motion planning, motion control and mobile manipulation. After receiving his diploma in Computer Science at the Karlsruhe Institute of Technology KIT, he joined the Robot and Assistive Systems department at Fraunhofer IPA in 2011. His research interests are the design and implementation of control algorithms for complex service robot systems as well as the deployment of mobile manipulation strategies for both service and industrial robot applications. Moreover he is involved in multiple national and European research projects at Fraunhofer IPA.

18th Fab Managers Forum
Fraunhofer IZM Tekin, Tolga
Hetero Silicon Photonics: Components, systems, packaging and beyond
Tekin, Tolga

Tekin, Tolga
Group Manager Photonic & Plasmonic Systems
Fraunhofer IZM

Abstract
A key bottleneck to the realization of high-performance microelectronic systems, including SiP, is the lack of low-latency, high-bandwidth, and high density off-chip interconnects. Some of the challenges in achieving high-bandwidth chip-to-chip communication using electrical interconnects include the high losses in the substrate dielectric, reflections and impedance discontinuities, and susceptibility to crosstalk. Obviously, the motivation for the use of photonics to overcome these challenges and leverage low-latency and high-bandwidth communication. The objective is to develop a CMOS compatible underlying technology to enable next generation photonic layer within the 3D SiP towards converged microsystems. Targeting high-performance, low-cost, low-energy and small-size components across the entire interconnect hierarchy level can definitely not rely on a single technology platform. Objective: - Create the optimal synergies between different technologies streamlining their deployment towards Tb/s-scale, high-performance, low-cost and low-energy optical interconnect components and sub-systems - "Mix & Match" components / building blocks to deliver the optimal heterogeneous integration and to align their synergistic deployment towards the specific needs of individual functions Advanced packaging technologies will improve future systems: - Packaging determines functionality, cost and reliability of future systems. - System-in-Package is the way for future subsystems. - Future systems are very high complex systems and contain different physical functions. Therefore modularity in heterogeneous integration is required. - Future systems combine optical and ultra high frequency functions. They contain antennas, batteries, sensors, optical components, and microelectronic devices. With this a large variety of materials will be applied. For all these components a common smart support substrate such as 'Silicon' will be of importance for future systems.

CV of presenting author
Tolga Tekin received his Ph.D. degree from Electrical Engineering and Computer Science at TU Berlin in 2004. He was a Research Scientist with the Optical Signal Processing Department, Fraunhofer HHI, where he was engaged in advanced research on optical signal processing, 3R-regeneration, all-optical switching, clock recovery, and integrated optics. He was a Postdoctoral Researcher on components for O-CDMA and terabit routers with the University of California. He worked at Teles AG on phased-array antennas and components for skyDSL. At the Fraunhofer IZM, he led projects on optical interconnects and Si photonics packaging. He is Senior Scientific Assistant and Research Coordinator at the Research Center of Microperipheric Technologies, TUB, engaged in microsystems, photonic-integrated system-in-package, photonic interconnects, and 3-D heterogeneous integration research activities. He is Photonic & Plasmonic Systems Group Manager in System Integration & Interconnection Technologies Department, Fraunhofer IZM. Tolga Tekin is Senior Member of IEEE.

Silicon Photonics (TechARENA)
Fraunhofer IZM Lang, Klaus-Dieter
Technologies and applications for thin flexible and stretchable electronics
Lang, Klaus-Dieter

Lang, Klaus-Dieter
Director
Fraunhofer IZM

Abstract
A broad spectrum of different technologies is currently developed and investigated in order to realize wearable electronics. This comprises miniaturized flexible modules, e.g. in wrist bands and as ultrathin electronic tatoos, as well as smart textiles. All these new products need flexibility and in many cases also stretchability in order to achieve a higher level of freedom of design. A very promising and highly manufacturable novel approach has been the implementation of conventional PCB processes for thermoplastic polyurethane (TPU) to form stretchable circuit boards (SCB). The principles for stretchable electronics were already developed in the collaborative research project "STELLA" funded by the EU. In other projects (E.g. place IT, PASTA), the materials and processes have been optimized and characterized. New areas of application, e.g. in the automotive sector, have been opened up. Different applications from medical to fashion and design have been realized to show the potential of the SCB technology. Nonetheless integration of rigid electronic components in stretchable surfaces is still difficult due to the mismatch of mechanical properties which affects the reliability, in particular at the transitions between elastic, flexible and rigid parts of the system. To create reliable textile systems while maintaining the desired textile properties, using stretchable circuits has a great potential in addition to the use of conductive yarns. The SCB technology is suitable especially for large area applications such as textile displays and sensor arrays, which are distributed all over the body in technical textiles. It is a clear advantage for manufacturing that textile and electronics manufacturing are performed separately and the two technologies are merged at the end of the integration process. For non-textile applications the thermoplasticity of the base material can be used to create 3-dimensional electronic modules by thermoforming after planar assembly.

CV of presenting author
Prof. Lang studied Electrical Engineering from 1976 to 1981 at Humboldt University in Berlin. He received his M.S. Equivalent Diploma (Metallization Layers on GaAs) in 1981. During his employment at Humboldt University from 1981 to 1991 he worked in the research fields of microelectronic assembly, packaging and quality assurance. In 1985 and 1989 he got his two Doctor Degrees (Wire Bonding of Multilayers and Quality Assurance in Assembly Processes). In 1991 he joined the company SLV Hannover to build up a department for microelectronic and optic components manufacturing. In 1993 he became Section Manager for Chip Interconnections at Fraunhofer IZM (Institute for Reliability and Microintegration Berlin). From 1995 to 2000 he has been Director's personal assistant at IZM, also responsible for Marketing and Public Relations. From 2001 to 2005 he coordinated the Branch Lab "Microsystem Engineering" in Berlin-Adlershof and from 2003 to 2005 he headed the Department "Photonic and Power System Assembly". From March 1th 2006 to March 31th 2010 he was Deputy Director of Fraunhofer IZM. Since February 1th 2011 he is Director of the institute and responsible for the chair "Nano Inter-connect Technologies" at Technical University Berlin. Prof. Lang is member of numerous scientific boards and conference committees. Examples are the SEMI Award Committee, the Scientific Advisory Board of EURIPIDES, the Executive Board of VDE-GMM and the scientific chair of the Conference "Technologies of Printed Circuit Boards" and "SMT/HYBRID/PACKAGING". He is member of DVS, IEEE, IMAPS and he plays an active role in the international packaging community (e.g. German Chapter Chair IEEE-CPMT) as well as in the field of conference organization (e.g. Committee member SSI). He is the author and co-author of 3 books and more than 230 publications in the field of wire bonding, microelectronic packaging, microsystems technologies, chip on board and others.

Plastic Electronics - PE2014
Freescale Osajda, Marc
Sensor for Internet of Things: challenge and opportunity
Osajda, Marc

Osajda, Marc
EMEA Business Development Manager, MEMS Sensors
Freescale

Abstract
Applications based on cloud and deeply embedded computing capabilities are paramount for Internet of Things . Sensors are a primary source data for Internet of things and its information can be either extracted raw or in an intelligent way. This paper will provide an overview of applications requirement impacting sensor ecosystem - from the product & technology trend to sensor fusion and software architecture trends. Product trend : Sensor are more pervasive and capable of measuring a wider range of physical stimulus: Motion (accelerometer, gyroscope, magnetometer), Environmental (humidity, temperature, source, proximity), Wireless (WiFi, BT, etc), chemical (Carbon monoxyde), Radiation, specific DNA sensors (pathogens), infrared,... We will cover the technology & challenges related to this different type of sensors. Sensor fusion & software Architecture trend : Sensor fusion is a topic growing of importance even if, sometimes, the definition of sensor fusion might seem unclear. Indeed, different sensor fusion concept will be reviewed, at physical, system and software levels, with discussion about their main advantages and drawbacks. Some of the features will include integration, data communication, and power consumption. Hence, sensor and MEMS fusion at package level and silicon level will be presented, sensor fusion using software and system approaches will also be reviewed together with a mixed approach. Finally, use cases and explanations will provide elements of answers to better understand the role of sensor fusion and stand alone sensors in the context of IoT applications

CV of presenting author
Marc Osajda is Business Development Manager for Freescale Automotive Sensors product lines. Prior to this position, M. Osajda was the Director of Freescale Pressure Sensor business unit, with a specific focus on Automotive pressure sensors such as Tire Pressure Monitoring sensors Prior to this position, M. Osajda was in charge of Freescale Global Automotive Strategy. Responsible for market analysis and strategy formulation. M. Osajda joined Motorola's European semiconductor business in 1992 as a design engineer. From 1995 to 2004, M. Osajda was involved with the European Automotive industry, respectively as application engineer for sensors, marketing engineer for sensors and program manager for automotive products M. Osajda is now working for Freescale Semiconductors in Munich, Germany Marc Osajda holds a Master Degree in mechanics and electronics from the French "Ecole Nationale Superieure d'Arts et Métiers" (ENSAM).

International MEMS Industry Forum
FRT GmbH Marheineke, Bastian
Multi Sensor Metrology for Control of MEMS Production
Marheineke, Bastian

Marheineke, Bastian
Head of Sales
FRT GmbH

Abstract
In this paper we present a surface metrology system developed to fulfill the needs of MEMS industry moving from lab to production. With this system wafers, chips, PCB or any other device surfaces can be investigated and paremeters such as TTV, bow or warp can be determined in fully automated routines. In addition high resolution topography, roughness or profiles for the whole surface can be analyzed. Last but not least thin film thickness can be measured. An outstanding innovation is the modular multi-sensor technology. Various optical sensors can be combined for fast and accurate measurements of different features on the same wafer. A complete vision setup is integrated to get the ability to fully automated surface inspection in production environments: utilizing a high resolution, telecentric CCD camera in combination with pattern recognition software enables the system to detect and identify reference marks and to perform Routine, repetitive measurements on predefined dies and measurement areas in full automation. To fulfill frontend needs, the metrology system can be integrated to a fully equipped EFEM with wafer handling robot, pre alignment, OCR, fan Units and FOUP or SMIF ports. Completed are these systems by a professional SECS/GEM integration.Different metrology tasks, like e.g. the fully automated measurement of topography data and film thickness data on MEMS wafers can be performed with more than 25 wafers per hour throughput. Results from fully automated measurements of various Parameters such as total thickness Variation TTV, bow, warp, roughness, film thickness, step height, pitch, profile, contour, edge structures, trenches, topography, geometry, coplanarity, critical dimensions and angles will be presented. In addition new challenges like TSV measurement, nano metrology and multi-layer thickness measurement are covered.

CV of presenting author
Bastian Marheineke graduated in Physics at RWTH Aachen and received his PhD from University of Ulm, working on MOCVD and PVD technologies for deposition of compound semiconductors. In 1998 he joined AIXTRON AG, Aachen Germany. Until end of 2013 he filled various management positions in Sales and Business Development for deposition tools for compound and organic semiconductors. In 2006 Bastian was appointed Vice President Sales, being in charge of global sales and service organisation. Beginning 2014 Bastian joined FRT GmbH, Bergisch Gladbach, Germany as Head of Sales.

Exhibitor Presentations: MEMS (TechARENA)
Fujifilm Electronic Materials N.V. Vanclooster, Stefan
Novel low temperature cure polyimide materials for enhanced package reliability in advanced packages like fan-in & fan-out CSP and 3D/IC TSV packages.
Vanclooster, Stefan

Vanclooster, Stefan
Business Development Manager, Polyimides & Formulated products
Fujifilm Electronic Materials N.V.

Abstract
Advanced IC packaging concepts like fine pitch copper pillar flip chip BGA or fan-in & fan-out Chip Scale Packages (CSP) require enhanced packaging materials to cope with the increasing expectations regarding functionality, package sizes, power dissipation, yield, cost and package reliability. As the material properties of the buffercoat and RDL dielectric show a huge impact on final package reliability, novel RDL dielectric materials with enhanced material properties need to be developed by material suppliers. The typical process temperature limitations in the fan-in and fan-out wafer level packaging process flows in combination with the more demanding package reliability requirements like drop test, Thermal Cycling Test (TCT) and Temperature Humidity Bias test (THB) make it even more challenging to develop these new RDL dielectrics.Polyimides are widely used in the microelectronic industry because of their very high reliability performance, but the imidization reaction of the polyimide precursor typically requires cure temperatures above 300°C. The main challenge for material suppliers is to lower the polyimide cure temperature while maintaining the well-known polyimide material properties. In this talk, we will present the advantages of low temperature cure polyimide materials for enhanced package reliability in advanced 3D and wafer level packages (WLP). The key material properties of buffercoat and/or RDL dielectric layers for advanced package reliability will be discussed. We will present the chemical compatibility of the low temperature cure polyimides typically needed in WLP processes. Further the importance of the main mechanical properties for the enhanced reliability performance will be addressed together with the electrical properties at frequencies up to 100 GHz which is currently requested for RF applications. Finally, the environmental, health and safety (EHS) aspects of a polyimide material in the final package will be discussed.

CV of presenting author
Stefan Vanclooster is Business Development Manager Polyimides and Formulated Products at FujiFilm Electronic Materials (FFEM), located in Belgium. Stefan is responsible for the development of photosensitive polymers used as buffercoat layer and/or ReDistribution Layer (RDL) Dielectrics typically used in Flip-chip, Wafer Level Packaging or 3D/IC TSV packaging. He also manages the Fujifilm formulated product roadmap for the 3D packaging area. Prior to joining Fujifilm, Stefan was working as a process engineer in Alcatel Mietec, now On Semi (Belgium). Stefan received a Master's degree in Chemical Engineering at the University of Ghent and a Master's degree in Polymer and Composite Materials at the University of Leuven.

3D integration (TechARENA)
G To top
G450C Robertson, Frank
Continued Progress on 450mm Development
Robertson, Frank

Robertson, Frank
VP/GM
G450C

Abstract
The Global 450mm Consortium (G450C), a public/private program based at the College of Nanoscale Science and Engineering (CNSE) in Albany, NY, is preparing for the 450mm transition with a broad set of enabling and collaborative efforts spanning the semiconductor industry worldwide. Good progress continues in the core program with comprehensive test wafer process and metrology capability available on excellent quality (SEMI M1!) silicon wafers, a significant tool set already installed at the CNSE cleanroom or available at Supplier sites and many further additions this year and next. As part of enabling tools for demonstration, G450C member company assignees and Supplier technical staff are working together to move the current capability to more advanced technology and readiness for High Volume Manufacturing. G450C updated its Equipment Performance Metrics to Sub-10nm this year with broad industry input and is currently working on the first demonstrations using globally-aligned standard methods. These demos include two tools being coordinated between G450C and the ENIAC SEA4KET program (one in Albany and one in Leuven). A key element of the program strategy over the 450mm development period is to identify and demonstrate elements beyond developing and demonstrating tools that might improve productivity, address technology needs or enhance industry sustainability regardless of wafer size. The intersection of EHS objectives, efficient facilities systems and control of wafer ambient conditions for future technology needs has been rich ground for multiple collaborations between G450C, the Facilities 450mm Consortium (F450C), SEMI members and EEMI450/Metro450 participants. Our presentation will provide an update on progress in the tool set, wafer quality, test wafer support capability and the global collaborative efforts to address key topics with benefit beyond 450mm.

CV of presenting author
Frank Robertson is Vice President and General Manager for Industry Interface and Program Strategy at the Global 450mm Consortium (G450C) based at the College of Nanoscale Science and Engineering in Albany, New York. His objective is to drive a cost-effective transition to the larger wafer size by ensuring support capabilities are available to enable Supplier development and by pursuing pre-competitive collaboration opportunities with Suppliers and other organizations. Before being assigned by Intel to G450C Frank managed External Programs for its Technology and Manufacturing Group, helping consortia, universities and government agencies keep the R&D pipeline filled with promising new work. Prior to joining Intel in 2000 Frank was Vice President and Chief Operating Officer of SEMATECH. In that role, he led the technology development programs and the consortium's transformation into an international organization. Frank was Vice President and General Manager of the International 300mm Initiative from 1995-1998. This global cooperative effort resulted in major industry cost savings through standardization and by leading equipment development for that wafer size transition. He spent a couple of decades before that in wafer fabs and started a company developing optical storage media to make use of his chemistry degree.

450mm
Galaxy Semiconductor Leblond, Nicolas
Multi-Variate Part-Average-Testing Analysis to Improve Outlier Identification
Leblond, Nicolas

Leblond, Nicolas
Senior Application Engineer
Galaxy Semiconductor

Abstract
Microelectronic products produced in a semiconductor fab may be valid in the sense that all their parameters are within the required specification limits but still unreliable in the sense that they have a high probability of early life failure. Such early life failures can be extremely prejudicial in application domains like the automotive sector, for instance. To screen unreliable products, test programs that were initially designed to check that a product's parameters are within the specification limits, are extended to make specific measurements under varying working conditions. Although this helps to increase product reliability, some early life failures continue to occur. At this point, software techniques are used to improve reliability without increasing the cost of test too much. Basically, such technique called Part Average Testing (PAT), aims to identify valid but unreliable products before they are shipped to the customer by scrutinizing the available test results. Typical PAT methods used to find outliers consider one test at a time and detect devices whose results (for this test) fall out of a given distribution. In this work, we consider by contrast parametric methods that operate on the joint results of a group of tests. This "multi-variate" approach is based on the computation of the Mahalanobis Distance that may denote a violation of the correlation pattern between multiple tests results. The paper gives details about this proposed technique to improve the traditional way of doing PAT, details the software options that were implemented to ease the flow for the end user, it reports on experimental results that were obtained using this technique and finally provides recommendations about possible improvements based on group of parameters which are not linearly correlated. This paper is coauthored with Jochen Matthias Stefan Product Engineer at Micronas GmbH and Jérôme Kodjabachian Senior Software Developer at Galaxy

CV of presenting author
Nicolas Leblond graduated from INP Grenoble with an Engineering degree, specialized in Microelectronics. He has been working for more than 10 years in the software and semiconductor industries, in startups as well as in larger companies like Xilinx, where he played various roles from design, quality and test to applications.

16th European Manufacturing Test Conference (EMTC)
Georg Fischer Piping Systems Mueller, Hanspeter
Upsizing Wafer Fab UPW Needs to 450mm Demands
Mueller, Hanspeter

Mueller, Hanspeter
Microelectronics Manager
Georg Fischer Piping Systems

Abstract
The long awaited upsizing of wafer fab utilities to accommodate 450mm wafer production has begun. Fabs are either built, under construction, in modification or planned on future roadmaps. Major stakeholders such as Intel, GLOBALFOUNDRIES, Samsung and TSMC continue to push equipment suppliers to these inevitable larger wafers. Outfitting a new fab (Greenfield) or providing a future expansion (Brownfield) with the various assortment of UPW piping systems needed to make all the twists and turns from the Central Utility Building to the wet bench offers polymer component suppliers a unique challenge. The authors wish to present a segmented approach for 450mm piping designs that can get the end-user/installer from the largest pipe necessary to tool hook-up and put some light on the completely controlled manufacturing processes required to meet the increasing specification demands for UPW used in the next generation Fabs.

CV of presenting author
Working in the Microelectronics Industry since 1994 in various functions: PRESENT PROFESSION Microelectronics Segment Management Georg Fischer Piping Systems Ltd. Schaffhausen, CH EDUCATION University Karlsruhe (TH) Karlsruhe, Germany Mechanical Engineering Degree: Dipl.-Ing. Mechanical Engineering RELATED EXPERIENCE 2004-Present: Market Manager Microelectronics Outstanding achievements: - Sustain product development for 450mm PVDF High Purity Piping System and introduction to the market: 2002-2004: SCP Germany Pliezhausen, GE Engineering Manager Automated Wet Processing Tools 1998-2002: CFM/Mattson Technology Pliezhausen, GE Manager Mechanical Engineering AWP Outstanding achievements: 1994-1998: STEAG MicroTech Pliezhausen, GE Designer/Team Leader Mechanical Engineering

450mm
GLOBALFOUNDRIES Horstmann, Manfred
From 32/28nm partial depleted volume production to energy efficient fully depleted solutions in 28nm and beyond
Horstmann, Manfred

Horstmann, Manfred
Director Products & Integration
GLOBALFOUNDRIES

Abstract
Within the semiconductor industry, pure leading edge foundries serve a special mission by delivering state-of-the-art competitive logic performance with a strong focus on system-on-chip (SoC). Therefore they have to support a broad portfolio of different technology options on each node and GLOBALFOUNDRIES is an industry leader by representing this particular business model. GLOBALFOUNDRIES has a long time experience in leading-edge semiconductor manufacturing and technology capabilities one particular on silicon on insulator (SOI) based high performance microprocessors. To achieve the "high performance per watt" figure of merit technology elements like partial depleted (PD) -SOI, strained-Si, ultra low K BEOL and HKMG is needed together with an efficient multiple core- and power-efficient design. Those technology elements were developed and optimized for multiple generations beginning from an 180nm down to the 28nm technology node which runs currently in high volume production. In particular the 28nm node should remain for a long time at the sweet spot in Foundry Industry for yield, performance and cost. This node will be the basis to add technology features like (Flash, HV, MEMS etc.) but also will enable new innovations like fully depleted devices, reducing power consumption even further. Therefore, extreme thin (ET) planer SOI devices with back bias options (BB) and their potential application in 28/20nm will be presented. Being a planar device, ET-SOI devices allow the continuation of previous nodes manufacturing and design experience. Vt-tunability and low GIDL currents are a clear advantage of ET-SOI BB devices for SoC applications, too. The presentation will conclude with an outlook on nodes beyond 20nm with 3d FINFET concepts.

CV of presenting author
Manfred Horstmann serves as Director at GLOBALFOUNDRIES in Dresden and is since 2009 responsible for 28nm technology development and subsequent production ramp. Manfred currently leads since b/o 2014 the Product & Integration organization with focus on 28nm volume production and yield improvement for multiple customers. Prior to this role he served 18 years in various leadership positions in research and development (R&D) at AMD and GLOBALFOUNDRIES. Before 2009 Manfred Horstmann focused as engineering senior manager at AMD in Dresden on definition, development and technology transfer of high-speed CMOS transistors from 0.35um down to the 28nm technology node. Center of this work was the development of high speed CMOS transistors and innovative integration concepts using a collaborative approach with technology development partners. Manfred Horstmann received his diploma degree in physics (MSc) from Technical University Aachen in 1994. From 1994 to 1996 he continued his work as member of technical stuff of Research Center Juelich. 1996 he received the PhD degree from Technical University Aachen on sub-100nm high speed compound semiconductors, awarded with the Borcher's medal of Technical University Aachen. He holds over 130 patents and authored or co-authored over 150 technical contributions. He was elected from the board of directors from Research Center Juelich as member of the scientific advisory board for their solid states institutes as well as serves since 2010 as advisor for the Helmholtz association in Germany.

Low Power Conference
GlobalSensing Technologies Brousse, Olivier
Artificial Neuro-Inspired Embedded Vision
Brousse, Olivier

Brousse, Olivier
R&D officer
GlobalSensing Technologies

Abstract
Global Sensing Technologies (GST), leader of NeuroSmart, aims at becoming the European leader of very high performance data processing solutions based on neural network technology. After many years of academic research works done by the co-founder of GST, expert of this disruptive ICT, many developments have been performed by GST since its creation in 2011, and some relevant R&D partnerships have been built with one of the world reference of this scientific area (CEA List) to design a very innovative architecture of neural processor and obviously users of the technology (Sagem,Vitec...) to design specific adaptations to different applications requirements. The current trend in embedded systems is to make them surrounding the users, providing services thanks to a knowledge of their environment. These self-awareness and context-awareness are provided by numerous sensors, from different types. The main objective is to make systems smart. Additionally, the needed applications that use these information are based on different recognition processing, sometimes not easy to formalize with conventional algorithms. Processing chains using neural-based algorithms are promising approaches for solving these kinds of issues. In the presentation GST shows how we envisage and promotes Neuro-inspired embedded vision systems.

CV of presenting author
Olivier Brousse received the PHD in Micro-electronics and automatic systems from Montpellier2 University, and information systems form Lausanne University in 2010. From 2009 to 2012, he was Research Engineer in the LEAD laboratory in University of Burgundy (Dijon) were he assisted the Prof Paindavoine in its researches in the field of neuro-Insipred systems. He is now the R&D officer of GlobalSensing Technologies since September 2012. He manages the R&D team to perform research and development in neuro-inspired electronics architectures. He obviously also continue to conduct researches in the field and to give lectures at the University of Burgundy. His main research topics concerns architectures for image acquisition and real time image processing. This with a strong orientation toward neuro-inspired and visual system inspired solutions. Some Publications in the topics of the project : O. Brousse, M. Paindavoine, and C. Gamrat, "Toward nano-device image processing : a neuro-inspired learning approach," June 2010. O. Brousse, M. Paindavoine, and C. Gamrat, "Neuro-inspired learning of low-level image processing tasks for implementation based on nano-devices," in DTIS 2010 conference proceeding, 2010. M. Paindavoine, A. Ngoua, O. Brousse, and C. Clerc, "Smart image sensor with adaptive correction of brightness," in International Conference SPIE Electronic Imaging, San Francisco - USA, January 2012.

Imaging Conference
H To top
Hamamatsu Photonics France Roux, Jean
Xray & high energy imaging : applied technologies oriented perspective
Roux, Jean

Roux, Jean
Business Developper Sales&Marketing
Hamamatsu Photonics France

Abstract
Imaging being our core business we will cover advance imaging applications and the related technologies involved. Outstanding design technics and original developments will be highlighted aiming in a constant improvement research for reliability and effective performances. Finally , this talk will address routes for opening innovation and sustaining future businesses

CV of presenting author
Master degree in Optoelectronics ( University of Saint-Etienne - 1987) MSe Management Technology Innovation ( Grenoble Ecole Management - 2013 ) Started as a sales engineer for the french company Jobin-Yvon Instruments S.A. (1987-1989) and for Princeton Applied Research (USA)(1989-1991) developping sales activities in the research domain ( Spectroscopy and Signal processing ). Joined Hamamatsu Photonics France in 1991 ( Business Developpement ) dealing with Imaging and High speed photonics research applications . In 2002, openned Hamamatsu Office in Grenoble (Meylan) to sustain business development of large equipments produced by the Systems Division of Hamamatsu Japan, adressing semiconductors manufacturers ( foundries ) and R&D process developments, especially in the reliability , failure analysis and novel technology bricks domains. Expertise in customer relationships and innovation management , with a daily involvement with the main actors of the semiconductors industry in France and several European countries , including also nanotechnologies R&D fields and new organic applications domains.

Imaging Conference
HAP GmbH Dresden Stegemann, Burkhard
Real HEROs: Latest developments for Automated Carrier Handling
Stegemann, Burkhard

Stegemann, Burkhard
Sales Director
HAP GmbH Dresden

Abstract
The big majority of European chip fabs still uses wafer sizes of 200mm and smaller. And most of these fabs are older and grew over many years. Hence, automation, especially hardware automation, is a challenging task, as this was not planed when these fabs were built. HAP GmbH Dresden has been offering Automated Carrier Handling (ACH) solutions for many years. The current standard system is the HAP-HERO®, which is rail based and requires straight lines of loadports. As many of the European fabs do not have these straight lines of equipment, but small and warped aisles, it is essential to offer a manoeuvrable, small system that can cope with this infrastructure. Therefore, HAP is developing the HAP-HERO® FAB. This new system can move and navigate freely in the cleanroom. No rail or cable are needed, anymore. The required minimum aisle width is less than 1 meter. Its on-board 6-axes robot can load all kind of carriers and the system could be used for the local transport as well.

CV of presenting author
Born in 1969, Burkhard Stegemann studied Physical Technics at the FH Aachen and completed his final year at Coventry University, resulting in a BSc in Applied Physics and a Dipl.-Ing. (FH) in Physikalische Technik. In 1996 he joined Carl Zeiss in Jena in the department of microscopic wafer inspection. After two years in R&D/ application, he changed to product and project management. As part of the acquisition of the Zeiss business field "optical wafer inspection" by HSEB Dresden GmbH in 2004, Burkhard Stegemann became sales director and in 2007 managing director of HSEB. His responsibilities were sales and service. In May 2014 he started at HAP GmbH Dresden as sales director.

Fab productivity (TechARENA)
Heliatek GmbH Le Seguillon, Thibaud
Le Seguillon, Thibaud

Le Seguillon, Thibaud
CEO
Heliatek GmbH

Biography
Based in Dresden, Germany, Thibaud Le Séguillon is CEO of Heliatek Gmbh, a high-technology start-up in organic solar film. Heliatek is a global leader in OPV technology utilizing nano molecules. The light-weight, flexible and possibly semi-transparent next generation solar films provide clean solar energy wherever it's needed. Mr. Le Séguillon was previously based in Shanghai, China, where he was the President of Parlex Corporation, a 1500-employee, $100MM worldwide leader in flexible interconnect that is part of the Johnson Electric Group. The company had engineering centers in the US and Europe, 2 manufacturing sites in the US, and a manufacturing site in China and in the UK. Previously, Mr. Le Séguillon was Vice President of a Business Unit of Parlex. Prior to working in China, Mr. Le Séguillon worked in Boston, MA, for Parlex Corporation (NASDAQ: PRLX) as Vice President of Operations with factories in the US and Mexico. Earlier in his career, Mr. Le Séguillon was General Manager at Axon' Cable Inc., a subsidiary of Axon' Cable SA, based in Chicago, IL. Mr. Le Séguillon is Conseiller du Commerce Exterieur de la France. He holds an MBA in International Business from Neoma Business School and a Master of Science in Engineering from ESEO.

Plastic Electronics - PE2014
Henkel Electronic Materials Josso, Stieven
Silver Sintering
Josso, Stieven

Josso, Stieven
Technical Service Engineer
Henkel Electronic Materials

Abstract
Abstract Looking to the trend on power modules, there is an increased need on higher operation temperatures and higher current densities. These trends are effecting all components used inside the powder module: on the IGBT/FET side there is a trend from Si to low band gap materials like SiC and GaN. It is also demonstrated that Cu wire bonds can replace the state-of-the-art Al wire bonds to enhance power cycle life time. For the chip interconnect materials, standard SAC solder can be replace by Pb-free solder solutions (AuSn alloys, SnSb-alloys, Bi-alloys, Zn-alloys) but all have their disadvantages (brittleness, cost,...). As such Ag sinter materials, diffusion solder or transient liquid phase sintering TLPS can be possible alternatives. In this paper Ag sintering is presented as a high reliable solution for IGBT die interconnection on DBC substrates to cope with the high temperature requirements. Material properties such as die shear adhesion, peel adhesion and porosity are presented and linked to its performance. Ways of tuning these properties by using adequate raw materials in the sinter formulation as well as selection of the sinter conditions (pressure or no pressure during the sinter process) are presented. From the paper it will be clear that with a silver sinter material much higher adhesion strengths can be obtained compared to a soldered interconnection and that life time can be enhanced at high temperatures.

CV of presenting author
Stieven Josso studied Industrial Engineering Chemistry at GroepT in Leuven (Belgium). He started working for AkzoNobel NV in Kalmthout (Belgium) in 2003 as a R&D chemist on Coatings and Inks. He became Lab manager and global R&d projects coordinator in 2006. From 2010 on he was a global colour project/process manager. He joined Henkel Electronics Materials (Westerlo, Belgium) in February 2014 as a Technical Service Engineer for the product lines of Underfill, Silver Sintering and Thermal Interface materials.

Advanced Packaging Conference (APC)
Heptagon Advanced MicroOptics Rossi, Markus
Wafer-level technologies for imaging and sensing applications in mobile devices
Rossi, Markus

Rossi, Markus
Chief Innovation Officer
Heptagon Advanced MicroOptics

Abstract
Mobile devices are benefiting from unprecedented innovations that deliver myriad benefits, including: radically reduced height and total footprint, enhanced image quality with computational cameras that incorporate greater depth sensing with video-stream information, and even entirely new use cases for smart phones, tablets, wearables and other mobile consumer electronics. Advanced packaging concepts, including those originally developed for wafer-level optics products, are helping to address these continually increasing requirements of performance, functionality and miniaturization for mobile devices' opto-electronic sensor modules, with very flexible, efficient and highly precise packaging processes. Wafer-level processes are ultra high precision and can achieve very tight tolerances - which in turn can enable entirely new functions. In addition, wafer-level processes enable a higher level of integration achieved through miniaturization, which are especially useful for devices with multi-sensing applications (such as medical devices), which may require proximity, temperature, gesture or humidity sensing capabilities in a single device with a limited footprint. The presentation will include an overview of the basic process steps, typical tolerances and features of the Wafer-Level Integration (WLI) technology and processes, as applied to the production of a wide range of miniature opto-electronic modules for mobile devices - including light sensors, computational camera modules, illumination modules, MEMS devices, infrared beam shaping, and supporting gesture control in natural user interfaces, including time of flight systems and other motion sensing applications. Examples of these various applications - such as small footprint camera modules, computational imaging arrays that enable both HD video and high-quality depth maps, dual LED flash systems to enhance image quality and new forms of sensing for natural user interfaces - will be presented.

CV of presenting author
Formerly head of CSEM Zurich Replicated Micro-Optical Elements, Markus became CTO of Heptagon after CSEM's microoptics division was acquired by Heptagon in 2000. He is an expert on fabricating diffractive and refractive micro-optic components for industrial applications in the European and US markets. Markus holds a Ph.D. from the University of Neuchatel, Switzerland and a master's degree in physics from ETH Zurich.

Imaging Conference
Hewlett Packard Barbarin, Rémi
Data Centers
Barbarin, Rémi

Barbarin, Rémi
Account Chief Technologist
Hewlett Packard

Abstract
-TBA-

CV of presenting author
Rémi Barbarin is HP Chief Technologist at Hewlett Packard where he specializes in providing end-to-end IT solutions for the Aerospace and Defense industry where energy efficiency is crucial both for Datacenters and High Performance Computing solutions. In this capacity, he is called to provide strategy recommendations, innovation workshops, technology briefings, and best practice sharing sessions as well as engage leading experts from all HP organizations worldwide. Remi's role also encompasses the supervision of the architects and of solution work done for the Aerospace Industry in EMEA. His responsibilities include as well technology strategy, continuous improvement, marketing and communication. Holding both a MBA and an engineering degree, Remi has an extensive background both in R&D and IT. In HP since 2000, he held various leadership roles in Enterprise Services, Product Manufacturing and Corporate IT. Remi is 40 years old, lives near Grenoble in the French Alps with his wife and two daughters. During his time off, he enjoys practicing martial arts.

Low Power Conference
Hillcrest Labs Lucien, Chad
Sensor Hubs: Enabling The Next Generation of High-Performance, Low-Power Mobile and Wearable Devices
Lucien, Chad

Lucien, Chad
SVP
Hillcrest Labs

Abstract
Advanced sensor hubs are bringing 'always on' tracking of motion and user contexts to an array of mobile and wearable devices, including smartphones, tablets, activity trackers, and head-mounted displays. These devices, enabled by high performance sensor fusion, are exploding the amount of sensor data available, and provide an exciting platform to intelligently interpret context, location, and position, and visually enrich real-world experiences with timely and useful information. This session will highlight cutting-edge developments in MEMS-enabled sensor hubs that provide more responsive, stable, and accurate heading, position and 3D motion tracking, through contextual smoothing for jitter-free visualization, comprehensive automated calibration to reduce gyro drift, and advanced magnetic field interference tracking and filtering to improve performance in various environmental settings. It will discuss specific features that make sensor hubs a powerful enabler of navigation solutions, and showcase advanced sensor hub-based navigation solutions in development today. Additionally, the presentation will highlight key technology trends that will help this technology mature across 2014 and through 2015.

CV of presenting author
Chad Lucien is responsible for Hillcrest Labs' worldwide sales, marketing and business development activities. Since joining Hillcrest in 2004, Chad has been a member of the company's executive management team where he has held positions encompassing corporate strategy, business development, and general management of the Freespace® motion computing product line. During his tenure, he has licensed Freespace solutions to global consumer electronics companies, developed a wide variety of strategic partnerships, and led numerous product launches in the Freespace product line. Chad has over 15 years of experience in corporate strategy, business development, venture consulting, and investment banking. Prior to Hillcrest, Chad was the Director of Strategic Development for TVGateway LLC, where he worked with the cable operators invested in TVGateway to execute a spin-off, reshape the strategy, and complete multiple financings and acquisitions. Prior positions also include Principal of Katalyst LLC, an operational consulting and venture capital firm, and Associate at Houlihan Lokey, an investment banking firm specializing in valuation and merger and acquisition transaction advisory services. Chad earned a bachelor of science in commerce with distinction from the University of Virginia, with concentrations in finance and marketing and is a CFA charterholder.

International MEMS Industry Forum
HP Renaud, Gallig
Using SoCs to build datacenter servers
Renaud, Gallig

Renaud, Gallig
Technology Consultant
HP

Abstract
Rather than using virtualization and other technics to efficiently use the power of traditional servers, we'll see how Moonshot is offering a different approach for the design of servers that fit perfectly identified workloads. By using technologies coming from the mobile industry such as SoC, specific processors and accelerators, Moonshot proposes servers tailored for specific range of applications that deliver a better performance/energy ratio. After reviewing the architecture of one of these software-defined servers, we will walk through a real customer use case to analyze the steps needed to get a perfect fit between hardware and software that allows an improvement in energy efficiency.

CV of presenting author
Gallig is working as a technology consultant part of the EMEA Discovery Lab. After spending 13 years at HP in the enterprise server group with various roles and responsibilities, his current job it to engage with customers and partners to identify applications that could leverage the software-defined approach from HP. Gallig is also part of an internal organization which is working closely with the engineering teams and that is reviewing upcoming HP server products.

Low Power Conference
I To top
IBS, Inc. Jones, Handel
FD SOI and Internet of Things
Jones, Handel

Jones, Handel
CEO
IBS, Inc.

Abstract
The high cost of migrating to 16/14nm and 10nm FinFETs is resulting in other options being evaluated by companies that want low power and low cost for high volume applications, including the emerging Internet of Things. The benefits of FD SOI, for supporting Internet of Things, will be applicable to medical, consumer, multimedia, industrial, and other applications. Scalability of FD SOI will allow the technology to be used for Internet of Things and other applications for the next 10 to 20 years.

CV of presenting author
Handel Jones is the founder, owner, and CEO of International Business Strategies, Inc. (Los Gatos, CA), which has been in business for more than 25 years. Prior to IBS, Handel Jones was Vice President at Rockwell International, where he managed 1,500+ engineers in avionics, communications, and semiconductors. Handel Jones was also in charge of international sales and marketing as well as business strategies for some of the business units. As CEO of IBS, Handel Jones provides strategic support for major global corporations in multiple industry segments. The clientele base includes Intel, IBM, Qualcomm, Broadcom, Microsoft, Nokia, Samsung, Sony, Toshiba, Apple, Cisco, Siemens, Motorola, Fujitsu, NEC, Hitachi, Renesas, TSMC, STMicroelectronics, TI, and others. IBS has customers in the U.S., China, Europe, South Korea, Japan, India, and other countries. IBS has also provided support to the French Government on Nano 2017 (their advanced technology initiatives). IBS also interfaces and supports financial institutions such as Goldman Sachs, Carlyle, Blackstone, CitiGroup, Credit Suisse, Exane BNP Paribas, Warburg Pincus, Walden, KKR, Morgan Stanley, Bain Capital, Bank of America, TPG, and others. A major part of the activities of IBS is involved with strategies for successful global business participation. This requires deep understanding of markets, competition, technologies, and the strengths and weaknesses of the management teams. The IBS analysis approaches can be applied to corporations, industries, as well as countries. There is also the need to understand future trends as well as the potential impact of destructive factors. IBS has strong expertise in China and published its first book called Chinamerica, which provides a detailed comparison between the industrial base and political policies of the U.S. and China (McGraw-Hill, 2010) as well as a second book called China Global Revolution: How China Can Become No. 1 (2014). Articles have been contributed to the China Daily, Global Times, and Forbes. The growth and opportunities in China is of special interest to IBS, and specifically to Handel Jones.

Low Power Conference
IHS Bouchaud, Jérémie
Sensors for the Internet of Things: how big is the opportunity
Bouchaud, Jérémie

Bouchaud, Jérémie
Principal Analyst MEMS & Sensors
IHS

Abstract
IHS is currently analyzing the MEMS & sensor content in a variety of pilot projects and scenarios related to smart cities, smart homes, smart factories and more generally for the Internet of Things. In factory automation and process control, pervasive sensing is available through the convergence of wireless automated systems, intelligent equipment, and the Internet. Advances in processor technology which allow for connected sensors running at low power for extended periods of time promote pervasive sensing. Additionally, as sensor packages have gotten more complex, it is now possible to utilize connected sensors in a cost effective way to monitor day-to-day operations of industrial machinery. Smart homes and smart cities are another major emerging mass market for sensors. Several pilot projects such as in Santander in Spain are showing how sensors can make a city safer and more efficient. Sub-surface magnetic sensors can report if parking spaces are occupied, sensors in street light can save energy, sensors can help monitor more closely and consecutively to diminish the air pollution as well as the acoustic pollution. IHS will present the results of this qualitative assessment and will quantify the opportunity for sensor maker. IHS will examine the market drivers for high volume deployment of sensors as well as the hurdles which need to be overcome.

CV of presenting author
Jérémie Bouchaud, leads the team at IHS which analyses the market for semiconductor based sensors (MEMS & other Sensors). His breadth of MEMS and sensors device and application knowledge is unmatched in this industry, particularly in terms of automotive, consumer markets and industrial and medical applications. He was a founder and head of MEMS & Sensors research for Wicht Technologie Consulting, acquired by iSuppli in 2008 and IHS in 2010. In the course of his career, he has led more than 100 MEMS-related market research endeavors. Prior to WTC, he oversaw technology transfer for sensors and MEMS at the German office of CEA-LETI.

International MEMS Industry Forum
Imagination Technologies Hasan, Munir
MIPS: Multi-Threaded RISC Architecture to Enable Higher Performance in Low Power Applications
Hasan, Munir

Hasan, Munir
Solutions Engineer
Imagination Technologies

Abstract
RISC Processors have been able to achieve low power due to the simplicity of its Pipeline Stages and Decode Logic, thus making it suitable for a wide range of applications; from Embedded Controllers to Network Servers. A factor that limits a Processor's Performance is the latency when accessing data from memory. With Processors cycle times reducing faster than the memory access time, there is a critical performance bottleneck. Deeper levels of Cache are able to mitigate this bottleneck, but this comes at the cost of increasing Area. Multi-threading offers a solution; it ensures another sequence of instructions progress through the pipeline, while the current memory access is being completed. Thus, Multi-threading increases throughput performance while maintaining low power. This presentation will discuss why MIPS Architecture is ideal for Multithreading, how it has been implemented, the Performance and Power benefits and example Applications using this technology.

CV of presenting author
Munir has recently joined Imagination Technologies as a Solutions Engineer for Europe. He is primarily focused on supporting customers with integrating MIPS processors into their SoC for the next generation of applications. Prior to joining Imagination Technologies, he had been working as Design Evaluation Engineer for Analog Devices Inc in the Digital Video Products group. He has an MEng in Electrical an Electronic Engineering from Imperial College London.

Low Power Conference
IMEC Willems, Maarten
CMOS-based innovations for specialty imaging industries to consumer applications
Willems, Maarten

Willems, Maarten
Business Director - Smart Systems
IMEC

Abstract
imec has pioneered for more than a decade industry-leading technology research in digital CMOS imaging with clear focus on reaching extremely high-speed, high QE, low power and low noise image sensor solutions. High speed ADCs, Hyperspectral filtering, backside illumination, UV imaging and embedded CCD pixels into CMOS circuits are new technology platforms with unique potential that imec has been recently bringing into reality. This presentation will give a high level overview update of the recent results and vast range of industries that can be served by these unique CMOS-based imaging technologies. From industrial inspection to aerial photogrammetry, security to spectroscopy, medical to astronomy, imec's imaging innovations allow our partners unprecedented capabilities, enabling new discoveries and competitive advantage.

CV of presenting author
Maarten Willems received the M.S. Degree in Electrotechnical Engineering in 1993 and subsequently the M.S. Degree in Artificial Intelligence in 1994 and an MBA, from the KU Leuven. After a career as a solution design engineer at Alcatel Bell, director of engineering at Keyware Technologies, and VP Professional services at GlobalSign, Maarten co-founded Hypertrust in 2000, an internet service company. In 2005, Maarten joined imec as market intelligence group leader. Since 2008, Maarten holds his current position as business director in the smart systems segment focusing on business development and sales of new sensor technology development and product marketing in the domains of imaging, healthcare and power electronics.

18th Fab Managers Forum
Imaging Conference
IMEC Dekoster, Johan
Dekoster, Johan

Dekoster, Johan
Program Manager
IMEC

Biography
Johan Dekoster received the M.S. degree in Exact Sciences (Physics) in 1988 from the KU Leuven, Belgium. In 1993 he received the Ph.D. degree (Physics), also from the KU Leuven. From 1993 till 1999 he held postdoctoral fellowships from the Research Council and the Fund for Scientific Research at the Institute of Nuclear and Radiation Physics of the KU Leuven. In 1999 he joined the OTN business unit of Siemens. He was project leader for several development projects for data, voice, video and LAN. In 2007 he became program manager OTN at Nokia Siemens Networks. In April 2008 he joined IMEC as R&D manager of the Epitaxy group with responsibility on epitaxial deposition of group IV and III-V semiconductor materials. Since November 2012 he is program manager of the equipment and materials suppliers collaborations within the Process Technology Unit at IMEC.

2D (TechARENA)
IMEC Lauwers, Lode
Eco system requirements to enable further system scaling and semiconductor manufacturing effectiveness
Lauwers, Lode

Lauwers, Lode
Vice President Business Development
Imec

Abstract
In the foreseeable future, we can rest assured that new application platforms will continue to drive the IC industry: Internet of Things, personal health management, ever increasing connectivity... Moore's Law has made the applications of today possible through a continuous cost reduction of transistors, enabling more complexity, functionality and performance of systems. Which materials, device and process technologies will we be able to bring to a manufacturable level in order to keep that pace, and to allow for next generation process platforms to offer benefits to the designers? Which measures are required in the ecosystem: material research and equipment R&D, in order to bear the continuously increasing cost of R&D in a climate of growing consolidation? It's a matter of scale and volume: will we have products which will generate sufficient volume in a sustainable way to enable further ecosystem development, amongst which the 450 wafer size developments, or other capital intensive transitions? Our imagination will lead the way.

CV of presenting author
Lode Lauwers is Vice President Business Development in IMEC, the nanoelectronics R&D Center in Leuven, Belgium. He oversees Corporate Business Development of IMEC Business Lines, CMOS scaling, Smart Systems and Energy, with a shared responsibility over sales with VP world wide Account Management. In the area of CMOS technology, he is responsible for IMEC business offerings, covering collaborations with leading IC manufacturers and equipment and material suppliers worldwide. Since he joined IMEC in 2005, he had various roles in IMEC's technology business and sales, a.o. as Director Strategic Program Partnerships, and having Regional Sales responsibility for IMEC business in Japan. Earlier, he has been general manager of an ASIC design house, part of a US-based ASSP provider for the telecom industry, and scientific advisor for government funding in local and European cooperative networks in micro-electronics and telecommunications.

450mm
IMEC Van Hoof, Chris
Generic Silicon Technologies for Individualized Medicine
Van Hoof, Chris

Van Hoof, Chris
Director Wearable Healthcare, imec Fellow
imec

Abstract
The healthcare arena is on a clear path towards preventative and personalized medicine. Semiconductor nanotechnology is a key enabler to advancing this goal. The market has already developed low-power analog, digital, and radio circuitry combined with novel sensors. These wearables can measure progressively more parameters with greater accuracy, have become smaller in size and are more energy efficient-such that their use is nearly transparent. Likewise, customized silicon chips will allow complex biochemical tests with a small, low-cost disposable such that anyone can perform a range of tests anywhere and anytime. The ability of silicon chips to measure and process data at enormous levels of parallelism has already enabled reading of the human genome at prices that were, until a few years ago, unthinkable. Currently silicon is customized for a number of healthcare applications at imec. Apart from managing chronic illness, a further disruption in our healthcare will be through the management of health where prediction and prevention will be essential enablers. Wearable and even disposable sensors that monitor whether you live a healthy life, that assess your stress levels, your pain, your emotions and so on, are examples of new tools that are moving out of the realm of science fiction and into everyday reality. Systems that achieve medically relevant information in a consumer form factor will be presented. These platforms have the potential to create a multitude of killer apps - and these killer apps will be saving lives.

CV of presenting author
Chris Van Hoof is Director of Wearable Healthcare at imec in Leuven, Belgium and Eindhoven, the Netherlands and imec Fellow. In the Wearable Healthcare program, imec and its industrial partners from across the value chain create and validate solutions at technology, component and application level. Chris Van Hoof has a track record of 20 years of initiating, executing and leading national and international contract R&D at imec. His work resulted in 3 startups (2 in the healthcare domain) and he delivered space qualified flight hardware to two cornerstone European Space Agency missions. After a PhD in Electrical Engineering (University of Leuven, 1992), Chris Van Hoof has held positions at imec at manager and director level in diverse technical fields (sensors and imagers, MEMS and autonomous microsystems, wireless sensors, body-area networks). Chris Van Hoof is also full professor at the University of Leuven (KULeuven).

Application driven technology: Nanoelectronic for Healthcare (TechARENA)
IMEC Hendrickx, Eric
EUV lithography: On the move from pre-production to production
Hendrickx, Eric

Hendrickx, Eric
Program manager EUV lithography
imec

Abstract
EUV lithography has made gradual and consistent progress over the last years, as currently the first production tools have been installed at the main chipmakers. Some important improvements remain to be demonstrated, but overall the technology is getting closer to pilot production. Imec started work on EUV lithography in 2006, and from 2008 to 2011 was one of the 2 sites that had an EUV alpha-demo tool operational. Subsequently, Imec was one of the first 2 sites to install an ASML NXE:3100 EUV pre-production scanner, and currently is preparing for the installation of the ASML NXE:3300 EUV production scanner. In this presentation we will review some of the main learnings seen over the last years, give current status of the EUV resists, masks, and scanner, and conclude with the main challenges that still lie ahead before EUV can become fully production worthy.

CV of presenting author
Eric Hendrickx graduated from the University of Leuven in 1996, and subsequently was a postdoctoral research scientist at the Optical Sciences Center at the University of Arizona and at the University of Leuven. He joined the lithography department at imec in 2001, and started working on EUV lithography in 2008 when imec started its use of the ASML EUV Alpha-demo tool.

Lithography: What lithography options for tomorrow? (TechARENA)
IMEC Barla, Kathy
FinFeT: challenges and opportunities
Barla, Kathy

Barla, Kathy
Unit Process & Modules Department Director
IMEC

Abstract
The multi-gate architecture has been demonstrated as a key enabler for further CMOS scaling thanks to its improved electrostatic and short-channel effect control. FinFets represent one the architecture of interest. It has been introduced by Intel in manufacturing at 22 nm technology and recently they provided first details of the FinFet evolution allowing 14nm technology to reach expected performance and cost. In this presentation we will present the benefits and challenges of FinFet structures for further technology scaling towards 7nm and below.

CV of presenting author
Kathy Barla is Unit Process & Modules Department Director at IMEC since October 2012. Kathy has 30 years of experience in microelectronics working for ST Microelectronics at Crolles for many years and at the International Semiconductor Development Alliance, IBM East Fishkill, to develop & transfer the 28nm technology. After a PhD in materials sciences, she started as Research Engineer at CNET, France Telecom Research Center dedicated to microelectronics. Then she moved to STMicroelectronics as Process Engineer to take in charge the development of gate dielectrics. In STMicroelectronics she was involved in many of the FEOL & BEOL process technology challenges starting with 0.5 m up to 20nm technology. She acquired an extensive experience in managing 200 & 300 mm R&D Unit Process. In her new position at IMEC, Kathy took up the responsibility in strengthening the links between unit process and modules with device & integration development. She is supporting concurrent innovation at the level of materials, unit steps and modules to shift the frontiers of technology development.

Low Power Conference
IMEC Heremans, Paul
Thin-film transistors on plastic: manufacturability and applications
Heremans, Paul

Heremans, Paul
Director
imec

Abstract
We will review the status of thin-film transistors on flexible plastic film, focusing on organic and oxide TFTs. Processes for organic and oxide TFTs on sheet-to-sheet are primarily developed for backplanes of active-matrix flexible displays. They should in particular be suited to drive OLEDs, as OLEDs are the frontplane technology of choice for flexible mobile displays. Their superior mechanical robustness will be a differentiator with respect to conventional silicon TFTs. The technological maturity of these organic and oxide TFTs on plastic film has reached the point where integration of these new TFT technologies into small-scale integrated circuits is viable. By nature of the technology, thin-film ICs need mass markets to reach economy of scale. Electronic tags represent such market. Passive HF TFT tags with increasing functionality have been shown in the last years, and NFC compatible tags are a nearby target. Meanwhile, the appearance of the first thin-film UHF energy harvesters allow to envisage UHF tags in the near future. Apart from this example in the consumer market, we will also discuss applications of ultra-flexible circuits in healthcare patches.

CV of presenting author
Paul Heremans received the Ph. D. degree in Electrical Engineering from the University of Leuven, Belgium, in 1990. He then joined the opto-electronics group of imec, Leuven, Belgium to work on optical inter-chip interconnects, and on high-efficiency III-V thin-film surface-textured light-emitting diodes. In 1998, he started the organic electronics activities at imec. In 2007, he became imec fellow and department director of the Large Area Electronics department. In 2012, he was appointed Technology Director of the Holst Center. The main topics of Paul's research today are OLEDs, organic and oxide thin-film electronics, flexible AM-OLED displays, RFID tags, thin-film sensors and memories, and organic photovoltaics. Since 2013, he holds an advanced grant of the European Research Council. He is the author of some 10 papers at ISSCC over the last years with thin-film circuits on film.

Plastic Electronics - PE2014
IMEC Huyghebaert, Cedric
2D materials : From Advanced CMOS to Beyond CMOS devices
Huyghebaert, Cedric

Huyghebaert, Cedric
R&D team leader
imec

Abstract
The information infrastructure is growing and becoming ubiquitous around us. Continuous connectivity, which we take for granted now, did not exist 10 years ago. This growth has been largely fueled by the scaling of the transistors which has allowed increased performance for comparable energy consumption and lower cost. Continuing growth further will demand a variety of electronic systems with different performance and energy efficiency requirements to satisfy a large set of functionality and cost needs. Early on, the scaling of the transistors was driven by the lithographic improvements. More recently, the scaling is that of the performance and relies on new materials (high K dielectrics and metal gates) and on devices structure innovations (fully-depleted channel devices). The performance scaling of the next decade will likely bring concerted changes not only at the transistor level but also at the interconnect and at the architecture level as the 3rd dimension will be conquered. The pace of innovation will likely continue further as it is driven by technological needs. The scaling of the transistor will be influenced by fundamental physical limits of device switching. At imec, we are a investigating not only advanced CMOS devices and "end of the roadmap" transistors, but also Beyond CMOS devices which rely on advanced materials like graphene and 2D semiconductors but also devices that employ a different state variable. This talk will outline the research on the 2D materials family. Imec has been carrying out endeavors whose main focus is to provide an answer to the question of whether the family of 2D materials could really hold the promises for a successful use in microelectronics. This is being accomplished with a strategy encompassing two main aspects of research: (1)to evaluate novel device concepts based on the fundamental properties of 2D materials (2) to work towards industrial compatible solutions for 2D material integration in a semiconductor environment.

CV of presenting author
Cedric Huyghebaert is currently leading the nano-applications and material engineering team at imec dealing with the integration of nano materials as CNT, nanowires,graphene and MoS2 in functional applications, in the field of beyond Si scaling, advanced interconnect and energy storage applications. He started as a junior researcher in the materials and component analyses group at imec. He studied the oxygen bean interactions during sputtering profiling of semiconductors. He received his PhD in Physics in 2006 at the KULeuven in Belgium. In 2005 he joined imecs pilot line management team, especially dealing with integration challenges and the process contamination control. In 2008 he joined the 3D integration team to organize the migration of the 3D technology from a lab environment to the a pilot line. He was the lead integration engineer of the first demonstration of 3D TSV interconnects by wafer to wafer bonding.

2D (TechARENA)
IMEC La Manna, Antonio
3D System Integration - Technology choices and challenges
La Manna, Antonio

La Manna, Antonio
Program Manager
imec

Abstract
3D integration technologies allow for a significant power reduction together with a strong increase in interconnect bandwidth. This is achieved by reducing both the interconnect connection pitch and wire-length. This can be done at different levels of the electronic system hierarchy and by repartitioning the electronic system. This results in a hierarchy of 3D technologies, which we group into 3 main categories: 3D-stacked-IC or 3D-SIC (Die-to-die, or Die-to-wafer stacking), 3D-System-on-chip or 3D-SOC (Wafer-to-Wafer stacking) and the 3D device stacking or 3D-IC technologies. On the other hand, the applications requirements and the technology limitations imply a decision process that can accelerate or delay the adoption of 3D technology for volume production. As example, due to thermal limitations, some applications require the use of a so-called interposer substrate to realize high bandwidth interconnects between subsystems. The imec 3D system integration program address these technology questions in detail, both from a system level and a technology perspective. In this presentation the technology choices and challenges for 3D integration will be discussed.

CV of presenting author
Antonio La Manna is currently program manager for 3D integration at IMEC, Belgium. Prior to join IMEC, he held various technical positions at ST Microelectronics and Infineon/Qimonda. Antonio has more than 12 years' experience in semiconductors industry and covered roles from IC package design to project management for assembly and 3D integration. He has authored or co-authored over 30 publications in international conferences and scientific journals. Mr. La Manna's activities involve the areas of 3D IC integration: TSV, wafer thinning, bumping and stacking. He earned a M. S. Degree in Electronic Engineering from the University Federico II in Naples (Italy).

Advanced Packaging Conference (APC)
3D integration (TechARENA)
IMEC & Ghent University Vanfleteren, Jan
The use of elastic and thermoplastic polymer carriers for the fabrication of randomly shaped electronic circuits
Vanfleteren, Jan

Vanfleteren, Jan
R&D manager
IMEC & Ghent University

Abstract
Today's mainstream electronic circuit manufacturing processes consists of the fabrication of a printed circuit board (PCB), followed by the assembly of packaged electronic components on the PCB using (lead free) soldering. The PCB consists in many cases of a rigid, glass fiber reinforced epoxy polymer (e.g. the FR4 material), carrying Cu interconnections, which are structured using photolithograpy and wet etching techniques. Besides rigid carriers also flexible substrates are used like e.g. polyimide. Standard manufacturing, including assembly, is done on flat substrates. After finishing the assembly flexible substrates can be deformed/bent from their flat state (as produced) to a limited number of other form factors like cylindrical or conical. However there is growing need for circuits with a random 2.5D shape. In this contribution we will present technologies for the production of such free-form circuits. In some aspects these technologies are identical to conventional circuit production : standard PCB type Cu conductors are structured, and components-off-the-shelf (COTS) are assembled using standard lead-free solder processes. The differences with standard rigid or flexible circuit production on the other hand, allowing for the random shaping, are the following : (1) the Cu conductors are structured as meanders, allowing for considerable (e.g. 60 to 100%) elongation without failure (2) instead of epoxy or polyimide, now elastic polymers like PDMS (silicone rubber) or thermoplastic materials (like PET, PC or PC/ABS) are used to serve as carriers for the electronics. This yields elastic, dynamically deformable, resp. rigid, thermoplastically deformable circuits. These carriers are applied after all necessary harsh chemical and thermal production steps (wet etching, solder assembly) are accomplished, meaning that a wide variety of polymer carrier materials can be used. The contribution will describe technologies in detail, as well as potential applications.

CV of presenting author
Prof. Dr. ir. Jan Vanfleteren received the Ph.D. degree in electronic engineering from Ghent University, Ghent, Belgium, in 1987. He is currently a senior engineer and R&D manager with the Center for Microsystems Technology (CMST) of imec, and is involved in the development of novel interconnection, assembly, and polymer microsystem technologies, especially for wearable and implantable electronics, biomedical, microfluidics, cell culturing, and tissue engineering applications. Jan Vanfleteren has a long-standing experience in coordination and cooperation in EC-funded projects. As an example he currently serves as the co-ordinator for the granted FP7-ICT-IP-"TERASEL" project on thermoplastically deformable circuits for embedded randomly shaped electronics. In 2004, he became a part-time professor with Ghent University. He is the co-author of over 200 papers in international journals and conferences. More than 130 of these publications are registered in ISI Web of Knowledge, of which more than 80 since 2008. For a complete detailed list we refer to the following Researcher-ID URL: http://www.researcherid.com/rid/D-7557-2012. J. Vanfleteren's scientific track record is also publically available from Google Scholar : http://scholar.google.com/citations?user=lRWgoJ4AAAAJ. He holds 14 patents and patent applications. He is a member of IEEE, IMAPS and MRS.

Plastic Electronics - PE2014
Imina Technologies SA Dagon, Benoît
Probe smaller, probe smarter, or how micro-robots can help shorten the development cycle of your products
Dagon, Benoît

Dagon, Benoît
CEO and co-founder of Imina Technologies SA
Imina Technologies SA

Abstract
The deep shortage of versatile, multi-domain tools capable of analyzing phenomena occurring at micro- and nanoscales seriously impacts the development speed of advanced semiconductor materials based devices. In this talk we will present a miniaturized robotic platform which provides capabilities for in situ characterization in both electron and light microscopes. This multi-functional system embeds up to four miBot, our piezoactuated micro robots, allowing the user to independently position the probes over centimeter scale displacements with a resolution down to the nanometer. These solutions, specifically designed for low current measurements, can be connected with standard third party signal analyzers to carry out electrical characterizations with an excellent signal-to-noise ratio. Moreover thanks of their compact designs, they can virtually retro-fit any microscope setups, even the most tiny ones. Customer applications and integrations examples will illustrate the advantages of these platforms for a wide range of applications in nanoelectronics, photonics and materials science.

CV of presenting author
Dr. Benoît Dagon currently serves as CEO of Imina Technologies SA, a company he co-founded in 2009. Before that, he conducted a research project at Stanford University and completed a PhD in the field of computer assisted surgery at EPFL Robotics Laboratory. Dr. Dagon also holds a M.S. from EPFL in microengineering with specialization in robotics and industrial manufacturing.

16th European Manufacturing Test Conference (EMTC)
Infineon Irsigler, Peter
Power Semiconductors on 300mm Wafers
Irsigler, Peter

Irsigler, Peter
Director Technology
Infineon

Abstract
Energy saving becomes a more and import issue in order to save resources and to lower the CO2 output worldwide. This is true for all fields of application of power semiconductors starting from electrical energy production, transportation, transformation and point of use conversion. Infineon phases a constant and steady growth in all fields of power technologies. To cope with the growing market demands additional capacities are necessary and have to be built up. To save capital invest and to insure future growth, the idea of 300mm production for power semiconductors was born. For high power applications the IGBT technology, for medium power applications CoolMOS and for low voltage and power the SFET technology/ SMART technology are used. Several hurdles had to be overcome before starting the first 300mm wafers. The first one was the unavailability of the proper substrate material. The state of the art 300mm wafers for CMOS technologies are p type while all power technologies need to have n type material in all ranges of resistivity. Also the issues of temperature budgets and thin wafer technology had to be solved. Today all major power technologies IGBT, CoolMOS and SFET are qualified and in production. The next generation technologies will be developed directly in 300mm

CV of presenting author
Dipl.Ing.Peter Irsigler study at the Johannes Kepler University in Linz physics (1977-1983). He joined Infineon the wafer production in Villach in 1984. He started with process integration for DRAM, CMOS and power devices. Later on he was manager for power technologies and unit processes. Now he is responsible for development, transfers and innovation in the wafer fabrication Villach and responsible for the conversion of technologies to 300mm wafer diameter.

Power Electronics Conference
Infineon AG Labs, Lutz
Increasing the Automation Level in running Fabs
Labs, Lutz

Labs, Lutz
Senior Director Production
Infineon AG

Abstract
Increasing productivity and reducing operational cost is essential for Semiconductor Fabs. Especially, Fabs located in Europe have to compete with Fabs in Asia with lower operator cost. Therefore, automation is one important factor for driving cost efficiency in European fabs. Automation is also seen as enabler for stabilization lot cycle times, flow factor and ensuring high product quality due to less manual intervention. Newest trends in robotics for manufacturing show potentials with regard to human-robot interaction. This allows for collaboration of robots and operators without endanger of human safety and provides flexibility in finding the appropriate degree of automation. State-of-the art automated material handling systems (AMHS) are available for 12" FOUP handling in Front End Factories. However, there is a lack of cost efficient and up-to-date AMHS solutions supporting 8" wafer carrier and box handling for retrofit projects in 8" Fabs. During the last years, Infineon has gathered experience in increasing the automation level in running 8" Fabs. One key question is the strategy how to bring a Fab to a higher automation level and where to start with automation projects - on equipment, work area or Fab level? This paper illustrates pros and cons of automation strategies for running 8" wafer size Fabs. It is shown that ongoing standardization effort is also required for 8" AMHS solutions in order to provide cost efficient automation retrofit projects in 8" wafer size Fabs.

CV of presenting author
EDUCATION: Diplom / M.S. of Physics, University of Jena, Germany, June 1987 EXECUTIVE SUMMARY: - Managing Director of FrontEnd Production in Regensburg/Germany - worked 27 years at Semiconductor R&D and Operations, includes 3 years at Elektromat Dresden and 5 years at DAS GmbH - experience in people management, covering line operating, maintenance engineering, engineering in production and development as well as in fostering cross functional cooperation PATENTS: 2 issued patent

18th Fab Managers Forum
Infineon Technologies AG Sturm, Johannes
Automation as Key Enabler for Productivity Increase
Sturm, Johannes

Sturm, Johannes
Productivity Management Frontend
Infineon Technologies AG

Abstract
The levers for productivity increase of mainly depreciated fabs are limited. One of the most important levers is automation, not only material handling and transport automation, but also automation of so-called "side activities" as tool checks and exception handling. The presentation focusses on automation besides robots and transport systems and gives some examples on how it can be added to mature fabs resulting in better cost position, better quality and less cycle time.

CV of presenting author
Physics Diploma at RWTH Aachen in 1991 Dr. rer. nat. at RWTH Aachen in 1993 Several positions at research institutes and companies including TU Berlin and Mühlbauer International, Roding 1998 until 2014 Manager at Infineon Technologies Dresden in different areas, e.g. Burn In, Furnace, WET, Communication and Automation Since 2014 at Infineon Technologies AG, Neubiberg, responsible for Frontend Productivity Management and Automation

18th Fab Managers Forum
Fab productivity (TechARENA)
Infineon Technologies AG Vock, Stefan
Vock, Stefan

Vock, Stefan
Principal Test Engineering
Infineon Technologies AG

Biography
Stefan Vock Biography Stefan Vock is holding a Diplom-Ingenieur (FH) degree from the University of Applied Science Augsburg and a Master degree in Electronic Systems with distinction from the University of Ulster. He received the designation of European Engineer (EUR ING) in 2009. Mr. Vock has been in the Automated Test Equipment (ATE) industry for more than 20 years delivering professional services to: ATE vendors like credence and Teradyne, and to design houses as well as to integrated device manufactures (IDM), and today to Infineon in the area test technology and innovation. Further he is currently a Ph.D. candidate at the University of Ulster with the research focus on semiconductor test engineering.

16th European Manufacturing Test Conference (EMTC)
Infineon Technologies AG Janker, Achim
Secondary Equipment and 300 mm - Opportunities & Challenges
Janker, Achim

Janker, Achim
Senior Director Purchasing
Infineon Technologies AG

Abstract
Infineon Technologies as leading manufacturer of power devices operates four semiconductor frontend fabs in Dresden and Regensburg (Germany), Villach (Austria) and Kulim (Malaysia). In order to fulfill the increasing customer demand and to stay cost competitive with its large manufacturing footprint in Europe, Infineon started the 300 mm project for power with a ramp to a high volume production in Dresden and a strong focus on further development in Villach. In order to compete with the installed base of mostly depreciated 200mm tools, secondary equipment is key to bring discrete power products on 300mm. Technically this includes some challenges for the implementation of the Infineon thinwafer process on 300 mm. The experiences and the learnings in this project with buying and using secondary equipment for 300 mm - including its challenges and opportunities - is shown by focusing on the: - Infineon frontend production strategy - 300 mm project for power device production - Secondary market for 300 mm - Requirements for the successful use of secondary equipment - Examples of successful purchases - Expectations to equipment suppliers

CV of presenting author
Achim Janker is Head of the Frontend Purchasing Organization at Infineon Technologies AG. He started his professional career at Siemens Semiconductor in 1990. He gained extended experience in purchasing equipment as a member of project teams for setting up new production sites in Europe, the U.S. and Asia. 1998 he took over the responsibility for the purchasing organization of the Siemens semiconductor manufacturing plant in Regensburg including waferfab-, assembly & test- and optoelectronics-productions. In 1999 the Siemens Semiconductor division was carved out to Infineon Technologies. From 2003 Achim Janker was responsible for the worldwide procurement of the assembly & test production cluster in Asia. He focused back on the frontend when he became head of the frontend purchasing organization of Infineon Technologies AG in 2006.

Secondary Equipment (TechARENA)
Infineon Technologies AG Wille, Catharina
One Material - Two Worlds: Sintering Die Attach on DCB and Leadframe
Wille, Catharina

Wille, Catharina
Senior Engineer Materials
Infineon Technologies AG

Abstract
With the upcoming review of several governmental directives limiting the use of lead (Pb) solder in microelectronic packaging, it is necessary to find a drop-in replacement for Pb-containing solder paste. Such replacement should enable the re-use of existing equipment in order to be cost-efficient. At the same time, several technical requirements have to be fulfilled: compatibility with existing processes and materials in front end and back end, good electrical and thermal conductivity, high reliability comparable to Pb-based solder, few and small voids as well as low stress on the device. As one possible solution, pressure-assisted Ag sintering has been developed for DCB (direct copper bonded) ceramic substrates and is gaining market share. The direct transfer of this process to leadframe (LF) products issues a challenge due to different material properties. Like for DCB applications, the long-term reliability of sintering joints on LF depends strongly on the density and mechanical properties of the joint material, and the quality of its interfaces to the chip and to the substrate metallizations. However, copper LFs offer a much higher CTE than DCBs, which results in a significantly higher CTE mismatch to silicon. As a consequence, LF- based products are much more susceptible to stress-induced failures. This circumstance calls for a less rigid, stress-buffering interconnect. In this paper, we present first promising reliability results for chips sintered to LF with a Si-to-Cu thickness ratio of 1:1 and a pressure-less Ag sintering paste, which we consider to be best-in-class according to our investigations. One of the obstacles on the way to productively applying silver sintering pastes in LF products is the fact that suppliers are continuously improving and refining the composition of their pressure-less sintering pastes. At present, no convergence of the development is noticeable.

CV of presenting author
Catharina Wille holds a diploma in physics (2006) and a PhD with specialization in materials physics (2009), both from the Georg-August-University Goettingen (Germany). She was working and teaching as a postdoctoral fellow in the field of thermodynamics and kinetics of interfacial reactions, metallic alloys, nanostructured materials and thermodynamics and kinetics of phase separation in alloys under equilibrium and non equilibrium conditions at the Georg-August-University Goettingen (Germany) and the King Abdullah University of Science and Technology (KAUST, Saudi Arabia). In 2012, she joined Infineon's R&D department for package technology and innovation, with emphasis on metallic die attach materials, especially sinter pastes.

Advanced Packaging Conference (APC)
Infineon Technologies AG Miller, Gerhard
Power Electronics - the ultimate path to CO2 reduction
Miller, Gerhard

Miller, Gerhard
Senior Director R&D
Infineon Technologies AG

Abstract
In a strongly growing worldwide population an even stronger demand for energy is rising - growing from today's tremendous 140*10exp12 kWh per year by further 40% over the next 25 years. At the same time knowing that the exhaust gases set free during energy generation and consumption - mainly CO2 - has to be reduced on values of the 90th of last century, to avoid climatic collapse in the near future. Here power electronics can contribute on many levels starting with electrical power generation out of renewable primary energy (solar, wind, bio-gases), sustaining transmission with lower losses and enabling final consumption with drastically reduced losses. Many examples for the beneficial application of power electronics during the long chain from generation to consumption are shown in the paper combined with underlying principles, numbers and facts. Some examples of power semiconductors with their enabler function to power electronics on their developmental roadmap are discussed.

CV of presenting author
- 30 years of experience in power semiconductors - Studied electrical engineering sciences focusing on electro physics and semiconductor physics at TU Munich/Germany finishing with a Dr. Ing. in the field of RF- capabilites of power-MOSFETs (SIPMOS). - 1984 entering Siemens power MOS group - 1986 project leader of first IGBT development within Siemens with several basic patents and publications. - 1992 leader of segment IGBT Modules including R&D as a total program manager. - 1997 leader of discrete high and low voltage MOS- and IGBT- R&D. - 2005 leader R&D in Infineon's Industrial Power group - 2008 leader of TI Power in Infineon's Division Industrial and Multimarket with responsibility for SiC and IGBT/Diode technologies. - 2012 leader R&D technology and Discrete products in division Industrial and Power Control - 2014 preparing retirement with Enabler and Consulting function in IFX industrial power group.

Power Electronics Conference
Infineon Technology AG Roemer, Bernd
Roemer, Bernd

Roemer, Bernd
Senior Principal
Infineon Technology AG

Biography
Bernd Römer received his diploma in mechanical engineering and precision engineering from the University of Applied Sciences Giessen/Germany in 1983. He joined Infineeon Technologies former Siemens Semiconductors in 1983. Bernd had various engineering and management positions in the area of semiconductor package / product development, technology & innovation, research & development and production. As Senior Principal Packaging and System Integration he is leading a Integration conpepts team within the Infineon Packaging Innovation group. Bernd Römer is an active member in different organizations like ITRS TG Assembly & Packaging, IEC, JEDEC, and JISSO International Council (JIC).

Advanced Packaging Conference (APC)
Institut de la vision Picaud, Serge
Imaging in ophthalmology: From eye astronomy to artificial retina for visual restoration in blind patients
Picaud, Serge

Picaud, Serge
Directeur de recherche
Institut de la vision

Abstract
Imaging technologies are important to assess the progression of retinal diseases. Imaging data were recently accepted as endpoints in clinical trials . Medical devices aiming at restoring vision in blind or visually impaired patients also introduce new imaging technologies. However, at video rates, the sequential waves of visual information are not able to produce biomimetic visual information processing. The presentation will illustrate the development of new technologies for restoring vision in patients by either medical devices or an alternative strategy based on archaic visual systems of algae and bacteria. In both cases, encoding visual information is required in an external medical device. To achieve biomimetic visual processing, we have used visual asynchronous sensors, which sample information along the X-axis (time) instead of along the Y-axis (light intensity) generating thereby a great time precision (µs to ms). The choice for the different forms of visual restoration is highly dependent upon the state of the residual retina. The presence of non-photosensitive "dormant" photoreceptors was for instance demonstrated in blind patients using optic coherence tomography. Other imaging technologies are emerging to assess the state of retinal diseases. For instance, adaptive optics, which relies on technologies developed by astronomers to compensate for atmospheric distortions, has been applied in ophthalmology to compensate for eye distortions. It allows a very precise photoreceptor cell counting, which was already used in a clinical trial. It can also document very precisely the front edge move in damaged areas reducing thereby the time to demonstrate drug efficacy. Imaging technologies are therefore essential for the future of ophthalmology not only for assessing diseases and validating therapies but also for the development of innovative medical devices to restore or improve vision. Supports: FAF, FFB, FRM, ANR, EC (NEUROCARE).

CV of presenting author
Serge PICAUD (Directeur de recherche, INSERM) is currently heading the team "Retinal information processing" at the Vision Institute in Paris. He aims at understanding normal vision and developing new therapeutic or rehabilitation strategies. He supported Pr Sahel for the creation of the Paris Vision Institute and is a founder in the start-ups Fovea Pharmaceuticals, Pixium Vision and GenSight biologics. Serge Picaud and team members have characterized the physiology of photoreceptors and mechanisms involved in their degeneration. They solved the retinal toxicity of the anti-epileptic drug, Vigabatrin (Sabril) showing a taurine depletion in animals and patients. Recently, the team has moved to developing strategies for restoring vision in blind patients having lost their photoreceptors. They have proposed innovative high-resolution retinal 3D implant design by mathematical modelling and in vivo rat validation. New materials such as diamond and graphene are evaluated for their biocompatibility and electronic window. In addition, new visual information encoding systems were generated from visual dynamic sensors to mimic the high retinal dynamic. Finally, reactivation of residual neurones was demonstrated in collaboration with Dr Roska using optogenetic tools originated from algae or bacteria. Their ongoing studies are testing efficacy and safety of these optogenetic proteins in non-human primates prior to clinical trials.

Imaging Conference
Intel Ireland Ltd Capraro, Bernie
Capraro, Bernie

Capraro, Bernie
EU Research Programme Manager
Intel Ireland Ltd

Biography
Bernie Capraro - Intel Ireland EU Research Programme and Project Manager Bernie received a Masters Degree in Engineering(MEng)with Distinction from Newcastle upon Tyne Polytechnic and has been working at Intel for the past 17 years holding various Engineering and Management roles across all four wafer fabrication facilities. Bernie is currently responsible for all silicon nanotechnology EU projects involving Intel Ireland, delivering potential solutions for materials, equipment and processing techniques required for the future technology nodes. Bernie's semiconductor career spans 27 years, with other Process and Equipment Engineering positions held at Telefunken GmbH, Nortel/Bell Northern Research, Applied Materials and Newport Wafer Fab.

450mm
Interposers GmbH Kaiser, Thomas
3D-printed Interposer as an intermediate layer for the 3D integration of micro electronic components
Kaiser, Thomas

Kaiser, Thomas
CEO
Interposers GmbH

Abstract
With the increasing importance of mobile electronics, the form factor is increasingly important. This leads to more and more functions and silicon chips being integrated into even smaller volumes. This mega trend means that the electronic components are no longer contiguous but are arranged in stacks. This presents a particular challenge due to the fact that the stacked components have different geometric dimensions and their contact surfaces are also very different. Interposers is offering an enabling technology built on own IP. A method of printing of functional structures applied directly to a wiring layer on the surface of a device that allows electrical contact to the next component. The connections between the chips to be stacked is printed on the finished wafer or on the individual component (chip) in the form a multilayered sequence. The IP of the technology is based upon a newly invented printing technology in combination with as of late available conductive nano ink to quasi assemble 3D-Micro electronic components in print technology by using a printed interposer, also known as link layer between 2 Si-chips. During several month of a prototype-phase a compound of an ASIC-chip and a sensor-chip was built. Applications of such a stacked-die can be future medical- and bio-sensor components and furthermore mobile devices. Example of applications are micro pacemakers, Cochlear hearing implants, blood glucose sensor, acceleration analysis systems, etc. all on Si-based chips or components.

CV of presenting author
Thomas Kaiser, Founder and CEO of Interposers GmbH. The company was founded 2012 and is holding IP for an enabling technology for 3D-printed interposer for mainly packaging and stacking heterogeneous Si-chips or wafers.

Advanced Packaging Conference (APC)
IOF Bräuer, Andreas
Bräuer, Andreas

Bräuer, Andreas
Director Micro Optical Systems
IOF

Biography
Braeuer graduated in physics in 1978 (PhD) at University of Jena (Germany) in the field of Solid State Physics. Since 1986 he is working in the field of microoptics. He contributed to the investigation of linear and nonlinear effects in waveguides, mainly realized in polymers like PPV or ORMOCER's. His particular interest was devoted to waveguide arrays and the demonstration of specific dispersion phenomena. Later on he was more engaged in free-space microoptics. He is currently head of the Department of Micro-Optical Systems at the Fraunhofer Institute for Applied Optics and Precision Engineering (IOF) in Jena, Germany. Main topics of research and development are new principles of LED and semiconductor laser based illumination systems using micro- and nanooptical technologies as well as new imaging microoptical systems. He is engaged in both, single channel microoptical imaging as well as new principles of insect-inspired imaging with multichannel systems. All these activities are devoted to applied research. He is author and co-author more than 120 papers in scientific journals and of more than 90 papers on international conferences.

Imaging Conference
ISORG Jamet, Laurent
Image sensors in organic and plastic electronics for Industry 4.0 and Internet-Of-Things
Jamet, Laurent

Jamet, Laurent
Co-Founder, Director Business Development
ISORG

Abstract
ISORG has developed disruptive technology of large area image sensors and photonic sensors in printed electronics based on latest developments of organic materials. These sensors on plastic offer unique benefits for easy mechanical integration (thin, light, conformable), cost and performances (operating in visible and near infra-red). Applications for inventory control, process control, equipment monitoring, user interfaces and x ray imaging will be exposed. ISORG is the pioneer company for optical sensors in organic electronics, with their pilot manufacturing line already operating in Grenoble.

CV of presenting author
Co-founder and Director of Business Development of ISORG Graduated from INPG Grenoble (electronics engineering school) and from Grenoble Business High School (DESS of international business). He joined STMicroelectronics at Grenoble in 1990 as designer. Quickly he handled various positions within ST as Marketing Manager for the Analog Products dedicated to wireless terminals, and then he became Business Development Director for his major customer Nokia. At the same time he was managing the development of new technologies for Nokia, including technologies developed internally by ST and transferred externally by research organizations and international start-ups. In 2007, he was named Business Development Director for Smart Textiles at SOFILETA (Bourgoin-Jallieu). He joined the CEA LITEN in 2010 as project manager for ISORG creation.

Plastic Electronics - PE2014
Imaging Conference
J To top
JEM Europe Mai, Joe
Trends in Wafer Probing: Challenges and Solutions
Mai, Joe

Mai, Joe
Managing Director
JEM Europe

Abstract
Successful semiconductor manufacturing is increasingly dependent on test at the wafer level. Some of the main reasons are: - To avoid the cost and delay of packaging bad devices; - To eliminate final handler test in cases such as WLCSP or known-good-die (KGD); - To obtain device characterization; - To provide in-line, or end-of-line, feedback for process-control; - To increase test parallelism for higher productivity However, new device, packaging, and system-integration trends pose numerous challenges for wafer probing. For example: - Shrinking device sizes, low-k dielectrics, and high test parallelism require high-accuracy, low-force probing; - Sensors require physical stimuli, such as light, pressure, magnetic fields, or motion, in addition to electrical inputs; - Automotive devices (including sensors) require tests over a wide temperature range; - Higher currents require new probe materials; - Cu-pillar interconnects require advanced probe cards to avoid pillar damage and to achieve high densities; - Full-wafer probing (contacting all devices on the wafer simultaneously) is required for low-margin, high-volume devices; This presentation will attempt to describe the major trends and challenges in wafer probing, and how the probe card industry has responded.

CV of presenting author
Joe Mai is managing director of the European subsidiary of Japan Electronic Materials (JEM), a leading probe card supplier, for whom he's worked nearly 20 years, playing both technical and management roles in the US and Europe. His technical experience includes R&D, product development, PCB design, automation equipment, and applications engineering. During these past two decades, he has worked closely with many wafer fab customers to improve their test capabilities and develop JEM's technologies. He is also a program committee member for the SEMI European Manufacturing Test Conference (EMTC).

16th European Manufacturing Test Conference (EMTC)
Joanneum Research Forschungsgesellschaft mbH Stadlober, Barbara
High performance organic electronics fabricated by self-aligned lithography on large scale
Stadlober, Barbara

Stadlober, Barbara
Head of department
Joanneum Research Forschungsgesellschaft mbH

Abstract
Miniaturization is the success strategy of the Silicon world and the enabler of today's ultrafast highly integrated electronics universe - adopting the same strategy to organic and large area electronics, fascinating with its unrivalled form factor and multifunctionality, will boost the still lagging performance of OLAE devices. For most applications in the field of internet of things, industry 4.0, lab-on-foil or food safety, where OLAE should have a strong homebase in principle, it is absolutely necessary to increase the bandwidth and speed of organic field effect transistors (OFET) and circuits. Accordingly, aggressively decreasing the critical dimensions in OFETs is a major prerequisite for the next generation of OLAE circuits. In this presentation all aspects of downscaling the dimensions of OFETs will be discussed under the guideline of proper scaling and future-oriented solutions will be presented, ranging from patterning strategies for decreasing the channel length and interlayer electrode overlap areas by self-aligned nanoimprinting, over the usage of novel crosslinkable dielectric materials that allow reliably decreasing their layer thickness to only some tens of nanometers without corrupting the isolation strength to large-area compatible concepts for minimizing the contact resistance. By exploiting all these ideas low-voltage OFETs with remarkably high cut-off frequencies in the 10 MHz regime, as well as circuits with high gain (> 100) and large noise margin (> 80% of Vsupply/2) were realized. Finally, it will be demonstrated, how the presented self-aligned process and the novel material concepts are transferred to large-area, high throughput roll-to-roll manufacturing.

CV of presenting author
Dr. Barbara Stadlober is Head of the Research Group "Micro- & Nanostructuring" at the Institute of Surface Technologies and Photonics of the JOANNEUM RESEARCH Forschungsgesellschaft mbH (JR) located in Graz/Weiz, Austria. She has a background in low temperature and solid state physics, was part of the technology development team at Infineon Technologies Austria in Villach and joined JR in 2003 for building up the group "Organic Field Effect Transistors". Her current interests range from organic and printed electronics over R2R-nanopatterning to large-area physical sensors and biomimetic structures.

Plastic Electronics - PE2014
K To top
Kaleido Technology ApS Holme, Christian
All-glass wafer-level lens manufacturing technology for industrial imaging applications
Holme, Christian

Holme, Christian
Chief Technology Officer, founder
Kaleido Technology ApS

Abstract
We present our all-glass approach to wafer-level lens manufacturing. Glass remains the preferred material for imaging optical lenses for a number of reasons, including availability of a wide range of glass types, superior optical transmission as well as thermal stability. The added cost compared to injection-molded plastic lenses has so far prevented the wide-spread use of glass in cost-sensitive imaging applications including lenses for mobile phone cameras. With our proprietary wafer-level glass lens technology, we can take advantage of the advantages of glass while reducing the cost compared to conventional glass molding and polishing technologies. In this presentation, we present the key process stages in our technology including hard tool manufacturing, wafer-level lens molding and lens module stacking, and we present performance of the resulting wafer-level lenses for imaging applications

CV of presenting author
Christian Holme (45) holds a Bachelor degree in Math (1991), and a Ph.D. degree in Physics from the University of Copenhagen (1997). In 2001 he was part of the group founding Kaleido Technology, since 2010 part of AAC Technology. His main focus has been on developing ultra-precision machining and glass molding for manufacturing of wafer-level optics.

Imaging Conference
L To top
Logitech ltd Forsyth, Kirstin
Akribis-Air: A new innovation in wafer processing
Forsyth, Kirstin

Forsyth, Kirstin
Sales Manager
Logitech ltd

Abstract
Logitech Ltd are world leaders in materials processing, shaping and surface finishing technology. We specialise in the design and manufacture of high precision cutting, lapping and polishing systems which enable high specification surface finishes to be prepared with precise geometric accuracy. Logitech systems provide exacting standards of material flatness and parallelism and are used to process fibre optic, laser, opto-electronic and semiconductor materials. The Akribis-Air is the latest edition to our lapping and polishing range and offers the ultimate in intelligent, integrated and fully automated processing of wafers. We will present the full features and benefits of the Akribis System , focusing on the optimised processing of hard materials such as SiC

CV of presenting author
Kirstin Forsyth is the European Technical Sales Manager for Logitech Ltd. After graduating at the University of Strathclyde with a Masters degree in Chemistry, Kirstin worked in R&D, manufacturing and commercial roles for 6 years within the polymer manufacturing industry before joining Logitech in 2014.

Application driven technology: Nanoelectronic for Healthcare (TechARENA)
Low-Power Electronics Association & Project (LEAP), Renesas Electronics Corporation Kamohara, Shiro
Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era
Kamohara, Shiro

Kamohara, Shiro
Chief Engineer
Low-Power Electronics Association & Project (LEAP), Renesas Electronics Corporation

Abstract
Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, we describe our recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other logic circuits. Our 32-bit RISC CPU chip, named "Perpetuum Mobile," has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.

CV of presenting author
Shiro Kamohara received the B. S. degree in physics from Keio University in 1986, M. E. degree from University of Tokyo Institute Technology in nuclear engineering in 1988 and Ph.D. from Tokyo metropolitan University in electrical and electronic engineering in 2008. He joined the Central Research Laboratory of Hitachi Ltd. in 1988. Since 1995, he was the member of Semiconductor & Integrated Circuit Div. of Hitachi Ltd. He is a member of Renesas Technology Corp since 2003 and Renesas Electronics Corp since 2010. He concurrently served as Semiconductor Leading Edge Technologies, Inc (Selete) since 2006. Now he has doubled as Low-power Electronics Association & Project(LEAP). He was the visiting industrial fellow of the University of California at Berkeley in 1996.

Low Power Conference
M To top
MCRT GmbH Dobler, Maximilian
Minienvironments: flexible solutions
Dobler, Maximilian

Dobler, Maximilian
Sales Manager
MCRT GmbH

Abstract
Minienvironments are localized solutions to generate a defined surrounding for a given process. This could be related to cleanliness, but could also include temperature and humidity control or special atmospheric conditions for sensitive materials. How a minienvironment is designed and build depends on the specific requirements of the process and the given surrounding. Based on the increasing degree of automation the concept of the minienvironments is widely used in semiconductor manufacturing and becomes more and more important as enabling technology for future developments like 450 mm wafers, EUV lithography and organic materials.

CV of presenting author
Maximilian Dobler: Short Biography Born: 13.04.1967, Munich, Germany University: 1994 Degree in Physics, Ludwig-Maximilian-University, Munich, Germany PhD-Thesis: 1994 - 1998, Research Centre Dresden (Germany), Institute of Ion Beam Physics and Material Sciences, subject: silcide formation and charaterisation, 1998 Degree from Technical University Dresden Post Doctoral Position: 1998 - 1999, Research Centre Dresden (Germany), Institute of Ion Beam Physics and Material Sciences, subject: semiconductor material characterisation Atomika Instruments GmbH (Munich, Germany): 1999 - 2000, Application Engineer, subject: trace contamination measurements with TXRF (Total reflection X-Ray Fluorescence Spectroscopy) Leica Microsystems Semiconductor GmbH (Wetzlar, Germany): 2001 - 2002, Application Engineer, subject: optical thin film measurement and characterisation with spectral photometry and ellipsometry 2002 - 2008, Product Manager, subject: optical inspection and review systems MCRT (Micro CleanRoom Technology) GmbH (Giessen, Germany): 2009 - today, Sales Manager, subject: cleanroom and minienvironment solutions

Fab productivity (TechARENA)
memsstar Limited Connock, Peter
Connock, Peter

Connock, Peter
Chairman
memsstar Limited

Biography
Peter Connock has been working in the semiconductor industry for over 30 years with positions in development, customer service, marketing and management at Edwards, Applied Materials and memsstar. His current role, Board Chairman at memsstar, has involved both operational and strategic activities in the global MEMS market and European secondary equipment industry. Peter has complemented his operational activities by establishing a long-term relationship with SEMI - serving on SEMICON, ISS and now the SEA committees for many years. As well as working with memsstar Peter is closely involved in the ENIAC & ECSEL EU funding programme for technology with special responsibility, as part of the AENEAS industrial association, for encouraging SME involvement in EU funded projects. Peter specialises in working with SME's at Board level in strategic marketing and business development. He is currently on the Board at several SME's and industrial organisations.

Secondary Equipment (TechARENA)
Microelectronic Packaging Dresden GmbH Steinhof, Falk
Packaging of integrated optical sensor systems
Steinhof, Falk

Steinhof, Falk
Key Account Manager
Microelectronic Packaging Dresden GmbH

Abstract
The article presents with actual state of the art samples the requirements in technology and material to fulfill customer demand in quality and accuracy for the production of these optical sensor systems. Starting with layout and (FR4) board concept, die bonding, wire bonding and optical glass mounting and implication of these steps to system performance and electrical as well as optical characteristics will be discussed. It will be demonstrated how optimization in technology and material selection as a system concept results in a stress relieved, controlled optical system. The demonstrator is a 16 die optical sensor array with 250 µm thick dies on a 6 layer COB substrate (one side complete SMD mounted), covered by 100 µm glass with goal of system warpage less than 50 µm. Die placement accuracy < 25 µm with 800 µm bonding street (Al wedge bonding) and 50 µm chip to chip without w/b. Future work: System change from COB with Al wedge bonding (+600 wires) to TSV technology using dies and solder ball technology.

CV of presenting author
Falk has over 30 years experience in electronic packaging and material science after he finished his study at the Technical University Dresden.

Advanced Packaging Conference (APC)
MultiXDetection Radisson, Patrick
MultiX - multi energy spectrometric X-ray detectors for various applications
Radisson, Patrick

Radisson, Patrick
Co-Founder & CTO
MultiXDetection

Abstract
MultiX is a technology start-up that designs, produces and sells advanced spectrometric X-ray detectors, used for the identification of materials in general, non-destructive testing (NDT) and the detection of explosives in luggage and packages in particular. The company was created in October, 2010 by Jacques Doremus and Patrick Radisson, both from the Thales group, with the support of the French CEA (Atomic Energy Commission). MultiX supplies x-rays system manufacturers with ME100 x-ray detectors as part of a complete data acquisition system which upgrades current x-ray systems and allows them to perform better. The new Multi energy spectrometric x-ray detectors are also applicable to non-destructive testing(NDT) applications, such as food and waste product processing where system performance can be can also significantly improved bringing a quick return on investment.The MultiX x-ray spectrometric detector technology has proved that it brings significant improvements in performance to current x-ray systems and hence has gained acceptance within the security market. OEMs started development of x-ray security systems based on the technology..More recently NDT and in particular Food contaminant detection get opportunities with the capability to segregate efficiently raw materials. The company benefits from important partnerships with x-ray system manufacturers and CEA-Leti, a French National Laboratory, in the field of spectroscopic imaging. MultiX is also active in various French and European research and development programs.

CV of presenting author
Patrick Radisson , Co-founder & CTO, Eng. Degree in electronics (ENST Paris) + MicroElectronics advanced degree + MBA (IAE). has 30 years experience in Detection and Imaging, Microelectronics and Micro- technologies through different positions in large companies and SME. His background includes more than 18 years in solid-state infrared detectors field (SOFRADIR) through the management of the complete product cycle from development to production and through an active management of the development and industrialization of new technologies. He also managed engineering and production in emerging MEMS/MOEMS field within a french start-up (PHSMEMS). He was formerly head of Advanced Studies at THALES XRIS in X-Ray and THZ detectors field.

Imaging Conference
N To top
NANIUM, S.A. Tavares, Armando
Tavares, Armando

Tavares, Armando
President and CEO
NANIUM, S.A.

Biography
Armando Tavares is president of the Executive Board of NANIUM S.A. He has over 35 years of experience in Semiconductor Business, having worked for Texas Instruments since 1979 in several positions: Engineering Director, Quality Director and Operations Director. In 1994 becomes also Vice President of Texas Instruments / Samsung Portugal. In 1996, he moves to Siemens as Managing Director of the newly established Siemens Semiconductors site in Portugal. In 2003, he moved to France as President and Managing Director of Infineon Technologies France and later also President of Infineon Technologies Portugal. He has a Degree in Electronics Engineering from Porto University and a tailored executive MBA from the European University.

Advanced Packaging Conference (APC)
NANIUM S.A. - Niederlassung Dresden Kroehnert, Steffen
New WLP-Technology-Fusion Concept Offers Significant Advantages
Kroehnert, Steffen

Kroehnert, Steffen
Director of Technology
NANIUM S.A. - Niederlassung Dresden

Abstract
NANIUM has developed a new advanced packaging solution for classical Fan-In WLP/ WLCSP, applying its leading edge Fan-Out WLP/ eWLB knowledge and HVM capabilities. Independent of the incoming wafer diameter, a new standardized 300mm reconstituted mold wafer is built with the Known-Good Dies (KGD) of those incoming wafers only. The dies are placed with very small distance to each other. That way two 200mm wafer or even four 150mm wafer can be WLP processed on one reconstituted 300mm mold wafer. This is giving significant cost advantage, depending on the incoming wafer diameter and die size. This new WLP-Technology-Fusion concept is called FIMP (Fan-In with Mold Protection), as the Fan-In/ WLCSP dies will have molded backside- and sidewall protection around the die after final package singulation, which makes it more robust for handling and operation. All the routing and bumps are placed on the die itself, so it remains a Fan-In WLP/ WLCSP solution. The molded sidewall protection in fact could be seen as very small Fan-Out area, which in that case is not used for routing and bumping. Besides the cost aspect, the FIMP concept is important for advanced CMOS technology nodes using Low-k and ULK materials. Wafer probe can be applied to already singulated dies, now embedded in the reconstituted mold wafer. This allows to test also for Si wafer dicing fails, which are more critical in advanced CMOS technology nodes, requiring new dicing methods like laser grooving. This has been possible so far only by expensive and inefficient WLCSP bare die handling and testing. Final package singulation of the reconstituted mold wafer is done by dicing of mold compound, while the singulated and tested Si die is protected.

CV of presenting author
Dipl.-Ing. Steffen Kröhnert received his master degree in Electrical Engineering and Microsystem Technology at Technical University of Chemnitz, Germany, in 1997. In the same year he started his professional career as Development Engineer in the Corporate Package Assembly, Interconnect and Test Development Center for Semiconductors of Siemens AG in Regensburg, Germany. After carve out of the Semiconductors Business Unit to Infineon Technologies AG in 1999, he worked as Project Manager and moved to Infineon Dresden GmbH & Co. OHG in 2002 to support local setup of Package Development Department for Memory Products. He became R&D Area Manager Component Development and took over Technology Platform ownership for FBGA products. From 2006 he was working as Senior Manager in Qimonda Dresden GmbH & Co. OHG, the carve out of the Memory Products Business Unit of Infineon Technologies. Begin 2007 he was assigned to Qimonda Portugal S.A. to setup and lead Package Development team at volume production site. Since 2009 he is Director of Technology at NANIUM S.A. in Vila do Conde, Portugal. Steffen is author and co-author of 23 patent filings in the area of Packaging Technology. He is member of IEEE CPMT, MEPTEC, SMTA, VDI, VDE and GPM. He contributes as Technical Committee member to SEMI Europe Advanced Packaging Conference (APC) and Electronics System Integration Technology Conference (ESTC).

Advanced Packaging Conference (APC)
Exhibitor Presentations: Packaging (TechARENA)
Nasiri Ventures Nasiri, Steve
Building Successful MEMS Company: From Start to IPO
Nasiri, Steve

Nasiri, Steve
Principal
Nasiri Ventures

Abstract
Mobile and wearable markets along with internet-of-things have presented large market opportunities for emergence of many MEMS startup companies. However, these markets can be very slow in adoption of new products or features unless there is real value or competitive advantages. Realizing the market dynamics and differentiating between market drivers and market followers is crucial to resource constrained startup companies. It is also important for startups to recognize challenges and time required with design and development, commercialization, and customer design-in cycle which often time are under estimated or ignored. Start-ups tend to focus most of their efforts on delivering the first working demo while neglecting crucial tasks for commercialization. This has been one of the main reasons for many false starts by MEMS start-up companies and leading early failures or longer than expected time to revenue. This talk addresses the topics presented above and also provides a case study for InvenSense from its startup phase in 2003 to its IPO in 2011. We will Review the company's strategy for developing a new class of consumer MEMS motion processing solutions based on all new and disruptive fabrication platform.

CV of presenting author
Steve Nasiri, Nasiri Ventures LLC, Nasiri Foundation InvenSense Inv. (2003-2012), Founder, CEO, Chairman Over the past 35 years, Mr. Nasiri has been a serial entrepreneur in Silicon Valley. His most recent and successful venture was InvenSense, which he founded in 2003 and served as the President, Chief Executive Officer and Chairmen since its inception until October of 2012. Under his leadership, the company became the pioneer and global market leader in motion tracking solutions for motion-based user interfaces in consumer electronic including smartphones, tablets, game consoles, wearable electronics, and more. In November 2011, Mr. Nasiri took the company through the initial public offering (IPO), listed on the New York Stock Exchange (NYSE) under the symbol INVN. Prior to founding InvenSense, Mr. Nasiri held various key positions as a co-founder and or executive of several pioneering startup companies, including SenSym (acquired by Honeywell), NovaSensor (acquired by General Electric), Integrated Sensor Solutions (acquired by Texas Instruments), ISS-Nagano GmbH, Intelligent Sensing Solutions (acquired by Maxim Integrated), and Transparent Optical Networks. Mr. Nasiri has been the inventor and co-inventor in over 80 patents and patent applications, and has authored many papers and articles in MEMS. In 2010, he was selected by Ernst & Young as Entrepreneur of the year for Northern California and in 2013 he was given Alumni Awards of Distinction by San Jose State University. Mr. Nasiri earned an M.B.A. from Santa Clara University, a M.S. in Mechanical Engineering from San Jose State University and a B.S. in Mechanical Engineering from the University of California, Berkeley.

International MEMS Industry Forum
National Center for Scientific Research DEMOKRITOS Dimoulas, Athanasios
Epitaxial MoSe2 semiconductor heterostructures on AlN/Si(111) substrates
Dimoulas, Athanasios

Dimoulas, Athanasios
Research Director
National Center for Scientific Research DEMOKRITOS

Abstract
Two dimensional (2D) semiconductors such as transition metal dichalcogenides (TMD) offer ultimate thickness scaling down to the single layer limit for low power versatile nanoelectronics. TMDs have already demonstrated their potential in electronics since generic ICs of the type used in CMOS have been fabricated [1]. However, most of these advancements have been made on small flakes exfoliated from bulk materials. For real world applications, materials must be epitaxially grown in thin film form on large area engineered substrates on silicon to demonstrate a scalable manufacturing. The availability of high quality 300 mm MOCVD grown AlN/Si(111) substrates already developed for III-Nitride lighting and power devices creates the prospect that 2D semiconductor devices and circuits can be manufactured in a Si compatible processing flow for future volume production. In this work, the first atomically thin MoSe2 layers grown by MBE on AlN(0001)/Si(111) substrates are reported. The growth optimization procedure monitored by electron diffraction, XRD, XPS and HRTEM will be reviewed emphasizing on the influence of the substrate on the physical properties. It will be shown that high quality single crystal MoSe2 can be obtained on nearly lattice matched AlN with abrupt crystalline interfaces. The quality is further improved using epitaxial Bi2Se3 buffer layers despite the large mismatch between the two materials. Using electronic valence band imaging by in-situ ARPES, it is shown that single layer MoSe2 directly deposited on AlN has a direct band gap making it suitable for optoelectronic applications. First results on planar FETs will be presented emphasizing on the immunity to short channel effects in <100 nm devices. Finally, excellent quality multilayer heterostructures of MoSe2 with Bi2Se3 topological insulator and other selenide compounds are grown showing the prospect for novel vertical transport devices. [1] e.g. B. Radisavljevic et al., ACS Nano 5, 9934 (2011).

CV of presenting author
Dr. Dimoulas obtained his Ph.D in Applied Physics from the University of Crete in Greece in 1991 on MBE heteroepitaxial gowth and characterization of GaAs and related compounds on Si. He was Human Capital & Mobility Fellow of the EU at the University of Groningen in Holland until 1994, a Research Fellow at the California Institute of Technology (CALTECH), Chemical Engineering, Pasadena USA until 1996 and Research Associate at the University of Maryland at College Park (UMCP) USA, until February 1999. In addition, he was visiting research scientist at NRL, Washington DC in 1992 and at IBM Zurich Resarch Laboratory, Switzerland in 2006 and 2007. Since 1999, he is Research Director and head of the Epitaxy and Surface Science laboratory at the National Center for Scientific Research DEMOKRITOS, Athens, Greece. He has coordinated several European-funded projects in the areas of advanced CMOS, the last being DUALLOGIC- a flagship CMOS project in FP7 and he is now leading the EU project 2D NANOLATTICES on silicene and other 2D crystal channels for post CMOS applications. Also, he has received the prestigious ERC (IDEAS) 2011 Advanced Investigator Grant -SMARTATE on smart gates for "green" electronics and the Greek Excellence (ARISTEIA) project TOP-ELECTRONICS. He has authored or co-authored more than 120 technical presentations in refereed journals including 3 monographs in Springer book chapters on high-k gates on Si and high mobility channels. In addition, he has more than 70 presentations in conferences including 30 invited in conferences, tutorials and summer schools. He has more than 2000 citations and an h-index of 27. He is co-editor in a Springer book and guest editor in three special volumes of international journals. He has organized MRS and E-MRS symposia in 2005, 2003, 2009, 2010 and 2013. He was the general chair of INFOS 2007 conference and he is in the steering committee of INFOS and ESSDERC/ESSCIRC conferences and he has chaired the TPC committee of ESSDERC/ESSCIRC 2007 and the IEDM 2012 Process Technology subcommittee. His expertise includes MBE growth of semiconductors and dielectric materials, VCD growth of graphene, nanodevice processing by optical and e-beam lithography materials structural and physical characterization & device electrical characterization.

2D (TechARENA)
New Imaging Technologies Potet, Pierre
New Developments on CMOS Logarithmic Image Sensor
Potet, Pierre

Potet, Pierre
CEO
New Imaging Technologies

Abstract
In this talk, I would like to present some new developments on CMOS logarithmic image sensing devices. The logarithmic law image sensing devices have a lot of advantages over classic linear law image sensing devices. Since long time, logarithmic sensors suffered from high FPN, image lag and other drawbacks. We believe that logarithmic law sensing method, universally used by all the biological vision systems on this earth, could be improved and reach the same image quality as today's CMOS 4T active pixel based sensors. The solar-cell mode photodiode based logarithmic sensing technology developed by NIT has overcome some of these drawbacks. I will present theoretical and technical details of this technology, highlight the advantages and shortcomings, which include temperature effects, noise performance, etc. Finally I give a glance at some new developments and extensions around this technology inside NIT.

CV of presenting author
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Imaging Conference
Nikkoia Jutant, Alain
Imaging applications based on organic materials
Jutant, Alain

Jutant, Alain
President &CEO
Nikkoia

Abstract
Organic materials have been mainly used in Photovoltaics and OLED so far. A new sensor technology based on organic materials and thin film processes is available from NikkoIA to replace at lower cost some existing large area image sensors and to enable new CMOS image sensor sensitive not only in the visible and the near-infrared but also in the short wave infrared (beyond the cut-off of the silicon). This paves the way for new imaging and vision applications to be reviewed during the presentation.

CV of presenting author
Before being President of NikkoIA SAS, Alain Jutant handled successively several positions as CEO and VP business development of a startup company, director of business development for Asia and product line director in stock-listed companies, director of Innovation and Strategy and industrial Marketing manager in subsidiaries of large industrial corporations. He has 28 years background experience in semiconductors and visible, X-ray and infrared image sensors acquired on many different professional markets (medical, industrial, graphic arts and digital photography) as well as mobile phone, computing, automotive, security and consumer markets. Alain has developed a vast network in such markets and has also a strong knowledge in company operational organization and management by projects, in 3-5 years strategic development plan, in investor relationship management, in R&D collaboration program and strategic alliance set-up as well as in sales contract and legal negotiation. Alain JUTANT graduated from Ecole Centrale de Lyon in 1985 with a degree in electronics and microelectronics.

Imaging Conference
Nokia Ryhänen, Tapani
Graphene in Flexible Electronics
Ryhänen, Tapani

Ryhänen, Tapani
Head of Business Line
Nokia

Abstract
The combination of outstanding chemical, electrical, optical, mechanical and thermal properties of graphene makes it an interesting new material for a multitude of applications in flexible and printed electronics. The key trends and drivers in flexible electronics are discussed, and the recent progress in flexible device manufacturing is presented. The applications of graphene and 2D materials in flexible electronics summarised. A short description of the flexible electronics work in the EU Graphene Flagship is given. Nokia's work in applying 2D materials to flexible electronics is described by examples in sensor and battery technologies. Finally, the commercial and technical challenges in productising graphene technologies are discussed. References: (1) S.Borini, R.White, Di Wei, M. Astley, S. Haque, E. Spigone, N. Harris, J. Kivioja, and T. Ryhänen, Ultrafast Graphene Oxide Humidity Sensors, ACS Nano, 2013, 7 (12), pp 11166-11173. (2) Di Wei et al., Ultrathin rechargeable all-solid-state batteries based on monolayer graphene, J. Mater. Chem. A 1 , 3177 (2013). (3) Di Wei, M.R.Astley, N.Harris, R.White, T.Ryhänen, and J. Kivioja, Graphene nanoarchitecture in batteries, Nanoscale, in press.

CV of presenting author
Tapani Ryhänen is heading Nokia Technologies Business Unit's Sensor Systems Business Line that operates in Cambridge and Espoo and focuses on high added-value solutions for customers' measurement problems, based on innovative sensors, ultra-low power signal and information processing, algorithms, and wireless connectivity. Before his current role he was leading Nokia's research in sensor and material technologies, especially focusing on various applications of nanotechnologies. His is one of the creators of the Nokia Morph concept and an author and editor of a book "Nanotechnologies for Future Mobile Devices". He is a member in the Scientific Advisory Committee of the EU Graphene Flagship Project, advices the X PRIZE Foundation on its Nokia Sensing X Challenge for revolutioning digital healthcare, and is a board member of the Nokia Foundation.

Plastic Electronics - PE2014
NovaCentrix Rawson, Ian
Commercialization Case Study: Implementation of Copper Oxide Conductive Ink with Photonic Curing for Production RFID in Integrated High-Volume Production
Rawson, Ian

Rawson, Ian
Sr. Development Engineer
NovaCentrix

Abstract
In a data-supported discussion, the speaker will present experiences and lessons learned in transitioning recent new materials and processing technologies into high-volume manufacturing. Specifically, in May at a formal launch event in Roding, Germany, RFID-equipment leader Muhlbauer debuted the world's first fully-qualified RFID production system integrating low-cost copper-oxide reduction ink and high-speed photonic curing tools. To cross the technology "valley of death", much work was done to evolve these technologies and collaboratively pass developmental hurdles. Key challenges which will be discussed included establishing batch-to-batch material consistency, achieving and repeating unit cost goals, meeting strict environmental exposure and reliability requirements, and transitioning the technology know-how to new users, with engineering teams based a continent apart. The presenter will include examples of "final mile" technology iteration, the need for which became apparent only in the integration and scale-up stages.

CV of presenting author
Ian Rawson is a senior development engineer at NovaCentrix focused on commercialization of PulseForge equipment and Metalon conductive inks. He began at NovaCentrix as a researcher focusing on RFID, display, battery, solar and lighting opportunities in printed electronics. He received a Bachelor of Science degree in Mechanical Engineer at Texas A&M university in 2008.

Plastic Electronics - PE2014
NUS Alioto, Massimo
Enabling the IoT through ultra-low voltage operation: down to the threshold and below
Alioto, Massimo

Alioto, Massimo
Prof.
NUS

Abstract
The demand for smaller integrated systems with significant computation-ability is driving a massive shift towards extremely compact energy-autonomous systems (e.g., wearable electronics, Internet-of-Things). Their size scaling is well-known to be limited by their energy efficiency, hence aggressive voltage downscaling is a forced choice in such applications, with voltages being pushed down to near-threshold (and sometimes even below). This talk addresses the fundamental issues entailed by the operation at near-threshold and below and related solutions. Due to the significantly different performance/energy/resiliency/leakage design tradeoff at ultra-low voltages, this talk provides a fresh view on near-threshold circuits (and below) and debunks several wrong assumptions stemming from traditional low-power common wisdom. In particular, design techniques that do (or do not) work at ultra-low voltages are discussed for logic and memory arrays. Also, near-threshold automated design flows and design hints for critical sub-systems (e.g., clock distribution) are discussed. To put things in perspective, design trends at near-threshold and below are discussed, including fine-grain voltage distribution/power gating, heterogeneity, specialization, among the others. Finally, the availability of designers with across-level expertise (e.g., circuit/architecture, architecture/software) is envisioned to be a fundamental necessity to truly enable the energy benefits promised by ultra-low voltage operation.

CV of presenting author
Massimo Alioto is Associate Professor at the Department of Electrical and Computer Engineering, National University of Singapore. Previously, he was Associate Professor at the University of Siena, Visiting Scientist at Intel Labs - CRL (2013), Visiting Professor at the University of Michigan - Ann Arbor (2011-2012), University of California - Berkeley (2009-2011) and EPFL - Lausanne. He is (co)author of 200 publications on journals (70, mostly IEEE Transactions) and conference proceedings, and two books. His primary research interests include ultra-low power VLSI circuits, self-powered and wireless nodes, near-threshold circuits for green computing, error-aware and widely energy-scalable VLSI circuits, circuit techniques for emerging technologies. Prof. Alioto was the Chair of the "VLSI Systems and Applications" Technical Committee of the IEEE Circuits and Systems Society (2010-2012), and Distinguished Lecturer (2009-2010). He is currently Associate Editor in Chief of the IEEE Transactions on VLSI Systems, and served as Guest Editor of several journal special issues. He also serves or has served as Associate Editor of a number of journals (including ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on CAS - part I). He serves or has served as panelist for several funding agencies and research programs in the US and Europe. He was Technical Program Chair of the ICECS 2013, NEWCAS 2012 and ICM 2010 conferences, and Track Chair in a number of conferences (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM).

Low Power Conference
O To top
Oclaro Technology Ltd. Wale, Michael
Low-Cost Access to Advanced Photonic Foundry Processes in InP
Wale, Michael

Wale, Michael
Director Active Products Research
Oclaro Technology Ltd.

Abstract
Photonic integrated circuits (PICs) provide a highly efficient means of realizing complex optical and opto-electronic functions in monolithic form. PICs in indium phosphide (InP) can provide a particularly complete set of functions, including optical amplification, laser operation, modulation, signal routing, wavelength multiplexing and detection, in arbitrary combinations. Over the last decade, European researchers and manufacturers have established generic platforms for InP PICs, based on libraries of standard (parameterized) building blocks and standard manufacturing processes, defined by process design kits (PDKs) and supported by sophisticated design tools . In this way access to PIC technologies becomes much more straightforward and less expensive, as a single platform now serves the needs of many users and applications; furthermore the standard process and building blocks facilitate the execution of multi-project wafer runs, further reducing development and prototyping costs. This route was pioneered in the silicon microelectronics industry 30 years ago but in optics the concept is still very new. More than 100 application-specific PICs have been successfully designed and fabricated on the platforms supported by the Joint European Platform for InP-Based Photonic Integrated Circuits (JePPIX) and the underlying platforms are now emerging from the research phase into commercial operations. The paper will review the current status of generic PIC platforms in InP and give pointers towards future developments.

CV of presenting author
Prof. Michael Wale is Director Active Products Research at Oclaro, a major supplier of photonic components for the global optical communications market, based at Caswell, Northamptonshire, UK. Mike received his B.A., M.A. and D. Phil. degrees in physics from the University of Oxford. Since moving into industry in the early 1980s, he has been involved in many different aspects of research, development and manufacturing of photonic devices and systems, with particular emphasis on photonic integrated circuit technology. Alongside his role at Oclaro, where he has responsibility for strategic technology activities, he is Professor of Photonic Integration/Industrial Aspects at Eindhoven University of Technology, The Netherlands, and an Honorary Professor at the University of Nottingham in the UK. Prof. Wale is a member of the Executive Board of the European Technology Platform, Photonics21, and chairman of its Working Group on Design and Manufacturing of Optical Components and Systems.

Silicon Photonics (TechARENA)
Oxford Instruments Bourke , Michelle
Leading Techniques for the Nano-scale Etching and Deep Etching of Silicon
Bourke , Michelle

Bourke , Michelle
Business Group Director
Oxford Instruments

Abstract
As Micro Electro Mechanical Structures (MEMS) are adopted in more and more commercial and industrial applications some areas look to the nano world for developing technologies. In this paper the two leading techniques for deep etching of silicon, namely the "Bosch" process and a cryogenically cooled process will be discussed. We will update the latest results for these techniques and also look at the growing importance of nano-scale etching of silicon, which can be achieved consistently using the cryogenically cooled process. The paper will also briefly discuss atomic layer deposition (ALD) and demonstrate the role it can play in advanced micro and nano devices.

CV of presenting author
Michelle Bourke, Business Group Director, Oxford Instruments Plasma Technology Michelle M. Bourke received a B.Sc. degree in Optoelectronics and Laser Engineering from Heriot-Watt University, Edinburgh, Scotland, U.K., in 1993. Subsequently she joined the Defence Evaluation and Research Agency (DERA), where she worked on advanced processing methods for GaAs/AlGaAs optoelectronic devices. Joining Trikon Technologies in 1997 as an etch engineer she developed technologies for <0.25µm processes for advanced silicon technologies and a variety of different compound semiconductor processes. In 1999 she moved into Product Marketing and after 2 years transferred to Ottawa as North American Product Marketing and Sales Support Manager. Joining STS plc in 2003 as a Product Marketing Engineer, she was promoted to Product Marketing Manager in 2004 and then to Business Development Manager in 2006. In 2010 Michelle joined Oxford Instrument Plasma Technology as a Senior Product Manager, where she is now Business Group Director.

Exhibitor Presentations: MEMS (TechARENA)
Oxford Instruments Cooke, Mike
Early production testing of 450mm process modules
Cooke, Mike

Cooke, Mike
CTO
Oxford Instruments

Abstract
The extending timescales for 450mm introduction are causing delays and doubt in the 450mm equipment community. A twin track development approach is proposed that looks for other markets with complementary requirements for some process modules. This enables some of the process scaling to 450mm to be tested, including real production tests, by using single wafer 450mm tools as large scale batch tools for different markets. The possible learning from this approach is discussed, highlighting the gaps that will remain to be tested in a 450mm wafer pilot line.

CV of presenting author
Oxford Instruments has been active in several rounds of ENIAC projects to prepare for the introduction of 450mm, designing modules for 450mm plasma etch and PECVD. Mike Cooke has more than 30 years experience in plasma technology, including plasma source developments, plasma enhanced ALD, and scaling plasma tools. He is CTO for Oxford Instruments Plasma Technology, and has represented the company in European collaborations.

450mm
P To top
PandA Europe Longford, Andy
Longford, Andy

Longford, Andy
Consultant
PandA Europe

Biography
Andy Longford is Managing Partner (CEO) and Senior Consultant at PandA Europe, a technical & market Consultancy Company involved in Semiconductor chip Packaging and Electronics Interconnection. He has worked on chip package designs for a number of years and is currently involved with emerging chip package design analysis and technical support work. He is a member of a number of technical committees, including SEMI Europe (APC), and also provides Secretariat Services for IMAPS-UK.

Advanced Packaging Conference (APC)
Parrot Dorval, David
ASIC and SYSTEM tests partitioning for consumer and automotive infotainment markets
Dorval, David

Dorval, David
ASIC Operations Director
PARROT

Abstract
PARROT is developping its own ASIC products to serve customers and business units in the consumer and automotive infotainment markets. Thanks to close cooperation and aanlysis, PARROT ASIC and SYSTEM testing groups manage to balance between cost of test, quality requirements, software and hardware constraints and scalability. We will show how complementary test flows, rapid data analysis and in-depth test knowledge can help to meet our goals of rapid ramp and high test quality to better serve internal and external customers.

CV of presenting author
David has more than 20 years experience in ASIC test development, qualification and ramp-up. David started his career at Texas Instruments as a test and product engineer from 1995 to 2001. From 2002 to 2011, he worked for DIBCOM as production director and VP Operations. Since 2012, David is ASIC Operations Director at PARROT. David holds a PhD in Physics and worked on CMOS reliability modeling.

16th European Manufacturing Test Conference (EMTC)
Parrot Levy, Yannick
Power Dissipation in the Design of Consumer Products and Drones
Levy, Yannick

Levy, Yannick
VP Corp. Business Development
Parrot

Abstract
New Consumer and Robotics Devices require intense image and signal processing. Processors with 64-bits CPU and multi-core GPUs consume several Watts that need to dissipate in consumer products. New Semiconductor nodes (20, 14nm...) lead to even higher power consumption especially on the leakage side, while the need for more Embedded computation also increases. Fans, large heat sinks can no longer be the solution. Parrot, as a chip designer and user of these chips into its own products is facing new challenges that need to be taken into account for designing new consumer products. Drones are 3D mobile robots that will ultimately fly autonomously for a number of missions (mapping, agriculture, surveillance, even delivery) and will need to carry heavy processing power in very light vehicles.

CV of presenting author
Yannick Lévy is the VP of Corporate Business Development of Parrot. Yannick is responsible for investments into subsidiaries of Parrot group as well as start-ups collaborating with Parrot. He manages the business development of these companies. Previously, Yannick headed the Digital Tuner Business Unit of Parrot, renamed from DiBcom that he founded in 2000 as the CEO, and sold to Parrot in 2011. DiBcom has developed the World leading chipsets for Digital TV and Radio reception in Cars and other mobile devices, its chips are used by car makers like BMW, Mercedes, Audi, Nissan, Hyundai. Prior to DiBcom, Yannick graduated from Supélec in 1991 and obtained his Ph. D. in Electrical Engineering in 1994 from the University of Notre Dame, U.S.A. He held several positions in R&D, Sales and Management at Sagem, SES Astra and Atmel prior to founding DiBcom.

Low Power Conference
Particle Measuring Systems Rodier, Dan
Recent Advances and Challenges in Nanoparticle Monitoring for the Semiconductor Industry
Rodier, Dan

Rodier, Dan
Technology Development Manager
Particle Measuring Systems

Abstract
As presented in the International Technology Roadmap for Semiconductors (ITRS), one of the key challenges facing the yield enhancement community is the determination of process stability vs. absolute contamination levels. This requires data for correlating defects caused by the wafer environment and wafer handling to yield. Ultimately, this will require data to determine control limits for contamination in air, gases, chemicals and ultrapure water. Recent advances in nanoparticle detection in air, gases, and fluids allow the wafer environment to be characterized at unprecedented levels of cleanliness. Data will be presented illustrating the power of the latest contamination monitoring technology to detect nanoparticle contamination events that often occur undetected by conventional monitoring approaches. Determination of contamination in the wafer environment is the necessary first step toward understanding and reducing defects caused by the wafer environment.

CV of presenting author
Dan Rodier is Technology Development Manager at Particle Measuring Systems. He has a Ph.D. in analytical chemistry from the University of Colorado and has over 23 years of experience developing and implementing technologies and strategies to measure airborne molecular species and particulate contamination. Dr. Rodier has four patents for microcontamination monitoring technologies. He has worked with customers across Asia, Europe, and North America to implement monitoring programs in the semiconductor, aerospace, hard disk drive, and flat panel display industries.

16th European Manufacturing Test Conference (EMTC)
PEER Group Schmalz, William
An Agile Approach to Automation Software for Tool Control
Schmalz, William

Schmalz, William
Director, Global OEM Sales
PEER Group

Abstract
As fabs strive for more productive manufacturing processes, OEMs are forced to become more agile in the deployment of their tools. In the old paradigm of tool automation and control development, this requirement for agility causes tension between cost-effective tool development and long-term maintainability. We are presenting our suite of off-the-shelf tool automation development products architected specifically for the semiconductor tool maker to enable agility and cost-effective maintainability. Using our products, OEMs can meet the fab's needs for productive manufacturing, while reducing turnaround times, time to market, and cost of ownership. Learn how PEER Group's product team has designed our OEM product suite to help tool builders become more agile and cost effective at developing and supporting next-generation tool development.

CV of presenting author
PEER Group provides factory automation software solutions and consulting services to wafer fabs, assembly plants, and equipment suppliers, facilitating the fastest time to market at the lowest cost of ownership in the semiconductor industry. As Director, Global OEM Sales, Bill leads PEER Group's global OEM sales and distribution organization across North America, Europe, and Asia. Since joining The PEER Group Inc. in 2002, Bill has been instrumental in building the company's software product and services position in the semiconductor equipment manufacturer (OEM) market. He helped drive a new cost effective perspective on the way OEMs looked at developing automation software, creating a new business area for PEER Group in equipment automation software.

Fab productivity (TechARENA)
PEER Group GmbH Arnold, Michael
Arnold, Michael

Arnold, Michael
Managing Director
PEER Group GmbH

Biography
Dr. Michael Arnold has been responsible for overseeing PEER Group´s European operations since the inception of the German office in 2003. As a hands-on leader, Michael is the account manager for several of PEER Group's top customers. He has served as a member of the SEMICON Europe technical program committee since 2009. Prior to joining PEER Group, Michael was the operations manager of TRW's European Manufacturing Solution Business Unit in Dresden, Germany. Before this he worked for a variety of companies, developing product software solutions and implementing industrial vision systems and factory automation solutions for European productions sites. Michael holds a Diploma degree in Physics and a Ph.D. from the Friedrich-Schiller University Jena.

Fab productivity (TechARENA)
Philips Research Cennini, Giovanni
What to plasticize and what not (yet) to plasticize? A general lighting application perspective
Cennini, Giovanni

Cennini, Giovanni
Research Program Officer
Philips Research

Abstract
Recent advancements in flexible plastic electronics suggest that we are at the onset of high-volume applications. Significant improvements have been made in efficacy, yield, quality and lifetime of OLED light sources and the first flexible lighting applications have been realized. But also organic electronic circuits have been demonstrated while various manufacturing technologies are being investigated. But is this technological progress sufficient for success? In order to move from technology demonstrators to commercial breakthrough we have to consider many more success factors. This presentation will address a number of key success factors from a general lighting application perspective, such as architectural 'separation of concerns', requirements to drive volume, killer application identification, and moving targets in performance and cost. Even hybrid integration has not only opportunities, but a number of challenges ahead.

CV of presenting author
T B A

Plastic Electronics - PE2014
Pixalys Rommevaux, Philippe
Specialized Design House for High Performances CMOS Image Sensors
Rommevaux, Philippe

Rommevaux, Philippe
CEO & President
Pixalys

Abstract
Pyxalis (Grenoble-France) is a leading company in CMOS image sensors development, serving a wide range of demanding applications in markets like medical, machine vision, security, photography, aerospace and more. Today's challenges in high performance CMOS image sensors will be briefly reviewed during the presentation.

CV of presenting author
Philippe Rommeveaux is Pyxalis CEO, and has co-founded the Company in 2010 together with colleagues formerly part of e2v Grenoble. Graduated from the Ecole Supérieure d'Optique -Orsay, France- in 1993, he then pursued a PhD in display technology in collaboration with Pixtech, a start-up company. After graduation in 1998, he joined Thomson Specific Semiconductors where he worked on CCD image sensors development for earth observation. As the company successively became Atmel Grenoble and then e2v, he've managed the business development team in charge of new activities set-up, M&A and innovation. And in 2007, he was appointed general manager for Medical, Industrial and Emerging Imaging products business unit covering marketing, CMOS/CCD image sensors and systems development, product engineering.

Imaging Conference
Plasma-Therm LLC Lazerand, Thierry
Plasma dicing, A new technology to improve the overall device manufacturing ecosystem
Lazerand, Thierry

Lazerand, Thierry
Director Technical Marketing
Plasma-Therm LLC

Abstract
Plasma singulation, developed in collaboration between ON Semiconductor and Plasma-Therm is a complete shift in how die should and will be singulated. This presentation will review the current performances of this new technology compared to the existing saw and laser techniques. The dice are singulated by plasma all the way through the wafer in a parallel process with clean sidewalls and no residue. Therefore, no post process wet cleaning is required, and no fracturing or roll cleaving is necessary. With no lateral damage during plasma dicing, and the ability to singulate any shape or form, plasma dicing offers the unique possibility to round the die corners, helping improve the die attach film process window and eliminating the stress in package. This also results in much higher die strength compare to saw and laser (>30% and up to 9x improvement have been measured against saw) allowing to accelerate the thinning roadmap and gain in heat conductance, device performance and package size. The thinner the wafer, the narrower the streets, and the shorter the process; leading to unseen throughput and die quality for wafers thinner than 100µm (full wafer singulation of a 50µm thin silicon wafer takes less than 5 minutes irrespective of the wafer size) Die size variation after singulation with lasers or saws can vary as much as 30µm per die side. The variation of plasma singulated die is solely dependent on the lithography definition of the streets, as such die size variation has been demonstrated to be <0.5µm die to die and wafer to wafer. Finally, in case of power or LED devices, a large amount of additional good die per wafer contributes to reduce the quantity of wafer start in front end fab or the expense of additional equipment for capacity expansion (more than 10% good die per wafer can be added resulting in saving over 4000 wafer start per month for 1mm² die on 8" wafers)

CV of presenting author
Thierry Lazerand is the Director of Technical Marketing at Plasma-Therm LLC in Florida. He received his Master in Material Sciences and MBA from universities of Limoges and Nantes in France. Mr. Lazerand experience in the semiconductor world spans over 30 years with various lead roles in front end device manufacturing, technical marketing and business development responsibilities at various equipment vendors in Europe and USA. His experience covers techniques and applications related to cleaning, thermal, plasma and atomic layer deposition and etch. He co-authored several publications in these fields and is the co-founder of Sunsonix, a start-up delivering bio-degradable chemistries for PV Solar applications.

Advanced Packaging Conference (APC)
Plastic Logic Banach, Mike
Flexible AMOLED display driven by organic TFTs on a plastic
Banach, Mike

Banach, Mike
Technical Director
Plastic Logic

Abstract
OTFTs are fundamentally the most flexible transistor technology available. Combined with recent improvements in organic materials, this offers a route to truly flexible AMOLED displays, which will transform new markets such as wearables. Plastic Logic has developed a flexible OTFT AMOLED display using low temperature processes compatible with mass manufacturing.

CV of presenting author
Mike is the Technical Director at Plastic Logic. Mike joined the company in 2003 and was instrumental in developing its flexible display technology platform and scaling the process for high volume manufacture. He now has over 15 years of experience in flexible electronics technology and is responsible for all the new innovation programs within Plastic Logic. He holds a doctorate degree in Physics from the University of Cambridge and a BA in Materials Engineering from the University of Cincinnati. He has previously worked at the Air Force Research Laboratories at Wright Patterson Air Force Base in the US and is currently the head of the UK delegation to IEC TC119, developing standards for printed electronics.

Plastic Electronics - PE2014
Presto Engineering de Ledinghen, Edouard
Cost-effective RF MEMS wafer test solution
de Ledinghen, Edouard

de Ledinghen, Edouard
Test manager
Presto Engineering

Abstract
New test challenges Moving MEMS test upstream to the wafer RF MEMS have a promising future for cellular phones. The associated test solution will have to manage a sharp ramp up while keeping the final cost as competitive as the GaAs competitor. This paper explains how it is possible to smoothly grow from device characterization to volume test in production. There is a traditional hurdle between first silicon characterization and the automatic test world. The first one still belongs to designers' team, while the second has already a foot in the production factory. It implies extra cost to bear for start-up companies, because they have to develop and maintain two different test systems: one for evaluation and characterization, and another one for production. It is very difficult to move from one system to the other given the capabilities required by each of them most of the time not compatible (accuracy, turn-around time) The main idea was here to develop the characterization system, keeping in mind the production test. We decided to select a PXI platform. PXI is easy to program and flexible for the lab, and has also a very low cost compared to traditional ATE. Moreover, we designed also the hardware in such a way that the same interface board can run complex characterization tests and also can be used to evaluate production test and correlate both. This paper will present economic rationales and technical aspects allowing this solution to claim for the lowest cost and highest scalability for production award.

CV of presenting author
After 10 interesting years developing measuring instrumentation for various industries, and posting 2 patents, Edouard de Lédinghen, today 46 years old, joined the semiconductor industry with Teradyne, the famous tester manufacturer. He helped to introduce new analog instruments before moving to NXP in Caen to put in place high volume production test for RF devices. When St-Ericsson collapsed, he joined Presto Engineering and put in place the new test activity. Today he drives the fast growing test department and develops Presto offering to lower the cost of test and answer to new requirements from high accuracy analog to 80GHz production test. Edouard is engineer from ISEP School in Paris. He also enjoys family life with 9 kids !

16th European Manufacturing Test Conference (EMTC)
Presto Engineering Mayor, Cedric
Mayor, Cedric

Mayor, Cedric
VP Marketing
Presto Engineering

Biography
Cédric started in 2000 his career as lead memory design architect on SOI substrate for advanced processor in SOISIC which became a ARM Ltd physical IP department in 2005. From inception he drove the innovation roadmap down to silicon proven circuit memory compilers. He took over a program manager role in the PHILIPS semiconductor PD, in charge of NPI & Lead Product industrialization in Crolles2 300mm wafer fab from the STMicroelectronics, Freescale, and PHILIPS Alliance. He was involved into yield improvement, process and product transfers to external foundries or within the internal NXP Semiconductors fabs. He successively hold responsibilities in Corporate NXP in Crolles (FR) and Nijmegen(NL)for all the advanced process nodes industrialization, including platform qualification down to 40 nm CMOS technology. In 2010, he became Vice President for Presto Engineering in charge of DFT innovation & back-end roadmap and strategic marketing, focused on the next generation High Performance Mixed Signal and RF MMW products industrialization needs. Cédric graduated from Ecole Centrale Marseille in France, and holds a MS of Physics and Electrical Engineering, four patents in the area of chip design and DFM, and contributed to several publication in the field of design and semiconductor test, and productization.

16th European Manufacturing Test Conference (EMTC)
Prismark Partners Swiggett, Brian
A Rapidly Changing Test Landscape
Swiggett, Brian

Swiggett, Brian
Managing Partner
Prismark Partners

Abstract
Smartphones, tablet computers and automotive electronics alone accounted for more than one third of all electronics systems value produced in 2013, up from only 13% five years ago. These markets combine high volume production, significant competitive cost pressure, and leading edge IC and sensor packaging requirements. With continuing market growth and device and systems design change, test equipment and production engineers will be challenged to adapt to an ever increasing set of challenges. The emerging "Internet of Things" will also drive significant volumes of low-cost wireless modules and sensors that adapt technologies spawned initially within the mobile and automotive sectors. This paper will review the key device and packaging trends for mobile and automotive IC and sensor packaging, and will discuss the test and handling complexities inherent in the growth of small form factor SMT and array packages, flip chip and WL-CSP, embedded components, modules and MEMs sensors, and ultimately 3D-TSV implementation. Conventional SMT packages have already reached saturation, and the high volume high complexity consumer-facing segments are rapidly changing the landscape and overall test requirements within the semiconductor supply chain.

CV of presenting author
Brian Swiggett is founder and Managing Partner of Prismark Partners, a thirty-person international electronics industry consulting firm that works at all industry levels from systems to semiconductors. The company focuses on providing strategic business advice and analysis to companies operating at the leading edge of the electronics industry. He holds BA and BE degrees from Dartmouth College and its Thayer School of Engineering and has had a wide range of experience in the electronics industry over the past thirty years. While at Kollmorgen Corporation, his management responsibilities ranged from systems development to manufacturing engineering, product marketing, and operations in the areas of electro-mechanical and electro-optic systems, printed circuit manufacturing and process development, elastomeric connectors, and materials development. He holds several US patents for his work in these areas. He works with a wide range of Prismark's clients in areas such as semiconductor packaging, system level interconnection and assembly, thermal management, electronic materials, intellectual property assessment, and acquisition strategy.

16th European Manufacturing Test Conference (EMTC)
Q To top
Qualcomm Technologies Badaroglu, Mustafa
System Integration: More Moore
Badaroglu, Mustafa

Badaroglu, Mustafa
Sr Program Manager
Qualcomm Technologies

Abstract
CMOS scaling enabled simultaneous system throughput scaling by concurrent delay, power, and area shrinks with thanks to Moore's law. System scaling brought in requirements that require a holistic approach for the optimal balance of performance and power under the limits of technology. We will address requirements and gaps in the new ITRS2.0 roadmap to maximize benefit from More Moore scaling.

CV of presenting author
Mustafa Badaroglu is senior program manager at Qualcomm, Leuven, Belgium. In this role, he has the responsibility to assess/track feasibiliy and supply chain readiness of new technologies through consortia projects and supplier collaborations in the areas of logic and memory, interconnect, lithography, optical IO, and 3D integration. Prior to joining Qualcomm, he was principle scientist at imec, Leuven, Belgium, working on targeting on More Moore technology requirements for design. Before imec he was design manager with ON Semiconductor in the automotive and power product development division, leading chip product development activities to hand over to high volume production. Dr. Badaroglu received the B.Sc. degree from Bilkent University, the M.Sc. degree from the Middle East Technical University, the Ph.D. degree from the Katholieke Universiteit Leuven (KU Leuven), all in electrical engineering, and the M.Sc. degree in Industrial Management from KU Leuven. He is the chair of the Process Integration, Devices, and Structures (PIDS) chapter of the International Technology Roadmap of Semiconductors (ITRS).

Low Power Conference
ITRS: Trends in Enabling Technologies (TechARENA)
R To top
RECIF Technologies Delpu, Guilhem
450mm progress - toward cross collaboration & cross utilization
Delpu, Guilhem

Delpu, Guilhem
Product marketing & collaborative programs
RECIF Technologies

Abstract
2014 is an important year for RECIF in 450mm, as it involves major milestones like: the delivery of their first 450mm system (EFEM / sorter) installed at imec in March, and the demonstration of the NGC450 wafer handling platform, concluding the project by December 2014 at imec as well. The presence of RECIF equipment at the imec makes possible to move the "450mm cross collaboration" with G450C, from a conceptual agreement to a practical phase. The first assessment results will be shared between imec and G450C through common "Demonstration Test Methodology", applied to wafer handling equipment, for which RECIF will have supported the consolidation. The "notch less" wafer standardization is another topic of collaboration between G450C, Recif and imec. 2014 was also a year during which question marks were set on the 450mm path by some actors, some of them being European based. These question marks are facts, but are not entirely conditioning the 450mm relevancy / viability at other places in the world. RECIF remains committed to support its partners and the 450mm transition wherever it is possible, at our level. Although a certain level of uncertainty resides in the timing and cadence of transition (demo => pilot line => volume production), industrial partners are maturing a retrofit & dissemination plan to value reuse of 450mm achievement throughout the value chain of smaller wafer diameters. The above mentioned "cross utilization concept" is declined in precise utilizations as explained here after: - Best practices retrofitted to 300mm (26nm cleanliness) - 450mm modules reused for "more than Moore" concept and advanced packaging (middle end) value chaine => TSV HANDY project proposal - Pocket wafers & bridge vacuum chamber enabling to work on advanced nodes de-correlated from wafer diameters (300mm or 450mm). RECIF will detail its position and vision on cross collaboration and cross utilization on 450mm achievements in the field of wafer handling.

CV of presenting author
Guilhem Delpu - Product marketing & Collaborative programs manager He joined RECIF Technologies 10 years ago and works as product marketing and collaborative programs manager. He has set up and leads the CATRENE NGC450 program, targeting the delivery of a 450mm wafer handling platform, dedicated to support the 450mm transition in Europe. He also takes an active position in subsequent ENIAC JU 450mm running projects (EEM450PR, E450EDL & E450-LMDAP). He is part of the EEMI450 steering committee and provides regular contributions to the 450mm sessions at SEMICON Europa since 2010. Guilhem graduated in mechanical engineering and in marketing, in Toulouse.

450mm
Red Belt SA Jaffard, Jean-Luc
Jaffard, Jean-Luc

Jaffard, Jean-Luc
Consultant & Advisor
Red Belt SA

Biography
Jean-Luc Jaffard has been graduated from Ecole Supérieure d'Electricité of Paris in 1979. He started his career 1980 joining Thomson- Semiconductor Bipolar Integrated Circuits Division as Analogue and Mixed Designer for Consumer applications. In 1987 after the creation of SGS Thomson Microelectronics (merger of Thomson Semiconductor and SGS Microelectronica) he became Video Division - TV Design Manager coordinating the development of Analog TV and VCR product family. From 1996 Jean-Luc Jaffard paved the way of imaging activity at STMicroelectronics being at the forefront of the emergence and growth of this business At STMicroelectronics Imaging Division he was successively appointed Research Development and Innovation Director managing a large multidisciplinary and multicultural team and later on promoted Deputy General Manager and Advanced Technology Director in charge of identifying and developing breakthrough Imaging Technologies and to transform them into innovative and profitable products In 2010 he was appointed STMicroelectronics Intellectual Property Business Unit Director In January 2014 he created the Technology and Innovation branch of Red Belt Conseil , bringing expertise in optimisation of complex and innovative solutions to develop competitive products.

Imaging Conference
Renault Cregut, Samuel
Technical and economical challenges and stakes of the charge of electric vehicles
Cregut, Samuel

Cregut, Samuel
Power Electronics Expert for Charging systems
Renault

Abstract
Renault has started to introduce Electric Vehicle in 2011 with Kangoo ZE, and Fluence ZE , then with Twizy and ZOE in 2012. With more than 170 000 electric vehicle sold, Renault-Nissan group is by far the first group in the world for pure EV makers. Between the different issues and difficulties, improving the charge of the Electric Vehicle is a key point. The presentation will explain in details the expectation of the customers, the different charging modes and the evolutions that are expected in the future. Among the different way of charging, Renault strategy wil be explained, taken into account standardization, future trends, for the different countries (especially Europe- US- Japan and China). To conclude, the expected benefits of large gap components will be discussed.

CV of presenting author
Samuel CREGUT ,PhD in Control Systems works in Renault since 2005. Involved in development of Electric Vehicle programs since the beginning of the EV, he first worked on control of power electronics for EV; he is now the technical responsible of charging System strategy and roadmap.

Power Electronics Conference
ReSeCo Segers, Rene
Segers, Rene

Segers, Rene
CEO
ReSeCo

Biography
After getting his degree from the University in Eindhoven, Rene Segers started his professional career at Philips. Rene held technical and managerial positions in various divisions from Philips, including Research, Consumer Electronics, the Centre for Manufacturing Technology and Philips Semiconductors which later became NXP. Technically, over the years the focus has broadened from just DfT towards Test and Product Engineering, Diagnosis, DfX and to supply chain management in general. The last couple of years Rene was responsible for the Test and DfX strategy and implementation for NXP. Rene left NXP in 2009 and is since then active as an independent consultant, supporting mainly smaller companies in developing their business. Rene maintains many contacts in the industry in Europe, Asia and the USA. Between 1988 and 2004, Rene was also as a (part-time) professor at the University of Eindhoven, teaching DfT and Testing of electronic circuitry.

16th European Manufacturing Test Conference (EMTC)
Robert Bosch GmbH Widmer, Thorsten
Secondary equipment- a strategic approach in a 200mm semiconductor and MEMS Fab
Widmer, Thorsten

Widmer, Thorsten
Vice President
Robert Bosch GmbH

Abstract
200mm semiconductor production in Europe stays under enormous cost pressure. Competitiveness can only be maintained, if all factors of cost are attacked consequently. The use of secondary equipment is one of the important pillars to stay competitive. The presentation will show challenges and experiences regarding the integration of secondary equipment in an operating 200mm semiconductor and MEMS Fab. Focus is also given on the influence of the secondary equipment approach to the demands for the Fab automation concept. The presentation will show based on examples what the main obstacles are and how to overcome them.

CV of presenting author
Dr. Thorsten Widmer was born and educated in Germany. His graduated in physics at TU Braunschweig in 1992. After PhD graduation in Paderborn in 1995 he worked for tree years as post doc at TU Braunschweig. In 1998 he started at Robert Bosch Reutlingen in diode manufacturing area. As section manager he was responsible for the process engineering and international customer support. Between 2003 and 2006 he worked as departmental Manager for Robert Bosch sensor manufacturing in Hatvan Hungary. From Septemer 2006 until 2010 he was the responsible Project Manager for the set up of the new 200 mm semiconductor production at Robert Bosch in Reutlingen. Since October 2010 he is Vice President Wafer Production in Reutlingen.

18th Fab Managers Forum
Secondary Equipment (TechARENA)
Robert Bosch GmbH Fischer, Andreas
Fischer, Andreas

Fischer, Andreas
Senior Manager Development ASIC Packaging
Robert Bosch GmbH

Biography
Andreas Fischer is heading the package development for application-specific ICs (ASICs) at the semiconductor division of Robert Bosch GmbH in Reutlingen, Germany. He received a master degree in physics in 1988 after focusing his studies on solid state - & polymer physics, as well as magnetic resonance spectroscopy. Andreas Fischer joined the Robert Bosch GmbH, Division Automotive Electronics, in 1990. He held various positions in development specializing in assembly & interconnect technology.

Advanced Packaging Conference (APC)
Robert Bosch GmbH Gross, David
Ultrasonic Heavy Copper Wire Bonding on Silicon Dies with Electroplated Copper Bond Pads
Gross, David

Gross, David
PhD Student
Robert Bosch GmbH

Abstract
Si power electronics have been quickly developing towards fundamental limits in a way that today, their capabilities are mainly limited by the potential and economical efficiency of the assembly and interconnect technology. In this context, wire bonding is still regarded as the most flexible and cost efficient top side interconnect technology. The transition to heavy Cu wires promises a leap forward in package density, operational temperature range and reliability, but Cu wires require a metallization of highly increased mechanical stability compared to Al wires. The fragility of the standard Al based metallizations leads to cratering during the bonding process and therefore to a destruction of the device. The straightforward approach for a metallization to enable Cu wire bonding is the implementation of a Cu metallization scheme which, concomitantly, leads to additional difficulties like Cu oxidation and diffusion. The surface of power devices consists of Si at the contact to the active device regions and of SiO2 as insulating field-oxide above the gate stacks. To analyze the influence of these different interfaces, both, pure Si and thermally oxidized Si wafers are used as substrates for the metallizations. To inhibit Cu diffusion, allow ohmic contact formation and enhance the adhesion of Cu to the diffusion barrier, three different liner stacks are used, Ti/Ti-N/Ti, Ti/Ta-N/Ta and Ti/Ta-N/Ru. The liner stacks and the succeeding Cu seed layer are deposited by DC sputtering. Using electro-chemical deposition, the thickness of the Cu bond pads is increased to a final thickness of 10 μm to 40 μm. We present results for the bonding of heavy Cu wires with 300 μm diameter on unstructured Si dies with the different Cu based metallization schemes and report on the influence of the metallization and the impact of the bonding process.

CV of presenting author
David Gross was born in 1985 in Frankfurt/Main, Germany. He received the Dipl.-Ing. degree in Electrical Engineering with focus on microelectronics from the Technische Universität Dresden, Germany, in 2012. In the same year, he joined the Corporate Research at Robert Bosch GmbH, Schwieberdingen, Germany and is currently working towards his Ph.D. degree in cooperation with the Technische Universität Berlin, Germany.

Advanced Packaging Conference (APC)
Robert Bosch GmbH Koyuncu, Metin
Koyuncu, Metin

Koyuncu, Metin
Senior Project Manager
Robert Bosch GmbH

Biography
Dr. Metin Koyuncu is a senior project manager at the corporate research division of Robert Bosch GmbH, Germany. He is active in the field of electronic packaging for the last 14 years. After his responsibility for development projects leading to mass production for the automotive industry, he switched to research on conformal and high density electronic packaging. During the last four years he coordinated an EC funded project "Interflex" that focused on the development of heterogeneous integration technologies for a hybrid System-in-Foil. Together with his team Mr. Koyuncu is active in the field of flexible electronic systems, additive manufacturing for electronic packaging and molded interconnect devices. He is the author and co-author of a number of publications and patents in these fields.

Plastic Electronics - PE2014
Rockwood Wafer Reclaim PEYRE, Georges
European bespoke wafer processing & development solutions for : Grinding, CMP, Edge Treatment, Wafer Bonding, Dicing and Cleaning
PEYRE, Georges

PEYRE, Georges
Sales & Marketing Director
Rockwood Wafer Reclaim

Abstract
Rockwood offers individually tailored solutions for each customer's requirements in wafer surface processing, cleaning and handling substrates. These services include:Wafer Grinding,CMP,Wafer Thinning + Double side Polishing,Wafer Dicing, Wafer Re-Sizing, Edge Processing & Edge Trimming, Wafer Bonding, Sapphire wafer surface preparation for EPI, Sapphire wafer reclaim, Silicon wafer reclaim, Wafer supply : New or Reclaimed. We have been providing wafer processing services offering a local, high quality, reliable, value for money service to our customers for over thirty years. As well as providing unrivalled technical support. We are dynamic and flexible to our customer's requirements and take the time to really understand beyond your expressed needs. Rockwood is located in the south of France in the Rousset region where ~40% of French Semiconductor manufacturing takes place.

CV of presenting author
Rockwood Wafer Services : Sales & Marketing Director.

3D integration (TechARENA)
Roos Instruments Roos, Marc
Finding meaning in semiconductor manufacturing data using Rich Interactive Test Data Base (RITdb)
Roos, Marc

Roos, Marc
Founder
Roos Instruments

Abstract
A paper by this title is being presented at TestVision 2020 on July 10, 2014. The EMTC paper will provide some of the same information plus a status update. Emerging products, applications and test strategies are demanding that test data collection and storage become efficient and flexible in supporting new use models e.g. real time or pseudo real time queries, adaptive test and streaming access. The current STDF standard does not support these use models. Hence there is a need in the industry to create a new standard to fulfill these needs. The STDF working group at SEMI/CAST has developed a next generation standard, RITdb, which can support not only the test data logs but other data/information from the test cell. The effort began by defining RITdb as a simple relational data model to represent STDF, plus mechanisms for storing the resulting tables as files in a RITdb file store along with metadata that can be used to locate files for downstream processing. As part of the effort, STDF to RITdb translators and sample tools for storing and locating files have been implemented. The effort has since expanded to map test equipment configuration information into the same data format, and there are plans to propose standards for ETest data, equipment event information, and an adaptive test interface to testers using the same RITdb format. A logical architecture based on the standard is being proposed. It includes a standard messaging format for RITdb data that can be streamed in real-time from data sources and uses a broker that supports combining and synchronizing data from multiple sources and delivering it to consumers selectively through subscription. The net result is a plug-and-play data driven architecture. While the overall architecture is a long-term effort, example use cases are provided to show how parts of the architecture can be implemented in the near-term to work with existing tools and applications.

CV of presenting author
Mark Roos is the founder and CEO of Roos Instruments, a position he has held since its inception in 1989. Mark graduated from California State Polytechnic University with a B.S. in Electrical Engineering in 1973 and holds a MS in Electrical Engineering from Stanford University and an MBA from Santa Clara University. Measurement technology has been the focus of his entire career starting with his early work experience as R&D Project Leader for Hewlett-Packard (later Agilent) Network Measurements Division in Santa Rosa where he was responsible for the microwave receiver and processing (i.e. "bottom box") of the record-breaking HP 8510 Microwave Network Analyzer. After the enormous success of that network analyzer, Mark went on to lead the marketing efforts for HP's RF and Scalar Microwave Network Analyzer products. The next phase of Mark's career was VP of Engineering for EIP Microwave, a maker of electronic counters and other instrumentation. While at EIP, he discovered a need for high performance automated instruments. He left EIP to found Roos Instruments to serve this market for high-speed RF instrumentation with capabilities suitable for high volume manufacturing. Early on, Roos Instruments received funding from DARPA via a Small Business Innovative Research (SBIR) grant. The grant allowed Roos Instruments to develop a totally new approach to RF measurements using a single receiver and advanced software -- ideas Mark pioneered. Early in 1994, Roos Instruments won a comprehensive benchmark at Motorola with the RI7100A, resulting in its first major success. Continuing innovate, Roos Instruments introduced Cassini, the first truly modular, high performance ATE. Thus continued Roos Instruments' rise as the supplier of these advanced technologies in production testers world-wide.

16th European Manufacturing Test Conference (EMTC)
Roth & Rau - Ortner GmbH Spannring, Ulrich
Higher Yield with Nitrogen: The retrofitable FOUP Purge System for Existing Storage Bins
Spannring, Ulrich

Spannring, Ulrich
Head of Sales
Roth & Rau - Ortner GmbH

Abstract
In the Semiconductor industry the leading edge companies are developing and producing at process nodes of 20nm and below. Smaller wafer structures are increasingly sensitive to process-related interactions such as humidity on the wafer's surface or the evaporation of chemicals after the etching process. In such instances, which are referred to as "side-reactions," it can lead to surface defects or- in worst case scenarios- voids and yield loss. To address these problems, Roth & Rau - Ortner developed a FOUP Nitrogen Purge System. This system is focused on an optimized use of the FOUP idle time in storage areas (e.g. Zero Footprint Storage) by purging the wafers with an inert gas such as Nitrogen. By doing so, the system avoids Airborne Molecular Contamination (AMC) and other chemical reactions, creating significant yield wins. In addition, standing time in process-critical steps (queue time) can be extended.

CV of presenting author
Ulrich Spannring, born in 1964, studied Business Administration in Munich and began his sales career in the Semiconductor Industry in 1992 at USHIO. After working in various sales positions for Johnson Matthey, Honeywell and Ultratech and the foundation of a Consulting Company, Ulrich Spannring joined Roth & Rau - Ortner as Sales Manager in 2011. As the Head of Sales he is primarily responsible for the sales of Ortners Automation Solutions.

Fab productivity (TechARENA)
Roth und Rau B.V. Lichtenberg, Claus K.
Printed Electronics: Hybrids
Lichtenberg, Claus K.

Lichtenberg, Claus K.
CEO
Roth und Rau B.V.

Abstract
In the next decade we recognize three major megatrends which will influence manufacturing technology and drive finally printed electronics: - New materials for micro and nano technology - Functional layers and structures in micro and nano format - Reduced value chains to further downsize cost Printed and plastic or organic electronics can fulfill a major part of these new requirements - in many cases in combination with other technologies and solutions which we call here as hybrids. Small devices and next gen products are depending on new material developments. Conventional materials like metals, glass and plastic materials are on their limits for miniaturization and mikro shaping. New requirements have to be fulfilled by structure, manufacturing technology, physical performance and material characteristics. Base materials and material deposition like coatings and structuring for manufacturing of micro devices and their surfaces are the new challenges. Some samples: - Small sheet metals are replaced by coated and etched materials - optical glass lenses are replaced by formed and printed organical coatings - added with further functionality by printed piezo elements instead of focus mechanism - control units are directly placed as bare dies (chips) on the device - classical printed circuit boards with single functionality will be replaced with new hybrid solutions Finally if successful these materials, technologies and miniaturization replace gigantic existing value chains with many process steps and partly different industries by lower cost, energy consumption and higher performance. These hybrid solutions combine existing technologies, new functional thin films and printed solutions. This presentation will show more than ten samples of realized hybrid solutions in the areas of Display, OLED, OPV, Electronics, Semiconductor and printed 3D Structuring.

CV of presenting author
Claus K. Lichtenberg, Roth & Rau B.V., CEO Started at Roth & Rau B.V. in 2009 and CEO since 2011. Claus studied at the Technical University Stuttgart Mechanical Engineering with a master certificate. Later he deepened his knowledge in Finance and Business Administration with several seminars at the Hochschule St. Gallen and Dr. Gerland in Frankfurt. Claus has more than 30 years global experience in machining and equipment industry mainly in semiconductor, electronics and precision optics. He comes with a strong background in R&D and operations for mass volume production in optics, semicon and electronics but also in midsize volume for equipment manufacturing. He has further experience with successful managed turn-around, start up and growth business. Claus fulfilled several C-level functions amongst others in stocklisted companies (Carl Zeiss, Suss Microtec AG, BE Semiconductor Industries N.V. and others).

Plastic Electronics - PE2014
Rudolph Technologies Kaoui, Mounir
Increasing fab productivity in mask shops
Kaoui, Mounir

Kaoui, Mounir
Application Engineer
Rudolph Technologies

Abstract
Mask shop productivity is strongly influenced by the 100% outgoing defect inspection of manufactured reticles by using reticle inspection tools. These highly sensitive tools with a throughput of 1-2 h are also used for incoming mask blank inspection as well as for production tool monitoring by using monitor mask blanks. During the inspection of mask blanks reticle inspection tools cannot be used for reticle inspection thus reducing the output of the factory. We are presenting a high throughput low COO mask blank inspection technology that can take the load of bare mask inspection off the reticle inspection tool and thus increase fab productivity significantly.

CV of presenting author
Mounir Kaoui has a Physics Diploma at Johannes Gutenberg University Mainz in 2011. He join Rudolph technologies 2012 as an Application Engineer. Mounir works closely with equipment and process engineers at major semiconductor fabs and mask shops. His extensive expertise includes collaborating on evaluations and providing customized solution, technical support and training for defect inspection tools that are used for bare wafer and Mask blank inspection.

Fab productivity (TechARENA)
Rudolph Technologies Cochet, Philippe
Advanced Packaging related lithography challenges
Cochet, Philippe

Cochet, Philippe
Director, Technical Account Management
Rudolph Technologies

Abstract
Semiconductor packages must be thin, small and cost-effective which is a given in the semiconductor back-end industry. Packaging today plays a critical role when it comes to device and system performance. Many different advanced packaging approaches are being pursued. Lithography is a very important process step for many of these so-called advanced packaging technologies. A few examples are: Wafer bumping or Cu pillars for FlipChip packages or 3D stacked chips. Wafer Level Chip Scale Packages (WLCSP) with their fan-in redistribution layers (RDL). Fan-Out packages which have similar RDL requirements but often exhibit significant substrate warpage due to the required molding process involved. 2.5D interposer which need "all of the above" in terms of bumps, pillars and RDL but in addition require TSV (Through Silicon Vias) or TGV (Through Glass Vias) and double-side processing. This presentation specifically lists the various lithography challenges which are being encountered when implementing a manufacturing process for the above mentioned Advanced Packaging technologies. Typical back-end litho requirements regarding resolution, overlay, sidewall angle and depth of focus are being discussed. In addition, the application-specific litho challenges such as a large exposure field size, IR backside alignment capability for TSV or TGV and unique handling requirements for warped wafers or large panels are being reviewed. Just like all back-end process steps, lithography must be extremely cost efficient and high yielding. A middle ground between costly front-end lithography techniques and more robust and lower cost back-end approaches has to be found. This work also discusses potential cost reduction via economy of scale for some packaging technologies which can be processed on large panels.

CV of presenting author
Philippe Cochet is the Director, Technical Account Management at Rudolph Technologies which acquired Azores Corp in 2012 where he hold the position of Director, Business Development. Mr. Cochet has 30 years of sales, marketing and customer service experience and hold different positions at Zeiss SMT, Accretech, Zygo, Fairchild Technologies and at GCA (19 years), a photolithography capital equipment manufacturer. Mr. Cochet hold degrees from the university of Montpellier.

Exhibitor Presentations: Packaging (TechARENA)
S To top
Salland Engineering Martignoni, Stefano
Martignoni, Stefano

Martignoni, Stefano
Vice President of Worldwide Sales and Marketing
Salland Engineering

Biography
Stefano Martignoni Vice President of Worldwide Sales and Marketing Stefano is responsible for worldwide sales and marketing for all Salland product lines. Prior to his appointment as director, Stefano was Salland's account manager for South Europe. He brings to Salland over 15 years experience in sales and marketing for the ATE industry. Prior to Salland, he was Senior Marketing director at Credence. He started his career with STMicroelectronics as a product engineer. Stefano holds a Master's Degree from Milan Polytechnics in Electronic Engineering.

16th European Manufacturing Test Conference (EMTC)
Schneider Electric Dorn, David
Multisensor Camera Architectures for Security and Operational Applications
Dorn, David

Dorn, David
Applied Technologies Manager
Schneider Electric

Abstract
This session will introduce participants to multi-sensor and multi-spectral imaging for security and operational applications. This talk discusses the differences between video for security and projects focussing on video for operational data. The ability to extract different types of real time data and information from different spectral regions is discussed. Video information combined with other sensors provides the ability to solve unique customer challenges and applications. Specific customer use cases and applications are presented. The camera technology associated with these applications is presented along with current technology challenges. Technical approaches to techniques such as multi-sensor stitching and multi-spectral fusion are discussed. Technical challenges associated with these techniques and associated algorithms are also introduced. Fundamental underlying principles and science behind this technology are explored, along with a brief summary of the development of these technologies. Looking forward, technology trends and roadmaps for multi-sensor and multi-spectral imaging are also presented.

CV of presenting author
David Dorn is the Applied Technologies Manager for Pelco by Schneider Electric. Mr. Dorn has been leading efforts with development of image sensors and camera systems for over 20 years. These cameras systems have spanned wavelengths from the IR to the UV for security, scientific, and medical applications. Currently, Dorn leads the engineering team developing thermal imaging cameras for Pelco by Schneider Electric. Earlier in his career, Dorn also led teams building visible and infrared camera systems for Hubble Space Telescope and interplanetary missions to Mars and Pluto. He has authored over 25 technical publications and has patents for CMOS image sensor and camera innovations.

Imaging Conference
Schneider Electric Wang, Miao-Xin
Power electronics in industrial applications: key innovations, impacts and perspectives
Wang, Miao-Xin

Wang, Miao-Xin
Manager , Advanced Electronics and Power Electronics
Schneider Electric

Abstract
Power Semiconductors become more and more present in many industrial applications. Especially for energy economy and CO2 reduction challenges, they are key in the use of renewable energy and energy efficiency. Tremendous progress had been made in Power Semiconductors, including potentially disruptive innovation thanks to Wide Band Gap technologies. This presentation will review key innovations in Power Electronics for industrial applications, from Power Semiconductor to cooling and passive component, and conclude new innovation challenges and perspectives

CV of presenting author
Miao-xin Wang received the Engineer degree in Automatics and Power electronics from ENSEEIHT, Toulouse, France, in 1989, and the Ph.D. degree in electrical engineering from INPT, Toulouse, in 1992. He joint Schneider Electric in 1993, before moving to UPS development and RD management within MGE UPS System from 2000 to 2007 and Eaton Electrical from 2007 to 2011. Since 2011, he has been leading Advanced Electronics and Power Electronics team, within Schneider Electric, Technology Strategy, Grenoble, France. He is the author and coauthor of several papers and patents on harmonic filtering, low-harmonic converter topology, and UPS topology.

Power Electronics Conference
Schneider Electric Venet, Cécile
Challenges & Opportunities for Printed Electronic and 3D-MID within Schneider Electric
Venet, Cécile

Venet, Cécile
Technology Innovation
Schneider Electric

Abstract
to come

CV of presenting author
Dr Cécile Venet is in charge of Large Area and Printed Electronic activities within Innovation department of Schneider Electric. She has a PhD degree in Physics & Material Science from Ecole des Mines de Paris, France (1996) and an engineering diploma in Material Physics from Institut National des Sciences Appliquées (1992). Skilled within materials forming processes and polymers rheology, she joined Schneider Electric R&D within Materials & Process department where she manages research projects for the company. She acts as industrial representative for Plastipolis French Pôle de compétitivité.

Plastic Electronics - PE2014
Schneider Electric Chabanis, Gilles
Ultra Low Power wireless sensors in Buildings
Chabanis, Gilles

Chabanis, Gilles
Pervasive Sensing Manager
Schneider Electric

Abstract
The talk will content the description of main characteristics of our developed ultra low power wireless sensors platform in the context of SE applications with a particular focus in Buildings. The architecture and power consumption of the wireless sensors per function will be presented with impact on autonomy depending on storage solution and type of sensors within the range of ambient buildings sensors. The optimized ZigBee Green Power (ZGP) sensors platform allows to measure a range of sensors like temperature, humidity, light, door/window contact, motion/presence sensor (PIR), CO2 with an average power consumption varying from 1 µA to 20µA depending on sensor types and measurement frequency. The optimized ZGP implemented protocol requires only 110 µJ to send a frame providing the flexibility to adjust the transmission frequency from few sec to few minutes depending on application requirements and still operated without wire for power supply. A unique disruptive ultra low power CO2 sensor co-developed in Partnership with Gas Sensing Solution will be described showing typical sensor technology challenges to overcome in order to be compatible with wireless solution. The remaining and overcame challenges of the platform will be also discussed targeting the diversity of sensors power consumption constraint, the weaknesses of today storage technologies and trends we foresee.

CV of presenting author
Gilles received his PhD in Physical Chemistry in 1997 from the University of Montpellier before working as a Post Doctoral Research Fellow at the Chemistry Department of University College London on a European Research project aiming at developing semiconducting oxide gas sensors. He gained many years of experience on sensors development as innovation project leader for the development of Aircraft Fire Detection systems at Siemens. Thereafter, he worked as product manager for Aerospace fire detection for Siemens before joining Schneider Electric Innovation Department in 2007 as project leader of the homes sensors project dedicated to the development of self-powered wireless multisensors for Buildings in the frame of the Homes Programme. Gilles is currently Pervasive Sensing manager in Schneider Electric Technology Strategy Department in Grenoble, France.

Low Power Conference
Schneider Electric Industries Brosset, Pascal
From pervasive sensing to operational efficiency a path towards internet of everything
Brosset, Pascal

Brosset, Pascal
Sr VP Innovation
Schneider Electric Industries

Abstract
Pascal Brosset, Chief Technology Officer of Schneider Electric will outline the roadmap of a products and systems company leveraging the combined opportunities of IoT, cloud computing and big data analytics to become an energy and operational efficiency solutions provider.

CV of presenting author
Pascal Brosset joined Schneider Electric as Chief Technology Officer and SVP Innovation in July 2010, coming from a software and high tech background. Prior to joining Schneider Electric, Pascal was Chief Strategy Officer of SAP AG, where he held multiple business development and strategy positions over 10 years. His international career started at Hewlett Packard followed by senior positions in consulting firms, leading large scale "technologyled transformations" across multiple industry sectors. Pascal holds a Master degree in Engineering from Ecole Polytechnique Fédérale de Lausanne(Switzerland) and graduated in executive development from INSEAD and Ashridge Business School.

Imaging Conference
Schweizer Electronic AG Gottwald, Thomas
Printed Circuit Board (PCB)-based IC Embedding and Package Technology
Gottwald, Thomas

Gottwald, Thomas
Director Innovation Center
Schweizer Electronic AG

Abstract
Since the rapid development of electronic devices, the traditional IC package technology reached its limit. PCB-based IC embedding is an attractive solution for advanced packaging technology. In this paper different ways of PCB-based IC embedding technology are presented. The I2-Board (integrated interposer Board) technology is a motherboard embedding method for logic ICs. The key of this technology is the integration of a thin polymer based interposer, which serves as a rerouting layer to fill the dimension gap between ICs and PCB. The bare dies and passive components are mounted on it before laminating process. Another p2-Pack (power PCB) technology focuses on the embedding for power semiconductors with vertical current flow. PCB technology allows to laminate thick Cu-layer with directly attach of power semiconductors (MOSFET, IGBT, etc.). This ensures a high heat dissipation and electrical dynamic performance by reducing the thermal resistance (Rth) and the dynamic resistance (Ron). In addition this approach also shows a significant cost reduction potential in comparison to conventional direct bond copper (DBC) technology with ceramic substrates. As a module embedding, µ2-Pack (µ thin, µ pitch) provides an ideal package solution for fine pitched multi ICs. By using classical PCB technology, fine pitch down to 40µm and the package thickness under 100µm (depending on the bare die thickness) can be achieved. This technology also allows the 3D integration by IC stacking without wire bonding. This could be another cost-efficient alternative to through-silicon via (TSV) solution. Various demonstrators were successfully fabricated. The evaluation results show the PC-based IC embedding technology have improvement potentials in aspects of the miniaturization, the electrical and thermal performance, long term reliability as well as the cost reduction.

CV of presenting author
Thomas Gottwald studied surface technology and material sciences. He entered Schweizer Electronic in 1991. He spent 10 Years in the process development department as a Project Manager. In 2001 he took over the responsibility for the Product Engineering Departement. Since 2011 he is Director of Innovation Center at Schweizer. His major topics are Component embedding technologies, Power Electronics and Thermal Management.

Advanced Packaging Conference (APC)
SEMI van den Kieboom, Ed
van den Kieboom, Ed

van den Kieboom, Ed
Chairman Plastic Electronics Special Interest Group
SEMI

Biography
Has over 25 years of hands-on management experience in launching, developing and leading both public and private technology companies. In his professional career he worked from 1986 through 1992 as a marketing and investment director for the Dutch government in attracting technology based companies from the US and the Far East. After establishing his own management consulting firm in 1992 he assisted as an outside consultant, major companies such as Philips Electronics, and Mitsubishi Electronics. Furthermore he established and/or assisted in establishing, over a period of 12 years, 7 companies in Europe in the areas of optical storage media, micro-electronics, information and communication technology. From 2002 to 2004 he assisted as an outside consultant to internationalize the scope of the Dutch Polymer Institute, a top technology institute in the Netherlands. In 2005 he founded and managed the Plastic Electronics Foundation, a worldwide technology platform for printable organic electronics, with stakeholders from both the academia, research institutes and industry. In 2012 he joined forced with the SEMI organization to become the Chairman of the Plastic Electronics Special Interest Group and to coordinate the program of the annual Plastic Electronics Conference.

Plastic Electronics - PE2014
SEMI Tracy, Daniel
SEMI Market Outlook- Fab Investments and Equipment Spending Forecast
Tracy, Daniel

Tracy, Daniel
Sr. Director, Industry Research & Statistics
SEMI

Abstract
The presentation will highlight the latest update on fab investment trends impacting the semiconductor industry. Where is the money going: new fabs, more capacity or new technology? What does the future hold for fabs? These investment trends include fab construction and equipment spending, and highlights of investments by foundry, memory and other industry sectors. The forecast for the semiconductor equipment will cover regional spending trends for 2014 and 2015 as well as the overall forecast for Wafer Processing, Test, and Assembly & Packaging equipment.

CV of presenting author
Dr. Dan Tracy is responsible for developing and executing the global strategy for SEMI industry research and statistics products and services. Tracy is responsible for preparing market reports and presenting on trends impacting the electronic materials and equipment markets globally. In addition, Tracy is responsible for managing market statistics partnerships globally. Prior to joining SEMI in 2000, Tracy was a Research Associate with Rose Associates, a prominent market research and consulting firm specializing in electronic materials. Prior to this, Tracy was employed at National Semiconductor's Package Technology Group. Tracy has a Ph.D. in Materials Engineering from Rensselaer Polytechnic Institute, a M.S in Materials Science & Engineering from Rochester Institute of Technology and a B.S. in Chemistry from State University of New York (SUNY) College of Environmental Science and Forestry.

Market Briefing (TechARENA)
Semi Consulting van Nooten, Bas
van Nooten, Bas

van Nooten, Bas
Founder
Semi Consulting

Biography
Sebastiaan (Bas) van Nooten graduated with a Master's degree from the Technical University Delft in 1971. After his military service he was involved in processing and design of integrated circuits till 1981 at Telefunken, Germany. After his return to Holland he went to an IC design house as group leader. In 1985 he moved to the semiconductor equipment industry in several positions, mainly as European product specialist for several equipment types. He joined ASM in 1989, first heading the German office in Munich, later as Sales Manager Europe in the Dutch head office. In 2007 he was appointed as Director of European Cooperative Programs, where he was engaged in several European cluster programs, like the Steering Group Technology of Catrene and as project coordinator for ENIAC projects and two 450mm related FP7 Support Actions. Since last year he is an independent consultant to the semiconductor and semiconductor equipment industry. He is the current spokesman of the Steering Committee of the 450mm Equipment & Materials Initiative EEMI450. He has several patents on his name.

450mm
SEMI Europe Raithel, Stephan
Raithel, Stephan

Raithel, Stephan
Managing Director
SEMI Europe

Biography
Stephan Raithel successfully completed his studies of Business Administration with a German Diploma degree and a bachelor of arts with honors in 2004. Prior to his career at SEMI he was working for a professional trade show organizer and was in total responsible for 4 different products focusing on consumer goods, financial services and creative industries. In 2007 he joined SEMI in the Brussels office as Senior Manager Operations where he became a key staff in implementing SEMI Europe's strategy and enlarging SEMI's presence within Europe. In 2009 he opened a SEMI branch in Berlin, Germany, where he is acting as managing director, being at the same time responsible for the direct reports in Berlin as well as acting as a CFO for all European activities. In his role as Director of PV in Europe he is facilitating and leading the combined industry effort in writing an International Technology Roadmap for PV (ITRPV, www.itrpv.net), enforcing the dialog between leading equipment, material suppliers and PV manufacturers on a global level. He is also regularly providing industry insights to articles in known trade magazines (e.g. Photovoltaics International, pv magazine, Global Solar Technology, photovoltaic production etc.). Throughout the year he is also active as a speaker and / or moderator at leading photovoltaic events and trade shows.

Exhibitor Presentations: MEMS (TechARENA)
SEMI Europe Kundert, Heinz
Kundert, Heinz

Kundert, Heinz
President
SEMI Europe

Biography
Heinz Kundert joined SEMI International, headquartered in San Jose, California as Vice President in 2005 and is acting as President of SEMI Europe with offices in Berlin, Brussels, Grenoble and Moscow. His main mission is to actively support the Microelectronics and related industry towards global competitiveness and sustainable growth. Activities include: industry advocacy, executive and technology conferences, Industry Research & Market Statistics, Roadmaps and Industry Standards. As part of the SEMI mission, Heinz is providing consultancy for SEMI members with the aim to strengthen the global and European-based Microelectronic food-chain. His support is given equally to large Caps and SMEs. Heinz has been in executive positions of stock-listed companies including Oerlikon-Buehrle, Balzers, Leybold and OC Oerlikon (former Unaxis) where he was CEO for several years. Kundert joined the Microelectronics Industry in 1981 and hold managerial functions in General Management, Operations, Sales and R&D. He lived 5 years in Asia. Heinz has a degree in mechanical engineering, education in large cap financing and business administration with a federal diploma from the FAH@University of St.Gallen, Switzerland. hkundert@semi.org

International MEMS Industry Forum
18th Fab Managers Forum
SEMI Europe Georgoutsakou, Ourania
Georgoutsakou, Ourania

Georgoutsakou, Ourania
Director of Public Policy
SEMI Europe

Biography
Ourania Georgoutsakou joined SEMI as Director of Public Policy for Europe in October 2012, with the role of liaising between SEMI members and European, national and regional decision-makers to reinforce cooperation between industry and public authorities in the interest of a globally competitive Europe semiconductor value chain. She has 10 years of experience in European policy-making processes and advocacy, gained as Senior Policy Coordinator for the Assembly of European Regions (AER), the largest independent network of regional politicians in Europe. She has worked on such diverse policy areas as the EU institutional set-up and the Lisbon Treaty, and EU health, social, innovation, competition and cohesion policy. Ourania holds postgraduate degrees in EU Law and in EU policy-making and lives with her family in Brussels.

Exhibitor Presentations: Packaging (TechARENA)
Sencio van Dommelen, Ignas
van Dommelen, Ignas

van Dommelen, Ignas
CMO, Manager Marketing & Sales
Sencio

Biography
Ignas has studied chemical engineering in Eindhoven (NL). In 1979 he started his career at the research lab of Philips Eindhoven. Since 1984 he has been active in semiconductor assembly , when he started as a package development engineer at Philips Semiconductor Nijmegen. In 1991 he joined Eurasem with responsibility for developing special assembly solutions for various MEMS,MST application and has been heavily involved in the company's assembly technology developments. Today Ignas is responsible for Sencio's business development, sales and marketing.

International MEMS Industry Forum
SiCrystal AG Stockmeier, Matthias
Status of silicon carbide substrate production by physical vapor transport method
Stockmeier, Matthias

Stockmeier, Matthias
Deputy Manager R&D
SiCrystal AG

Abstract
4H Silicon Carbide has always been a favorite candidate as substrate material for high power electronics due to its wide bandgap, high electric breakdown field and high thermal conductivity. Possible benefits range from improved high voltage switching for energy savings in electric power conversion systems to sensors for harsh environments. Since the beginning of SiC development in the 1990s, the substrate diameter was continuously increased and today substrates with a diameter up to 150mm are commercially available. In parallel, the crystal quality has been improved. Main defect types, like micropipes and polytype conversions, have been markedly reduced and uni-polar devices like SBD have entered mass production. Today, the reduction of dislocations is in the focus of material research. Especially basal plane dislocations (BPDs), characterized by a Burgers vector perpendicular to the crystallographic c-axis, are known to enhance the degradation of bipolar electronic devices. In this paper, a discussion on recent developments of SiC substrates produced with the PVT process concerning defects as well as diameter will be given. Special attention will be given to dislocations. Several methods for the evaluation of material properties were applied to determine substrate quality most precisely, e.g. KOH-defect-etching, optical microscopy and high resolution X-ray-diffraction. We found out that several parameters in growth conditions have to be controlled in a proper manner to achieve basal plane dislocation reduction. Based on these investigations we were able to improve our process and the crystal quality significantly. Best values for 100mm 4H substrates show that BPD = 500cm-2, MPD < 0.1cm-2 and rocking curve FWHM-values < 15 arcsec can be achieved.

CV of presenting author
Dr. Matthias Stockmeier Birthday 30/08/1978 matthias.stockmeier@sicrystal.de Professional Experience: 2013 : Deputy Manager R&D at SiCrystal AG, Germany 2008-2013 : R&D Engineer (Crystal Growth) at SiCrystal AG, Germany Academic Career: 2008: PHD in Crystallography: "Real structure and lattice parameters of SiC: Influence of growth direction, doping and temperature" 2004-2008: Research scientist at university Erlangen-Nuremberg (Crystallography and Structural Physics; Defects and Real structure of SiC) 1999-2004: Studies of Physics (Diploma) at University of Erlangen -Nuremberg, Germany and Joensuu, Finland

Power Electronics Conference
Siliconware Precision Industries Co., Ltd.(SPIL) Lan, Albert
Challenges of Flip Chip Packaging with Embedded Fine Line and Coreless Substrate
Lan, Albert

Lan, Albert
Senior Director
Siliconware Precision Industries Co., Ltd.(SPIL)

Abstract
As mobile electronics are continuously driven for compact, slim and lightweight, miniaturization of IC packaging has been a must. Coreless substrate with fine-trace embedded technology is the key to achieve package miniaturization. Compare to conventional substrate, coreless substrate technology eliminates the substrate core, and utilize build-up layers to interconnect the chip and the mother-board. It brings about not only low z-height, lightweight, but also short interconnection and good power integrity. Coreless technology is a promising solution for the next generation substrate. With a coreless substrate that has no rigid core layer, the major challenges for coreless substrate come from the warpage throughout substrate manufacturing and assembly process. In order to diminish the warpage during substrate manufacturing, pre-preg (PP) was employed as the dielectric layer of a substrate. Furthermore the glass fiber in PP can reinforce the rigidity and flatness. For assembly process, lots of experiments were conducted extensively to reduce the package warpage, including molding compound selection (which focus on its CTE and Tg adjustments), post-mold cure optimization, die thickness decision, and so on. In this paper, a test vehicle (flip-chip package, 12x12mm2 body size, above 500 IO count) was carried out. This test vehicle adopted embedded trace technology to make a fine trace width and space of 15um on the bumping side of a substrate for a higher layout density. Stress simulation was conducted to determine the package structure and work out the bill of material. Screen and corner DOEs which includes molding compound selection, die-bond reflow profile and post-mold cure parameters were performed to come out the optimal material and process window. Reliability and functional test have been passed as well. Hence coreless substrate with embedded pattern technology has been proven to be a feasible and reliable way for the miniaturization in assembly industry.

CV of presenting author
Education: Master of industrial & mechanical engineering department, Univ. of Wisconsin, Madison. Experience: Over 20 years of job experience on semiconductor industry, especially focus on bumping and flip chip advanced assembly technology. Committee member of Semiconductor Equipment and Materials International Taiwan Association. Chairman of TILA (Taiwan Intelligent Leader Association). Now: Senior Director of Engineering Center of SPIL (Siliconware, Taiwan), which is 3rd biggest assembly house in the world now.

Advanced Packaging Conference (APC)
Siltronic AG Muemmler, Frank
Advanced Silicon Substrates for Power Technologies
Muemmler, Frank

Muemmler, Frank
Senior Manager Technology Crystal Growing FZ / CZ
Siltronic AG

Abstract
In recent years new Silicon substrates have been developed for power semiconductor devices. Requirements for these wafers are quite different to wafers for CMOS processes. The presentation will cover various types of Silicon substrates. As PowerMOS devices are now being transferred to 300mm by first companies like Infineon, Siltronic AG has also developed low resistivity wafers on 300mm. Properties of these wafers and the specific challenges due to the high dopant concentrations are being shown. For IGBT devices thick epi wafers have been more and more replaced by FZ wafers. Siltronic AG has been ramping up production for 200mm FZ wafers to large volumes within the last few years. Challenges of FZ crystal growth and properties of FZ wafers are being explained. Due to principle limits of FZ crystal growth, for 300mm IGBTs low Oi CZ solutions are being pursued. The pros and cons of such solutions will be discussed.

CV of presenting author
About the author: Frank Muemmler is currently Senior Manager at Siltronic AG in Burghausen,Germany for Technology Crystal Growing FZ and CZ. He has been working in this area since 2006. Main focus is on Crystals for Power Technologies, i.e. FZ Crystals and highly doped CZ crystals with Arsenic, Antimony and Boron doping 2003-2006 Senior Manager Applications Technology at Siltronic AG in Burghausen, Germany 1999-2003 Senior Manager Line Engineering (Process Integration) at Wacker Siltronic Corporation, Portland, OR, USA 1996-1999 Process Engineer Line Engineering at Wacker Siltronic, Burghausen, Germany 1996 Masters degree in Physics, with main subject solid state physics

Power Electronics Conference
Soda Ltd Warman, Fiddian
How can design thinking type approaches be effective in facilitating innovative technological development and open up new markets and opportunities?
Warman, Fiddian

Warman, Fiddian
Director
Soda Ltd

Abstract
Abstract: Fiddian will demonstrate some of the creative digital and mechatronic works he has produced over his last 18 years with Soda including science communication works, consultancy to industry, academia and government as well as social innovation projects. He will focus on a few case studies that serve to illustrate how he feels creative approaches, and design thinking in particular, can be transformative in the development and delivery of technological projects. He will also discuss other projects, approaches and theories that are in use today and seek to propose how deep collaboration between people with an arts or design led approach and those with a more scientific or technical focus can be an effective way to drive development and open up new commercial opportunities. He will seek to define some of the attributes of design led thinking from his experience and suggest how they can be effectively applied in a wide range of projects.

CV of presenting author
Biography: With a grounding in fine and digital arts Fiddian embodies a synthesis of creativity and technology and is passionate about the application of this hybrid in commercial, cultural, learning and social contexts. He is skilled and experienced in identifying underlying opportunities or challenges and innovating elegant strategies and solutions to meet these needs. His eighteen years of experience leading creative teams enables efficient and effective delivery of these innovations. Formerly a sculptor and furniture maker, Fiddian became interested in the creative possibilities of computing and mechatronics in the early 90s and completed a digital arts MA in 1996. He then cofounded SoDA (Society of Digital Artists) in 1996 to cross digital and physical making for commercial projects. This synthesis of digital and physical still informs SoDA's practice, which encompasses creating interactive installations, objects and online experiences for a broad international range of clients from cultural organisations such as the Tate and the Science Museum, publishers such as Pearson Education and commercial clients such as Boeing. SoDA is now stepping up its development of products, principally focusing on new manifestations of the BAFTA-winning SoDAplay online simulation suite and the media montage system MASH. Interested in the rapid growth of the Maker movement and in particular the intersection of creative practice with digital and physical making, Fiddian launched Makers' Guild in 2011. Fiddian consults to both industry and government, and has taken part in many creative research collaborations with academic and commercial partners, including Plastic Electronics research with Cambridge University and Science communication projects with a number of Universities.

Plastic Electronics - PE2014
Sofradir Billon-Lanfrey, David
French infrared technologies offering competitive edges to imaging sensors business
Billon-Lanfrey, David

Billon-Lanfrey, David
CTO
Sofradir

Abstract
Last year, Sofradir has extended its technologies portfolio by consolidating all IR technologies available in France. These different technologies, HgCdTe, InSb, GaAs QWIP, InGaAs and A-Si microbolometers, are complementary and are used depending on the needs of the applications. The infrared (IR) detector R&D is driven by the same trends already experienced by the visible market: Decrease of pixel pitch and increase of array format, decrease of detectors prices thanks to High Operating Temperature (HOT) studies. This paper presents recent developments on HOT and small pixel pitch technologies supported by the long term R&D relationship with CEA-Leti.

CV of presenting author
Mr. Billon-Lanfrey was appointed Chief Technology Officer at Sofradir in 2011, he formerly headed the R&D optronics characterization team at the company for five years. Before that, he served for 12 years as project manager for R&D and product development. Mr. Billon-Lanfrey is a graduate of optronics at Joseph Fourier University in Grenoble.

Imaging Conference
SOITEC Auberton-Herve, André-Jacques
Agile manufacturing in an innovative and competitive European semiconductor ecosystem
Auberton-Herve, André-Jacques

Auberton-Herve, André-Jacques
CEO
Soitec

Abstract
Consumer demand drives innovation. Internet of Things (IoT), mobile applications, energy and transportation societal challenges are an opportunity for Europe to gain industrial competitiveness. Semiconductor is identified as a Key Enabling Technology (KET) to create value through an holistic approach.. Therefore, an efficient and agile manufacturing, close to R&D, is required to bring our innovation to market. European Union launched initiatives as KETs Key Enabling Technology (KET) and Electronics Leaders Group (ELG) to support overall industrial competitiveness for growth, and especially the micro- and nano-electronics. These European initiatives identified the three pillars of development from technological research to advanced manufacturing through product demonstration and pilot lines. The ambitious "10/100/20" strategy was defined (10 Billion Public / Private Funding, for 100 Billion investments from the industry for manufacturing) to capture 20% of the semiconductor market value back to Europe by 2020. This presentation will describe the ELG implementation plan focused on demand accelerators (IoT, mobile convergence), supply chain strengthening, and an enhanced framework development over Europe. Pilot lines initiative was started in 2012, and industry is ready to invest, with 5 pilot lines in progress, and numerous projects deposited. It will highlight how European semiconductor industry manufacturing performance is key, from materials and equipment, to components design and wafer production.. Agile and efficient manufacturing in a multicultural environment support transition from R&D to high volume.

CV of presenting author
Prior to founding Soitec in 1992, AJ Auberton-Hervé managed several joint development programs between Leti and Thomson-CSF, which focused on transferring technologies from R&D to production. Since 2010 André-Jacques Auberton-Hervé is a member of the High-Level Group on Key Enabling Technologies and of the Electronic Leaders Group, groups of European industrial and academic experts working for the European Commission to reinforce Europe's industrial competitiveness. AJ Auberton-Hervé is the treasurer of the AENEAS (Association for European NanoElectronics Activities) presidium since 2008. He also is a member of the Electrochemical Society, the IEEE and ENIAC. AJ Auberton-Hervé is a Board member of the association Semiconductor Equipment and Materials International (SEMI) since 1995. In July 2010, he was elected chairman of the SEMI European Advisory Board and in July 2013, chairman of the SEMI International Board of Directors. He also received the 1999 European SEMI Award. AJ Auberton-Hervé served as the first chairman of the SOI Industry Consortium, founded in 2007 by 19 companies. Today, he remains chair emeritus of the consortium's board of directors. AJ Auberton-Hervé holds a doctorate degree in semiconductor physics and a master's degree in materials science from Ecole Centrale de Lyon (France).

18th Fab Managers Forum
SOITEC Mazure, Carlos
Material Solutions to address the Wireless Low Power Demands
Mazure, Carlos

Mazure, Carlos
Chief Technology Officer, Executive Vice President
Soitec

Abstract
Engineered substrates are well established for the manufacturing of numerous devices which are essential for mobile chipsets and wireless applications. Silicon-on-sapphire (SOS) is being used for the fabrication of high performance RF devices. SOI-on-high resistive substrates (SOI-HR) is the preferred solution for the manufacturing of RF Front End Module (FEM) devices and has become the de facto standard for switches and antenna tuners. Movement sensors are made using SOI substrates. Fabrication of backside illuminated imagers (BIS) includes thin film transfer onto a new substrate of the originally processed layer. The recent big innovation is the introduction of fully depleted (FD) CMOS technologies to make possible low power, low VDD IC operation without significant performance loss. FD devices can be vertical, (FinFETs, 3D MOSFET), or planar (FD-SOI). Their key characteristic is that the silicon channel is undoped. FD-SOI is an evolutionary innovation because it has the advantage of being a planar transistor structure that extends the applicability of bulk design flows with existing design and EDA tools. It is a non-disruptive MOSFET architecture change for SOC design and processing. FD-SOI requires ultra-thin Si (<20nm) over an ultra-thin buried oxide (BOX<25nm) for improved electrostatics. FDSOI is particularly optimized for mobile CMOS technologies. In this review, the contributions and benefits of the different substrates solutions will be discussed focusing on the devices used in the mobile space.

CV of presenting author
Dr. Mazure joined Soitec in 2001. He is the Head of Corporate R&D, responsible for the management of Academia and Industry R&D collaborations. He helps define company strategy; analyze technology trends; anticipate new applications and products; identify incubator and spin-off opportunities. Prior to joining Soitec, Dr. Mazure worked for Infineon Technologies in Munich, Germany, where he headed the ferroelectric FeRAM development program. Later, as Director of Business Development at Infineon he initiated the Infineon-Toshiba FeRAM Development Alliance. Before moving to Germany, he worked for the IBM/Infineon DRAM Development Alliance in East Fishkill, New York; and for Motorola in Austin, Texas. During his years at Motorola Semiconductor, in APRDL, he worked on SOI, BiCMOS high performance SRAM. He has extensive expertise in materials, unit processess, CMOS integration, MOSFET and Memories. Dr. Mazure holds two doctorates in sciences, one from the University of Grenoble, France, and the other from the Technical University of Munich, Germany. He has authored or co-authored more than 120 technical papers and holds more than 100 US patents and significantly more worldwide. He is a member of several international technology and advisory committees, IEEE Fellow member and a regular invited speaker at international conferences and workshops.

Low Power Conference
SOITEC Radu, Ionut
Radu, Ionut

Radu, Ionut
Senior Scientist, R&D
SOITEC

Biography
Ionut Radu joined Soitec's R&D organization in 2006 as staff scientist to develop wafer bonding solutions for advanced SOI substrates, such as sSOI, UTBOX and FD-SOI. He held several positions including group and project leader, and since 2008 he led the development of new applications for wafer bonding, including layer stacking technologies for 3D device integration and advanced CMOS. Dr. Radu is currently involved with academic and industrial research collaborations to support strategic developments of advanced substrate materials and technologies. Dr. Radu has 15 years experience in R&D semiconductor industry. Prior to joining Soitec, he was with Max Planck Institute of Microstructure Physics in Halle, Germany where he developed wafer bonding and thin film layer transfer technologies for semiconductor and ferroelectric materials. His experience also includes design of semiconductor components and optimized layout design at Semiconix Design Center in Bucharest. Ionut Radu obtained his B.S. in physics from University of Bucharest in 1999 and Ph.D (Dr. rer. nat.) in physics from Martin-Luther University Halle-Wittenberg in 2003. He has co-authored more than 60 papers in scientific journals, conference proceedings and reference handbooks and holds several patents in the field of semiconductor technologies. Dr. Radu is a member of IEEE society and was an invited speaker at ECS 2008 and 2010, IEEE LTB-3D 2010 and 2012 and ICICDT 2011.

3D integration (TechARENA)
SOITEC Rigny, Arnaud
Smart power technology needs smart substrate
Rigny, Arnaud

Rigny, Arnaud
Business Development Manager
SOITEC

Abstract
The smart power electronics allows remote control power conversion for real time system optimization. One of the most significant example is the automotive electronics evolution, where more and more mechanical systems (windows, sits, fuel injection, mass air flow sensor, breaks, etc) are remotely controlled through a communication bus (CAN, LIN or FlexRay). The BUS transceiver is a good example of a smart power device that integrates logic, analog and power functions in a harsh automotive environment: voltage spike in the bus of 100V, electromagnetic perturbation that induce noise current, extended temperature range (-40°C to 175°C), while maintaining a very high degree of reliability. In order to realize such transceiver, the industry has developed a dielectric isolation BCDMOS process, based on a Silicon-on-Insulator substrate (SOI), which consists in integrating power, analog and logic functions onto the same chip in different silicon island to prevent any perturbation. As a consequence, short circuit induced by voltage spike (latch-up) is avoided, as well as electromagnetic induced current noise. The dielectric isolation is also intrinsically temperature independent allowing operation higher than 175°C. Traditional SOI-BCDMOS process uses a thick SOI wafer (>5µm), shows excellent reliability performances, but with temperature and switching speed limitations. To further improve the performances, thin SOI-BCDMOS technology has been developed, using a thin SOI wafer (~1µm with high uniformity requirement) and based on fully-depleted power device to reduce all parasitic capacitances. The device then shows improved temperature performances, switching speed and low leakage. The thin SOI-BCDMOS approach brings additional value to the system by improving power efficiency, reducing leakage and system size. And besides automotive, these features are of particular interest in industrial, mobile and emerging applications such as internet of things.

CV of presenting author
Arnaud RIGNY, Buisness Development Manager Arnaud Rigny has been Business Development Manager since 2011 for Analog and Power application as well as silicon photonics application. He joined Soitec in 2006 and was managing R&D program between Soitec and CEA-Leti. For several years, he led the customer technical interface for non-digital applications and managed customers in developping new products on SOI and engineered substrates, including imagers, RF, Power and Photonics, working closely with key customers worldwide.. Prior to joining Soitec, he was Product Line Manager at Avanex (prior Alactel Optronics) where he was involved in optoelectronics devices such as pump lasers and Optical add-drops modules. His experience also includes project leader at Corning in optoelectronics device. Arnaud Rigny holds a PhD and a Master degree in Electronic and Communication from Ecole National Supérieur des Telecomunications at Paris (France).

Power Electronics Conference
Soligie, Inc. Heitzinger, John
Advances in Additive Manufacturing of Electronics
Heitzinger, John

Heitzinger, John
President
Soligie, Inc.

Abstract
The attractiveness of manufacturing electronics through additive methods such as printing, coating and related methods has been the topic of many conferences over the last decade. Much of the enthusiasm is an outgrowth from the success of using these processes, and the materials developed for them, in the membrane switch and electroluminescent lighting industries. The widely adopted vision of moving beyond single component or simple passive circuits to highly complex, integrated products produced by an "all printed" approach has been pursued by many in academic, military and commercial fields. Indeed, much progress has been made in the demonstration of technologies critical for the production of electronics through additive manufacturing. These, include improvements in materials, components and devices such as transistors, memory, OLEDs, batteries and sensors as well as processing methods and equipment. Despite these advances, there remain significant gaps in capabilities to manufacture and commercialize complex electronic products using purely additive methods. As a result, a hybrid approach where circuit elements fabricated using additive means are combined with traditional electronic components is being pursued. This talk will discuss the state-of-the-art in additive manufacturing of electronics, areas for improvement and the need for taking a system level approach to product design.

CV of presenting author
John M. Heitzinger, Ph.D., President at Soligie, Inc. - Dr. Heitzinger earned B.S. degrees in physics and chemistry from the University of Wisconsin at Stevens Point and a Ph.D. in chemistry from the University of Colorado - Boulder. He is a veteran of the semiconductor industry and held positions in research and development, engineering management, customer service and product management. His efforts led to successful product launches and product penetration into new accounts at fabs in the U.S., Europe and Asia. He joined Soligie at its start in 2005, built the engineering team and led programs that defined the manufacturing processes and services that Soligie offers to its customers today. John became President of Soligie in 2011 and manages the commercial aspects of the company while continuing to drive advances in manufacturing and the establishment of partnerships with technology and component providers. John is also a member of the Technical Advisory Board for the Nano-Bio Manufacturing Consortium, an organization created to mature an integrated suite of nano-bio manufacturing technologies and transition them to industrial manufacturing.

Plastic Electronics - PE2014
SORIN CRM Dal Molin, Renzo
Active implantable medical devices requirements for Nanoelectronics
Dal Molin, Renzo

Dal Molin, Renzo
Director of Scientific and Technical Coordination
SORIN CRM

Abstract
Active implantable medical devices have already a long history of innovation for improving their reliability and robustness, for decreasing their size, for increasing their longevity, for increasing their functionalities, for decreasing the cost of the therapy. There are still some barriers that limit their use in a much greater way than it should be. Barriers like: - Affordability by patient or healthcare system - Lack of evidence of cost-risk benefit - Acceptance by patient of an implant - Removal of the active implantable medical devices - Reliability of the active implantable medical devices In the presentation we will discuss how nanoelectronics can help to improve the use of active implantable medical devices.

CV of presenting author
Renzo Dal Molin is the Director of Scientific and Technical Coordination for SORIN CRM (Cardiac Rhythm Management), which is a business unit of SORIN GROUP. He is responsible for research mainly conducted in European projects. His scope is to bring innovation in pacemakers, implantable sensors and defibrillators, active implantable medical devices communication and home monitoring systems. He is Vice Chairman of EPoSS,(European Technology Platform on Smart Systems) Chairman of Working Groups Smart Systems for Healthy Living and Applied Micro-­Nano-­Bio Systems. He is very active in telecommunication standardization as he was involved in ECC reports 149 and 150 published by the European Communications Office and rapporteur of ETSI standards EN 301 559 and EN 301 489-­35. He is Project Coordinator or SORIN CRM responsible for European or national projects. He has a 34 years experience in bioelectronics, ASIC design, Microelectronics Packaging, Interconnect and Assembly. He obtained his master in Electronics and Biomedical Engineering in 1979 from ESSTIN and University of Nancy France. He then occupied in SORIN CRM different positions like hardware & software project engineer, pacemaker & defibrillator project manager, MEMS analog&digital integrated circuits design manager. He holds more than 20 US and European patents.

Low Power Conference
Application driven technology: Nanoelectronic for Healthcare (TechARENA)
ST Microelectronics Rabouin, Jean Pierre
Lean : the ST Manufacturing strategy for Efficiency
Rabouin, Jean Pierre

Rabouin, Jean Pierre
Director Lean manufacturing STM Rousset
ST Microelectronics

Abstract
STMicroelectronics Rousset 8 inches fab, 0.18µm to 80 nm, 7800 wafers/week, smiffed and fully automated. In 2008, a comprehensive program of Lean transformation involving manufacturing and support teams started to enhance its industrial competitiveness. Lean principles deployed are summarized in 6 axes (Visual Management, go and see on the shop floor, global vision thinking flow of product, standardization, problem solving and recognition). After 5 years, the 200 lean workshops closed, the new management principles and the new organization improved KPI by of 42% in global equipment down-time, 28% in average lot cycle time, 83% on the external customer claim and 58% on people accident rate. To give a new dynamic, mid-2013, a new program is launched, new vision and new KPI, based on 5 key axes to reinforce lean principles and to go deeper in using tools.

CV of presenting author
1984 ESEO Angers Engineer 1977 - 1985 Incoming inspection manager Thomson Angers 1985 - 1987 QA Fab Manager Thomson Angers 1987 - 1992 EPROM EEPROM Test Engi SGS Thomson Rousset 1992 - 2011 EWS Manager ST Micro Rousset 2011 - 2014 Lean Program manager ST Micro Rousset

18th Fab Managers Forum
STMicroelectronics Portelli-Hale, Chris
Portelli-Hale, Chris

Portelli-Hale, Chris
SPA Front-End Manufacturing & Technology R&D
STMicroelectronics

Biography
Chris Portelli-Hale holds the post of Operational Programs Director in the Manufacturing Execution Excellence team within the Front-End Manufacturing & Technology R&D organization of ST Microelectronics, based in Rousset France. He holds a degree in Electronics Engineering from the University of Malta and joined ST in 1989 where he has held various positions is Test Engineering and Test Operations Management within different organizations and locations of the company in Malta, France and Singapore. Chris is Chairman of CAST the Collaborative Alliance of Semiconductor Test group which brings together several actors within the test arena from IDMs, Fabless and Equipment vendors.

16th European Manufacturing Test Conference (EMTC)
STMicroelectronics Le Pailleur, Laurent
Le Pailleur, Laurent

Le Pailleur, Laurent
Conference Chair and Technology Line Management Director
STMicroelectronics

Biography
In 1989, Laurent Le Pailleur received the degree in electrical engineering from ENSICAEN (National Engineering School) , the M.S. degree in instrumentation and automation from Caen University and the Business degree from IAE (Enterprise Administration Institute). He has been working on mixed-signal video systems and imaging digital processors with Philips Semiconductors as designer then design team manager. In 1997, he joined STMicroelectronics, Grenoble, to develop dedicated solutions for wireless and multimedia applications. He also enjoyed various positions as audio and power management product line manager, 2.5G mobile platform product manager then 3G mobile digital System-on-Chip product management director. This allowed him to develop deep understanding on RF, analog and digital technologies, architecture, cost structure and system partitioning. He built new methodologies as head of technology management (semiconductor, packaging and IPs) with ST-Ericsson. He is now director for advanced Cmos technology line with STMicroelectronics, Crolles, as well as ST Management Committee Member within the 10nm international development team, covering bulk, FD-SOi and FinFet technologies. He participated to numerous international conferences and hold multiple patents.

Low Power Conference
STMicroelectronics Zuffada, Maurizio
Zuffada, Maurizio

Zuffada, Maurizio
R&D Director
STMicroelectronics

Biography
Maurizio Zuffada received the Laurea Degree in Electrical Engineering from Università di Pavia. He joined SGS-ATES Semiconductors in 1981 as analog design engineer. Since 1985 he has been managing a team of analog designers aimed at industrializing analog mixed signal integrated circuits for the consumer market applications. In 1990 he joined the Data Storage Division beginning a new R&D initiative in analog mixed signal ICs for hard disk drives rw-channel applications. In 1994 he was appointed R&D Director of the Data Storage Division, inside the Telecommunication Peripheral and Automotive Group of STMicroelectronics. In 1996 he took the R&D responsibility of peripheral products targeting the hard disk drive, tape storage and printer applications. In 2003 with the foundation of the Computer Peripheral Group he was appointed R&D Group Director. In 2005 he moved to Advanced R&D with particular emphasis on strategic IPs. In 2005 he joined the Medea_Plus European R&D organization as representative for STMicroelectronics Italy. Since 2006 he is the president of the Scientific Steering Committee of the Studio di Microelettronica which is an R&D ST Lab joint with and housed inside the University of Pavia. Currently he is involved in strategic researches and R&D programs for high speed low energy communications. He is currently inside the Catrene SGA European's organization and EPIC's board member. During the last 8 years he and his R&D team were following the progresses on the emerging "Silicon Photonics Technology". On that particular technology he has summarized the state of the art and his vision in the joint plenary session of the ESSCIRC 2012, EU Nanotech Forum 2012, in the work shop of EU Photonics21 2013, ECOC 2013 and SEMICON 2013. He holds many patents of which 28 are US patents.

Silicon Photonics (TechARENA)
STMicroelectronics Vasseur, Marc
Vasseur, Marc

Vasseur, Marc
Imaging Division
STMicroelectronics

Biography
Marc graduated in Masters in Business Administration in 1983. Marc started his professional career holding various positions in Marketing or Sales, in France and in Asia at Citroën, Philips TV and Thomson Semiconductors. Marc's involvement in semiconductors started in 1985, when he joined Thomson-Semiconductors, then STMicroelectronics. Marc specialized in large volume consumer oriented activities, by holding various management position in the Video Division of STMicroelectronics and managing related external partnerships (Joint-ventures, common R&D centers and external acquisitions). After the acquisition of VLSI Vision, one of the pioneers of the CMOS Image Sensors by STMicroelectronics in 1999, Marc became General Manager for the Imaging Division, in the forefront of the Camera Phone technologies and industry development. In 2007, Marc joined Sensitive-Object, a start-up company developing acoustic touch technologies and products, as Vice President, in charge of Marketing, Operations and Business Development. The company was subsequently acquired by Tyco Electronics. Since 2009, Marc is also the owner and managing Director of MVAssociates SARL, a consulting entity working in technology business models and high technology to mass volumes projects. In STMicroelectronics since 2011, Marc currently holds the position of Director, Camera Modules Business Line at STMicroelectronics, and also manages the contracts and partnerships team for the Imaging Division.

Imaging Conference
STMicroelectronics Finck, François
Improving manufacturing efficiency thanks to collaborative European projects
Finck, François

Finck, François
Director, R&D Cooperative Programs
STMicroelectronics

Abstract
ST Crolles 300mm manufacturing line is both facing the problems of developing industrializing More Moore and More than Moore technologies which demands high flexibility to manage a high diversity of technologies and products. To maintain its competitiveness ST Crolles must efficiently manage a high product and technology mix and heterogeneous lots of different size and priority for development, engineering and prototyping. This implies to conduct research to support the development of new manufacturing procedures, organizations and information and control systems (FICS) and their implementation without disrupting the Crolles Fab-lab environment. The ENIAC project INTEGRATE is gathering a strong consortium of European SC manufacturers, solution providers and academics that are bringing their complementary skills and experience to address these challenges. INTEGRATE consortium is considering the development of enhanced integrated process control and equipment control tools, together with advanced lot flow control techniques. The developed tools and methods will have to interact with lower and upper decisions levels and also consider various elements of the fab (tool status, auxiliary resources, qualifications, etc). Mandatory to enable the integration of the developed tools and techniques, dynamic knowledge management methodologies are also addressed in INTEGRATE.

CV of presenting author
François Finck, aged 59, is an engineer in semi-conductor physics from the Institut Polytechnique de Grenoble. He is currently R&D Cooperative Programs Director at STMicroelectronics in Crolles. He is leading many R&D collaborative projects especially in the domain of manufacturing sciences. He has an experience of more than 35 years in Device Engineering, Yield Management and Statistical Data analysis.

Fab productivity (TechARENA)
STMicroelectronics Cathelin, Andreia
Fully integrated CMOS THz Imaging Solutions
Cathelin, Andreia

Cathelin, Andreia
Senior Member of Technical Staff
STMicroelectronics

Abstract
THz systems with commercial viability will require portability, high integration-levels, video-rate speeds, low power-consumptions as well as room-temperature operation. Therefore, Silicon technologies are attractive system-on-chip alternatives to classical expensive Terahertz systems based on III-V compounds, micro-bolometers and others. In this talk we will discuss the ability of THz detection well beyond fT/fmax of standard Silicon-based transistors. We will then address the key design challenges and techniques for designing, operating and characterizing efficient focal-plane arrays of direct power-detectors for Terahertz video-rate multi-pixel imaging, as well as the trade-offs involving bandwidth, sensitivity and power-consumption, in view of various electrical and electromagnetic constraints. Full system integration capabilities will be demonstrated based on a recently reported work of a 1kpixel 65nm CMOS video-camera for active THz-imaging (0.6-1.1THz).

CV of presenting author
Andreia Cathelin (M'04, SM'11) started her electronic studies at the Polytechnic Institute of Bucarest, Romania and graduated from the Institut Supérieur d'Electronique du Nord (ISEN), Lille, France in 1994. In 1998, she received the Ph. D. degree from IEMN/ISEN, Lille, France regarding the work on a fully-integrated BiCMOS low power - low voltage FM/RDS receiver. In June 2013, she received the "habilitation à diriger des recherches" (habilitation) degree from the Université de Lille 1. In 1997, she was with Info Technologies, Gradignan, France, working on analog and RF communications design. Since 1998, she has been with STMicroelectronics, Crolles, France, now in Embedded Processing Solutions Segment, Design Enablement & Services, as Senior Member of the Technical Staff. Her major fields of interest are in the area of RF/mmW/THz systems for communications and imaging. June 2012, Andreia has been designated winner of the STMicroelectronics Technology Council Innovation Prize. She is member of the Technical Program Committee of ISSCC, VLSI Symposium on Circuits and ESSCIRC; she currently serves as chair for the RF sub-committee at ISSCC and secretary for the 2014 VLSI Circuits Symposium. In September 2013, Andreia has been elected on the Steering committee of ESSCIRC-ESSDERC conferences. She is as well member of the experts' team of the AERES (French Evaluation Agency for Research and Higher Education). She has authored or co-authored 100 technical papers and 4 book chapters, and has filed more than 25 patents. Andreia is a co-recipient of the ISSCC 2012 Jan Van Vessem Award for Outstanding European Paper and of the ISSCC 2013 Jack Kilby Award for Outstanding Student Paper.

Imaging Conference
STMicroelectronics Cogez, Patrick
Outside system connectivity
Cogez, Patrick

Cogez, Patrick
Director, Innovation and External Research
STMicroelectronics

Abstract
Connectivity is nowadays a main driver of the semiconductor industry, on a par with data processing and storage requirements, and the much-publicized "Internet of Everything" wave will reinforce that trend. This calls for technology that provides cost effective energy efficient connectivity whatever the environment. Within the so-called "ITRS 2.0" structure, the Outside System Connectivity (OSC) Team was established in order to identify the capabilities required to support these connectivity needs over a fifteen years horizon, and work with ITRS technology competence centers to translate these future communication capabilities into components and technologies roadmaps. The talk will present the initial technologies being included in the scope of the OSC Focus Team, the roadmapping process envisioned by the team, and the stakeholders it would like to engage with.

CV of presenting author
Patrick COGEZ graduated from Ecole Polytechnique and from Ecole Nationale des Ponts et Chaussées. He also holds a MSc. Degree in Operations Research and a PhD in Industrial Engineering, both from University of California, Berkeley. After starting his career as a civil servant in the French Ministry of Industry, he joined STMicroelectronics, where he held various management positions in Information Systems, Knowledge Management, and Central R&D Program Direction. Since 2005, he is in charge of innovation and external research for Crolles site, within STMicroelectronics Embedded Processing Solutions Sector. Patrick COGEZ is STMicroelectronics representative within the steering committee of the International Technology Roadmap for Semiconductors, and Chair of the European Nanoelectronics Infrastructure for Innovation (ENI²).

ITRS: Trends in Enabling Technologies (TechARENA)
STMicroelectronics Jacquet, David
Architectures for Energy Efficiency and power management
Jacquet, David

Jacquet, David
System architect
STMicroelectronics

Abstract
With the increasing demand of processing power to be delivered by the System On Chips, it is key to improve their energy efficiency, not only for thermal or battery life duration purposes but also for environmental considerations such as green supercomputers, wireless base stations and micro servers. After a first section dedicated to the different techniques for energy efficiency { DVFS, Body Biasing, Power domains, AVS & process sensors }, we will see how the FD-SOI technology can further enhance the efficiency of those techniques and create new opportunities like Wide DVFS and dynamic leakage management. The architecture of the key IPs to implement those techniques is detailed. The benefit of FD-SOI in multi-processing computing systems will also be illustrated showing the added value compared to bulk technology. Silicon results will demonstrate the potential of body-bias for obtaining very high speeds in very-low voltage conditions.

CV of presenting author
David Jacquet is a Senior Principal Engineer at STMicroelectronics. He joined STMicroelectronics in 1995 as a Design and Architecture team lead for the development of a 64-bit VLIW DSP. In 2003 he moved into a new role leading the SOC low power architecture for digital baseband and application processor products for mobile platforms at ST-Ericsson. He currently leads the architecture activities for energy efficient high performance CPU/GPU implementation at STMicroelectronics. David holds a degree in microelectronics engineering from ENSERG-ENSIMAG in Grenoble, France.

Low Power Conference
STMicroelectronics Ferrera, Marco
Manufacturing challenges of MEMS for wearable electronics
Ferrera, Marco

Ferrera, Marco
Technology Development Manager
STMicroelectronics

Abstract
T B A

CV of presenting author
Marco Ferrera graduated in Electronics Engineering at Politecnico di Milano (Italy). He joined STMicroelectronics (STM) in September 1994. He has been part of the initial team that pioneered MEMS and has actively contributed to the entire MEMS history in STM. He has strong experience all over the product supply chain, from prototyping to mass production, aimed at supporting new business opportunities, products and road maps developed internally in ST and in direct collaboration with key partners and customers.

Plastic Electronics - PE2014
STMicroelectronics Pagani, Alberto
3D IC Test through Power-Line Methodology
Pagani, Alberto

Pagani, Alberto
Test R&D and Competitive Intelligence
STMicroelectronics

Abstract
Today, the main challenge of 3D IC is testing. A mixed signal architecture to test a 3D IC was investigated. This new methodology introduces low complex power line communication circuits to exchange testing signals between ATE tester and at least one chip that belongs to a 3D stack, or between at least two chips. Significant benefits for probing and 3D DFT access can be highlighted, and some main advantages for using power line communication to test a 3D stack can be: 1) Architecture is fault tolerant for power TSV defects due to multiple TSVs used for each power supply (in order to provide right current to each DUT), then there is TSV self-redundancy that will allow to test 3D DUT in case of some defective power TSVs 2) Architecture simplifies test standardization in particular when in a 3D stack there are chips from different suppliers. 3) Architecture has less constraint at design level regarding routing, because it avoids the introduction of extra test signal TSVs among different ICs of a 3D stack. Then this new approach has some advantages with respect to other developments in state-of-art. Preliminary studies confirm feasibility of this new methodology applied on standard wafer testing and 3D IC testing through a power line communication architecture.

CV of presenting author
Alberto Pagani received master degree in Electronic Engineering from Politecnico di Milano, Italy. He joined STMicroelectronics in 2000 where he worked for five years in wafer sort department in Agrate as Process Engineer and Test Engineer on Flash memories. Since 2006, he has been working in Europe EWS (Electrical Wafer Sort) and EWS Technology and he is in charge of Test R&D and Competitive Intelligence. He is Member of STMicroelectronics Technical Staff as Senior Staff Engineer. His work is mainly focused on innovative testing and probing methodologies also to develop new products for new markets. He is author of some scientific papers and holds more than 40 patents in several countries.

16th European Manufacturing Test Conference (EMTC)
STMicroelectronics Boeuf, Frederic
Recent Progress in 300mm Si-Photonics R&D and Manufacturing
Boeuf, Frederic

Boeuf, Frederic
Silicon Photonics, BiCMOS and Advanced Device Process Integration Manager
STMicroelectronics

Abstract
The maturity level reached in the integration of the key photonics devices into silicon substrate has generated an increased interest in developing a Silicon Photonics technology platform capable of fulfilling HPC and Data Center requirements. Already present in the optical communication market through the development of dedicated BiCMOS technologies, STMicroelectronics started the development and qualification of a 300 mm Silicon Photonics technology. We will describe the process integration and the key devices allowing to achieving efficient electro-optical transceivers. The advantage of 300mm process control over 200mm will be discussed. Performance of optical passive component, and especially grating coupler I/Os will be described. Integration and performance of 25Gb/s compatible High Speed Phase Modulator and Ge-based High-Speed Photodiode with Electronic chip using a 3D approach will be shown.

CV of presenting author
Frédéric Boeuf , born 1972, obtained his M.Eng. and M.Sc. degree from Institut National Polytechnique de Grenoble in 1996 and Ph.D. from the University Joseph Fourier of Grenoble (France) in 2000. Then he joined STMicroelectronics where he was successively responsible for the research phases of 65nm, 45nm, 32nm UTBB and 20nm FDSOI CMOS technologies. In 2012 he co-received the French "General Ferrie" Grand Prize Award for his work on FDSOI technology. He authored and co-authored over 150 technical papers. Since 2010 he is managing the Silicon Photonics, BiCMOS and Advanced Devices Technology group inside STMicroelectronics's Silicon Technology Development Group.

Silicon Photonics (TechARENA)
STMicroelectronics Clerc, Christian
Secondary equipment opportunities, risks and advantages
Clerc, Christian

Clerc, Christian
Director- Industrial Engineering & Process Technical Committee
STMicroelectronics

Abstract
STMicroelectronics is a global Semiconductor Leader and the Largest European Semiconductor Company. With Front-End Manufacturing sites in Europe ( Italy and France ) and in Singapore the pressure on cost is enormous to continue to be competitive, means the use of second hand equipment to increase or adapt capacity in 8" is mandatory. 200mm second hand equipment can be addressed in different way and opportunities according tools set, European constraint and tools available on the market. The presentation will be done to show the ST approach, the challenges ( more and more important in Europe ) and the different opportunities existing.

CV of presenting author
Christian CLERC, STMicroelectronics, WW Engineering programs director. 33 years' experience in Semiconductor Operations Graduated of the Science and Technology university of Marseille with license in chemistry and a master of metallurgy, he started in 1981 in Eurotechnique, Rousset (France) as lithography process engineer, moving to process and maintenance in etch and litho areas . In the 90's has been in charge to implement the TPM ( total productive maintenance) and the CIP ( capacity improvement program) approaches in manufacturing area. Next he get different responsibilities in the global operation covering process, maintenance, manufacturing and process control. He was in charge in 1999 of the new 8" fab start up in Rousset ( France ) for equipment choice, hook up, installation, qualification. In 2001 in charge of the fab ramp up with stabilization of the maintenance in term of equipment performances ( reliability, cost of ownership, and OEE improvement programs). Since 2005, he is responsible in Front End central function WW for the Engineering programs covering manufacturing execution in process, equipment and industrial Engineering, managing and coordinating the assets across the company WW.

Secondary Equipment (TechARENA)
STMicroelectronics Chery, Jean-Marc
Highly Energy Efficient Nanotechnologies and Applications
Chery, Jean-Marc

Chery, Jean-Marc
Chief Operating Officer
STMicroelectronics

Abstract
After decades of steady gradual evolution, the semiconductor industry is now facing its biggest and most interesting challenge. The number of connected electronics devices is growing exponentially, starting with mobile devices and it is now accelerating with the internet of things. To sustain this exponential growth, the semiconductor industry requires a real breakthrough in energy efficiency both for the connected devices and for the communication infrastructure. At the same time, the traditional planar bulk CMOS technology is plateauing in power consumption and performance after 28nm. Therefore innovative solution for very energy efficient systems are mandatory to continue the growth the semiconductor industry enjoyed, covering ultra low power systems, energy management and harvesting. We will explore some of these solutions which have to be as well cost effective and simple to put in very large volume production.

CV of presenting author
Jean-Marc Chery is Chief Operating Officer, General Manager, Embedded Processing Solutions (EPS) at STMicroelectronics . He also holds overall responsibility for the EPS Technology R&D and Front-End Manufacturing, as well as the Packaging & Test Manufacturing for the whole Company. Chery is Vice Chairman of ST's Corporate Strategic Committee

Low Power Conference
STMicroelectronics Imbs, Yvon
From Design To Packaging: Necessity & Limitation Of Verification & Simulation Tools
Imbs, Yvon

Imbs, Yvon
Electrical Modeling & Co-design Manager
STMicroelectronics

Abstract
Following the trend of growing complexity for electronics devices due to increasing level of integration and continuously performance improvements, efficient design, verification & simulation tools are mandatory to ensure optimized quality, time to market and performances vs cost design. The scope of this article is to explore these principles when dealing with IC packaging design & manufacturing. Secure package assembly processes are mandatory to sustain Time to market & quality requirements. Therefore, STMicroelectronics developed its own verification tool for wire bonding assembly process that permits custom assembly rules checks. For the flip chip assembly process, an external tool is used to code the complex design & assembly rules for BGA/LGA substrate. In parallel, to get the best cost/performance trade-off and again ensure the best time to market, the co-design approach has become mandatory. This system-aware (IC, Pkg & Board) way of designing is requesting parallel designs flows. Specific EDA tools are enabling optimized implementations of the Die, Package and PCB layouts. However these co-designs way of working requires deeper planning management to enable some database synchronizations and may lead to numerous feedback (ECO) loops. To assess the performances, enable some choices & define some margin levels, the co-simulation is necessary to get more predictive assessment of electrical behavior of each sub part of the platform. This activity permits the electrical verification of the always higher signal & power integrity constraints. The drawback of such simulations is the time and hardware resources necessary, and the variability of some processes. If not well delimited, such analysis can lead to overdesign and can be critical for the time to market. These assembly, co-design & co-simulation steps will be developed as implemented at STMicroelectronics thru flow & tools. Theirs benefits and limitations will also be discussed.

CV of presenting author
Yvon Imbs joined ST Microelectronics in 2000 after an Ph.D. on Ultra Wide Band antennas. He is now responsible of the Electrical and Design Rules Management Team in the ST Corporate Packaging & Automation organization. His team is in charge of Design Rules management, implementation with Package Design Technology Kits and automated checks. Package electrical optimization thru modeling, SI/PI analysis and co-design methodologies is also part of his responsibilities.

Advanced Packaging Conference (APC)
STMicroelectronics Skotnicki, Thomas
Ultimate scaling of CMOS technologies
Skotnicki, Thomas

Skotnicki, Thomas
ST Company Fellow
STMicroelectronics

Abstract
Electronics is more and more pervasive in everyday life: smartphones, connected cars, Internet of Things. All this is not only about mobile energy efficient technologies, but also about energy harvesting and storage, about power management, and also about sensors and MEMS devices. UTBB (ultra-thin body and BOX) FD-SOI (Fully Depleted Silicon On Insulator) is a planar semiconductor technology that is particularly well suited for low power applications such as Internet of Things. We will demonstrate this on the example of the 28nm UTBB SOI technology that ST is offering for LP mobile applications. We will also describe briefly the energy harvesting technologies that help to reduce power required from the supply. Convergent use of the intrinsically low power consumption offered by the UTBB SOI and of the energy harvesting, further reducing the demand on the supplied power, will be shown as the key enabler for low power applications such as Internet of Things. The paper describes the development of the FD-SOI technology, the choice of devices centering and their main characteristics, We will explain how the intrinsic device characteristics enabled by their UTBB SOI structure contribute to promoting the technology for high speed energy efficient operation, even in low voltage conditions.

CV of presenting author
Thomas SKOTNICKI is the STMicroelectronics Fellow and Director of Advanced Devices at STMicroelectronics Crolles, France, that he joint in 1999. He received his Master and EE degrees from the Warsaw University of Technology in 1979, the PhD diploma from the Institute of Electron Technology, Warsaw Poland in 1985, and in 1993 he received the HDR (Habilitated for Directing Research) diploma from the Institut National Polytechnique de Grenoble, France. In 2007, he received the title of Professor from the President of Poland. The focus of his program at STMicroelectronics is on Low Power / Low Variability for 20nm and beyond CMOS, on innovative device structures, new memory concepts and cells, and on integration of new materials for CMOS. Recently he has extended the scope to include Energy Harvesting for autonomous Low Power systems and devices. He holds about 80 patents on new devices, circuits and technologies. He has presented over 50 Invited Papers and Short Course Lectures, co-edited one book, (co-) authored about 350 scientific papers (review based), and several book chapters in the field of CMOS devices and circuits. From 2001 to 2007, he served as Editor for IEEE Transactions On Electron Devices. He has been teaching at EPFL (Lausanne) and INPG (Grenoble), and has supervised and led to successful defence 25 PhD theses. He has been serving in numerous Conference Program and Executive Committees (IEDM, VLSI, ESSDERC, ECS, SNW, IWJT), Academia Advisory Boards, Governmental Expert Commissions, R&D Program Steering Committees, ITRS, and Award Committees. He is an IEEE Fellow and SEE Senior Member.

Low Power Conference
STMicroelectronics Perriaud, Eric
ST Low cost wire bonding solution : Copper Cu, CuPd and Silver alloy results and startegy down to Ultra Fine Pitch 45 µm BPP (30µm Ball diameter process)
Perriaud, Eric

Perriaud, Eric
Wire Bonding Enginieur
STMicroelectronics

Abstract
Wire bonding low cost solution implementation is a priority for Semiconductor packaging R&D teams worldwide as gold wire is one of the major package cost contributor. Copper wire bonding has been successfully deployed in the past years and ST was among key players on that program. More than 16B units produced since the beginning of that program in ST without any customer complaint / ECC for all business segments : Automotive, Wireless, computer, set-up box, Industrial, Tablet*** Two types of copper wire are used massively in ST : 1) Bare copper wire 2) CuPd wire when bare copper showed some productivity limitation at second bond issue. CuPd wire used in ST to enhance the second bond productivity which is starting to become challenging at 0.7 mils wire diameter and not possible with 0.6 mils bare copper. In addition of this, wire bond engineers are still working on new materials, new wire bonder algorithms, as well as new process solutions to alleviate product reliability related problems associated to copper wire bonding in ultra-fine pitch application / Ultra small ball process : 45 µm BPP / 39µm Bond Pad Opening. 45µm Bond Pad Pitch require a 30µm bonding ball diameter process which start to be at the limit of copper wire capability vs workability & product mission profile reliability target. Type of package & Bill Of Materials are playing a key role also on this copper reliability performance limitation. For this advanced ball diameter range, a solution has been identified to move forward the limit : Silver Alloy (Ag-Alloy) Effectively, Silver Alloy (Ag-Alloy) is a solution to enlarge the process window for different type of packages or BOM and to extend the time to failure / product mission profile. This technical presentation aims to share low cost wire bonding results (Copper, Copper-Palladium, Silver-Alloy) & associated strategy down to 45 µm BPP / 0.6 mils wire diameter.

CV of presenting author
Eric Perriaud Fabien Quercia

Advanced Packaging Conference (APC)
STMicroelectronics Rochereau, Krysten
What's aside of Megapixel race: Imager & Photonics Process Development for Mass Production
Rochereau, Krysten

Rochereau, Krysten
Img div. / CMOS & CIS process manager
STMicroelectronics

Abstract
This talk is to discuss about serving the new growing opportunities aside of megapixels mobile applications, disrupting with the needs for integrating more and more pixels on the same piece of silicon. Let's see how the advanced R&D work to optimize opto-electrical performances of small pixels can fuel the development and mass volume industrialization for dedicated sensors and cameras on specific markets, such as Automotive or Medical ones and how alternative photo-site technology like embedded SPADs can be more adapted for some dedicated applications.

CV of presenting author
Krysten is CMOS and CIS process manager for Imaging division at STMicroelectronics. He's got a Msc from Ecole Nationale Supérieure de Physique (ENSPG) de Grenoble in 2001 and from Joseph Fourier University with semiconductor physics specialty in 2002. From 2002 to 2007, he worked as test and characterization engineer for Philips Semiconductors focusing on analog behavior of advanced CMOS devices. In 2007, he joined ST and its Wireless Business Division supporting the silicon and package process development for Power and AMS products then for RF and Baseband applications. In 2011 he moved to Imaging Division, where he is currently in charge of CMOS and CIS process development in collaboration with Technology R&D group.

Imaging Conference
STMicroelectronics Lule, Tarek
Automotive Camera Systems - Photons to Ethernet
Lule, Tarek

Lule, Tarek
Camera System Engineer
STMicroelectronics

Abstract
Automotive applications are multiplying in coming years, and ask for image sensor systems with moderate resolutions but very high dynamic range and excellent low light performance while operating with low power consumption, and very high ambient temperatures. However, most CMOS imagers are optimized for high resolution consumer requirements. By combining process advancements from consumer application with automotive technology and design, the optimal automotive image sensor and processor chip set system is achieved, which transforms incoming light into an H264 image stream over Ethernet. This presentation will summarize the various specific automotive camera demands and how they were covered by choices of architecture, design and technology. The constrained power envelope can further be leveraged in surveillance cameras for battery powered security applications.

CV of presenting author
T. Lulé is working for STMicroelectronics since 2003 on CMOS Image Sensors. His current research topics include HDR camera systems for automotive and security application. Before his activities domains included Autofocus mobile cameras, waferscale packaging, analogue design, Above-IC technology. Prior to working STMicroelectronics he worked for Silicon Vision AG which he co-founded in 1996, and which amongst others already developed HDR automotive imagers in TFA technology. T. Lulé obtained the M.phil. degree in Microelectronics and Semiconductor Physics in 1992 from University of Cambridge, UK, and the Bachelor in Physics 1990 from University of Siegen.

Imaging Conference
STMicroelectronics Saggio, Mario
SiC and GaN power devices: technologies and products
Saggio, Mario

Saggio, Mario
R&D
STMicroelectronics

Abstract
Compound semiconductors (and mainly at the moment SiC and GaN) power devices have practically shown a quantum leap in the performances of power devices and in the possibility to enlarge the use of power electronics especially at very high voltages and high power. However, the status of SiC and GaN devices today is much less mature than that of Si power devices in terms of manufacturability, material quality and process control, cost and reliability. In this talk activities on SiC and GaN power devices at STMicroelectronics will be presented. SiC devices (Power Schottly, MOSFETs) in the fast few years has moved from academic curiosity and outstanding proof of concepts to products with excellent performances and proven reliability. Progress in the quality of substrates and epitaxial layers has been outstanding and evidences will be given on how the screening of residual defects is of paramount importance to achieve high yield and reliability. Also, performances of current products will be presented and roadmaps highlighted. GaN Devices are also getting out of simple academic curiosity and are promising not only to enlarge the field of use of power devices but also to challenges Si in some of today markets. It will be shown that performances of GaN HEMT devices and the possibility to build them on GaN epitaxial layers grown on Si are opening paths to this scenario. However, especially for high voltage devices (600 V and above), robustness in term of final reliability in the application has to be improved, in spite of the fact that significant progresses in understanding and correcting some of the issues have been made in the last period. Finally, for both SiC and GaN devices the expected trends of the cost/performances ratio will be presented.

CV of presenting author
Mario Giuseppe Saggio was born in Assoro, near Enna, Italy, in 1967. He graduated in Physics at Catania University in 1991. From 1993 to 1995 he was with CNR IMETEM involved with application of computer simulation to process and device engineering in Microelectronics. In 1995 he was with FhG-IIS B in Erlangen (Germany) in the frame of the European program Human Capital and Mobility. From December 1995 he is with R&D department of STMicroelectronics in Catania. He led high-voltage power devices design team for Si and and Silicon Carbide devices from 1999. He is director for SiC technologies and devices. He has authored or coauthored over 40 papers in journals and conference and holds 30 patents

Power Electronics Conference
STMicroelectronics Srl Contiero, Claudio
Challenges on BCD Technology Evolution
Contiero, Claudio

Contiero, Claudio
R&D Senior Director - Company Fellow
STMicroelectronics Srl

Abstract
Mixed Power technologies like Bipolar-CMOS-DMOS (BCD), represent a good example of the so called "More than Moore" concept where the progress does not depend merely on the evolution of technology node, like in the "Moore's Law" centered on digital, but more on device conception and addition of features driven mainly by application requirements. The availability on the same platform of a large variety of components to realize high power stages, analog and digital functions, poses many technology challenges to find the best trade-off among the ingredients necessary to guarantee reliable and optimal power device performance and those required to achieve good analog features and large density in the control circuit. As a matter of fact the roadmap of BCD follows with a few years delay the digital CMOS and the advantages coming from scaling down of lithography are showing saturation on improvement of power device performance. This presentation will provide an overview about the challenges on BCD technology evolution where to achieve better power devices and added analog functions it requires conception and introduction of innovative device architectures and materials.

CV of presenting author
Claudio Contiero is Senior Director of Process Development and TCAD for Smart Power Technology in STMicroelectronics R&D, Milano, Italy and ST Company Fellow. He received his Master degree in Physics from the University of Padova in 1976. He joined SGS-ATES (now STMicroelectronics) in 1978 where he started working on Power Discrete MOS technology. In 1983 he pioneered a new integrated silicon technology called "BCD" that combined Bipolar, CMOS and power DMOS devices on the same chip. Subsequently he contributed to its extension from 20V to 700V and evolution from the 1st (4 µm) to the 9th (0.11 µm) generation. He is co-holder of many patents and co-author of numerous technical papers on integrated semiconductor power technology. He served several times as technical committee member of various international Symposia and Conferences, and presented many invited papers. In 2006 he was the "Technical Program Chairman" at the IEEE - International Symposium on Power Semiconductor Devices & ICs.

Power Electronics Conference
Sunchon National University Cho, Gyoujin
Fundamentals to Start Fully R2R Gravure Printed Flexible Logic Circuits and TFT Backplane Arrays
Cho, Gyoujin

Cho, Gyoujin
Professor
Sunchon National University

Abstract
R2R gravure has been considered as the most practical process for the production of costless flexible logic circuits and TFT backplane arrays, key units for the realization of ubiquitous society. As a consequence of pursuing fully R2R gravure printed logic circuits and TFT backplane arrays, this presentation will introduce fundamentals in R2R gravure systems including web handling, overlay printing registration accuracy, electronic ink formulations and printed device physics for printing flexible RFID tags and 20 x 20 TFT backplane arrays on plastic foils using a R2R gravure system.

CV of presenting author
Gyoujin Cho received the Ph. D degree from the University of Oklahoma, Norman, in 1995. In 1996, he joined as a faculty member of the Department of Chemical Engineering, Sunchon National University, Korea, and currently he joined as a faculty member at Department of Printed Electronics Engineering, World Class University Program in Sunchon National University. Since 2002, he has focused his research on printed electronics and successfully demonstrated all gravure printed 13.56 MHz operated 4, 16, 32, and 96 bit RFID tags. Recently, he is working in developing fully R2R gravure printed TFT backplane arrays and successfully demonstrated R2R gravure printed 20 x 20 TFT arrays with 99% yield with 60% of threshold voltage variation. Those works were introduced by BBC News Technology on Aug. 13, 2012 and NHK on Jan, 1, 2013.

Plastic Electronics - PE2014
Supergrid Institute Mermet-Guyennet, Michel
Silicon Carbide devices for high voltage / high current applications
Mermet-Guyennet, Michel

Mermet-Guyennet, Michel
Programme Director
Supergrid Institute

Abstract
From scientific and market surveys on wide-band gap semiconductors, SiC devices will mainly find potential applications with high voltage and high current (Voltage Breakdown Vbr >1700V & Nominal Current Inom > 100 A). Among these applications, smart grid, super grid, electricity generation (wind turbine, hydro turbine, and photovoltaic) and traction drive for trains will be the main users of high voltage and high current devices. The available technology is MOSFET for transistor and JBS for diodes (up to 3,3 kV), some suppliers propose JFET but the trend is mainly towards MOSFET for two reasons : normally-off devices and easy control & paralleling. For very high voltage 6,5 kV, 10kV, 15 kV and over, bipolar based structure is more relevant and several technologies have been investigated : Thyristors,IGBT. Another aspect in the introduction of high voltage SiC devices is the global supply chain from the material to the final applications: 1)Base wafers 2)Thick epitaxy (100 m for 10kV) 3)Device processing (choice and design of the structure ) 4)Packaging (paralleling for high current, electrical isolation) 5)Integration of gate-drive and capacitor (optimization of switching frequency) 6)Integration of power electronics with sources and loads (cable for grids, motors for traction) This paper will details some key aspects on the device technologies linked with the applications and the potential solutions for packaging to get high current capability.

CV of presenting author
Michel MERMET GUYENNET is born in 1957. He holds PhD (1984) in Applied Physics from Université de Marseille-Luminy and is graduated from Ecole Centrale de Paris (1981). He successively worked for Thomson Militaire et Spatial, SGS-Thomson, Advanced Computer Research Institute and Compagnie des Signaux where he had in charge R&D programmes in the field of electronic components and system hardware. He joined ALSTOM Transport in 1996 in charge of technology development for IGBT power converters for traction. From 2001 to 2010, he has been Technical Director of Power Electronics Associated Research Laboratory (PEARL). From 2011 to 2013, he has been in charge of development of full SiC converter with high speed motor. He is now with Supergrid Institute in Villeurbanne as Director of Programme Power Electronics & Power Converters.

Power Electronics Conference
System Plus Consulting Fraux, Romain
Technological and cost evolution of consumer inertial combo sensors
Fraux, Romain

Fraux, Romain
Project Manager
System Plus Consulting

Abstract
The combo sensor market is estimated to be $446M in 2013, growing to $1.97B in 2018. This represents 21% of the global inertial consumer market in 2013, and will grow to an impressive 66% by 2018. The market acceptance of combo solutions has been extremely quick, not only for 6-axis IMU (adopted in a growing number of platforms) but also for 6-axis e-compass. In addition, 9-axis solutions are being introduced to the market and innovative solutions should follow. Price is still sharply dropping, with IMUs sold to some large volume customers below $1 in 2013. To stay in the race, the 3 leaders (STMicroelectronics, Bosch Sensortec and InvenSense) are going to introduce technical innovations. To show the technological evolutions of consumer combo sensors, we will make a review of several 6-Axis IMU (Accelero/Gyro), 6-Axis eCompass (Accelero/Compass) and 9-Axis IMU (Accelero/Gyro/Compass) from STMicroelectronics, Bosch Sensortec and InvenSense. We will highlight how they manage to decrease their package footprint years after years by shrinking their dies, using new wafer bonding processes or integrating monolithically multiple axes on the same die and see how that impact cost.

CV of presenting author
Romain Fraux is Project Manager for Reverse Costing analyses at System Plus Consulting. Since 2006, Romain is in charge of costing analyses of MEMS devices, Integrated Circuit and electronics boards. He has significant experience in the modeling of the manufacturing costs of electronics components. Romain has a BEng from Heriot-Watt University of Edinburgh, Scotland and a master's degree in Microelectronics from the University of Nantes, France.

International MEMS Industry Forum
SYSTEMA GmbH Luhn, Gerhard
Manufacturing Intelligence and BIG DATA in Real-Time
Luhn, Gerhard

Luhn, Gerhard
Research and Program Manager
SYSTEMA GmbH

Abstract
The increasing availability of information in a connected world is a growing challenge also for the Semiconductor industry. It surfaces in the need for Real-Time information and joined analysis of data from a rising number of sources; ranging from fab to company-wide granularity. That is, manufacturing deciders need granular, Real-Time situational insights to support ad-hoc improvements and decisions. They also require best support for exponentially growing data volumes in testing and production quality control. Overall, Real-Time capability is seen as critical component related to continuous learning and shaping company-wide developments. Based on thorough research, SYSTEMA GmbH, Technical University of Dresden and SQL Project AG Dresden in cooperation with XFab Erfurt evaluated and analyzed detailed use cases with regard to such challenges. Logical and mathematical analysis led to a new, deeper insight resulting in an innovative conceptual approach toward Real-Time information processing in logistical and technical domains. Known peak phases and bottlenecks of previously applied methods (batch jobs) are becoming obsolete. Contrary to the common expectation, this approach leads to a simplified system model, which enables maximum algorithmic efficiency and the desired Real-Time behavior at the same time. Any desired data, such as KPIs or statistical data, are continuously aggregated and evaluated, which systematically reduces the required system load while deploying standard software. Ad-hoc value creation and knowledge discovery with the highest degree of parallelization is available using existing hardware (ex.: identification of dynamically moving production bottlenecks). An example are continuous quality checks of test results in Real-Time, which is of importance to minimize learning cycles. The presentation will include a scientific discussion from within the perspective of general Database / Big Data related research activities of TU Dresden.

CV of presenting author
Gerhard holds a Ph.D in engineering science from the University of Erlangen-Nuremberg (Germany). He has more than 25 years of experience in semiconductor manufacturing and information science. Currently, he is heading a program at SYSTEMA GmbH together with the Technical University of Dresden and several major renowned industry partners, which aims at the industrial proof, prototypical and scientific validation of a new, mathematically grounded method of Real-Time information processing, including large data volumes. Gerhard previously worked as team leader / program manager and research fellow for Infineon/Dresden and Siemens/Munich. He also held various positions in France with Siemens / IBM joint venture in Essonnes; and ST Microelectronics in Crolles.

16th European Manufacturing Test Conference (EMTC)
T To top
Techcet Group, a Techcet CA LLC Company Shon-Roy, Lita
The Impact on Process Materials Requirements for 3D Transistors and Vertical NAND
Shon-Roy, Lita

Shon-Roy, Lita
President / CEO
Techcet Group, a Techcet CA LLC Company

Abstract
Current 3-dimensional structures present new challenges relating to uniformity, lithographic resolution, high aspect ratio etching and fills, and planarization while addressing continuing need to stay at or below current technology node scaling. For example, printing of structures for logic or memory devices below 20nm, without EUV, requires improved photolithography and hardmask materials used for multi-patterning processes. 3D transistors used in logic devices now demand better ion implant more isotropic doping processes, driving end users to look at alternatives to traditional ion implantation. Gap fill will continue to be a challenge as structures become more 3-dimensional and shrink. Better fill properties and perhaps lower K dielectrics from front end materials will be required. High K Gate dielectric precursors will continue to evolve, as higher mobility materials are needed, while cleaning requirements will become even more stringent, seeking ways of ensuring no net addition of impurities that may shift sensitive threshold voltages. For Vertical NAND, while less complex than logic devices, have transistor structures that will continue to push the limits of lithography with the extended use of multi-patterning, using even lower temperature dielectrics, required for numerous thin, conformal, and defect free material stacks. These devices will have similar challenging issues to logic devices with regard to high aspect ratio via and trench etches, and subsequent dielectric deposition, metal via and trench gap fill. What do these challenges really mean in terms of changing material requirements and volume opportunity? In this presentation we highlight those processes that must have better, alternative process materials, and contrast these with materials used for current devices. Finally, market forecasts will be presented on those materials that offer the best opportunity for the future.

CV of presenting author
Lita Shon-Roy , President/CEO of Techcet, has worked in the electronics materials industry in business development and technical marketing for more than 25 years. Her work experience spans from business development, marketing and sales of IC's, equipment, and materials to process development of flat panel displays (TFTs). She has developed new business opportunities for companies such as RASIRC/Matheson Gases and IPEC/Speedfam and helped establish marketing and sales proficiency in companies such as Air Products/Schumacher, Brooktree/Rockwell, and Hughes Aircraft. Lita helped build IPEC as a leader in CMP equipment as Director of International Sales. In 1998, Lita co-founded Techcet Group, LLC. She has authored and co-authored various articles and texts focused on the semiconductor processing, industry forecasting, and the world economy and is now a recognized expert in electronic materials marketing and business development. Lita holds a Master's Degree in Electrical Engineering, with a specialty in Solid State Physics from USC and a Bachelor's Degree in Chemical Engineering from UCSD. She is currently completing her MBA at California State University.

Market Briefing (TechARENA)
Telekom Innovation Laboratories Swaminathan, Rahul
Imaging and Telcommunications
Swaminathan, Rahul

Swaminathan, Rahul
Senior Expert
Telekom Innovation Laboratories

Abstract
Imaging and Telecommunications are two complete and huge fields of research and development in their own right. Hence, in order to tie them together and juxtapose the role of imaging within Telcos we shall first provide an overview of Imaging itself. Imaging encompasses a wide area of technologies spanning decades of research and development. In this talk we shall primarily be focusing on computational imaging. We begin with an overview of imaging sensors and challenge our basic notion of what a "camera" is. Thereafter, we present various applications of these imaging sensors, from image recognition to 3D reconstruction, which are all highly relevant to the telecommunications industry. Various advancements in hardware, sensors, and algorithms have today enabled real-time computational vision systems to operate on mobile handheld devices. Cameras that started out as fancy ad-ons on mobile phones are now generating the most content on data networks. Based on these observations, excerpts from a recent study shall be presented. The study looked into the future of such enabling technologies, the services, and challenges they bring to society. With the current trend of visual consumption and the growing appetite for the same, we must ask ourselves whether our systems are ready to deal with the challenges of tomorrow. More importantly, in what way can we as a Telco play a bigger role in the future of imaging and telecommunications?

CV of presenting author
Dr. Rahul Swaminathan is a Senior Expert (Scientist) at the Telekom Innovation Laboratories of Deutsche Telekom since 2005. He obtained his B.E. in computer engineer at Pune University (India) in 1996. In 2003 he obtained his PhD in computer vision at Columbia University, New York. His PhD thesis titled "Non Perspective Imaging Systems" focussed on imaging geometries that go beyond the pinhole (perspective) model, developing new image formation models as well as designing new sensors for general catadioptric imaging. Over the last few years his research has spanned a wide are of research including camera networks for 3D reconstruction, Human Computer Interaction, Augmented Reality and off late Machine Learning, resulting in various publications and patents.

Imaging Conference
TestCIM Consulting Hartman, Don
Outlier technologies ... how to select the right method
Hartman, Don

Hartman, Don
Consultant
TestCIM Consulting

Abstract
Co_Author: Peter O'Neill, Avago Technologies The goal of outlier detection is to use test measurement data to identify parts that pass specification limits, but are likely to fail future test steps or to become early failures in the field. Many different methods are available, and most methods are based on parametric measurements, geographic information, or a combination of both. The most common method used is Part Average Testing (PAT) which runs on a test that provides a single measurement for each part in a wafer or lot. Our experience is that this method works well for tests with a normal distribution and which are not highly correlated with other tests. However, in other circumstances, other methods are more effective. For example, if tests have measurements that are very wafer position dependent, methods like nearest neighbor residual and Location averaging improve the separation between outliers and the good population of parts; if tests are pairwise highly correlated, methods like linear regression offer improved discrimination, and if groups of tests are highly correlated (e.g., IDDQ), methods like Principal Component Analysis work best; if wafers have areas with high defect density, methods that look at clusters work well and if wafers have scratches, scratch detection methods work well. This paper identifies a range of outlier detection methods and provides guidance on when it makes sense to use which methods. The paper also describes software tools that can automatically analyze a collection of tests and select methods to use based on a set of criteria including distribution shape, measurement variation across a wafer, correlation coefficients between pairs or groups of tests, cluster and scratch detection and geographical position within a wafer or a stack of wafers, etc. The tools are recipe based and allow for an engineer to modify the automatic method selection mechanisms based on engineering knowledge of the tests.

CV of presenting author
Current: - Consultant working primarily for Salland Engineering on software tools to support semiconductor test - Main focus is Outlier Detection and work with SEMI CAST team to develop standards for test Work History: - 16 years at Motorola and Freescale managing teams supporting automation in probe, assembly and test - 12 years at for AT&T Bell Laboratories doing software development and management Education: - BS in Electrical Engineering from University of Texas - MS and PhD in Electrical Engineering from MIT

16th European Manufacturing Test Conference (EMTC)
Thin Film Electronics AB Eriksson, Torbjörn
Printed Electronics: Status, outlook and manufacturing challenges
Eriksson, Torbjörn

Eriksson, Torbjörn
VP Engineering Operations
Thin Film Electronics AB

Abstract
Imagine a not-too-distant future in which thin, flexible sensors are affordable enough to help keep food fresh in transit, preserve vaccine efficacy on its way to the point of care, and even monitor your vital signs away from the doctor's office. In this world, a package of fresh food can tell you whether it's been mishandled in transit to the store, share nutritional information - easily and wirelessly - to a shopper's mobile device, and even alert you to a product's allergens or recalls that could harm loved ones. Once brought into your home, those same sensors can communicate directly with your refrigerator to update stock levels, recommend recipes to use expiring food to avoid waste, and trigger reorders of commonly used items. A vision on this scale requires trillions of low-cost sensors, but we can't rely on traditional semiconductor manufacturing methods to make this a reality. There simply aren't enough semiconductor wafer factories in the world to produce trillions of sensors in a cost effective manner. The answer to this challenge is printed electronics, a field in which Thin Film Electronics is one of the world leaders. Printed electronics uses a combination of printing and coating technologies to produce electronic components such as sensors and smart labels. Using printing technologies, it will be possible to produce sensors and labels at a scale of billions or even trillions. This talk will discuss the status of the printed electronics industry and future challenges in order to manufacture devices on an ultra-high scale.

CV of presenting author
Dr Torbjörn Eriksson holds a Ph. D. in Mechanical Engineering specializing in polymer flow from the Technical University of Denmark. He has more than 10 years' experience of micro and nano technology including process development, machine design and management. Dr Eriksson spent five years at Obducat Technologies, producers of Nanoimprint Lithography machines in different leading roles. Since 2012, Dr Eriksson is VP Engineering Operations at Thin Film Electronics, one of the world leading companies that are commercializing printed electronics.

Plastic Electronics - PE2014
TNO Kievit, Olaf
450mm synergies for smaller wafer diameters: contamination control
Kievit, Olaf

Kievit, Olaf
Projectmanager
TNO

Abstract
Uncertainties about the introduction of 450mm wafers in high volume manufacturing are increasing and delay is expected. As a consequence, questions arise on how R&D activities targeted at 450mm technology can be re-directed towards smaller wafer sizes and other areas of semiconductor manufacturing. A successful transfer of 450mm innovations to other areas is important to ensure the continuity and profitability of the semiconductor industry. In this presentation we will give a view on 450mm synergies from the perspective of the Research Institute TNO. We will show that contamination control developments for the 450mm platform can also be applied to 300mm and Xnm equipment and processes. In addition to current and planned research activities on molecular and particle contamination control, the presentation will include strategies and opportunities for applications beyond the 450mm transition.

CV of presenting author
Dr.ir. Olaf Kievit is Project manager in the Industrial Innovation department at TNO. He graduated in 1990 for his MsC in Chemical Engineering and obtained a PhD in Aerosol Technology at Delft University of Technology in 1995. Olaf worked at 3M Corporation for 6 years, developing new technology for air filtration. He joined TNO in 2001 as a project manager and research scientist. Focusing more and more on project management, he has been active in the field of high end equipment development for over 10 years. Olaf was and is involved in the definition and execution of several European projects including EEMI450, EEM450PR, E450EDL, SEA4KET and E450LMDAP. He currently manages a number of international research projects.

450mm
TRONICS Renard, Stephane
Submicron Technologies for MEMS at Tronics : evolution or revolution ? A new industrial generic technology platform for Integrated MultiDOF Sensor
Renard, Stephane

Renard, Stephane
Founder and CTO
TRONICS

Abstract
"Internet of Things" (IoT) is promising to be the new booster for the MEMS market; it will require a wide variety of combo sensors. By the way, submicron technologies are more and more penetrating the MEMS field. After industrializing the CEA-Leti's M&NEMS technologies, Tronics has developed a new generic technology platform for integrated multiDOF sensors based on this disruptive piezoresistive submicronic nanowires detection principle. Building on its experience in industrial high performance capacitive MEMS technologies, and its know-how in DRIE, wafer bonding and Vacuum Wafer Level Packaging, Tronics designed a manufacturable process flow that combines traditional inertial MEMS blocks and sub-micron processing technology. On the beginning of 2014, a single chip 6 DOF MEMS (3 accels + 3 gyros), as small as less than 4 mm², has been manufactured. In parallel, a single chip 9DOF demonstrator is on manufacturing. In addition, the principle of a single chip 10DOF integrating sensor, including a pressure sensor, is being investigated. Besides its size advantage, the technology significantly decreases power consumption and allows manufacture of various single chips 6DOF, 9DOF and 10DOF devices using a common process flow. With the delivery of these chips, the main technical challenges linked to the manufacturing of the nanowires have been successfully addressed. This new technology, which constitutes a real technology breakthrough for combo sensors, is completing a growing portfolio of submicronic technologies in Tronics, such as high performance optical mirrors and nanoimprint optical components.

CV of presenting author
Stephane RENARD is the founder and CTO of TRONIC'S Microsystems. He received his engineering degree from Ecole Centrale de Paris (1979) and his PhD degree from Grenoble-INP, the Grenoble Institute of Technology (1983). In 1983, he joined LETI (CEA) where he participated in various R&D projects and technology transfers in optoelectronics. From 1991 to 1997, he managed LETI's micro-sensors and MEMS R&D team; the one that invented the in-plane MEMS capacitive accelerometer and the MEMS on SOI technology. In May 1997, Stephane Renard founded TRONIC'S Microsystems: the first private European company specialised in the manufacturing of dedicated SOI MEMS. The company grew steadily in the last 15 years, and has been profitable since 2006. With wafer fabs in Europe and the USA, Tronics is now, one of the largest independent full-service MEMS manufacturers.

International MEMS Industry Forum
TRUMPF Hüttinger & SPM Andreea Vasiliu, Tobias Keller,
State of the art RF generators - cost-efficient adaptation to your systems
Andreea Vasiliu, Tobias Keller,

Andreea Vasiliu, Tobias Keller,
Productmanager RF-Systems, Business Manager
TRUMPF Hüttinger & SPM

Abstract
Development of 450mm systems is ongoing and a long term goal due to the fact that 300mm tools still have a lot of room for improvement to increase their production yield. 6" and 8" are treated as legacy products and are not a focus for improvements. The mission is to support a variety of tool designers and provide top class performance with stability, reliability and repeatability of power with respect to install-base standards and requirements. The solution we offer to tool designers assures full compatibility with legacy products and delivers visible improvements in production performance (yield, energy consumption etc.).

CV of presenting author
T B A

Secondary Equipment (TechARENA)
TSMC Yu, Douglas
Wafer-Level-System-Integration (WLSI) Technologies For 2D and 3D System-in-Packaging
Yu, Douglas

Yu, Douglas
Senior Director, TSMC R&D
TSMC

Abstract
New semiconductor market demands driven by smart mobile computing, cloud computing and Next Big Things (wearable, IoT, etc) are pushing existing packaging technologies, such as flip-chip, multi-chip-module (MCM) and package-on-package (PoP), beyond their technology limitation. Small form-factor and power efficiency requirement are the main challenges. These coupled with the specific product requirements such as highly cost sensitive mobile consumer market, fast increasing memory bandwidth and thermal dissipation challenges for performance-oriented device market, and the continuation of Moore's Law, that is a major concern involving every product segments have pushed not only the technology front, but also make change to the whole conventional semiconductor supply chain. New System-in-Package (SiP) with innovative Wafer-Level-System-Integration (WLSI) technologies have been proposed for flexible and powerful integration of 2D and 3D systems. Examples including CoWoSTM, Integrated Fan-Out and WLCSP will be presented in this talk.

CV of presenting author
Douglas Yu is a Senior Director of TSMC R&D. He has been in charge of advanced backend technology development for 9 major technology nodes. He assumes both principal technical contributor and program manager roles and responsibilities. He led TSMC teams to deliver industry's first production of on-chip interconnects- Cu/Low-K (k= 2.9) in 2001 at TSMC's 0.13m technology node and Low-R/ULK (k= 2.6) in 2009 at 28nm node. His success in delivering these industry standard-setting technologies significantly advanced the performance of ICs and alleviated what ITRS called "Submicron Grand Challenge"- the interconnect limitation to scaling. In addition, the success established the foundry industry as viable providers of high performance technology and indirectly enabled the modern vibrant fabless industry fab-lite companies. More recently, Dr. Yu led TSMC teams to deliver first advanced packaging technologies developed by foundry. He played leadership role to innovate TSMC Cu_BOT (Bump-on-Trace) technology and resolve package-induced issues. This is first foundry's solution of low-cost, and high Cu-bumping density advanced flip-chip (FCCSP) technology. He also established and led TSMC 3D-IC team to deliver industry's first high performance 3D-IC, with innovative CoWoSTM process flow and TSV (Through-Si-Via) architecture, to volume production. The products include both homogeneous and heterogeneous integrations of advanced Logic ICs. His works on advanced packaging and 3D-IC technologies enable chip-partition of advanced Logic ICs and sustain Moore's Law longer. These works have profound impact on the landscape of semiconductor manufacturing. Doug served as general co-chairs of IEEE IITC and chaired ITRS Interconnect conferences. He is an advisory board member of IEEE IMPACT and an Industrial Advisory Board member of Microsystems Industrial Group at Microsystems Technology Laboratories/MIT. He received Ph.D. degree on Material Science and Technology from Georgia Institute of Technology, currently holds more than 430 granted US patents with numerous publications on semiconductor technologies. Doug is an IEEE Fellow.

3D integration (TechARENA)
TU Delft Graef, Mart
ITRS 2.0
Graef, Mart

Graef, Mart
Strategic Programma Manager
TU Delft

Abstract
The International Technology Roadmap for Semiconductors (ITRS), is the fifteen-year assessment of the semiconductor industry's future technology requirements. These future needs drive present-day strategies for world-wide research and development at industrial research facilities, universities and institutes. The objective of the ITRS is to guide the semiconductor community to cost-effective advancements in the performance of integrated circuits and the products that employ such devices, thereby enabling the continued success of this industry and innovation in all sectors of the economy. Through the cooperative efforts of the global chip manufacturers, equipment suppliers, research communities and consortia, the ITRS teams identify critical challenges and encourage innovative solutions. In its 20+ years of existence, the ITRS has clearly demonstrated the benefits that roadmapping brings to the semiconductor industry: the alignment of the research ecosystem on its future needs, enabling an efficient use of R&D resources, resulting in the shortening of development cycles and decreased development costs. Recently, the ITRS has expanded its scope both in terms of technologies (beyond Moore's law, including the "More than Moore" trend) and in the coverage of the value chain (linking technologies and applications). While ITRS has essentially been a bottom up roadmap where products were designed by utilizing standard logic, graphics and memory components, it is evident that, in the present ecosystem, products are now driving the requirements of the semiconductor industry. In ITRS 2.0, which has been launched this year, the roadmapping methodology is based upon the combination of top down generated technology requirements with bottom up availability of new components amenable to new applications.

CV of presenting author
art Graef is strategic program manager at the faculty of Electrical Engineering, Mathematics and Computer Science at Delft University of Technology (TU Delft) in The Netherlands. In this position, he develops technology partnerships with companies, institutes and universities, often within the framework of national and European cooperative projects. He participates in initiatives aimed at defining strategies and technology roadmaps in nanoelectronics, such as NANO-TEC, ENI2 and the ITRS. He is a member of the International Roadmap Committee, which guides the creation of the International Technology Roadmap for Semiconductors (ITRS). He is the chair of the ENIAC Scientific Community Council and participates in the AENEAS Support Group. Mart Graef received a PhD in Solid State Chemistry from the University of Nijmegen, the Netherlands, in 1980. Subsequently, he joined Philips Research, where he held various positions in Eindhoven (the Netherlands) and Sunnyvale (USA) as a scientist and manager in the field of semiconductor process technology. He was strategic program manager at Philips Semiconductors and NXP until 2008, when he joined TU Delft.

ITRS: Trends in Enabling Technologies (TechARENA)
U To top
UJF / CNRS / CHU Grenoble Cinquin, Philippe
From Computer Assisted Medical Interventions to micro-nano implanted medical robots
Cinquin, Philippe

Cinquin, Philippe
Director
UJF / CNRS / CHU Grenoble

Abstract
The medical objective of "Computer Assisted Medical Interventions" (CAMI) is to perform previously defined operative strategies more accurately and less invasively by use of guiding systems under intra-operative sensor surveillance. When we initiated this research in 1984, a methodological framework had to be developed, the technical feasibility had to be proven, the medical interest had to be established, and the potential for a real "market" was not obvious. Nowadays, the methodology we defined is widely accepted, and numerous clinical studies established the clinical added value of systems that are applied in a wide variety of clinical situations. Since the first efforts in CAMI, a major issue has been to bring Information Technology (computers, navigation devices, robots, ...) in the Operating Room, and to use them to enhance a specific component of a complex medical or surgical intervention. The challenge now is to "invert this movement": instead of moving the computer in the Operating Room, we should embed the surgeon (or at least his or her expertise) into the tools he or she uses, exploiting the possibilities of micro-nanotechnologies combined with real-time information processing. The objective of augmentation of the Quality of interventional procedures can be achieved by "augmenting the surgeon" (meaning augmenting his or her capacity of decision or of action, via efficient use of multimodal information and more efficient effectors). This is why we coined the term "Augmented Medical Interventions". We will see which role micro-nanotechnologies may play in this vision, by their capacity to augment intra-operative sensors and effectors, and also by their application to the design of implanted robots capable to scavenge their energy from the glucose of the patient and to compensate for failure of physiological functions. This work is supported by French state funds managed by the ANR within the Investissements d'Avenir, ANR-11-LABX-0004, http://cami-labex.fr/

CV of presenting author
Philippe Cinquin, 58, is Professor of Medical Informatics at Grenoble University (France). He heads TIMC-IMAG, UMR5525, a Research Unit of CNRS and of Université Joseph Fourier, CAMI (Computer Assisted Medical Interventions) Labex, and co-heads CIC-IT 803 (Centre of Clinical Investigation - Technological Innovation) of INSERM, Grenoble's University Hospital and Joseph Fourier University. He holds a PhD in Applied Mathematics and is a Medical Doctor. In 1984, he launched a research team on Computer-Assisted Medical Interventions (CAMI), which led to innovative surgical practice, benefiting to more than 100 000 patients, thanks to the creation of several startup companies. He recently turned on intra-body energy scavenging in order to power implanted medical devices. He was the recipient of the 1999 Maurice E. Muller Award for excellence in computer-assisted orthopedic surgery, of the 2003 CNRS Silver Award, of the 2013 CNRS Innovation Award and of the 2014 Ambroise Paré award of the French Academy of Surgery. He is a member of the French Academy of Surgery. He is co-lead inventor of the "Biofuel cell with glucose" patent, which is finalist of the 2014 European Inventor Award.

Application driven technology: Nanoelectronic for Healthcare (TechARENA)
Imaging Conference
Univ. of Cambridge / EPSRC Centre for Innovative Manufacturing in Large-Area Electronics Occhipinti, Luigi G.
Occhipinti, Luigi G.

Occhipinti, Luigi G.
National Outreach Manager
Univ. of Cambridge / EPSRC Centre for Innovative Manufacturing in Large-Area Electronics

Biography
Dr. Luigi G. Occhipinti is National Outreach Manager of the EPSRC Center of Innovative Manufacturing for Large Area Electronics, a partnership between the University of Cambridge, the Centre for Plastic Electronics at Imperial College, the Welsh Centre for Printing and Coating at Swansea University and the Organic Materials Innovation Centre at the University of Manchester, created to work with industry to address key research challenges for manufacturing large-area electronic systems, and Business Development Manager of the Cambridge Innovation and Knowledge Centre (CIKC). He has more than 19 years of experience driving research and innovation in the semiconductor industry, pioneering the field of post-silicon technologies, including development and applications of: organic and printed electronics, MEMS and bio-MEMS devices, graphene-based flexible electronics, smart systems heterogeneous integration, chemical and bio-sensors for personalized diagnostics and therapeutics. Prior to that he was R&D Programs Director and Senior Group Manager at STMicroelectronics, a global semiconductor company, leading research teams and new business development based on Heterogeneous Integrated Smart Systems, Flexible and Disposable Electronics and New Sensors technologies. During the career in Industry he developed unique achievements and success stories in terms of new business creation with strategic customers (incl. some of the top 100 global brands), new product concepts, and state of the art technology platforms (e.g. for flexible and disposable electronics, personalized diagnostics, IVD). He has authored and co-authored over 80 scientific publications and 35 patents. Since 2004 he has been member of IEEE standardization committees P1620 and P1620.1, dedicated to organic electronics devices and circuits, and, of IEC-CEI standardization Technical Committees, TC 105, 111 and 113.

Plastic Electronics - PE2014
Univ. Paris Sud Marris-Morini, Delphine
Silicon photonics on 300mm platform
Marris-Morini, Delphine

Marris-Morini, Delphine
Assistant professor
Univ. Paris Sud

Abstract
Silicon-based photonics has generated a strong interest in recent years, mainly for optical telecommunications and optical interconnects in integrated circuits. The main rationales of silicon photonics are the reduction of photonic system costs and the increase of the number of functionalities on the same chip combining photonics and electronics. Silicon based-optoelectronic devices (source, modulator and photodetector) have been particularly studied as key building blocks for the development of silicon photonics. Their successful demonstrations proved the capability of silicon photonics to be used for high speed communication for different length range from chip to chip to long haul communications. From the stand-alone devices, today's important challenge is the integration of both photonic and electronic circuits (modulator with electrical driver, photodetector with TIA amplifier...). Before this ultimate integration, a crucial intermediate step is the fabrication of high-performance building blocks in large-scale microelectronic foundries. Silicon modulators and germanium photodetectors have recently been processed on 300 mm SOI wafers in microelectronics foundry. Such a platform allows mass production of silicon photonic circuits compatible with advances sub-65nm CMOS node, using state of the art 193nm photolithography with sub-50nm resolution as well as a good thickness uniformity. A 40Gbit/s optical link has thus been demonstrated by coupling a silicon (Si) optical modulator to a germanium (Ge) photo-detector from two separate photonic chips fabricated on 300 mm SOI wafers. These demonstrations paved the way of achieving further technological nodes, targeting high-performance and low power consumption of microelectronic chips.

CV of presenting author
Delphine Marris-Morini received her PhD in 2004 on optical modulation in silicon. She then became an assistant professor at the University of Paris Sud, pursuing her research at the Institute of Fundamental Electronics (IEF). Her activities are dedicated to silicon optoelectronics and cover modulators and photodetectors made of silicon and germanium. Delphine Marris-Morini participated to a numerous of French and European international projects focused on silicon photonics. She has published more than 60 papers in international journals. She contributed to several books on silicon photonics and is holder of 4 patents.

Silicon Photonics (TechARENA)
Universal laser Systems Hillman, Joseph
Application of Multiple Wavelength Laser Processing to the Fabrication of Flexible Electronic Circuits
Hillman, Joseph

Hillman, Joseph
Manager, Advanced Materials Processing Center
Universal laser Systems

Abstract
The fabrication of flexible electronic circuits presents several challenges, two of which can be addressed specifically by laser processing. One of these challenges is the selective ablation of conductive layers from the surface of a plastic substrate without damaging the polymer. The second is trimming the plastic substrate to its final shape without imparting mechanical stress, which could damage the circuit. In this paper, we will show how the first challenge can be met using a fiber laser with a wavelength of 1.06 micro-meters. This wavelength of light is readily absorbed by conducting materials, such as silver and carbon nanotube based composites. This wavelength is also efficiently transmitted by insulating materials such as polyimide (PI) and polyethylene terephthalate (PET). This set of properties allows the 1.06 micro-meter laser beam to completely ablate the conductive layer, without damaging the substrate. We will provide a detailed technical explanation for this process, and also explore several practical applications such as circuit repair and rapid prototyping. We shall also explore the application of a different laser wavelength to trimming the plastic substrate to its final shape following circuit fabrication. The CO2 laser provides a laser beam wavelength that is absorbed efficiently by organic materials such as plastics. The efficient absorption of the laser energy, coupled with the collimated nature of the laser beam allows the laser to cut cut cleanly through the plastic substrate without imparting any mechanical stress to the finished circuit. This allows for cutting very closely to the active circuitry, thereby enabling smaller package sizes.

CV of presenting author
Mr. Hillman has a degree in Materials Science and Engineering from the Massachusetts Institute of Technology. He has over 20 years of experience in development of advanced fabrication processes for microelectronics, with 4 years dedicated to laser processing techniques. He has published more than 100 technical papers, and has over 50 patents in the advanced electronics field.

Plastic Electronics - PE2014
University of Applied Sciences Wiener Neustadt Nemecek, Alexander
System-On Chip Gas Sensor with TSV-contacts in 0.35µm CMOS technology
Nemecek, Alexander

Nemecek, Alexander
Head of Department
University of Applied Sciences Wiener Neustadt

Abstract
Within this work a fully integrated System-On Chip (SOC) gas sensor containing a micro-hotplate (µHP) with a gas sensitive layer on top, an integrated temperature control as well as an electronic readout circuit is presented. In order to exploit the high sensitivity of metal oxides like TiO2 to diverse target gases, relative high operating temperatures are required. Based on finite element simulations and results from first silicon samples, an optimized design of the µHP is realized by a MEMS front side etching step. Exploiting standard CMOS technology, the fully released µHP shows an arm length l=150µm, a poly-silicon heater with an active area Aheat=70x70µm² plus integrated thermocouples for temperature sensing. As a result of this fully released µHP, very low power consumption Pel=9mW/15mW at T=300°C/400°C ending up in highest thermal efficiency n=39K/mW...26.5K/mW together with high mechanical stability is achieved. Measurements using thermal imaging confirm high operating temperatures and very good uniformity of only DeltaT~1K across the active area. Furthermore long-term measurements with 10million(!) heating T=400°C and cooling cycles T=20°C at a rise/fall time t=9.1ms/11.3ms proved the reliability of the µHP. The actual temperature can be adjusted depending on the specific target gas and is controlled by an integrated circuit. A highly linear readout circuit indicates even smallest gas concentrations, i.e. resistance changes, down to ppm range for e.g. CO in humid air. The realized smart and tiny packaging concept of the SOC sensor features Through Silicon Via (TSV) contacts with a diameter d=80µm, aspect ratio AR=2.5 ending up in a total chip size A=3x3mm² and can directly be mounted on a PCB. Despite the challenging process combination of 0.35µm standard CMOS technology including TSV integration for smart packaging, MEMS front side release etch for the µHP plus deposition of the gas sensing metal oxide, the entire SOC sensor could be realized successfully.

CV of presenting author
Alexander Nemecek was born in Vienna, Austria in 1975 and graduated in electrical engineering from Vienna University of Technology (VUT), Austria in 2003. Until 2008 he worked at the Institute of Electrical Measurement and Circuit Design at VUT on optoelectronic circuit design and completed his doctoral thesis awarded with the "Joseph Ressel-Award" of VUT in 2006. In 2008 he joined the University of Applied Sciences Wiener Neustadt. Since 2012 he is head of department for Micro- and Nanosystems. His main research interests are microelectronics, circuit design, MEMS, photonics, measurement engineering, model analysis and automation control.

International MEMS Industry Forum
University of Pisa Fiori, Gianluca
What can we expect from two-dimensional materials for electronic applications? A simulation study
Fiori, Gianluca

Fiori, Gianluca
Assistant Professor
University of Pisa

Abstract
Research community has great expectations towards two-dimensional materials, since they could be the option for ultimately scaled devices. Many issues however still remain open due to the embryonic stage of nowadays fabrication technology. Computer simulations can represent a powerful tool in order to predict the real performance of two-dimensional material, giving useful hints on the solutions to be discarded as well as those to bet on. Here we provide an overview of state-of-the-art devices, showing which solutions are in our opinion the most promising, as well as those which we believe will never comply with Industry requirements. In particular, attention will be posed on vertical and lateral heterostructures, as well as bilayer graphene based devices for both digital and analog applications. An overview on energy applications will be provided as well, showing that graphene can represent a viable option for transparent electrode and a valid substitute for Indium Thin Oxide contact in organic solar cells.

CV of presenting author
Gianluca Fiori is an Assistant Professor at the University of Pisa. His main field of activity includes the development of models and codes for the simulation of CMOS transistors with ultra-short channel and innovative devices based on new architectures and new materials. In particular, at the beginning he focused his attention on quantum confinement, short channel effects and the random distribution of dopants in Silicon MOSFETs: part of these models have been included into the commercial device simulator ATLAS, within a collaboration, in Autumn 2002, with Silvaco International, one of the worldwide leading developers and vendors of Technology Computer Aided Design (TCAD) software dedicated to Process and Device Simulation. Due to the increased interest in carbon electronics, Dr. Fiori has focused his attention on carbon based devices, through repeated research visits (in 2004, 2005 and 2008) at the Network for Computational Nanotechnology, at Purdue University, (IN-USA). Within these activities, he has developed codes based on semi-empirical tight binding Hamiltonians and the Non-Equilibrium Green's Function Formalism (NEGF). Dr. Fiori has recently released, under the BSD open-source license, the in-house developed code NanoTCAD ViDES (http://vides.nanotcad.com), which includes most of the physical models implemented during his research activity.

2D (TechARENA)
V To top
VALEO Vanhelle, Stephane
Flexible electronics in Intuitive Driving
Vanhelle, Stephane

Vanhelle, Stephane
P2P3 Innovation Manager
VALEO

Abstract
-Fluidity in styling , flush surface , curved surfaces (dematerialization , less complexity) -Multi functionality, Configurability , contextualization, personalization -Perceived quality , intuitivity from interfaces (Visual , touch, sound..) "smart" surface -Brand image from OEMs driven with visible and touchable parts and particularly HMI perimeter As provider of HMI solutions , Valeo is thinking to best solutions combining increasing number of functionalities and types of input/output devices (including displays) including styling trends and ergonomics approach . In one question: How to bring more intelligence close to visible complex surfaces? Smart surfaces are requesting new thinking in term of foil material , decoration ,lighting, sensors , displays technologies (TFT, OLED..) ,flexible circuit combination with components for architecture optimization...It's a difficult but exciting challenge!

CV of presenting author
Project Manager at G.Cartier Systems and Magneti Marelli until 1988 Innovation and RFQ Manager at Sylea (Labinal Group) for automotive switches market In charge since 2000 to Innovation programs for Human Machine Interfaces in Automotive Industry for VALEO Switches & Smart Controls VALEO Expert status in 2003 Branch Product Line Director and P2P3 Innovation Manager. Expertize in touch sensitive and haptic feedback technologies as well as human factors in automotive world

Plastic Electronics - PE2014
VTT technical research centre of Finland Kaisto, Ilkka
PrintoCent towards industrialization of Printed Intelligence
Kaisto, Ilkka

Kaisto, Ilkka
PrintoCent, Director
VTT technical research centre of Finland

Abstract
Printocent community has been established to build capabilities in industrialisation and commercialization of Printed Intelligence. The focus in its first phase during years 2009 - 2012 was in the Pilot Factory Concept, in activation of start-up creation and in pushing forward the commercialization and industrial networking with Prinse seminars - industrial talks and stimulating demonstrator shows. The second phase 2012-2015 aims at clustering of 50 companies, utilizing, learning and developing the Pilot Factory Concept, hunting killer applications, building value chains and delivering 100 000 volume demonstrators for market trials. Ongoing PrintoCent activities like Printed Intelligence Designer`s Handbook, design tool and component library development, roll-to-roll PrintoCent pilot factory service for manufacturing upscaling, printed component and system demonstrators, Innofest like innovation competition and active start-up creation process and European cooperation in COLAE project are shown as examples. Besides, it is very clearly seen that from regional and national point of view there has to be smart specialization to selected application areas utilizing local strengths, manufacturing services/technologies and finding complementing services/technologies by co-operations as already has been carried out in Europe by COLAE partners. The challenge of PrintoCent community in the coming years will be concentrating regionally to the needs of fast growing start-up companies and in global perspective to the innovation and development of new type of products and services. The availability of design, development and manufacturing services provided by companies and research centres of innovation clusters will be in crucial role to make this new industry fly.

CV of presenting author
Mr. Ilkka Kaisto received his his MSc and Tech.Lic. degrees in electronics and optoelectronics engineering from the University of Oulu, Finland, in 1981 and 1987, respectively. He has been working in SME companies (Prometrics Oy, PolarporoOy, A.M.S: Accuracy Management Services Ltd) as an entrepreneur and in Insta Oy (Instrumentointi Oy, Insta Visual Solutions) in various positions from R&D management to business and quality manager to Vice President 1984 - 2005. Since then he worked in Oulu region as a regional developer in Micro- and nanotechnology clustering and started the Printocent initiative with VTT year 2008. At beginning of 2011 he started to work at VTT and currently he is Director of Printocent.

Plastic Electronics - PE2014
W To top
Wavelens Pouydebasque, Arnaud
Wavelens - Shaped for Sharpness
Pouydebasque, Arnaud

Pouydebasque, Arnaud
Co-Founder and Product Development VP
Wavelens

Abstract
In the cameras and optics miniaturization trend (mainly led by Camera Phones), optical performances must not be neglected, quite the opposite. The image quality is increasingly important and complex optical functions such as Autofocus, Image Stabilization and Zoom are becoming essential. Wavelens is leveraging MEMS technologies to provide their customers with compact, slim and high speed solutions in order to help them to develop and integrate such complex optical functions easily. With their low actuation voltage and their high power efficiency, Wavelens' optical MEMS offer a cost effective solution to customers.

CV of presenting author
Arnaud Pouydebasque received the M.Sc. and Ph.D. degrees in materials science and electrical engineering from the Institut National des Sciences Appliquées (INSA), Toulouse, France, in 1997 and 2001, respectively. From 2002 to 2007, he worked for Philips Semiconductors (currently NXP Semiconductors) in Crolles, France, where he focused on the integration of advanced CMOS technologies. In 2007, he joined the MEMS department of the CEA-LETI, Grenoble, France to develop optical microsystems such as variable-focus liquid lenses. In 2012, he co-founded Wavelens, where he is currently in charge of the product development.

Imaging Conference
X To top
X-Celeprint Limited Bower, Christopher
Micro-Transfer-Printing: Assembly of Microscale Components Using Elastomer Stamps
Bower, Christopher

Bower, Christopher
Chief Technology Officer
X-Celeprint Limited

Abstract
Micro-Transfer-Printing is an assembly technology for integrating microscale components onto non-native substrates. In Micro-Transfer-Printing an engineered elastomer stamp coupled to a precision motion controller is utilized to pick-up and transfer arrays of microscale devices. A wide range of materials and devices have been micro-transfer-printed, including; Silicon integrated circuits, Gallium Arsenide LEDs, Gallium Arsenide solar cells, Gallium Arsenide lasers and Gallium Nitride LEDs. Transfer-printable devices are very thin (< 10 microns) and small (< 100um lateral dimensions) and are ideally suited for making flexible devices and are also well-suited for 3D heterogeneous integration onto CMOS or MEMS wafers. Here, we review the state-of-the art in Micro-Transfer-Printing and also present Micro-Transfer-Printing as a cost-effective approach to heterogeneous integration. We will present strategies for making printable Silicon integrated circuit devices and compound semiconductor devices (eg. GaAs and GaN). Finally, we will discuss several key applications of microscale assembly.

CV of presenting author
Dr. Chris Bower obtained B.S. and Ph.D. degrees in physics from the University of North Carolina in Chapel Hill, NC in 1996 and 2000. He has more than 15 years of experience in the fabrication and packaging of novel electronic and photonic devices, both at the nanoscale and the microscale levels. For the past seven years he led micro-transfer-printing technology development at Semprius, Inc. His interests include three-dimensional integration of integrated circuits, heterogeneous integration of compound semiconductors onto non-native substrates and the fabrication of low-cost, large-format electronics using novel assembly methods.

International MEMS Industry Forum
Xcerra Cockburn, Peter
Using a Test-Cell-Solution Approach to Achieve Device Quality and Production-Efficiency Goals for 77GHz Automotive Radar ICs
Cockburn, Peter

Cockburn, Peter
Senior Product Manager
Xcerra

Abstract
Radar-based ADAS are moving from 24GHz to 77GHz, providing better range, bandwidth and resolution for detecting objects. Automotive 0 ppm failure rates necessitate full functional test of the ADAS ICs at 24GHz or 77GHz in both Engineering and HVM. Specialized ATE solutions may be under-utilized as requirements change and are not well adapted for HVM. An ideal solution should be usable with different RF and Automotive applications. A co-development between ST and Xcerra has already implemented 28GHz RF test to maintain the highest quality levels. This is based on a flexible test cell base that can be used for other requirements and a system-level solution to maximize OEE and minimize cost. The test cell is now being extended to provide a 77GHz test solution. The DUT has 38GHz IF and several 77GHz TxRx to implement a multiple beam solution for best performance. The device also uses >1 Gigabit serial I/O to facilitate high speed data transfer. The test cell uses a low-cost 6GHz subsystem and optional radar frequency test modules to balance flexibility and cost of full-speed test. An integrated test cell design of the complete signal path, from RF instrumentation, through the fixture and contactor to the DUT, is used to maintain 77GHz signal quality. Production contactors are required for WLCSP and packaged devices. In-socket calibration verifies signal performance at the DUT. Because automotive ICs operate at extended Hot and Cold temperatures, a "tri-temp" handler ensures the highest test coverage. A systems-level mechanical design enables temperature accuracy of +/-2 DegC. In conclusion, the customer's DUT is tested to the highest levels of coverage, to guarantee quality at the OEMs. The vendor has proven an optimized test cell approach to provide a cost-effective solution with the highest OEE.

CV of presenting author
Peter Cockburn has worked in the ATE industry for over 24 years at Schlumberger, NPTest, Credence, LTX-Credence and now Xcerra. He has developed real-time and GUI software for ATE systems, managed the launch of several SOC ATE systems and new analog test options and provided marketing and sales support in USA, Asia and Europe. As Product Manager in the Test Cell Innovation team, he is now defining new ways to reduce cost and increase uptime when testing semiconductors. He has an Engineering degree from the University of Southampton, UK.

16th European Manufacturing Test Conference (EMTC)
Xfab Mixed Signal Foundry Richter, Steffen
Optimizing Automatic Parametric Test (APT) in Mixed Signal / MEMS foundry
Richter, Steffen

Richter, Steffen
Group Manager Process Control Monitoring
Xfab Mixed Signal Foundry

Abstract
SUMMARY: Addresses implementation of improved efficiency in automated parametric test in a manufacturing environment, also across different hardware platforms. Issues to resolve include correlation of tools as well as optimizing test routines for improved throughput and improved accuracy. Describes partnership effort between the device manufacturing and tool supplier. DETAIL Test Speed Optimization o Analysis of the test program (Pareto tool) to identify what the main test time contributors are. Evaluate distribution by test type and test macro. Prioritization of the effort, always 'there is not enough time to optimize the program'. o Evaluate Fixed range vs Auto range, advantages and disadvantages, speed vs dynamic range trade-offs, compromise is LowRange capability to have dynamic range and speed o Review standard cases where test program can be optimized o Review Breakdown tests and optimize for throughput - Different breakdown tests: a) WLR style: Gate Oxide breakdown with FN current; more recent "Soft break downs" of GOX detected by the higher noise of the current; qbdrampI, qbdrampI b) ILD, MOS transistor breakdown; recoverable (MOS) and destructive (ILD) - differences between Voltage sweep and current force technique - bv technique, which forces current and monitors measurements to detect various "breakdown" conditions. - Test conversion from one test environment to another (I.e. different types of testers, or testers from different vendors) - how to move test information from one environment to another, advantages to stay within close environments, automated scripts to move the data; advantages of "data driven test environments, such as KTE" - General test requirements: correlation, how to handle and expectations; only parameters that actually characterize the dut/process can be correlated; - Miscellaneous considerations o COO o HV tests o Using remote testing as a collaborative tool o Importance of Data sharing between partners.

CV of presenting author
Steffen Richter. Group Manager Process Control Monitoring Xfab Mixed Signal Foundry, Erfurt, Germany Steffen Richter was born in 1963 in Germany. He finished his study of Physics and Microelectronic Components at the Chemnitz University Of Technology with degree Diploma Engineer in 1989. He works as Group Manager Process Control Monitoring at X-FAB's R&D department. About X-FAB Silicon Foundries As the world's leading foundry group for analog/mixed-signal semiconductor applications, X-FAB creates a clear alternative to typical foundry services by combining solid, specialized expertise in advanced analog and mixed-signal process technologies with excellent service, a high level of responsiveness and first-class technical support. X-FAB Silicon Foundries worldwide With its five manufacturing sites in Germany, Malaysia and the USA, X-FAB has a combined capacity of around 62,000 eight inch equivalent wafer starts per month and employs around 2,400 employees worldwide. Sales representatives in major countries in Asia, Europe and in the USA ensure that we stay in close contact with our customers all around the world. www.xfab.com CO Author: Alex Pronin, Applications Engineer Ph.D. Keithley Instruments, Cleveland, OH, USA Alex Pronin is currently a lead applications engineer with Keithley Instruments, Inc. in Cleveland, Ohio and has been with the company since 1996. Alex holds a Master's Degree in Physics from the Moscow Institute of Physics and Technology and a Ph.D. in Material Science from Dartmouth. About Keithley Keithley, a Tektronix company, designs, develops, manufactures, and markets advanced electrical test instruments and systems for the specialized needs of electronics manufacturers in high-performance production testing, process monitoring, product development, and research. Keithley has approximately 500 products that are used to source, measure, connect, control, or communicate direct current (DC) or pulsed electrical signals. Product offerings include integrated systems along with instruments and personal computer (PC) plug-in boards that can be used as system components or stand-alone solutions. Keithley customers include scientists and engineers in the worldwide electronics industry involved with advanced materials research, semiconductor device development and fabrication, and the production of end products such as portable wireless devices. www.keithley.com

16th European Manufacturing Test Conference (EMTC)
Y To top
Ynvisible Henriques, Ines
Printoo - a new prototyping platform for printed electronics
Henriques, Ines

Henriques, Ines
CEO
Ynvisible

Abstract
In response to early adopter demand, Ynvisible developed Printoo. Printoo is an arduino-compatible, open source, lego-like platform which allows anyone to prototype and create new interactive, connected products, using flexible, printed electronics components, including Ynvisible's displays. Printoo consists of a set of flexible boards and components that may be connected to one another to bring everyday objects to life. In a world where computers have become an integral part of our lives, Printoo aims to give people the ability to embed computational power into everyday object and devices. Printoo also enables new ways to link the physical and the digital worlds, and, because it does not require knowledge of electronic circuits, programming or soldering skills, is ideal for use by non-engineers - i.e. designers, educators, researchers. We believe that Printoo and other similar open platforms can take printed electronics beyond traditional markets and challenge the industry to explore alternative business approaches.

CV of presenting author
Inês Henriques is Ynvisible's CEO. From 2007 to 2010, Inês led and managed the research initiative at YDreams (Ynvisible's mother company) which gave way to Ynvisible. She has led the founding of the company, designed the organization of the new commercial entity and led its first financing round. Inês has a degree in Environmental Engineering from the New University of Lisbon and a PhD in Civil Engineering from Virginia Tech. She has over six years of experience working and living in the U.S. She has authored several scientific papers and patents, and received several awards for her research and academic achievements. In 2010, Inês was profiled in leading Portuguese newspaper Expresso, as one of the country's "female top talents to watch in the coming decade".

Plastic Electronics - PE2014
Yole Mounier, Eric
Future of MEMS: Market and technologies perspective
Mounier, Eric

Mounier, Eric
Senior Analyst
Yole

Abstract
The MEMS market is still on a high dynamic growth, driven by consumer applications. Among the different devices, inertial MEMS represent a major share. Indeed, the inertial sensor market has been very active in the past few years and innovation is still ongoing. Those sensors today represent the largest MEMS market - accounting for more than $3.5B - and this should not change in the near future. Several market drivers motivate current inertial technological developments. For example integrators for consumer products apply a strong price pressure on component manufacturers thus motivating die size reduction in order to lower manufacturing costs. Other industry requirements include low power consumption for mobile applications, better performances and higher integration of functionalities. Those required improvements have not changed for quite some time now. The difference mainly lies in the way technology adapts in order to meet these more and more stringent specifications. In the past several years, the tendency was at increasing the number of axis for standalone components while decreasing size; now the industry looks at complete integration of 9+ axis sensors and standardization of platforms. In our talk, we will review the MEMS market and emphasizes on new technical innovations adopted by players to answer to the low cost/high integration demand, specifically for inertial. We did reverse engineering & cost structure analysis upon more than 40 different inertial MEMS and will present main conclusions for performances, costs, size (MEMS, ASIC and package), ASIC lithography node, and manufacturing approach. This factual analysis will underline the previously mentioned trends and will permit a concrete visualization of the current status of different companies in term of integration We will conclude by giving a long term perspective of what the new detection technologies for MEMS could be in the future.

CV of presenting author
Dr Eric Mounier has a PhD in microelectronics from the INPG in Grenoble. He previously worked at CEA LETI R&D lab in Grenoble, France in marketing dept. Since 1998 he is a cofounder of Yole Développement, a market research company based in France. At Yole Développement, Dr. Eric Mounier is in charge of market analysis for MEMS & Sensors, visible and IR imagers (CIS, microbolometers), semiconductors, printed electronics and photonics (e.g. Silicon photonics). He is Chief Editor of Micronews, and Yole Développement magazines: MEMS'Trends, Power Dev, iLEDS, 3D Packaging. He has contributed to more than 150 marketing & technological analysis and 60 reports. Eric is also an expert at the OMNT ("Observatoire des Micro & Nanootechnologies") for Optics.

Imaging Conference
Plastic Electronics - PE2014
International MEMS Industry Forum
Yole Developpement Breussin, Frédéric
Medical & healthcare: What are the opportunities for MEMS and sensors?
Breussin, Frédéric

Breussin, Frédéric
Business Unit Manager MEMS & Sensors
Yole Developpement

Abstract
The medical and healthcare market are nowadays considered by most electronics and semiconductors suppliers as a new growth opportunity. The potential is huge, ranging from high value/high margin medical devices to health consumer products for wellness and fitness. As part of this market, Wearable electronics is a significantly growing market, mainly driven by smart watches. Many products are already on the market, measuring physical and physiological parameters, which are transferred to a base station (typically a mobile phone). Added value is then created by specific "smart" applications. To feed these applications with data, the demand for all types of so-called bio-sensors is significantly increasing and affecting the way the sensor industry is organized. Pressure sensors, IR sensors, microfluidic chips, chemical and gas sensors are just few examples. Yole Développement will provide an overview of the applications and the challenges industry will face to enter this market.

CV of presenting author
Frédéric Breussin is responsible for the MEMS and Sensors activity. He has supported many companies in their innovation and product development strategy in making the bridge between micro systems technologies and their applications in consumer, automotive, industrial, Life sciences, diagnostics and medical device industries. He holds an Engineering diploma from INSA Rouen & a DEA in fluid mechanics from University of Rouen.

International MEMS Industry Forum
Imaging Conference
Application driven technology: Nanoelectronic for Healthcare (TechARENA)
Yole Developpement Gueguen, Pierric
Market & technology overview of power electronics industry and impact of WBG devices
Gueguen, Pierric

Gueguen, Pierric
Marketing & Technology Senior Analyst
YOLE DEVELOPPEMENT

Abstract
Emergence of new wide bandgap (WBG) technologies such as SiC and GaN will definitely reshape part of the established power electronics industry, especially on the high and very high voltage side (>1.7kV) SiC and GaN offer higher frequency switching, higher power density, higher junction T° and higher voltage capabilities (>15kV). To now, the incumbent packaging solution does not fit SiC/GaN specifications. In particular, only a tiny part of the WBG added-value could be captured by using current approaches. Some companies offer a new enhanced package strategy that can help addressing the demand for improved performance, in line with SiC and GaN specifications At midterm, these new power modules could expect targeting a ~$200M market in 2016, exceeding $1B at longer term (2020+).

CV of presenting author
Pierric GUEGUEN is currently working for Yole Développement as a marketing & technology Senior Analyst. He has a PhD in Micro and Nano Electronics from Grenoble INP Institute of Technology , and a Master of Micro and Nanotechnologies for Integrated Circuits (European program with Grenoble INP/ Politecnico di Torino, Italy / EPFL, Lausanne, Switzerland. He is author and co-author of more than 20 technical papers and 15 patents. Main knowledge & skills : Power electronics, Power module packaging and assembly technologies, Wide Band Gap devices, 3D-Integrated Circuit (IC) and Packaging processes, Material and semiconductor physics for electronic components, Technological process for micro-nano manufacturing and characterization in clean room Previous experience : Project Manager on electric vehicles, Vehicle Energy System Division of RENAULT PARIS, Power Electronics R&D Engineer, Advanced Electronic Division of RENAULT PARIS, R&D Engineer, Technical Research Division CEA-Leti (Soitec & STMicroelectronics collaboration) GRENOBLE, FRANCE His contact: gueguen@yole.fr

Power Electronics Conference
YOLE DÉVELOPPEMENT Eloy, Jean-Christophe
Market & Technology Trends in Materials & Equipment for Printed & Flexible Electronics:
Eloy, Jean-Christophe

Eloy, Jean-Christophe
President / CEO
YOLE DÉVELOPPEMENT

Abstract
For now, organic electronics are made on rigid substrates and mainly manufactured using vapor deposition techniques, which are costly, generally require high temperatures and generate significant product waste. Printed and flexible electronics has been a very hot topic in this past decade, holding the promise of a tremendous new market. While the printing of electronics is mainly a way to produce large electronic surfaces and reduce manufacturing costs, flexibility will provide higher robustness to the end products as well as new features, designs and shapes. The presentation will explain how this market will be addressed by players that do not necessarily come from the semiconductor field. In this emerging part of the electronics industry, chemical companies and printing equipment companies are the players that will enable volume manufacturing and will leverage technical bottlenecks. Technology enablers are therefore not those usually involved in electronics development. The solution printing & coating industry is very far from the standard electronics industry, in terms of equipment and materials and they have completely different industrial cultures. The presentation will also estimate and forecast the equipment and material markets for printed and flexible electronics. Equipment and materials markets are still low, and will remain so over the next several years. Nevertheless the start of the industry ramp up is expected in 2018 for materials. It will be driven by the OLED industry that will represent a global market of almost $ 170M in 2020 (OLED only). The equipment market will start its ramp up sooner than materials, as device manufacturers will have to prepare for upcoming volumes. Our model for equipment forecasts is based on existing and future projects in printed and flexible electronics. Today it is unclear which deposition process will be used and companies often buy cluster tools with different deposition processes inside.

CV of presenting author
JC Eloy has created YOLE Développement in 1998 and is managing Yole Développement in term of international development and strategic orientations of the company. He is directly in charge of the Mems and 3D IC activities at Yole Développement JC Eloy and the 20 analysts of YOLE Développement are working directly with the key players of the industry from equipment and materials suppliers to device manufacturers and system integrators. Jean-Christophe Eloy has been 6 years manager of the marketing department of CEA/LETI (France), applied R&D organization involved in the semiconductor, Mems and instrumentation fields (1300 researchers). He then created the semiconductor practice at Ernst & Young in Europe and worked as senior manager in charge of the development of European activities. Jean-Christophe Eloy is involved since 1991 in the Mems and semiconductor areas. EDUCATION JC Eloy is Engineer from INPG/ENSERG (semiconductor and telecommunications) and has a MBA from EM Lyon.

Advanced Packaging Conference (APC)